QEMU RISC-V Emulation Support (RV64GC, RV32GC)

This version of the RISC-V patch series "lucky number five" contains
cleanups to the FPU code, fixes several FPU related test failures in
riscv-tests and updates the syscalls for RISC-V linux-user emulation.

The git tree for this v5 patch series (squashed and rebased):

- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v5

The git tree for the v1-v4 patch series with review commit history:

- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v4
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v3
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v2
- https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v1

*** Known Issues ***

- FPU code needs further work to handle NaN-Boxing of Narrower Values
- Disassembler has some checkpatch warnings for the sake of code brevity
- scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
- PMP (Physical Memory Protection) is as-of-yet unused and needs testing

*** Changelog ***

v5

- Fixed 4 test failures in riscv-tests, only one set to go...
- Use float_muladd_negate_* flags to floatXX_muladd
- Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
- Fix TARGET_NR_syscalls
- Update linux-user/riscv/syscall_nr.h
- Fix FENCE.I, needs to terminate translation block
- Adjust unusual convention for interruptno >= 0

v4

- Add @riscv: since 2.12 to CpuInfoArch
- Remove misleading little-endian comment from load_kernel
- Rename cpu-model property to cpu-type
- Drop some unnecessary inline function attributes
- Don't allow GDB to set value of x0 register
- Remove unnecessary empty property lists
- Add Test Finisher device to implement poweroff in virt machine
- Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior
- Store fflags data in fp_status
- Purge runtime users of helper_raise_exception
- Fix validate_csr
- Tidy gen_jalr
- Tidy immediate shifts
- Add gen_exception_inst_addr_mis
- Add gen_exception_debug
- Add gen_exception_illegal
- Tidy helper_fclass_*
- Split rounding mode setting to a new function
- Enforce MSTATUS_FS via TB flags
- Implement acquire/release barrier semantics
- Use atomic operations as required
- Fix FENCE and FENCE_I
- Remove commented code from spike machines
- PAGE_WRITE permissions can be set on loads if page is already dirty
- The result of format conversion on an NaN must be a quiet NaN
- Add missing process_queued_cpu_work to riscv linux-user
- Remove float(32|64)_classify from cpu.h
- Removed nonsensical unions aliasing the same type
- Use uintN_t instead of uintN_fast_t in fpu_helper.c
- Use macros for FPU exception values in softfloat_flags_to_riscv
- Move code to set round mode into set_fp_round_mode function
- Convert set_fp_exceptions from a macro to an inline function
- Convert round mode helper into an inline function
- Make fpu_helper ieee_rm array static const
- Include cpu_mmu_index in cpu_get_tb_cpu_state flags
- Eliminate MPRV influence on mmu_index
- Remove unrecoverable do_unassigned_access function
- Only update PTE accessed and dirty bits if necessary
- Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx
- Remove buggy support for misa writes. misa writes are optional
  and are not implemented in any known hardware
- Always set PTE read or execute permissions during page walk
- Reorder helper function declarations to match order in helper.c
- Remove redundant variable declaration in get_physical_address
- Remove duplicated code from get_physical_address
- Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug

v3

- Fix indentation in PMP and HTIF debug macros
- Fix disassembler checkpatch open brace '{' on next line errors
- Fix trailing statements on next line in decode_inst_decompress
- NOTE: the other checkpatch issues have been reviewed previously

v2

- Remove redundant NULL terminators from disassembler register arrays
- Change disassembler register name arrays to const
- Refine disassembler internal function names
- Update dates in disassembler copyright message
- Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work
- Use ULL suffix on 64-bit constants
- Move riscv_cpu_mmu_index from cpu.h to helper.c
- Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c
- Remove redundant TARGET_HAS_ICE from cpu.h
- Use qemu_irq instead of void* for irq definition in cpu.h
- Remove duplicate typedef from struct CPURISCVState
- Remove redundant g_strdup from cpu_register
- Remove redundant tlb_flush from riscv_cpu_reset
- Remove redundant mode calculation from get_physical_address
- Remove redundant debug mode printf and dcsr comment
- Remove redundant clearing of MSB for bare physical addresses
- Use g_assert_not_reached for invalid mode in get_physical_address
- Use g_assert_not_reached for unreachable checks in get_physical_address
- Use g_assert_not_reached for unreachable type in raise_mmu_exception
- Return exception instead of aborting for misaligned fetches
- Move exception defines from cpu.h to cpu_bits.h
- Remove redundant breakpoint control definitions from cpu_bits.h
- Implement riscv_cpu_unassigned_access exception handling
- Log and raise exceptions for unimplemented CSRs
- Match Spike HTIF exit behavior - don’t print TEST-PASSED
- Make frm,fflags,fcsr writes trap when mstatus.FS is clear
- Use g_assert_not_reached for unreachable invalid mode
- Make hret,uret,dret generate illegal instructions
- Move riscv_cpu_dump_state and int/fpr regnames to cpu.c
- Lift interrupt flag and mask into constants in cpu_bits.h
- Change trap debugging to use qemu_log_mask LOG_TRACE 
- Change CSR debugging to use qemu_log_mask LOG_TRACE
- Change PMP debugging to use qemu_log_mask LOG_TRACE
- Remove commented code from pmp.c
- Change CpuInfoRISCV qapi schema docs to Since 2.12
- Change RV feature macro to use target_ulong cast
- Remove riscv_feature and instead use misa extension flags
- Make riscv_flush_icache_syscall a no-op
- Undo checkpatch whitespace fixes in unrelated linux-user code
- Remove redudant constants and tidy up cpu_bits.h
- Make helper_fence_i a no-op
- Move include "exec/cpu-all" to end of cpu.h
- Rename set_privilege to riscv_set_mode
- Move redundant forward declaration for cpu_riscv_translate_address
- Remove TCGV_UNUSED from riscv_translate_init
- Add comment to pmp.c stating the code is untested and currently unused
- Use ctz to simplify decoding of PMP NAPOT address ranges
- Change pmp_is_in_range to use than equal for end addresses
- Fix off by one error in pmp_update_rule
- Rearrange PMP_DEBUG so that formatting is compile-time checked
- Rearrange trap debugging so that formatting is compile-time checked
- Rearrange PLIC debugging so that formatting is compile-time checked
- Use qemu_log/qemu_log_mask for HTIF logging and debugging
- Move exception and interrupt names into cpu.c
- Add Palmer Dabbelt as a RISC-V Maintainer
- Rebase against current qemu master branch

v1

- initial version based on forward port from riscv-qemu repository

*** Background ***

"RISC-V is an open, free ISA enabling a new era of processor innovation
through open standard collaboration. Born in academia and research,
RISC-V ISA delivers a new level of free, extensible software and
hardware freedom on architecture, paving the way for the next 50 years
of computing design and innovation."

The QEMU RISC-V port has been developed and maintained out-of-tree for
several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V
Privileged specification has evolved substantially over this period but
has recently been solidifying. The RISC-V Base ISA has been frozon for
some time and the Privileged ISA, GCC toolchain and Linux ABI are now
quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU
Maintainer and hope to support upstreaming the port. 

There are multiple vendors taping out, preparing to ship, or shipping
silicon that implements the RISC-V Privileged ISA Version 1.10. There
are also several RISC-V Soft-IP cores implementing Privileged ISA
Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform
and the U54‑MC RISC-V Core IP, among many more implementations from a
variety of vendors. See https://riscv.org/ for more details.

RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first
half of 2016. RISC-V support is now available in LLVM top-of-tree and
the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year
and is available in the Linux 4.15 release. GLIBC 2.27 added support
for the RISC-V ISA running on Linux (requires at least binutils-2.30,
gcc-7.3.0, and linux-4.15). We believe it is timely to submit the
RISC-V QEMU port for upstream review with the goal of incorporating
RISC-V support into the upcoming QEMU 2.12 release.

The RISC-V QEMU port is still under active development, mostly with
respect to device emulation, the addition of Hypervisor support as
specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector
support once the first draft is finalized later this year. We believe
now is the appropriate time for RISC-V QEMU development to be carried
out in the main QEMU repository as the code will benefit from more
rigorous review. The RISC-V QEMU port currently supports all the ISA
extensions that have been finalized and frozen in the Base ISA.

Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk

The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki

Instructions for building a busybox+dropbear root image, BBL (Berkeley
Boot Loader) and linux kernel image for use with the RISC-V QEMU
'virt' machine: https://github.com/michaeljclark/busybear-linux

*** Overview ***

The RISC-V QEMU port implements the following specifications:

- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

The RISC-V QEMU port supports the following instruction set extensions:

- RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
- RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)

The RISC-V QEMU port adds the following targets to QEMU:

- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user

The RISC-V QEMU port supports the following hardware:

- HTIF Console (Host Target Interface)
- SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
- SiFive PLIC (Platform Level Interrupt Controller)
- SiFive Test (Test Finisher) for exiting simulation
- SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
- VirtIO MMIO (GPEX PCI support will be added in a future patch)
- Generic 16550A UART emulation using 'hw/char/serial.c'
- Experimental SMP support (PLIC and CLINT) on the 'virt' machine

The RISC-V QEMU full system emulator supports 5 machines:

- 'spike_v1.9';  CLINT, PLIC, HTIF console, config-string, Priv v1.9.1
- 'spike_v1.10'; CLINT, PLIC, HTIF console, device-tree, Priv v1.10
- 'sifive_e300'; CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10
- 'sifive_u500'; CLINT, PLIC, SiFive UART, device-tree, Priv v1.10
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10

This is a list of RISC-V QEMU Port Contributors:

- Alex Suykov
- Andreas Schwab
- Antony Pavlov
- Bastian Koppelmann
- Bruce Hoult
- Chih-Min Chao
- Daire McNamara
- Darius Rad
- David Abdurachmanov
- Ivan Griffin
- Jim Wilson
- Kito Cheng
- Michael Clark
- Palmer Dabbelt
- Richard Henderon
- Sagar Karandikar
- Stefan O'Rear

Notes:

- contributor email addresses available off-list on request.
- checkpatch has been run on all 22 patches.
- checkpatch exceptions are noted in 2 patches that have errors.
- tested linux on 'spike_v1.9', 'spike_v1.10' and 'virt' machines
- passes "make check" on full build for all targets

This patch series includes the following patches:

Michael Clark (23):
  RISC-V Maintainers
  RISC-V ELF Machine Definition
  RISC-V CPU Core Definition
  RISC-V Disassembler
  RISC-V CPU Helpers
  Softfloat support for IEEE 754-201x minimumNumber/maximumNumber
  RISC-V FPU Support
  RISC-V GDB Stub
  RISC-V TCG Code Generation
  RISC-V Physical Memory Protection
  RISC-V Linux User Emulation
  RISC-V HTIF Console
  RISC-V HART Array
  SiFive RISC-V CLINT Block
  SiFive RISC-V PLIC Block
  RISC-V Spike Machines
  RISC-V VirtIO Machine
  SiFive RISC-V UART Device
  SiFive RISC-V PRCI Block
  SiFive RISC-V Test Finisher
  SiFive Freedom E300 RISC-V Machine
  SiFive Freedom U500 RISC-V Machine
  RISC-V Build Infrastructure

 MAINTAINERS                            |   11 +
 Makefile.objs                          |    1 +
 arch_init.c                            |    2 +
 configure                              |   11 +
 cpus.c                                 |    6 +
 default-configs/riscv32-linux-user.mak |    1 +
 default-configs/riscv32-softmmu.mak    |    4 +
 default-configs/riscv64-linux-user.mak |    1 +
 default-configs/riscv64-softmmu.mak    |    4 +
 disas.c                                |    2 +
 disas/Makefile.objs                    |    1 +
 disas/riscv.c                          | 3054 ++++++++++++++++++++++++++++++++
 fpu/softfloat-specialize.h             |    7 +-
 fpu/softfloat.c                        |   41 +-
 hw/riscv/Makefile.objs                 |   13 +
 hw/riscv/riscv_elf.c                   |  244 +++
 hw/riscv/riscv_hart.c                  |   95 +
 hw/riscv/riscv_htif.c                  |  373 ++++
 hw/riscv/sifive_clint.c                |  312 ++++
 hw/riscv/sifive_e300.c                 |  232 +++
 hw/riscv/sifive_plic.c                 |  554 ++++++
 hw/riscv/sifive_prci.c                 |   95 +
 hw/riscv/sifive_test.c                 |   99 ++
 hw/riscv/sifive_u500.c                 |  338 ++++
 hw/riscv/sifive_uart.c                 |  182 ++
 hw/riscv/spike_v1_09.c                 |  204 +++
 hw/riscv/spike_v1_10.c                 |  278 +++
 hw/riscv/virt.c                        |  375 ++++
 include/disas/bfd.h                    |    2 +
 include/elf.h                          |    2 +
 include/fpu/softfloat.h                |    4 +
 include/hw/riscv/riscv_elf.h           |   69 +
 include/hw/riscv/riscv_hart.h          |   45 +
 include/hw/riscv/riscv_htif.h          |   62 +
 include/hw/riscv/sifive_clint.h        |   56 +
 include/hw/riscv/sifive_e300.h         |   79 +
 include/hw/riscv/sifive_plic.h         |   91 +
 include/hw/riscv/sifive_prci.h         |   43 +
 include/hw/riscv/sifive_test.h         |   48 +
 include/hw/riscv/sifive_u500.h         |   69 +
 include/hw/riscv/sifive_uart.h         |   76 +
 include/hw/riscv/spike.h               |   51 +
 include/hw/riscv/virt.h                |   74 +
 include/sysemu/arch_init.h             |    1 +
 linux-user/elfload.c                   |   22 +
 linux-user/main.c                      |   97 +
 linux-user/riscv/syscall_nr.h          |  287 +++
 linux-user/riscv/target_cpu.h          |   18 +
 linux-user/riscv/target_signal.h       |   23 +
 linux-user/riscv/target_structs.h      |   46 +
 linux-user/riscv/target_syscall.h      |   56 +
 linux-user/riscv/termbits.h            |  220 +++
 linux-user/signal.c                    |  203 ++-
 linux-user/syscall.c                   |    2 +
 linux-user/syscall_defs.h              |   13 +-
 qapi-schema.json                       |   16 +-
 scripts/qemu-binfmt-conf.sh            |   13 +-
 target/riscv/Makefile.objs             |    1 +
 target/riscv/cpu.c                     |  385 ++++
 target/riscv/cpu.h                     |  256 +++
 target/riscv/cpu_bits.h                |  417 +++++
 target/riscv/cpu_user.h                |   16 +
 target/riscv/fpu_helper.c              |  375 ++++
 target/riscv/gdbstub.c                 |   60 +
 target/riscv/helper.c                  |  464 +++++
 target/riscv/helper.h                  |   78 +
 target/riscv/instmap.h                 |  366 ++++
 target/riscv/op_helper.c               |  644 +++++++
 target/riscv/pmp.c                     |  386 ++++
 target/riscv/pmp.h                     |   70 +
 target/riscv/trace-events              |    1 +
 target/riscv/translate.c               | 1970 ++++++++++++++++++++
 72 files changed, 13800 insertions(+), 17 deletions(-)
 create mode 100644 default-configs/riscv32-linux-user.mak
 create mode 100644 default-configs/riscv32-softmmu.mak
 create mode 100644 default-configs/riscv64-linux-user.mak
 create mode 100644 default-configs/riscv64-softmmu.mak
 create mode 100644 disas/riscv.c
 create mode 100644 hw/riscv/Makefile.objs
 create mode 100644 hw/riscv/riscv_elf.c
 create mode 100644 hw/riscv/riscv_hart.c
 create mode 100644 hw/riscv/riscv_htif.c
 create mode 100644 hw/riscv/sifive_clint.c
 create mode 100644 hw/riscv/sifive_e300.c
 create mode 100644 hw/riscv/sifive_plic.c
 create mode 100644 hw/riscv/sifive_prci.c
 create mode 100644 hw/riscv/sifive_test.c
 create mode 100644 hw/riscv/sifive_u500.c
 create mode 100644 hw/riscv/sifive_uart.c
 create mode 100644 hw/riscv/spike_v1_09.c
 create mode 100644 hw/riscv/spike_v1_10.c
 create mode 100644 hw/riscv/virt.c
 create mode 100644 include/hw/riscv/riscv_elf.h
 create mode 100644 include/hw/riscv/riscv_hart.h
 create mode 100644 include/hw/riscv/riscv_htif.h
 create mode 100644 include/hw/riscv/sifive_clint.h
 create mode 100644 include/hw/riscv/sifive_e300.h
 create mode 100644 include/hw/riscv/sifive_plic.h
 create mode 100644 include/hw/riscv/sifive_prci.h
 create mode 100644 include/hw/riscv/sifive_test.h
 create mode 100644 include/hw/riscv/sifive_u500.h
 create mode 100644 include/hw/riscv/sifive_uart.h
 create mode 100644 include/hw/riscv/spike.h
 create mode 100644 include/hw/riscv/virt.h
 create mode 100644 linux-user/riscv/syscall_nr.h
 create mode 100644 linux-user/riscv/target_cpu.h
 create mode 100644 linux-user/riscv/target_signal.h
 create mode 100644 linux-user/riscv/target_structs.h
 create mode 100644 linux-user/riscv/target_syscall.h
 create mode 100644 linux-user/riscv/termbits.h
 create mode 100644 target/riscv/Makefile.objs
 create mode 100644 target/riscv/cpu.c
 create mode 100644 target/riscv/cpu.h
 create mode 100644 target/riscv/cpu_bits.h
 create mode 100644 target/riscv/cpu_user.h
 create mode 100644 target/riscv/fpu_helper.c
 create mode 100644 target/riscv/gdbstub.c
 create mode 100644 target/riscv/helper.c
 create mode 100644 target/riscv/helper.h
 create mode 100644 target/riscv/instmap.h
 create mode 100644 target/riscv/op_helper.c
 create mode 100644 target/riscv/pmp.c
 create mode 100644 target/riscv/pmp.h
 create mode 100644 target/riscv/trace-events
 create mode 100644 target/riscv/translate.c

-- 
2.7.0

We are now passing all but one of the set of tests cases in riscv-tests.
The one failing set of tests relates to support for "9.2 NaN Boxing of
Narrower Values" as per the RISC-V ISA Specification v2.2. The remaining
case is where we try to use a single-precision operation on an input that
doesn't have bits 63:32 all 1s, the input is treated as if it were a quiet
NaN, rather than as the embedded single, as using a wider value (i.e.
double) as an input to a single precision operation is defined to be NaN.
The NaN Boxing of Narrower Values was added to the specification to specify
the binary format for single precision values in memory
when fsd/fld (load/store double fp value) is used to save/restore them.
Indeed, the mechanism is generic and is designed to also handle boxing of
singles and doubles within quad precision floating point values. The
implication of supporting NaN Boxing completely (i.e. 100% test passing)
will require tests for canonical NaN-boxing in all single precision
floating point operations, and it may be worthwhile having a switch for
compliance vs performance?

QEMU=./riscv64-softmmu/qemu-system-riscv64
ALL_TESTS=$(find ../riscv-tools/riscv-tests/build/isa -name 'rv64*-v-*' -a
! -name '*.dump'  | sort)

for i in ${ALL_TESTS}; do
        test=$(basename $i)
        echo ${test}
        ${QEMU} -nographic -machine spike_v1.10 -kernel $i
done

rv64ua-v-amoadd_d
rv64ua-v-amoadd_w
rv64ua-v-amoand_d
rv64ua-v-amoand_w
rv64ua-v-amomax_d
rv64ua-v-amomax_w
rv64ua-v-amomaxu_d
rv64ua-v-amomaxu_w
rv64ua-v-amomin_d
rv64ua-v-amomin_w
rv64ua-v-amominu_d
rv64ua-v-amominu_w
rv64ua-v-amoor_d
rv64ua-v-amoor_w
rv64ua-v-amoswap_d
rv64ua-v-amoswap_w
rv64ua-v-amoxor_d
rv64ua-v-amoxor_w
rv64ua-v-lrsc
rv64uc-v-rvc
rv64ud-v-fadd
rv64ud-v-fclass
rv64ud-v-fcmp
rv64ud-v-fcvt
rv64ud-v-fcvt_w
rv64ud-v-fdiv
rv64ud-v-fmadd
rv64ud-v-fmin
rv64ud-v-ldst
rv64ud-v-move
*** FAILED *** (tohost = 40)
rv64ud-v-recoding
rv64ud-v-structural
rv64uf-v-fadd
rv64uf-v-fclass
rv64uf-v-fcmp
rv64uf-v-fcvt
rv64uf-v-fcvt_w
rv64uf-v-fdiv
rv64uf-v-fmadd
rv64uf-v-fmin
rv64uf-v-ldst
rv64uf-v-move
rv64uf-v-recoding
rv64ui-v-add
rv64ui-v-addi
rv64ui-v-addiw
rv64ui-v-addw
rv64ui-v-and
rv64ui-v-andi
rv64ui-v-auipc
rv64ui-v-beq
rv64ui-v-bge
rv64ui-v-bgeu
rv64ui-v-blt
rv64ui-v-bltu
rv64ui-v-bne
rv64ui-v-fence_i
rv64ui-v-jal
rv64ui-v-jalr
rv64ui-v-lb
rv64ui-v-lbu
rv64ui-v-ld
rv64ui-v-lh
rv64ui-v-lhu
rv64ui-v-lui
rv64ui-v-lw
rv64ui-v-lwu
rv64ui-v-or
rv64ui-v-ori
rv64ui-v-sb
rv64ui-v-sd
rv64ui-v-sh
rv64ui-v-simple
rv64ui-v-sll
rv64ui-v-slli
rv64ui-v-slliw
rv64ui-v-sllw
rv64ui-v-slt
rv64ui-v-slti
rv64ui-v-sltiu
rv64ui-v-sltu
rv64ui-v-sra
rv64ui-v-srai
rv64ui-v-sraiw
rv64ui-v-sraw
rv64ui-v-srl
rv64ui-v-srli
rv64ui-v-srliw
rv64ui-v-srlw
rv64ui-v-sub
rv64ui-v-subw
rv64ui-v-sw
rv64ui-v-xor
rv64ui-v-xori
rv64um-v-div
rv64um-v-divu
rv64um-v-divuw
rv64um-v-divw
rv64um-v-mul
rv64um-v-mulh
rv64um-v-mulhsu
rv64um-v-mulhu
rv64um-v-mulw
rv64um-v-rem
rv64um-v-remu
rv64um-v-remuw
rv64um-v-remw


On Thu, Feb 8, 2018 at 2:28 PM, Michael Clark <mjc@sifive.com> wrote:

> QEMU RISC-V Emulation Support (RV64GC, RV32GC)
>
> This version of the RISC-V patch series "lucky number five" contains
> cleanups to the FPU code, fixes several FPU related test failures in
> riscv-tests and updates the syscalls for RISC-V linux-user emulation.
>
> The git tree for this v5 patch series (squashed and rebased):
>
> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v5
>
> The git tree for the v1-v4 patch series with review commit history:
>
> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v4
> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v3
> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v2
> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v1
>
> *** Known Issues ***
>
> - FPU code needs further work to handle NaN-Boxing of Narrower Values
> - Disassembler has some checkpatch warnings for the sake of code brevity
> - scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
> - PMP (Physical Memory Protection) is as-of-yet unused and needs testing
>
> *** Changelog ***
>
> v5
>
> - Fixed 4 test failures in riscv-tests, only one set to go...
> - Use float_muladd_negate_* flags to floatXX_muladd
> - Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
> - Fix TARGET_NR_syscalls
> - Update linux-user/riscv/syscall_nr.h
> - Fix FENCE.I, needs to terminate translation block
> - Adjust unusual convention for interruptno >= 0
>
> v4
>
> - Add @riscv: since 2.12 to CpuInfoArch
> - Remove misleading little-endian comment from load_kernel
> - Rename cpu-model property to cpu-type
> - Drop some unnecessary inline function attributes
> - Don't allow GDB to set value of x0 register
> - Remove unnecessary empty property lists
> - Add Test Finisher device to implement poweroff in virt machine
> - Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior
> - Store fflags data in fp_status
> - Purge runtime users of helper_raise_exception
> - Fix validate_csr
> - Tidy gen_jalr
> - Tidy immediate shifts
> - Add gen_exception_inst_addr_mis
> - Add gen_exception_debug
> - Add gen_exception_illegal
> - Tidy helper_fclass_*
> - Split rounding mode setting to a new function
> - Enforce MSTATUS_FS via TB flags
> - Implement acquire/release barrier semantics
> - Use atomic operations as required
> - Fix FENCE and FENCE_I
> - Remove commented code from spike machines
> - PAGE_WRITE permissions can be set on loads if page is already dirty
> - The result of format conversion on an NaN must be a quiet NaN
> - Add missing process_queued_cpu_work to riscv linux-user
> - Remove float(32|64)_classify from cpu.h
> - Removed nonsensical unions aliasing the same type
> - Use uintN_t instead of uintN_fast_t in fpu_helper.c
> - Use macros for FPU exception values in softfloat_flags_to_riscv
> - Move code to set round mode into set_fp_round_mode function
> - Convert set_fp_exceptions from a macro to an inline function
> - Convert round mode helper into an inline function
> - Make fpu_helper ieee_rm array static const
> - Include cpu_mmu_index in cpu_get_tb_cpu_state flags
> - Eliminate MPRV influence on mmu_index
> - Remove unrecoverable do_unassigned_access function
> - Only update PTE accessed and dirty bits if necessary
> - Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx
> - Remove buggy support for misa writes. misa writes are optional
>   and are not implemented in any known hardware
> - Always set PTE read or execute permissions during page walk
> - Reorder helper function declarations to match order in helper.c
> - Remove redundant variable declaration in get_physical_address
> - Remove duplicated code from get_physical_address
> - Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug
>
> v3
>
> - Fix indentation in PMP and HTIF debug macros
> - Fix disassembler checkpatch open brace '{' on next line errors
> - Fix trailing statements on next line in decode_inst_decompress
> - NOTE: the other checkpatch issues have been reviewed previously
>
> v2
>
> - Remove redundant NULL terminators from disassembler register arrays
> - Change disassembler register name arrays to const
> - Refine disassembler internal function names
> - Update dates in disassembler copyright message
> - Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work
> - Use ULL suffix on 64-bit constants
> - Move riscv_cpu_mmu_index from cpu.h to helper.c
> - Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c
> - Remove redundant TARGET_HAS_ICE from cpu.h
> - Use qemu_irq instead of void* for irq definition in cpu.h
> - Remove duplicate typedef from struct CPURISCVState
> - Remove redundant g_strdup from cpu_register
> - Remove redundant tlb_flush from riscv_cpu_reset
> - Remove redundant mode calculation from get_physical_address
> - Remove redundant debug mode printf and dcsr comment
> - Remove redundant clearing of MSB for bare physical addresses
> - Use g_assert_not_reached for invalid mode in get_physical_address
> - Use g_assert_not_reached for unreachable checks in get_physical_address
> - Use g_assert_not_reached for unreachable type in raise_mmu_exception
> - Return exception instead of aborting for misaligned fetches
> - Move exception defines from cpu.h to cpu_bits.h
> - Remove redundant breakpoint control definitions from cpu_bits.h
> - Implement riscv_cpu_unassigned_access exception handling
> - Log and raise exceptions for unimplemented CSRs
> - Match Spike HTIF exit behavior - don’t print TEST-PASSED
> - Make frm,fflags,fcsr writes trap when mstatus.FS is clear
> - Use g_assert_not_reached for unreachable invalid mode
> - Make hret,uret,dret generate illegal instructions
> - Move riscv_cpu_dump_state and int/fpr regnames to cpu.c
> - Lift interrupt flag and mask into constants in cpu_bits.h
> - Change trap debugging to use qemu_log_mask LOG_TRACE
> - Change CSR debugging to use qemu_log_mask LOG_TRACE
> - Change PMP debugging to use qemu_log_mask LOG_TRACE
> - Remove commented code from pmp.c
> - Change CpuInfoRISCV qapi schema docs to Since 2.12
> - Change RV feature macro to use target_ulong cast
> - Remove riscv_feature and instead use misa extension flags
> - Make riscv_flush_icache_syscall a no-op
> - Undo checkpatch whitespace fixes in unrelated linux-user code
> - Remove redudant constants and tidy up cpu_bits.h
> - Make helper_fence_i a no-op
> - Move include "exec/cpu-all" to end of cpu.h
> - Rename set_privilege to riscv_set_mode
> - Move redundant forward declaration for cpu_riscv_translate_address
> - Remove TCGV_UNUSED from riscv_translate_init
> - Add comment to pmp.c stating the code is untested and currently unused
> - Use ctz to simplify decoding of PMP NAPOT address ranges
> - Change pmp_is_in_range to use than equal for end addresses
> - Fix off by one error in pmp_update_rule
> - Rearrange PMP_DEBUG so that formatting is compile-time checked
> - Rearrange trap debugging so that formatting is compile-time checked
> - Rearrange PLIC debugging so that formatting is compile-time checked
> - Use qemu_log/qemu_log_mask for HTIF logging and debugging
> - Move exception and interrupt names into cpu.c
> - Add Palmer Dabbelt as a RISC-V Maintainer
> - Rebase against current qemu master branch
>
> v1
>
> - initial version based on forward port from riscv-qemu repository
>
> *** Background ***
>
> "RISC-V is an open, free ISA enabling a new era of processor innovation
> through open standard collaboration. Born in academia and research,
> RISC-V ISA delivers a new level of free, extensible software and
> hardware freedom on architecture, paving the way for the next 50 years
> of computing design and innovation."
>
> The QEMU RISC-V port has been developed and maintained out-of-tree for
> several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V
> Privileged specification has evolved substantially over this period but
> has recently been solidifying. The RISC-V Base ISA has been frozon for
> some time and the Privileged ISA, GCC toolchain and Linux ABI are now
> quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU
> Maintainer and hope to support upstreaming the port.
>
> There are multiple vendors taping out, preparing to ship, or shipping
> silicon that implements the RISC-V Privileged ISA Version 1.10. There
> are also several RISC-V Soft-IP cores implementing Privileged ISA
> Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform
> and the U54‑MC RISC-V Core IP, among many more implementations from a
> variety of vendors. See https://riscv.org/ for more details.
>
> RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first
> half of 2016. RISC-V support is now available in LLVM top-of-tree and
> the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year
> and is available in the Linux 4.15 release. GLIBC 2.27 added support
> for the RISC-V ISA running on Linux (requires at least binutils-2.30,
> gcc-7.3.0, and linux-4.15). We believe it is timely to submit the
> RISC-V QEMU port for upstream review with the goal of incorporating
> RISC-V support into the upcoming QEMU 2.12 release.
>
> The RISC-V QEMU port is still under active development, mostly with
> respect to device emulation, the addition of Hypervisor support as
> specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector
> support once the first draft is finalized later this year. We believe
> now is the appropriate time for RISC-V QEMU development to be carried
> out in the main QEMU repository as the code will benefit from more
> rigorous review. The RISC-V QEMU port currently supports all the ISA
> extensions that have been finalized and frozen in the Base ISA.
>
> Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk
>
> The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki
>
> Instructions for building a busybox+dropbear root image, BBL (Berkeley
> Boot Loader) and linux kernel image for use with the RISC-V QEMU
> 'virt' machine: https://github.com/michaeljclark/busybear-linux
>
> *** Overview ***
>
> The RISC-V QEMU port implements the following specifications:
>
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>
> The RISC-V QEMU port supports the following instruction set extensions:
>
> - RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
> - RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)
>
> The RISC-V QEMU port adds the following targets to QEMU:
>
> - riscv32-softmmu
> - riscv64-softmmu
> - riscv32-linux-user
> - riscv64-linux-user
>
> The RISC-V QEMU port supports the following hardware:
>
> - HTIF Console (Host Target Interface)
> - SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
> - SiFive PLIC (Platform Level Interrupt Controller)
> - SiFive Test (Test Finisher) for exiting simulation
> - SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
> - VirtIO MMIO (GPEX PCI support will be added in a future patch)
> - Generic 16550A UART emulation using 'hw/char/serial.c'
> - Experimental SMP support (PLIC and CLINT) on the 'virt' machine
>
> The RISC-V QEMU full system emulator supports 5 machines:
>
> - 'spike_v1.9';  CLINT, PLIC, HTIF console, config-string, Priv v1.9.1
> - 'spike_v1.10'; CLINT, PLIC, HTIF console, device-tree, Priv v1.10
> - 'sifive_e300'; CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10
> - 'sifive_u500'; CLINT, PLIC, SiFive UART, device-tree, Priv v1.10
> - 'virt'; CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10
>
> This is a list of RISC-V QEMU Port Contributors:
>
> - Alex Suykov
> - Andreas Schwab
> - Antony Pavlov
> - Bastian Koppelmann
> - Bruce Hoult
> - Chih-Min Chao
> - Daire McNamara
> - Darius Rad
> - David Abdurachmanov
> - Ivan Griffin
> - Jim Wilson
> - Kito Cheng
> - Michael Clark
> - Palmer Dabbelt
> - Richard Henderon
> - Sagar Karandikar
> - Stefan O'Rear
>
> Notes:
>
> - contributor email addresses available off-list on request.
> - checkpatch has been run on all 22 patches.
> - checkpatch exceptions are noted in 2 patches that have errors.
> - tested linux on 'spike_v1.9', 'spike_v1.10' and 'virt' machines
> - passes "make check" on full build for all targets
>
> This patch series includes the following patches:
>
> Michael Clark (23):
>   RISC-V Maintainers
>   RISC-V ELF Machine Definition
>   RISC-V CPU Core Definition
>   RISC-V Disassembler
>   RISC-V CPU Helpers
>   Softfloat support for IEEE 754-201x minimumNumber/maximumNumber
>   RISC-V FPU Support
>   RISC-V GDB Stub
>   RISC-V TCG Code Generation
>   RISC-V Physical Memory Protection
>   RISC-V Linux User Emulation
>   RISC-V HTIF Console
>   RISC-V HART Array
>   SiFive RISC-V CLINT Block
>   SiFive RISC-V PLIC Block
>   RISC-V Spike Machines
>   RISC-V VirtIO Machine
>   SiFive RISC-V UART Device
>   SiFive RISC-V PRCI Block
>   SiFive RISC-V Test Finisher
>   SiFive Freedom E300 RISC-V Machine
>   SiFive Freedom U500 RISC-V Machine
>   RISC-V Build Infrastructure
>
>  MAINTAINERS                            |   11 +
>  Makefile.objs                          |    1 +
>  arch_init.c                            |    2 +
>  configure                              |   11 +
>  cpus.c                                 |    6 +
>  default-configs/riscv32-linux-user.mak |    1 +
>  default-configs/riscv32-softmmu.mak    |    4 +
>  default-configs/riscv64-linux-user.mak |    1 +
>  default-configs/riscv64-softmmu.mak    |    4 +
>  disas.c                                |    2 +
>  disas/Makefile.objs                    |    1 +
>  disas/riscv.c                          | 3054
> ++++++++++++++++++++++++++++++++
>  fpu/softfloat-specialize.h             |    7 +-
>  fpu/softfloat.c                        |   41 +-
>  hw/riscv/Makefile.objs                 |   13 +
>  hw/riscv/riscv_elf.c                   |  244 +++
>  hw/riscv/riscv_hart.c                  |   95 +
>  hw/riscv/riscv_htif.c                  |  373 ++++
>  hw/riscv/sifive_clint.c                |  312 ++++
>  hw/riscv/sifive_e300.c                 |  232 +++
>  hw/riscv/sifive_plic.c                 |  554 ++++++
>  hw/riscv/sifive_prci.c                 |   95 +
>  hw/riscv/sifive_test.c                 |   99 ++
>  hw/riscv/sifive_u500.c                 |  338 ++++
>  hw/riscv/sifive_uart.c                 |  182 ++
>  hw/riscv/spike_v1_09.c                 |  204 +++
>  hw/riscv/spike_v1_10.c                 |  278 +++
>  hw/riscv/virt.c                        |  375 ++++
>  include/disas/bfd.h                    |    2 +
>  include/elf.h                          |    2 +
>  include/fpu/softfloat.h                |    4 +
>  include/hw/riscv/riscv_elf.h           |   69 +
>  include/hw/riscv/riscv_hart.h          |   45 +
>  include/hw/riscv/riscv_htif.h          |   62 +
>  include/hw/riscv/sifive_clint.h        |   56 +
>  include/hw/riscv/sifive_e300.h         |   79 +
>  include/hw/riscv/sifive_plic.h         |   91 +
>  include/hw/riscv/sifive_prci.h         |   43 +
>  include/hw/riscv/sifive_test.h         |   48 +
>  include/hw/riscv/sifive_u500.h         |   69 +
>  include/hw/riscv/sifive_uart.h         |   76 +
>  include/hw/riscv/spike.h               |   51 +
>  include/hw/riscv/virt.h                |   74 +
>  include/sysemu/arch_init.h             |    1 +
>  linux-user/elfload.c                   |   22 +
>  linux-user/main.c                      |   97 +
>  linux-user/riscv/syscall_nr.h          |  287 +++
>  linux-user/riscv/target_cpu.h          |   18 +
>  linux-user/riscv/target_signal.h       |   23 +
>  linux-user/riscv/target_structs.h      |   46 +
>  linux-user/riscv/target_syscall.h      |   56 +
>  linux-user/riscv/termbits.h            |  220 +++
>  linux-user/signal.c                    |  203 ++-
>  linux-user/syscall.c                   |    2 +
>  linux-user/syscall_defs.h              |   13 +-
>  qapi-schema.json                       |   16 +-
>  scripts/qemu-binfmt-conf.sh            |   13 +-
>  target/riscv/Makefile.objs             |    1 +
>  target/riscv/cpu.c                     |  385 ++++
>  target/riscv/cpu.h                     |  256 +++
>  target/riscv/cpu_bits.h                |  417 +++++
>  target/riscv/cpu_user.h                |   16 +
>  target/riscv/fpu_helper.c              |  375 ++++
>  target/riscv/gdbstub.c                 |   60 +
>  target/riscv/helper.c                  |  464 +++++
>  target/riscv/helper.h                  |   78 +
>  target/riscv/instmap.h                 |  366 ++++
>  target/riscv/op_helper.c               |  644 +++++++
>  target/riscv/pmp.c                     |  386 ++++
>  target/riscv/pmp.h                     |   70 +
>  target/riscv/trace-events              |    1 +
>  target/riscv/translate.c               | 1970 ++++++++++++++++++++
>  72 files changed, 13800 insertions(+), 17 deletions(-)
>  create mode 100644 default-configs/riscv32-linux-user.mak
>  create mode 100644 default-configs/riscv32-softmmu.mak
>  create mode 100644 default-configs/riscv64-linux-user.mak
>  create mode 100644 default-configs/riscv64-softmmu.mak
>  create mode 100644 disas/riscv.c
>  create mode 100644 hw/riscv/Makefile.objs
>  create mode 100644 hw/riscv/riscv_elf.c
>  create mode 100644 hw/riscv/riscv_hart.c
>  create mode 100644 hw/riscv/riscv_htif.c
>  create mode 100644 hw/riscv/sifive_clint.c
>  create mode 100644 hw/riscv/sifive_e300.c
>  create mode 100644 hw/riscv/sifive_plic.c
>  create mode 100644 hw/riscv/sifive_prci.c
>  create mode 100644 hw/riscv/sifive_test.c
>  create mode 100644 hw/riscv/sifive_u500.c
>  create mode 100644 hw/riscv/sifive_uart.c
>  create mode 100644 hw/riscv/spike_v1_09.c
>  create mode 100644 hw/riscv/spike_v1_10.c
>  create mode 100644 hw/riscv/virt.c
>  create mode 100644 include/hw/riscv/riscv_elf.h
>  create mode 100644 include/hw/riscv/riscv_hart.h
>  create mode 100644 include/hw/riscv/riscv_htif.h
>  create mode 100644 include/hw/riscv/sifive_clint.h
>  create mode 100644 include/hw/riscv/sifive_e300.h
>  create mode 100644 include/hw/riscv/sifive_plic.h
>  create mode 100644 include/hw/riscv/sifive_prci.h
>  create mode 100644 include/hw/riscv/sifive_test.h
>  create mode 100644 include/hw/riscv/sifive_u500.h
>  create mode 100644 include/hw/riscv/sifive_uart.h
>  create mode 100644 include/hw/riscv/spike.h
>  create mode 100644 include/hw/riscv/virt.h
>  create mode 100644 linux-user/riscv/syscall_nr.h
>  create mode 100644 linux-user/riscv/target_cpu.h
>  create mode 100644 linux-user/riscv/target_signal.h
>  create mode 100644 linux-user/riscv/target_structs.h
>  create mode 100644 linux-user/riscv/target_syscall.h
>  create mode 100644 linux-user/riscv/termbits.h
>  create mode 100644 target/riscv/Makefile.objs
>  create mode 100644 target/riscv/cpu.c
>  create mode 100644 target/riscv/cpu.h
>  create mode 100644 target/riscv/cpu_bits.h
>  create mode 100644 target/riscv/cpu_user.h
>  create mode 100644 target/riscv/fpu_helper.c
>  create mode 100644 target/riscv/gdbstub.c
>  create mode 100644 target/riscv/helper.c
>  create mode 100644 target/riscv/helper.h
>  create mode 100644 target/riscv/instmap.h
>  create mode 100644 target/riscv/op_helper.c
>  create mode 100644 target/riscv/pmp.c
>  create mode 100644 target/riscv/pmp.h
>  create mode 100644 target/riscv/trace-events
>  create mode 100644 target/riscv/translate.c
>
> --
> 2.7.0
>
>

To paraphrase; the case we are failing on is a corner case, where a
register containing a double is used as input to a single precision op. It
won't happen in correct code.

On Thu, Feb 8, 2018 at 2:55 PM, Michael Clark <mjc@sifive.com> wrote:

> We are now passing all but one of the set of tests cases in riscv-tests.
> The one failing set of tests relates to support for "9.2 NaN Boxing of
> Narrower Values" as per the RISC-V ISA Specification v2.2. The remaining
> case is where we try to use a single-precision operation on an input that
> doesn't have bits 63:32 all 1s, the input is treated as if it were a quiet
> NaN, rather than as the embedded single, as using a wider value (i.e.
> double) as an input to a single precision operation is defined to be NaN.
> The NaN Boxing of Narrower Values was added to the specification to specify
> the binary format for single precision values in memory
> when fsd/fld (load/store double fp value) is used to save/restore them.
> Indeed, the mechanism is generic and is designed to also handle boxing of
> singles and doubles within quad precision floating point values. The
> implication of supporting NaN Boxing completely (i.e. 100% test passing)
> will require tests for canonical NaN-boxing in all single precision
> floating point operations, and it may be worthwhile having a switch for
> compliance vs performance?
>
> QEMU=./riscv64-softmmu/qemu-system-riscv64
> ALL_TESTS=$(find ../riscv-tools/riscv-tests/build/isa -name 'rv64*-v-*'
> -a ! -name '*.dump'  | sort)
>
> for i in ${ALL_TESTS}; do
>         test=$(basename $i)
>         echo ${test}
>         ${QEMU} -nographic -machine spike_v1.10 -kernel $i
> done
>
> rv64ua-v-amoadd_d
> rv64ua-v-amoadd_w
> rv64ua-v-amoand_d
> rv64ua-v-amoand_w
> rv64ua-v-amomax_d
> rv64ua-v-amomax_w
> rv64ua-v-amomaxu_d
> rv64ua-v-amomaxu_w
> rv64ua-v-amomin_d
> rv64ua-v-amomin_w
> rv64ua-v-amominu_d
> rv64ua-v-amominu_w
> rv64ua-v-amoor_d
> rv64ua-v-amoor_w
> rv64ua-v-amoswap_d
> rv64ua-v-amoswap_w
> rv64ua-v-amoxor_d
> rv64ua-v-amoxor_w
> rv64ua-v-lrsc
> rv64uc-v-rvc
> rv64ud-v-fadd
> rv64ud-v-fclass
> rv64ud-v-fcmp
> rv64ud-v-fcvt
> rv64ud-v-fcvt_w
> rv64ud-v-fdiv
> rv64ud-v-fmadd
> rv64ud-v-fmin
> rv64ud-v-ldst
> rv64ud-v-move
> *** FAILED *** (tohost = 40)
> rv64ud-v-recoding
> rv64ud-v-structural
> rv64uf-v-fadd
> rv64uf-v-fclass
> rv64uf-v-fcmp
> rv64uf-v-fcvt
> rv64uf-v-fcvt_w
> rv64uf-v-fdiv
> rv64uf-v-fmadd
> rv64uf-v-fmin
> rv64uf-v-ldst
> rv64uf-v-move
> rv64uf-v-recoding
> rv64ui-v-add
> rv64ui-v-addi
> rv64ui-v-addiw
> rv64ui-v-addw
> rv64ui-v-and
> rv64ui-v-andi
> rv64ui-v-auipc
> rv64ui-v-beq
> rv64ui-v-bge
> rv64ui-v-bgeu
> rv64ui-v-blt
> rv64ui-v-bltu
> rv64ui-v-bne
> rv64ui-v-fence_i
> rv64ui-v-jal
> rv64ui-v-jalr
> rv64ui-v-lb
> rv64ui-v-lbu
> rv64ui-v-ld
> rv64ui-v-lh
> rv64ui-v-lhu
> rv64ui-v-lui
> rv64ui-v-lw
> rv64ui-v-lwu
> rv64ui-v-or
> rv64ui-v-ori
> rv64ui-v-sb
> rv64ui-v-sd
> rv64ui-v-sh
> rv64ui-v-simple
> rv64ui-v-sll
> rv64ui-v-slli
> rv64ui-v-slliw
> rv64ui-v-sllw
> rv64ui-v-slt
> rv64ui-v-slti
> rv64ui-v-sltiu
> rv64ui-v-sltu
> rv64ui-v-sra
> rv64ui-v-srai
> rv64ui-v-sraiw
> rv64ui-v-sraw
> rv64ui-v-srl
> rv64ui-v-srli
> rv64ui-v-srliw
> rv64ui-v-srlw
> rv64ui-v-sub
> rv64ui-v-subw
> rv64ui-v-sw
> rv64ui-v-xor
> rv64ui-v-xori
> rv64um-v-div
> rv64um-v-divu
> rv64um-v-divuw
> rv64um-v-divw
> rv64um-v-mul
> rv64um-v-mulh
> rv64um-v-mulhsu
> rv64um-v-mulhu
> rv64um-v-mulw
> rv64um-v-rem
> rv64um-v-remu
> rv64um-v-remuw
> rv64um-v-remw
>
>
> On Thu, Feb 8, 2018 at 2:28 PM, Michael Clark <mjc@sifive.com> wrote:
>
>> QEMU RISC-V Emulation Support (RV64GC, RV32GC)
>>
>> This version of the RISC-V patch series "lucky number five" contains
>> cleanups to the FPU code, fixes several FPU related test failures in
>> riscv-tests and updates the syscalls for RISC-V linux-user emulation.
>>
>> The git tree for this v5 patch series (squashed and rebased):
>>
>> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v5
>>
>> The git tree for the v1-v4 patch series with review commit history:
>>
>> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v4
>> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v3
>> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v2
>> - https://github.com/riscv/riscv-qemu/tree/qemu-upstream-v1
>>
>> *** Known Issues ***
>>
>> - FPU code needs further work to handle NaN-Boxing of Narrower Values
>> - Disassembler has some checkpatch warnings for the sake of code brevity
>> - scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
>> - PMP (Physical Memory Protection) is as-of-yet unused and needs testing
>>
>> *** Changelog ***
>>
>> v5
>>
>> - Fixed 4 test failures in riscv-tests, only one set to go...
>> - Use float_muladd_negate_* flags to floatXX_muladd
>> - Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
>> - Fix TARGET_NR_syscalls
>> - Update linux-user/riscv/syscall_nr.h
>> - Fix FENCE.I, needs to terminate translation block
>> - Adjust unusual convention for interruptno >= 0
>>
>> v4
>>
>> - Add @riscv: since 2.12 to CpuInfoArch
>> - Remove misleading little-endian comment from load_kernel
>> - Rename cpu-model property to cpu-type
>> - Drop some unnecessary inline function attributes
>> - Don't allow GDB to set value of x0 register
>> - Remove unnecessary empty property lists
>> - Add Test Finisher device to implement poweroff in virt machine
>> - Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior
>> - Store fflags data in fp_status
>> - Purge runtime users of helper_raise_exception
>> - Fix validate_csr
>> - Tidy gen_jalr
>> - Tidy immediate shifts
>> - Add gen_exception_inst_addr_mis
>> - Add gen_exception_debug
>> - Add gen_exception_illegal
>> - Tidy helper_fclass_*
>> - Split rounding mode setting to a new function
>> - Enforce MSTATUS_FS via TB flags
>> - Implement acquire/release barrier semantics
>> - Use atomic operations as required
>> - Fix FENCE and FENCE_I
>> - Remove commented code from spike machines
>> - PAGE_WRITE permissions can be set on loads if page is already dirty
>> - The result of format conversion on an NaN must be a quiet NaN
>> - Add missing process_queued_cpu_work to riscv linux-user
>> - Remove float(32|64)_classify from cpu.h
>> - Removed nonsensical unions aliasing the same type
>> - Use uintN_t instead of uintN_fast_t in fpu_helper.c
>> - Use macros for FPU exception values in softfloat_flags_to_riscv
>> - Move code to set round mode into set_fp_round_mode function
>> - Convert set_fp_exceptions from a macro to an inline function
>> - Convert round mode helper into an inline function
>> - Make fpu_helper ieee_rm array static const
>> - Include cpu_mmu_index in cpu_get_tb_cpu_state flags
>> - Eliminate MPRV influence on mmu_index
>> - Remove unrecoverable do_unassigned_access function
>> - Only update PTE accessed and dirty bits if necessary
>> - Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx
>> - Remove buggy support for misa writes. misa writes are optional
>>   and are not implemented in any known hardware
>> - Always set PTE read or execute permissions during page walk
>> - Reorder helper function declarations to match order in helper.c
>> - Remove redundant variable declaration in get_physical_address
>> - Remove duplicated code from get_physical_address
>> - Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug
>>
>> v3
>>
>> - Fix indentation in PMP and HTIF debug macros
>> - Fix disassembler checkpatch open brace '{' on next line errors
>> - Fix trailing statements on next line in decode_inst_decompress
>> - NOTE: the other checkpatch issues have been reviewed previously
>>
>> v2
>>
>> - Remove redundant NULL terminators from disassembler register arrays
>> - Change disassembler register name arrays to const
>> - Refine disassembler internal function names
>> - Update dates in disassembler copyright message
>> - Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work
>> - Use ULL suffix on 64-bit constants
>> - Move riscv_cpu_mmu_index from cpu.h to helper.c
>> - Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c
>> - Remove redundant TARGET_HAS_ICE from cpu.h
>> - Use qemu_irq instead of void* for irq definition in cpu.h
>> - Remove duplicate typedef from struct CPURISCVState
>> - Remove redundant g_strdup from cpu_register
>> - Remove redundant tlb_flush from riscv_cpu_reset
>> - Remove redundant mode calculation from get_physical_address
>> - Remove redundant debug mode printf and dcsr comment
>> - Remove redundant clearing of MSB for bare physical addresses
>> - Use g_assert_not_reached for invalid mode in get_physical_address
>> - Use g_assert_not_reached for unreachable checks in get_physical_address
>> - Use g_assert_not_reached for unreachable type in raise_mmu_exception
>> - Return exception instead of aborting for misaligned fetches
>> - Move exception defines from cpu.h to cpu_bits.h
>> - Remove redundant breakpoint control definitions from cpu_bits.h
>> - Implement riscv_cpu_unassigned_access exception handling
>> - Log and raise exceptions for unimplemented CSRs
>> - Match Spike HTIF exit behavior - don’t print TEST-PASSED
>> - Make frm,fflags,fcsr writes trap when mstatus.FS is clear
>> - Use g_assert_not_reached for unreachable invalid mode
>> - Make hret,uret,dret generate illegal instructions
>> - Move riscv_cpu_dump_state and int/fpr regnames to cpu.c
>> - Lift interrupt flag and mask into constants in cpu_bits.h
>> - Change trap debugging to use qemu_log_mask LOG_TRACE
>> - Change CSR debugging to use qemu_log_mask LOG_TRACE
>> - Change PMP debugging to use qemu_log_mask LOG_TRACE
>> - Remove commented code from pmp.c
>> - Change CpuInfoRISCV qapi schema docs to Since 2.12
>> - Change RV feature macro to use target_ulong cast
>> - Remove riscv_feature and instead use misa extension flags
>> - Make riscv_flush_icache_syscall a no-op
>> - Undo checkpatch whitespace fixes in unrelated linux-user code
>> - Remove redudant constants and tidy up cpu_bits.h
>> - Make helper_fence_i a no-op
>> - Move include "exec/cpu-all" to end of cpu.h
>> - Rename set_privilege to riscv_set_mode
>> - Move redundant forward declaration for cpu_riscv_translate_address
>> - Remove TCGV_UNUSED from riscv_translate_init
>> - Add comment to pmp.c stating the code is untested and currently unused
>> - Use ctz to simplify decoding of PMP NAPOT address ranges
>> - Change pmp_is_in_range to use than equal for end addresses
>> - Fix off by one error in pmp_update_rule
>> - Rearrange PMP_DEBUG so that formatting is compile-time checked
>> - Rearrange trap debugging so that formatting is compile-time checked
>> - Rearrange PLIC debugging so that formatting is compile-time checked
>> - Use qemu_log/qemu_log_mask for HTIF logging and debugging
>> - Move exception and interrupt names into cpu.c
>> - Add Palmer Dabbelt as a RISC-V Maintainer
>> - Rebase against current qemu master branch
>>
>> v1
>>
>> - initial version based on forward port from riscv-qemu repository
>>
>> *** Background ***
>>
>> "RISC-V is an open, free ISA enabling a new era of processor innovation
>> through open standard collaboration. Born in academia and research,
>> RISC-V ISA delivers a new level of free, extensible software and
>> hardware freedom on architecture, paving the way for the next 50 years
>> of computing design and innovation."
>>
>> The QEMU RISC-V port has been developed and maintained out-of-tree for
>> several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V
>> Privileged specification has evolved substantially over this period but
>> has recently been solidifying. The RISC-V Base ISA has been frozon for
>> some time and the Privileged ISA, GCC toolchain and Linux ABI are now
>> quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU
>> Maintainer and hope to support upstreaming the port.
>>
>> There are multiple vendors taping out, preparing to ship, or shipping
>> silicon that implements the RISC-V Privileged ISA Version 1.10. There
>> are also several RISC-V Soft-IP cores implementing Privileged ISA
>> Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform
>> and the U54‑MC RISC-V Core IP, among many more implementations from a
>> variety of vendors. See https://riscv.org/ for more details.
>>
>> RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first
>> half of 2016. RISC-V support is now available in LLVM top-of-tree and
>> the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year
>> and is available in the Linux 4.15 release. GLIBC 2.27 added support
>> for the RISC-V ISA running on Linux (requires at least binutils-2.30,
>> gcc-7.3.0, and linux-4.15). We believe it is timely to submit the
>> RISC-V QEMU port for upstream review with the goal of incorporating
>> RISC-V support into the upcoming QEMU 2.12 release.
>>
>> The RISC-V QEMU port is still under active development, mostly with
>> respect to device emulation, the addition of Hypervisor support as
>> specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector
>> support once the first draft is finalized later this year. We believe
>> now is the appropriate time for RISC-V QEMU development to be carried
>> out in the main QEMU repository as the code will benefit from more
>> rigorous review. The RISC-V QEMU port currently supports all the ISA
>> extensions that have been finalized and frozen in the Base ISA.
>>
>> Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk
>>
>> The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki
>>
>> Instructions for building a busybox+dropbear root image, BBL (Berkeley
>> Boot Loader) and linux kernel image for use with the RISC-V QEMU
>> 'virt' machine: https://github.com/michaeljclark/busybear-linux
>>
>> *** Overview ***
>>
>> The RISC-V QEMU port implements the following specifications:
>>
>> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
>> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
>> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>>
>> The RISC-V QEMU port supports the following instruction set extensions:
>>
>> - RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
>> - RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)
>>
>> The RISC-V QEMU port adds the following targets to QEMU:
>>
>> - riscv32-softmmu
>> - riscv64-softmmu
>> - riscv32-linux-user
>> - riscv64-linux-user
>>
>> The RISC-V QEMU port supports the following hardware:
>>
>> - HTIF Console (Host Target Interface)
>> - SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
>> - SiFive PLIC (Platform Level Interrupt Controller)
>> - SiFive Test (Test Finisher) for exiting simulation
>> - SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
>> - VirtIO MMIO (GPEX PCI support will be added in a future patch)
>> - Generic 16550A UART emulation using 'hw/char/serial.c'
>> - Experimental SMP support (PLIC and CLINT) on the 'virt' machine
>>
>> The RISC-V QEMU full system emulator supports 5 machines:
>>
>> - 'spike_v1.9';  CLINT, PLIC, HTIF console, config-string, Priv v1.9.1
>> - 'spike_v1.10'; CLINT, PLIC, HTIF console, device-tree, Priv v1.10
>> - 'sifive_e300'; CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10
>> - 'sifive_u500'; CLINT, PLIC, SiFive UART, device-tree, Priv v1.10
>> - 'virt'; CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10
>>
>> This is a list of RISC-V QEMU Port Contributors:
>>
>> - Alex Suykov
>> - Andreas Schwab
>> - Antony Pavlov
>> - Bastian Koppelmann
>> - Bruce Hoult
>> - Chih-Min Chao
>> - Daire McNamara
>> - Darius Rad
>> - David Abdurachmanov
>> - Ivan Griffin
>> - Jim Wilson
>> - Kito Cheng
>> - Michael Clark
>> - Palmer Dabbelt
>> - Richard Henderon
>> - Sagar Karandikar
>> - Stefan O'Rear
>>
>> Notes:
>>
>> - contributor email addresses available off-list on request.
>> - checkpatch has been run on all 22 patches.
>> - checkpatch exceptions are noted in 2 patches that have errors.
>> - tested linux on 'spike_v1.9', 'spike_v1.10' and 'virt' machines
>> - passes "make check" on full build for all targets
>>
>> This patch series includes the following patches:
>>
>> Michael Clark (23):
>>   RISC-V Maintainers
>>   RISC-V ELF Machine Definition
>>   RISC-V CPU Core Definition
>>   RISC-V Disassembler
>>   RISC-V CPU Helpers
>>   Softfloat support for IEEE 754-201x minimumNumber/maximumNumber
>>   RISC-V FPU Support
>>   RISC-V GDB Stub
>>   RISC-V TCG Code Generation
>>   RISC-V Physical Memory Protection
>>   RISC-V Linux User Emulation
>>   RISC-V HTIF Console
>>   RISC-V HART Array
>>   SiFive RISC-V CLINT Block
>>   SiFive RISC-V PLIC Block
>>   RISC-V Spike Machines
>>   RISC-V VirtIO Machine
>>   SiFive RISC-V UART Device
>>   SiFive RISC-V PRCI Block
>>   SiFive RISC-V Test Finisher
>>   SiFive Freedom E300 RISC-V Machine
>>   SiFive Freedom U500 RISC-V Machine
>>   RISC-V Build Infrastructure
>>
>>  MAINTAINERS                            |   11 +
>>  Makefile.objs                          |    1 +
>>  arch_init.c                            |    2 +
>>  configure                              |   11 +
>>  cpus.c                                 |    6 +
>>  default-configs/riscv32-linux-user.mak |    1 +
>>  default-configs/riscv32-softmmu.mak    |    4 +
>>  default-configs/riscv64-linux-user.mak |    1 +
>>  default-configs/riscv64-softmmu.mak    |    4 +
>>  disas.c                                |    2 +
>>  disas/Makefile.objs                    |    1 +
>>  disas/riscv.c                          | 3054
>> ++++++++++++++++++++++++++++++++
>>  fpu/softfloat-specialize.h             |    7 +-
>>  fpu/softfloat.c                        |   41 +-
>>  hw/riscv/Makefile.objs                 |   13 +
>>  hw/riscv/riscv_elf.c                   |  244 +++
>>  hw/riscv/riscv_hart.c                  |   95 +
>>  hw/riscv/riscv_htif.c                  |  373 ++++
>>  hw/riscv/sifive_clint.c                |  312 ++++
>>  hw/riscv/sifive_e300.c                 |  232 +++
>>  hw/riscv/sifive_plic.c                 |  554 ++++++
>>  hw/riscv/sifive_prci.c                 |   95 +
>>  hw/riscv/sifive_test.c                 |   99 ++
>>  hw/riscv/sifive_u500.c                 |  338 ++++
>>  hw/riscv/sifive_uart.c                 |  182 ++
>>  hw/riscv/spike_v1_09.c                 |  204 +++
>>  hw/riscv/spike_v1_10.c                 |  278 +++
>>  hw/riscv/virt.c                        |  375 ++++
>>  include/disas/bfd.h                    |    2 +
>>  include/elf.h                          |    2 +
>>  include/fpu/softfloat.h                |    4 +
>>  include/hw/riscv/riscv_elf.h           |   69 +
>>  include/hw/riscv/riscv_hart.h          |   45 +
>>  include/hw/riscv/riscv_htif.h          |   62 +
>>  include/hw/riscv/sifive_clint.h        |   56 +
>>  include/hw/riscv/sifive_e300.h         |   79 +
>>  include/hw/riscv/sifive_plic.h         |   91 +
>>  include/hw/riscv/sifive_prci.h         |   43 +
>>  include/hw/riscv/sifive_test.h         |   48 +
>>  include/hw/riscv/sifive_u500.h         |   69 +
>>  include/hw/riscv/sifive_uart.h         |   76 +
>>  include/hw/riscv/spike.h               |   51 +
>>  include/hw/riscv/virt.h                |   74 +
>>  include/sysemu/arch_init.h             |    1 +
>>  linux-user/elfload.c                   |   22 +
>>  linux-user/main.c                      |   97 +
>>  linux-user/riscv/syscall_nr.h          |  287 +++
>>  linux-user/riscv/target_cpu.h          |   18 +
>>  linux-user/riscv/target_signal.h       |   23 +
>>  linux-user/riscv/target_structs.h      |   46 +
>>  linux-user/riscv/target_syscall.h      |   56 +
>>  linux-user/riscv/termbits.h            |  220 +++
>>  linux-user/signal.c                    |  203 ++-
>>  linux-user/syscall.c                   |    2 +
>>  linux-user/syscall_defs.h              |   13 +-
>>  qapi-schema.json                       |   16 +-
>>  scripts/qemu-binfmt-conf.sh            |   13 +-
>>  target/riscv/Makefile.objs             |    1 +
>>  target/riscv/cpu.c                     |  385 ++++
>>  target/riscv/cpu.h                     |  256 +++
>>  target/riscv/cpu_bits.h                |  417 +++++
>>  target/riscv/cpu_user.h                |   16 +
>>  target/riscv/fpu_helper.c              |  375 ++++
>>  target/riscv/gdbstub.c                 |   60 +
>>  target/riscv/helper.c                  |  464 +++++
>>  target/riscv/helper.h                  |   78 +
>>  target/riscv/instmap.h                 |  366 ++++
>>  target/riscv/op_helper.c               |  644 +++++++
>>  target/riscv/pmp.c                     |  386 ++++
>>  target/riscv/pmp.h                     |   70 +
>>  target/riscv/trace-events              |    1 +
>>  target/riscv/translate.c               | 1970 ++++++++++++++++++++
>>  72 files changed, 13800 insertions(+), 17 deletions(-)
>>  create mode 100644 default-configs/riscv32-linux-user.mak
>>  create mode 100644 default-configs/riscv32-softmmu.mak
>>  create mode 100644 default-configs/riscv64-linux-user.mak
>>  create mode 100644 default-configs/riscv64-softmmu.mak
>>  create mode 100644 disas/riscv.c
>>  create mode 100644 hw/riscv/Makefile.objs
>>  create mode 100644 hw/riscv/riscv_elf.c
>>  create mode 100644 hw/riscv/riscv_hart.c
>>  create mode 100644 hw/riscv/riscv_htif.c
>>  create mode 100644 hw/riscv/sifive_clint.c
>>  create mode 100644 hw/riscv/sifive_e300.c
>>  create mode 100644 hw/riscv/sifive_plic.c
>>  create mode 100644 hw/riscv/sifive_prci.c
>>  create mode 100644 hw/riscv/sifive_test.c
>>  create mode 100644 hw/riscv/sifive_u500.c
>>  create mode 100644 hw/riscv/sifive_uart.c
>>  create mode 100644 hw/riscv/spike_v1_09.c
>>  create mode 100644 hw/riscv/spike_v1_10.c
>>  create mode 100644 hw/riscv/virt.c
>>  create mode 100644 include/hw/riscv/riscv_elf.h
>>  create mode 100644 include/hw/riscv/riscv_hart.h
>>  create mode 100644 include/hw/riscv/riscv_htif.h
>>  create mode 100644 include/hw/riscv/sifive_clint.h
>>  create mode 100644 include/hw/riscv/sifive_e300.h
>>  create mode 100644 include/hw/riscv/sifive_plic.h
>>  create mode 100644 include/hw/riscv/sifive_prci.h
>>  create mode 100644 include/hw/riscv/sifive_test.h
>>  create mode 100644 include/hw/riscv/sifive_u500.h
>>  create mode 100644 include/hw/riscv/sifive_uart.h
>>  create mode 100644 include/hw/riscv/spike.h
>>  create mode 100644 include/hw/riscv/virt.h
>>  create mode 100644 linux-user/riscv/syscall_nr.h
>>  create mode 100644 linux-user/riscv/target_cpu.h
>>  create mode 100644 linux-user/riscv/target_signal.h
>>  create mode 100644 linux-user/riscv/target_structs.h
>>  create mode 100644 linux-user/riscv/target_syscall.h
>>  create mode 100644 linux-user/riscv/termbits.h
>>  create mode 100644 target/riscv/Makefile.objs
>>  create mode 100644 target/riscv/cpu.c
>>  create mode 100644 target/riscv/cpu.h
>>  create mode 100644 target/riscv/cpu_bits.h
>>  create mode 100644 target/riscv/cpu_user.h
>>  create mode 100644 target/riscv/fpu_helper.c
>>  create mode 100644 target/riscv/gdbstub.c
>>  create mode 100644 target/riscv/helper.c
>>  create mode 100644 target/riscv/helper.h
>>  create mode 100644 target/riscv/instmap.h
>>  create mode 100644 target/riscv/op_helper.c
>>  create mode 100644 target/riscv/pmp.c
>>  create mode 100644 target/riscv/pmp.h
>>  create mode 100644 target/riscv/trace-events
>>  create mode 100644 target/riscv/translate.c
>>
>> --
>> 2.7.0
>>
>>
>

I just want to mention that we've been running this patch set in
production for a few days, doing hundreds of Fedora RISC-V builds with
‘-smp 4’ and it has been rock solid.

Therefore:

Tested-by: Richard W.M. Jones <rjones@redhat.com>

Rich.

-- 
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-df lists disk usage of guests without needing to install any
software inside the virtual machine.  Supports Linux and Windows.
http://people.redhat.com/~rjones/virt-df/

On 02/07/2018 05:28 PM, Michael Clark wrote:
>  create mode 100644 hw/riscv/Makefile.objs
>  create mode 100644 hw/riscv/riscv_elf.c
>  create mode 100644 hw/riscv/riscv_hart.c
>  create mode 100644 hw/riscv/riscv_htif.c
>  create mode 100644 hw/riscv/sifive_clint.c
>  create mode 100644 hw/riscv/sifive_e300.c
>  create mode 100644 hw/riscv/sifive_plic.c
>  create mode 100644 hw/riscv/sifive_prci.c
>  create mode 100644 hw/riscv/sifive_test.c
>  create mode 100644 hw/riscv/sifive_u500.c
>  create mode 100644 hw/riscv/sifive_uart.c
>  create mode 100644 hw/riscv/spike_v1_09.c
>  create mode 100644 hw/riscv/spike_v1_10.c
>  create mode 100644 hw/riscv/virt.c

I have no plans to review these last 9 patches.
They all look plausible to me, but I'm not so
up-to-date on best practices within hw/.


r~

On Sat, Feb 10, 2018 at 8:42 AM, Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 02/07/2018 05:28 PM, Michael Clark wrote:
> >  create mode 100644 hw/riscv/Makefile.objs
> >  create mode 100644 hw/riscv/riscv_elf.c
> >  create mode 100644 hw/riscv/riscv_hart.c
> >  create mode 100644 hw/riscv/riscv_htif.c
> >  create mode 100644 hw/riscv/sifive_clint.c
> >  create mode 100644 hw/riscv/sifive_e300.c
> >  create mode 100644 hw/riscv/sifive_plic.c
> >  create mode 100644 hw/riscv/sifive_prci.c
> >  create mode 100644 hw/riscv/sifive_test.c
> >  create mode 100644 hw/riscv/sifive_u500.c
> >  create mode 100644 hw/riscv/sifive_uart.c
> >  create mode 100644 hw/riscv/spike_v1_09.c
> >  create mode 100644 hw/riscv/spike_v1_10.c
> >  create mode 100644 hw/riscv/virt.c
>
> I have no plans to review these last 9 patches.
> They all look plausible to me, but I'm not so
> up-to-date on best practices within hw/.
>

No problem. Thanks a lot for your help with reviewing disas, target/riscv
and linux-user. The code is now in much much better shape than it was
before. The patches that have been reviewed represent the bulk of the port
(over ~10K LOC of the ~14K LOC in total). The remaining 11 or so patches
are relatively small in comparison.

We could submit the core of the port which would give us linux-user however
it would be nice to get the spike machines and virt machine upstream. The
spike v1.10 machine is required to run riscv-tests and the virt machine is
being used by linux porters.

BTW Let us know when the softfloat changes have landed. We could
potentially point fmin/fmax at minnum/maxnum in the interim.

In any case, we still have a reasonable amount of time left if we want to
get in to the 2.12 release... I see that March 13th is the soft feature
freeze:

- https://wiki.qemu.org/Planning/2.12

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1518053328-34687-1-git-send-email-mjc@sifive.com
Subject: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/1518053328-34687-1-git-send-email-mjc@sifive.com -> patchew/1518053328-34687-1-git-send-email-mjc@sifive.com
Switched to a new branch 'test'
8022c5a111 RISC-V Build Infrastructure
8b46ed37aa SiFive Freedom U500 RISC-V Machine
1dd26280b0 SiFive Freedom E300 RISC-V Machine
2d431636f4 SiFive RISC-V Test Finisher
03a4df16ad SiFive RISC-V PRCI Block
c0dccdd8ed SiFive RISC-V UART Device
08560578bb RISC-V VirtIO Machine
5b89909e62 RISC-V Spike Machines
cde7fa5ea9 SiFive RISC-V PLIC Block
e400eaefb9 SiFive RISC-V CLINT Block
a430e598f7 RISC-V HART Array
c45a277438 RISC-V HTIF Console
3a0a74d402 RISC-V Linux User Emulation
d78dca19bf RISC-V Physical Memory Protection
ae5027152f RISC-V TCG Code Generation
52ea577b2e RISC-V GDB Stub
2a63a79f26 RISC-V FPU Support
f25138784b Softfloat support for IEEE 754-201x minimumNumber/maximumNumber
2c9b5b7366 RISC-V CPU Helpers
196018aa4c RISC-V Disassembler
899fe05eb7 RISC-V CPU Core Definition
e92dd56c7a RISC-V ELF Machine Definition
e6ed9d413e RISC-V Maintainers

=== OUTPUT BEGIN ===
Checking PATCH 1/23: RISC-V Maintainers...
Checking PATCH 2/23: RISC-V ELF Machine Definition...
Checking PATCH 3/23: RISC-V CPU Core Definition...
Checking PATCH 4/23: RISC-V Disassembler...
WARNING: line over 80 characters
#655: FILE: disas/riscv.c:603:
+static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };

ERROR: line over 90 characters
#656: FILE: disas/riscv.c:604:
+static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };

WARNING: line over 80 characters
#686: FILE: disas/riscv.c:634:
+static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };

WARNING: line over 80 characters
#687: FILE: disas/riscv.c:635:
+static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };

WARNING: line over 80 characters
#688: FILE: disas/riscv.c:636:
+static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };

WARNING: line over 80 characters
#689: FILE: disas/riscv.c:637:
+static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };

ERROR: line over 90 characters
#690: FILE: disas/riscv.c:638:
+static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };

ERROR: line over 90 characters
#691: FILE: disas/riscv.c:639:
+static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };

WARNING: line over 80 characters
#692: FILE: disas/riscv.c:640:
+static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };

ERROR: line over 90 characters
#693: FILE: disas/riscv.c:641:
+static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };

WARNING: line over 80 characters
#694: FILE: disas/riscv.c:642:
+static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };

WARNING: line over 80 characters
#695: FILE: disas/riscv.c:643:
+static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };

WARNING: line over 80 characters
#696: FILE: disas/riscv.c:644:
+static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };

ERROR: line over 90 characters
#1095: FILE: disas/riscv.c:1043:
+    { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },

WARNING: line over 80 characters
#1096: FILE: disas/riscv.c:1044:
+    { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },

WARNING: line over 80 characters
#1097: FILE: disas/riscv.c:1045:
+    { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },

WARNING: line over 80 characters
#1099: FILE: disas/riscv.c:1047:
+    { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },

WARNING: line over 80 characters
#1100: FILE: disas/riscv.c:1048:
+    { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },

WARNING: line over 80 characters
#1102: FILE: disas/riscv.c:1050:
+    { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },

ERROR: line over 90 characters
#1103: FILE: disas/riscv.c:1051:
+    { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },

ERROR: line over 90 characters
#1105: FILE: disas/riscv.c:1053:
+    { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },

ERROR: line over 90 characters
#1106: FILE: disas/riscv.c:1054:
+    { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },

WARNING: line over 80 characters
#1107: FILE: disas/riscv.c:1055:
+    { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui },

ERROR: line over 90 characters
#1108: FILE: disas/riscv.c:1056:
+    { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli },

ERROR: line over 90 characters
#1109: FILE: disas/riscv.c:1057:
+    { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai },

ERROR: line over 90 characters
#1110: FILE: disas/riscv.c:1058:
+    { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi },

WARNING: line over 80 characters
#1111: FILE: disas/riscv.c:1059:
+    { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },

WARNING: line over 80 characters
#1112: FILE: disas/riscv.c:1060:
+    { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },

WARNING: line over 80 characters
#1113: FILE: disas/riscv.c:1061:
+    { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },

WARNING: line over 80 characters
#1114: FILE: disas/riscv.c:1062:
+    { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },

ERROR: line over 90 characters
#1115: FILE: disas/riscv.c:1063:
+    { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },

ERROR: line over 90 characters
#1116: FILE: disas/riscv.c:1064:
+    { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },

WARNING: line over 80 characters
#1117: FILE: disas/riscv.c:1065:
+    { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },

ERROR: line over 90 characters
#1118: FILE: disas/riscv.c:1066:
+    { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },

ERROR: line over 90 characters
#1119: FILE: disas/riscv.c:1067:
+    { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },

ERROR: line over 90 characters
#1120: FILE: disas/riscv.c:1068:
+    { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli },

ERROR: line over 90 characters
#1121: FILE: disas/riscv.c:1069:
+    { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },

ERROR: line over 90 characters
#1122: FILE: disas/riscv.c:1070:
+    { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },

WARNING: line over 80 characters
#1123: FILE: disas/riscv.c:1071:
+    { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },

ERROR: line over 90 characters
#1124: FILE: disas/riscv.c:1072:
+    { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },

ERROR: line over 90 characters
#1125: FILE: disas/riscv.c:1073:
+    { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },

ERROR: line over 90 characters
#1126: FILE: disas/riscv.c:1074:
+    { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },

ERROR: line over 90 characters
#1127: FILE: disas/riscv.c:1075:
+    { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },

WARNING: line over 80 characters
#1128: FILE: disas/riscv.c:1076:
+    { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },

ERROR: line over 90 characters
#1129: FILE: disas/riscv.c:1077:
+    { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },

ERROR: line over 90 characters
#1130: FILE: disas/riscv.c:1078:
+    { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },

WARNING: line over 80 characters
#1131: FILE: disas/riscv.c:1079:
+    { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },

WARNING: line over 80 characters
#1132: FILE: disas/riscv.c:1080:
+    { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },

WARNING: line over 80 characters
#1133: FILE: disas/riscv.c:1081:
+    { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },

WARNING: line over 80 characters
#1134: FILE: disas/riscv.c:1082:
+    { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },

WARNING: line over 80 characters
#1135: FILE: disas/riscv.c:1083:
+    { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },

WARNING: line over 80 characters
#1136: FILE: disas/riscv.c:1084:
+    { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },

WARNING: line over 80 characters
#1140: FILE: disas/riscv.c:1088:
+    { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },

ERROR: trailing statements should be on next line
#1405: FILE: disas/riscv.c:1353:
+        case 0: op = rv_op_c_addi4spn; break;

ERROR: trailing statements should be on next line
#1413: FILE: disas/riscv.c:1361:
+        case 2: op = rv_op_c_lw; break;

ERROR: trailing statements should be on next line
#1428: FILE: disas/riscv.c:1376:
+        case 6: op = rv_op_c_sw; break;

ERROR: trailing statements should be on next line
#1442: FILE: disas/riscv.c:1390:
+            case 0: op = rv_op_c_nop; break;

ERROR: trailing statements should be on next line
#1443: FILE: disas/riscv.c:1391:
+            default: op = rv_op_c_addi; break;

ERROR: trailing statements should be on next line
#1453: FILE: disas/riscv.c:1401:
+        case 2: op = rv_op_c_li; break;

ERROR: trailing statements should be on next line
#1456: FILE: disas/riscv.c:1404:
+            case 2: op = rv_op_c_addi16sp; break;

ERROR: trailing statements should be on next line
#1457: FILE: disas/riscv.c:1405:
+            default: op = rv_op_c_lui; break;

ERROR: trailing statements should be on next line
#1468: FILE: disas/riscv.c:1416:
+            case 2: op = rv_op_c_andi; break;

ERROR: trailing statements should be on next line
#1471: FILE: disas/riscv.c:1419:
+                case 0: op = rv_op_c_sub; break;

ERROR: trailing statements should be on next line
#1472: FILE: disas/riscv.c:1420:
+                case 1: op = rv_op_c_xor; break;

ERROR: trailing statements should be on next line
#1473: FILE: disas/riscv.c:1421:
+                case 2: op = rv_op_c_or; break;

ERROR: trailing statements should be on next line
#1474: FILE: disas/riscv.c:1422:
+                case 3: op = rv_op_c_and; break;

ERROR: trailing statements should be on next line
#1475: FILE: disas/riscv.c:1423:
+                case 4: op = rv_op_c_subw; break;

ERROR: trailing statements should be on next line
#1476: FILE: disas/riscv.c:1424:
+                case 5: op = rv_op_c_addw; break;

ERROR: trailing statements should be on next line
#1481: FILE: disas/riscv.c:1429:
+        case 5: op = rv_op_c_j; break;

ERROR: trailing statements should be on next line
#1482: FILE: disas/riscv.c:1430:
+        case 6: op = rv_op_c_beqz; break;

ERROR: trailing statements should be on next line
#1483: FILE: disas/riscv.c:1431:
+        case 7: op = rv_op_c_bnez; break;

ERROR: trailing statements should be on next line
#1498: FILE: disas/riscv.c:1446:
+        case 2: op = rv_op_c_lwsp; break;

ERROR: trailing statements should be on next line
#1510: FILE: disas/riscv.c:1458:
+                case 0: op = rv_op_c_jr; break;

ERROR: trailing statements should be on next line
#1511: FILE: disas/riscv.c:1459:
+                default: op = rv_op_c_mv; break;

ERROR: trailing statements should be on next line
#1518: FILE: disas/riscv.c:1466:
+                    case 0: op = rv_op_c_ebreak; break;

ERROR: trailing statements should be on next line
#1519: FILE: disas/riscv.c:1467:
+                    default: op = rv_op_c_jalr; break;

ERROR: trailing statements should be on next line
#1522: FILE: disas/riscv.c:1470:
+                default: op = rv_op_c_add; break;

ERROR: trailing statements should be on next line
#1533: FILE: disas/riscv.c:1481:
+        case 6: op = rv_op_c_swsp; break;

ERROR: trailing statements should be on next line
#1547: FILE: disas/riscv.c:1495:
+            case 0: op = rv_op_lb; break;

ERROR: trailing statements should be on next line
#1548: FILE: disas/riscv.c:1496:
+            case 1: op = rv_op_lh; break;

ERROR: trailing statements should be on next line
#1549: FILE: disas/riscv.c:1497:
+            case 2: op = rv_op_lw; break;

ERROR: trailing statements should be on next line
#1550: FILE: disas/riscv.c:1498:
+            case 3: op = rv_op_ld; break;

ERROR: trailing statements should be on next line
#1551: FILE: disas/riscv.c:1499:
+            case 4: op = rv_op_lbu; break;

ERROR: trailing statements should be on next line
#1552: FILE: disas/riscv.c:1500:
+            case 5: op = rv_op_lhu; break;

ERROR: trailing statements should be on next line
#1553: FILE: disas/riscv.c:1501:
+            case 6: op = rv_op_lwu; break;

ERROR: trailing statements should be on next line
#1554: FILE: disas/riscv.c:1502:
+            case 7: op = rv_op_ldu; break;

ERROR: trailing statements should be on next line
#1559: FILE: disas/riscv.c:1507:
+            case 2: op = rv_op_flw; break;

ERROR: trailing statements should be on next line
#1560: FILE: disas/riscv.c:1508:
+            case 3: op = rv_op_fld; break;

ERROR: trailing statements should be on next line
#1561: FILE: disas/riscv.c:1509:
+            case 4: op = rv_op_flq; break;

ERROR: trailing statements should be on next line
#1566: FILE: disas/riscv.c:1514:
+            case 0: op = rv_op_fence; break;

ERROR: trailing statements should be on next line
#1567: FILE: disas/riscv.c:1515:
+            case 1: op = rv_op_fence_i; break;

ERROR: trailing statements should be on next line
#1568: FILE: disas/riscv.c:1516:
+            case 2: op = rv_op_lq; break;

ERROR: trailing statements should be on next line
#1573: FILE: disas/riscv.c:1521:
+            case 0: op = rv_op_addi; break;

ERROR: trailing statements should be on next line
#1576: FILE: disas/riscv.c:1524:
+                case 0: op = rv_op_slli; break;

ERROR: trailing statements should be on next line
#1579: FILE: disas/riscv.c:1527:
+            case 2: op = rv_op_slti; break;

ERROR: trailing statements should be on next line
#1580: FILE: disas/riscv.c:1528:
+            case 3: op = rv_op_sltiu; break;

ERROR: trailing statements should be on next line
#1581: FILE: disas/riscv.c:1529:
+            case 4: op = rv_op_xori; break;

ERROR: trailing statements should be on next line
#1584: FILE: disas/riscv.c:1532:
+                case 0: op = rv_op_srli; break;

ERROR: trailing statements should be on next line
#1585: FILE: disas/riscv.c:1533:
+                case 8: op = rv_op_srai; break;

ERROR: trailing statements should be on next line
#1588: FILE: disas/riscv.c:1536:
+            case 6: op = rv_op_ori; break;

ERROR: trailing statements should be on next line
#1589: FILE: disas/riscv.c:1537:
+            case 7: op = rv_op_andi; break;

ERROR: trailing statements should be on next line
#1592: FILE: disas/riscv.c:1540:
+        case 5: op = rv_op_auipc; break;

ERROR: trailing statements should be on next line
#1595: FILE: disas/riscv.c:1543:
+            case 0: op = rv_op_addiw; break;

ERROR: trailing statements should be on next line
#1598: FILE: disas/riscv.c:1546:
+                case 0: op = rv_op_slliw; break;

ERROR: trailing statements should be on next line
#1603: FILE: disas/riscv.c:1551:
+                case 0: op = rv_op_srliw; break;

ERROR: trailing statements should be on next line
#1604: FILE: disas/riscv.c:1552:
+                case 32: op = rv_op_sraiw; break;

ERROR: trailing statements should be on next line
#1611: FILE: disas/riscv.c:1559:
+            case 0: op = rv_op_sb; break;

ERROR: trailing statements should be on next line
#1612: FILE: disas/riscv.c:1560:
+            case 1: op = rv_op_sh; break;

ERROR: trailing statements should be on next line
#1613: FILE: disas/riscv.c:1561:
+            case 2: op = rv_op_sw; break;

ERROR: trailing statements should be on next line
#1614: FILE: disas/riscv.c:1562:
+            case 3: op = rv_op_sd; break;

ERROR: trailing statements should be on next line
#1615: FILE: disas/riscv.c:1563:
+            case 4: op = rv_op_sq; break;

ERROR: trailing statements should be on next line
#1620: FILE: disas/riscv.c:1568:
+            case 2: op = rv_op_fsw; break;

ERROR: trailing statements should be on next line
#1621: FILE: disas/riscv.c:1569:
+            case 3: op = rv_op_fsd; break;

ERROR: trailing statements should be on next line
#1622: FILE: disas/riscv.c:1570:
+            case 4: op = rv_op_fsq; break;

ERROR: trailing statements should be on next line
#1627: FILE: disas/riscv.c:1575:
+            case 2: op = rv_op_amoadd_w; break;

ERROR: trailing statements should be on next line
#1628: FILE: disas/riscv.c:1576:
+            case 3: op = rv_op_amoadd_d; break;

ERROR: trailing statements should be on next line
#1629: FILE: disas/riscv.c:1577:
+            case 4: op = rv_op_amoadd_q; break;

ERROR: trailing statements should be on next line
#1630: FILE: disas/riscv.c:1578:
+            case 10: op = rv_op_amoswap_w; break;

ERROR: trailing statements should be on next line
#1631: FILE: disas/riscv.c:1579:
+            case 11: op = rv_op_amoswap_d; break;

ERROR: trailing statements should be on next line
#1632: FILE: disas/riscv.c:1580:
+            case 12: op = rv_op_amoswap_q; break;

ERROR: trailing statements should be on next line
#1635: FILE: disas/riscv.c:1583:
+                case 0: op = rv_op_lr_w; break;

ERROR: trailing statements should be on next line
#1640: FILE: disas/riscv.c:1588:
+                case 0: op = rv_op_lr_d; break;

ERROR: trailing statements should be on next line
#1645: FILE: disas/riscv.c:1593:
+                case 0: op = rv_op_lr_q; break;

ERROR: trailing statements should be on next line
#1648: FILE: disas/riscv.c:1596:
+            case 26: op = rv_op_sc_w; break;

ERROR: trailing statements should be on next line
#1649: FILE: disas/riscv.c:1597:
+            case 27: op = rv_op_sc_d; break;

ERROR: trailing statements should be on next line
#1650: FILE: disas/riscv.c:1598:
+            case 28: op = rv_op_sc_q; break;

ERROR: trailing statements should be on next line
#1651: FILE: disas/riscv.c:1599:
+            case 34: op = rv_op_amoxor_w; break;

ERROR: trailing statements should be on next line
#1652: FILE: disas/riscv.c:1600:
+            case 35: op = rv_op_amoxor_d; break;

ERROR: trailing statements should be on next line
#1653: FILE: disas/riscv.c:1601:
+            case 36: op = rv_op_amoxor_q; break;

ERROR: trailing statements should be on next line
#1654: FILE: disas/riscv.c:1602:
+            case 66: op = rv_op_amoor_w; break;

ERROR: trailing statements should be on next line
#1655: FILE: disas/riscv.c:1603:
+            case 67: op = rv_op_amoor_d; break;

ERROR: trailing statements should be on next line
#1656: FILE: disas/riscv.c:1604:
+            case 68: op = rv_op_amoor_q; break;

ERROR: trailing statements should be on next line
#1657: FILE: disas/riscv.c:1605:
+            case 98: op = rv_op_amoand_w; break;

ERROR: trailing statements should be on next line
#1658: FILE: disas/riscv.c:1606:
+            case 99: op = rv_op_amoand_d; break;

ERROR: trailing statements should be on next line
#1659: FILE: disas/riscv.c:1607:
+            case 100: op = rv_op_amoand_q; break;

ERROR: trailing statements should be on next line
#1660: FILE: disas/riscv.c:1608:
+            case 130: op = rv_op_amomin_w; break;

ERROR: trailing statements should be on next line
#1661: FILE: disas/riscv.c:1609:
+            case 131: op = rv_op_amomin_d; break;

ERROR: trailing statements should be on next line
#1662: FILE: disas/riscv.c:1610:
+            case 132: op = rv_op_amomin_q; break;

ERROR: trailing statements should be on next line
#1663: FILE: disas/riscv.c:1611:
+            case 162: op = rv_op_amomax_w; break;

ERROR: trailing statements should be on next line
#1664: FILE: disas/riscv.c:1612:
+            case 163: op = rv_op_amomax_d; break;

ERROR: trailing statements should be on next line
#1665: FILE: disas/riscv.c:1613:
+            case 164: op = rv_op_amomax_q; break;

ERROR: trailing statements should be on next line
#1666: FILE: disas/riscv.c:1614:
+            case 194: op = rv_op_amominu_w; break;

ERROR: trailing statements should be on next line
#1667: FILE: disas/riscv.c:1615:
+            case 195: op = rv_op_amominu_d; break;

ERROR: trailing statements should be on next line
#1668: FILE: disas/riscv.c:1616:
+            case 196: op = rv_op_amominu_q; break;

ERROR: trailing statements should be on next line
#1669: FILE: disas/riscv.c:1617:
+            case 226: op = rv_op_amomaxu_w; break;

ERROR: trailing statements should be on next line
#1670: FILE: disas/riscv.c:1618:
+            case 227: op = rv_op_amomaxu_d; break;

ERROR: trailing statements should be on next line
#1671: FILE: disas/riscv.c:1619:
+            case 228: op = rv_op_amomaxu_q; break;

WARNING: line over 80 characters
#1675: FILE: disas/riscv.c:1623:
+            switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {

ERROR: trailing statements should be on next line
#1676: FILE: disas/riscv.c:1624:
+            case 0: op = rv_op_add; break;

ERROR: trailing statements should be on next line
#1677: FILE: disas/riscv.c:1625:
+            case 1: op = rv_op_sll; break;

ERROR: trailing statements should be on next line
#1678: FILE: disas/riscv.c:1626:
+            case 2: op = rv_op_slt; break;

ERROR: trailing statements should be on next line
#1679: FILE: disas/riscv.c:1627:
+            case 3: op = rv_op_sltu; break;

ERROR: trailing statements should be on next line
#1680: FILE: disas/riscv.c:1628:
+            case 4: op = rv_op_xor; break;

ERROR: trailing statements should be on next line
#1681: FILE: disas/riscv.c:1629:
+            case 5: op = rv_op_srl; break;

ERROR: trailing statements should be on next line
#1682: FILE: disas/riscv.c:1630:
+            case 6: op = rv_op_or; break;

ERROR: trailing statements should be on next line
#1683: FILE: disas/riscv.c:1631:
+            case 7: op = rv_op_and; break;

ERROR: trailing statements should be on next line
#1684: FILE: disas/riscv.c:1632:
+            case 8: op = rv_op_mul; break;

ERROR: trailing statements should be on next line
#1685: FILE: disas/riscv.c:1633:
+            case 9: op = rv_op_mulh; break;

ERROR: trailing statements should be on next line
#1686: FILE: disas/riscv.c:1634:
+            case 10: op = rv_op_mulhsu; break;

ERROR: trailing statements should be on next line
#1687: FILE: disas/riscv.c:1635:
+            case 11: op = rv_op_mulhu; break;

ERROR: trailing statements should be on next line
#1688: FILE: disas/riscv.c:1636:
+            case 12: op = rv_op_div; break;

ERROR: trailing statements should be on next line
#1689: FILE: disas/riscv.c:1637:
+            case 13: op = rv_op_divu; break;

ERROR: trailing statements should be on next line
#1690: FILE: disas/riscv.c:1638:
+            case 14: op = rv_op_rem; break;

ERROR: trailing statements should be on next line
#1691: FILE: disas/riscv.c:1639:
+            case 15: op = rv_op_remu; break;

ERROR: trailing statements should be on next line
#1692: FILE: disas/riscv.c:1640:
+            case 256: op = rv_op_sub; break;

ERROR: trailing statements should be on next line
#1693: FILE: disas/riscv.c:1641:
+            case 261: op = rv_op_sra; break;

ERROR: trailing statements should be on next line
#1696: FILE: disas/riscv.c:1644:
+        case 13: op = rv_op_lui; break;

WARNING: line over 80 characters
#1698: FILE: disas/riscv.c:1646:
+            switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {

ERROR: trailing statements should be on next line
#1699: FILE: disas/riscv.c:1647:
+            case 0: op = rv_op_addw; break;

ERROR: trailing statements should be on next line
#1700: FILE: disas/riscv.c:1648:
+            case 1: op = rv_op_sllw; break;

ERROR: trailing statements should be on next line
#1701: FILE: disas/riscv.c:1649:
+            case 5: op = rv_op_srlw; break;

ERROR: trailing statements should be on next line
#1702: FILE: disas/riscv.c:1650:
+            case 8: op = rv_op_mulw; break;

ERROR: trailing statements should be on next line
#1703: FILE: disas/riscv.c:1651:
+            case 12: op = rv_op_divw; break;

ERROR: trailing statements should be on next line
#1704: FILE: disas/riscv.c:1652:
+            case 13: op = rv_op_divuw; break;

ERROR: trailing statements should be on next line
#1705: FILE: disas/riscv.c:1653:
+            case 14: op = rv_op_remw; break;

ERROR: trailing statements should be on next line
#1706: FILE: disas/riscv.c:1654:
+            case 15: op = rv_op_remuw; break;

ERROR: trailing statements should be on next line
#1707: FILE: disas/riscv.c:1655:
+            case 256: op = rv_op_subw; break;

ERROR: trailing statements should be on next line
#1708: FILE: disas/riscv.c:1656:
+            case 261: op = rv_op_sraw; break;

ERROR: trailing statements should be on next line
#1713: FILE: disas/riscv.c:1661:
+            case 0: op = rv_op_fmadd_s; break;

ERROR: trailing statements should be on next line
#1714: FILE: disas/riscv.c:1662:
+            case 1: op = rv_op_fmadd_d; break;

ERROR: trailing statements should be on next line
#1715: FILE: disas/riscv.c:1663:
+            case 3: op = rv_op_fmadd_q; break;

ERROR: trailing statements should be on next line
#1720: FILE: disas/riscv.c:1668:
+            case 0: op = rv_op_fmsub_s; break;

ERROR: trailing statements should be on next line
#1721: FILE: disas/riscv.c:1669:
+            case 1: op = rv_op_fmsub_d; break;

ERROR: trailing statements should be on next line
#1722: FILE: disas/riscv.c:1670:
+            case 3: op = rv_op_fmsub_q; break;

ERROR: trailing statements should be on next line
#1727: FILE: disas/riscv.c:1675:
+            case 0: op = rv_op_fnmsub_s; break;

ERROR: trailing statements should be on next line
#1728: FILE: disas/riscv.c:1676:
+            case 1: op = rv_op_fnmsub_d; break;

ERROR: trailing statements should be on next line
#1729: FILE: disas/riscv.c:1677:
+            case 3: op = rv_op_fnmsub_q; break;

ERROR: trailing statements should be on next line
#1734: FILE: disas/riscv.c:1682:
+            case 0: op = rv_op_fnmadd_s; break;

ERROR: trailing statements should be on next line
#1735: FILE: disas/riscv.c:1683:
+            case 1: op = rv_op_fnmadd_d; break;

ERROR: trailing statements should be on next line
#1736: FILE: disas/riscv.c:1684:
+            case 3: op = rv_op_fnmadd_q; break;

ERROR: trailing statements should be on next line
#1741: FILE: disas/riscv.c:1689:
+            case 0: op = rv_op_fadd_s; break;

ERROR: trailing statements should be on next line
#1742: FILE: disas/riscv.c:1690:
+            case 1: op = rv_op_fadd_d; break;

ERROR: trailing statements should be on next line
#1743: FILE: disas/riscv.c:1691:
+            case 3: op = rv_op_fadd_q; break;

ERROR: trailing statements should be on next line
#1744: FILE: disas/riscv.c:1692:
+            case 4: op = rv_op_fsub_s; break;

ERROR: trailing statements should be on next line
#1745: FILE: disas/riscv.c:1693:
+            case 5: op = rv_op_fsub_d; break;

ERROR: trailing statements should be on next line
#1746: FILE: disas/riscv.c:1694:
+            case 7: op = rv_op_fsub_q; break;

ERROR: trailing statements should be on next line
#1747: FILE: disas/riscv.c:1695:
+            case 8: op = rv_op_fmul_s; break;

ERROR: trailing statements should be on next line
#1748: FILE: disas/riscv.c:1696:
+            case 9: op = rv_op_fmul_d; break;

ERROR: trailing statements should be on next line
#1749: FILE: disas/riscv.c:1697:
+            case 11: op = rv_op_fmul_q; break;

ERROR: trailing statements should be on next line
#1750: FILE: disas/riscv.c:1698:
+            case 12: op = rv_op_fdiv_s; break;

ERROR: trailing statements should be on next line
#1751: FILE: disas/riscv.c:1699:
+            case 13: op = rv_op_fdiv_d; break;

ERROR: trailing statements should be on next line
#1752: FILE: disas/riscv.c:1700:
+            case 15: op = rv_op_fdiv_q; break;

ERROR: trailing statements should be on next line
#1755: FILE: disas/riscv.c:1703:
+                case 0: op = rv_op_fsgnj_s; break;

ERROR: trailing statements should be on next line
#1756: FILE: disas/riscv.c:1704:
+                case 1: op = rv_op_fsgnjn_s; break;

ERROR: trailing statements should be on next line
#1757: FILE: disas/riscv.c:1705:
+                case 2: op = rv_op_fsgnjx_s; break;

ERROR: trailing statements should be on next line
#1762: FILE: disas/riscv.c:1710:
+                case 0: op = rv_op_fsgnj_d; break;

ERROR: trailing statements should be on next line
#1763: FILE: disas/riscv.c:1711:
+                case 1: op = rv_op_fsgnjn_d; break;

ERROR: trailing statements should be on next line
#1764: FILE: disas/riscv.c:1712:
+                case 2: op = rv_op_fsgnjx_d; break;

ERROR: trailing statements should be on next line
#1769: FILE: disas/riscv.c:1717:
+                case 0: op = rv_op_fsgnj_q; break;

ERROR: trailing statements should be on next line
#1770: FILE: disas/riscv.c:1718:
+                case 1: op = rv_op_fsgnjn_q; break;

ERROR: trailing statements should be on next line
#1771: FILE: disas/riscv.c:1719:
+                case 2: op = rv_op_fsgnjx_q; break;

ERROR: trailing statements should be on next line
#1776: FILE: disas/riscv.c:1724:
+                case 0: op = rv_op_fmin_s; break;

ERROR: trailing statements should be on next line
#1777: FILE: disas/riscv.c:1725:
+                case 1: op = rv_op_fmax_s; break;

ERROR: trailing statements should be on next line
#1782: FILE: disas/riscv.c:1730:
+                case 0: op = rv_op_fmin_d; break;

ERROR: trailing statements should be on next line
#1783: FILE: disas/riscv.c:1731:
+                case 1: op = rv_op_fmax_d; break;

ERROR: trailing statements should be on next line
#1788: FILE: disas/riscv.c:1736:
+                case 0: op = rv_op_fmin_q; break;

ERROR: trailing statements should be on next line
#1789: FILE: disas/riscv.c:1737:
+                case 1: op = rv_op_fmax_q; break;

ERROR: trailing statements should be on next line
#1794: FILE: disas/riscv.c:1742:
+                case 1: op = rv_op_fcvt_s_d; break;

ERROR: trailing statements should be on next line
#1795: FILE: disas/riscv.c:1743:
+                case 3: op = rv_op_fcvt_s_q; break;

ERROR: trailing statements should be on next line
#1800: FILE: disas/riscv.c:1748:
+                case 0: op = rv_op_fcvt_d_s; break;

ERROR: trailing statements should be on next line
#1801: FILE: disas/riscv.c:1749:
+                case 3: op = rv_op_fcvt_d_q; break;

ERROR: trailing statements should be on next line
#1806: FILE: disas/riscv.c:1754:
+                case 0: op = rv_op_fcvt_q_s; break;

ERROR: trailing statements should be on next line
#1807: FILE: disas/riscv.c:1755:
+                case 1: op = rv_op_fcvt_q_d; break;

ERROR: trailing statements should be on next line
#1812: FILE: disas/riscv.c:1760:
+                case 0: op = rv_op_fsqrt_s; break;

ERROR: trailing statements should be on next line
#1817: FILE: disas/riscv.c:1765:
+                case 0: op = rv_op_fsqrt_d; break;

ERROR: trailing statements should be on next line
#1822: FILE: disas/riscv.c:1770:
+                case 0: op = rv_op_fsqrt_q; break;

ERROR: trailing statements should be on next line
#1827: FILE: disas/riscv.c:1775:
+                case 0: op = rv_op_fle_s; break;

ERROR: trailing statements should be on next line
#1828: FILE: disas/riscv.c:1776:
+                case 1: op = rv_op_flt_s; break;

ERROR: trailing statements should be on next line
#1829: FILE: disas/riscv.c:1777:
+                case 2: op = rv_op_feq_s; break;

ERROR: trailing statements should be on next line
#1834: FILE: disas/riscv.c:1782:
+                case 0: op = rv_op_fle_d; break;

ERROR: trailing statements should be on next line
#1835: FILE: disas/riscv.c:1783:
+                case 1: op = rv_op_flt_d; break;

ERROR: trailing statements should be on next line
#1836: FILE: disas/riscv.c:1784:
+                case 2: op = rv_op_feq_d; break;

ERROR: trailing statements should be on next line
#1841: FILE: disas/riscv.c:1789:
+                case 0: op = rv_op_fle_q; break;

ERROR: trailing statements should be on next line
#1842: FILE: disas/riscv.c:1790:
+                case 1: op = rv_op_flt_q; break;

ERROR: trailing statements should be on next line
#1843: FILE: disas/riscv.c:1791:
+                case 2: op = rv_op_feq_q; break;

ERROR: trailing statements should be on next line
#1848: FILE: disas/riscv.c:1796:
+                case 0: op = rv_op_fcvt_w_s; break;

ERROR: trailing statements should be on next line
#1849: FILE: disas/riscv.c:1797:
+                case 1: op = rv_op_fcvt_wu_s; break;

ERROR: trailing statements should be on next line
#1850: FILE: disas/riscv.c:1798:
+                case 2: op = rv_op_fcvt_l_s; break;

ERROR: trailing statements should be on next line
#1851: FILE: disas/riscv.c:1799:
+                case 3: op = rv_op_fcvt_lu_s; break;

ERROR: trailing statements should be on next line
#1856: FILE: disas/riscv.c:1804:
+                case 0: op = rv_op_fcvt_w_d; break;

ERROR: trailing statements should be on next line
#1857: FILE: disas/riscv.c:1805:
+                case 1: op = rv_op_fcvt_wu_d; break;

ERROR: trailing statements should be on next line
#1858: FILE: disas/riscv.c:1806:
+                case 2: op = rv_op_fcvt_l_d; break;

ERROR: trailing statements should be on next line
#1859: FILE: disas/riscv.c:1807:
+                case 3: op = rv_op_fcvt_lu_d; break;

ERROR: trailing statements should be on next line
#1864: FILE: disas/riscv.c:1812:
+                case 0: op = rv_op_fcvt_w_q; break;

ERROR: trailing statements should be on next line
#1865: FILE: disas/riscv.c:1813:
+                case 1: op = rv_op_fcvt_wu_q; break;

ERROR: trailing statements should be on next line
#1866: FILE: disas/riscv.c:1814:
+                case 2: op = rv_op_fcvt_l_q; break;

ERROR: trailing statements should be on next line
#1867: FILE: disas/riscv.c:1815:
+                case 3: op = rv_op_fcvt_lu_q; break;

ERROR: trailing statements should be on next line
#1872: FILE: disas/riscv.c:1820:
+                case 0: op = rv_op_fcvt_s_w; break;

ERROR: trailing statements should be on next line
#1873: FILE: disas/riscv.c:1821:
+                case 1: op = rv_op_fcvt_s_wu; break;

ERROR: trailing statements should be on next line
#1874: FILE: disas/riscv.c:1822:
+                case 2: op = rv_op_fcvt_s_l; break;

ERROR: trailing statements should be on next line
#1875: FILE: disas/riscv.c:1823:
+                case 3: op = rv_op_fcvt_s_lu; break;

ERROR: trailing statements should be on next line
#1880: FILE: disas/riscv.c:1828:
+                case 0: op = rv_op_fcvt_d_w; break;

ERROR: trailing statements should be on next line
#1881: FILE: disas/riscv.c:1829:
+                case 1: op = rv_op_fcvt_d_wu; break;

ERROR: trailing statements should be on next line
#1882: FILE: disas/riscv.c:1830:
+                case 2: op = rv_op_fcvt_d_l; break;

ERROR: trailing statements should be on next line
#1883: FILE: disas/riscv.c:1831:
+                case 3: op = rv_op_fcvt_d_lu; break;

ERROR: trailing statements should be on next line
#1888: FILE: disas/riscv.c:1836:
+                case 0: op = rv_op_fcvt_q_w; break;

ERROR: trailing statements should be on next line
#1889: FILE: disas/riscv.c:1837:
+                case 1: op = rv_op_fcvt_q_wu; break;

ERROR: trailing statements should be on next line
#1890: FILE: disas/riscv.c:1838:
+                case 2: op = rv_op_fcvt_q_l; break;

ERROR: trailing statements should be on next line
#1891: FILE: disas/riscv.c:1839:
+                case 3: op = rv_op_fcvt_q_lu; break;

WARNING: line over 80 characters
#1895: FILE: disas/riscv.c:1843:
+                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {

ERROR: trailing statements should be on next line
#1896: FILE: disas/riscv.c:1844:
+                case 0: op = rv_op_fmv_x_s; break;

ERROR: trailing statements should be on next line
#1897: FILE: disas/riscv.c:1845:
+                case 1: op = rv_op_fclass_s; break;

WARNING: line over 80 characters
#1901: FILE: disas/riscv.c:1849:
+                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {

ERROR: trailing statements should be on next line
#1902: FILE: disas/riscv.c:1850:
+                case 0: op = rv_op_fmv_x_d; break;

ERROR: trailing statements should be on next line
#1903: FILE: disas/riscv.c:1851:
+                case 1: op = rv_op_fclass_d; break;

WARNING: line over 80 characters
#1907: FILE: disas/riscv.c:1855:
+                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {

ERROR: trailing statements should be on next line
#1908: FILE: disas/riscv.c:1856:
+                case 0: op = rv_op_fmv_x_q; break;

ERROR: trailing statements should be on next line
#1909: FILE: disas/riscv.c:1857:
+                case 1: op = rv_op_fclass_q; break;

WARNING: line over 80 characters
#1913: FILE: disas/riscv.c:1861:
+                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {

ERROR: trailing statements should be on next line
#1914: FILE: disas/riscv.c:1862:
+                case 0: op = rv_op_fmv_s_x; break;

WARNING: line over 80 characters
#1918: FILE: disas/riscv.c:1866:
+                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {

ERROR: trailing statements should be on next line
#1919: FILE: disas/riscv.c:1867:
+                case 0: op = rv_op_fmv_d_x; break;

WARNING: line over 80 characters
#1923: FILE: disas/riscv.c:1871:
+                switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {

ERROR: trailing statements should be on next line
#1924: FILE: disas/riscv.c:1872:
+                case 0: op = rv_op_fmv_q_x; break;

ERROR: trailing statements should be on next line
#1931: FILE: disas/riscv.c:1879:
+            case 0: op = rv_op_addid; break;

ERROR: trailing statements should be on next line
#1934: FILE: disas/riscv.c:1882:
+                case 0: op = rv_op_sllid; break;

ERROR: trailing statements should be on next line
#1939: FILE: disas/riscv.c:1887:
+                case 0: op = rv_op_srlid; break;

ERROR: trailing statements should be on next line
#1940: FILE: disas/riscv.c:1888:
+                case 16: op = rv_op_sraid; break;

ERROR: trailing statements should be on next line
#1947: FILE: disas/riscv.c:1895:
+            case 0: op = rv_op_beq; break;

ERROR: trailing statements should be on next line
#1948: FILE: disas/riscv.c:1896:
+            case 1: op = rv_op_bne; break;

ERROR: trailing statements should be on next line
#1949: FILE: disas/riscv.c:1897:
+            case 4: op = rv_op_blt; break;

ERROR: trailing statements should be on next line
#1950: FILE: disas/riscv.c:1898:
+            case 5: op = rv_op_bge; break;

ERROR: trailing statements should be on next line
#1951: FILE: disas/riscv.c:1899:
+            case 6: op = rv_op_bltu; break;

ERROR: trailing statements should be on next line
#1952: FILE: disas/riscv.c:1900:
+            case 7: op = rv_op_bgeu; break;

ERROR: trailing statements should be on next line
#1957: FILE: disas/riscv.c:1905:
+            case 0: op = rv_op_jalr; break;

ERROR: trailing statements should be on next line
#1960: FILE: disas/riscv.c:1908:
+        case 27: op = rv_op_jal; break;

ERROR: line over 90 characters
#1964: FILE: disas/riscv.c:1912:
+                switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {

ERROR: trailing statements should be on next line
#1967: FILE: disas/riscv.c:1915:
+                    case 0: op = rv_op_ecall; break;

ERROR: trailing statements should be on next line
#1968: FILE: disas/riscv.c:1916:
+                    case 32: op = rv_op_ebreak; break;

ERROR: trailing statements should be on next line
#1969: FILE: disas/riscv.c:1917:
+                    case 64: op = rv_op_uret; break;

ERROR: trailing statements should be on next line
#1976: FILE: disas/riscv.c:1924:
+                        case 0: op = rv_op_sret; break;

ERROR: trailing statements should be on next line
#1979: FILE: disas/riscv.c:1927:
+                    case 4: op = rv_op_sfence_vm; break;

ERROR: trailing statements should be on next line
#1982: FILE: disas/riscv.c:1930:
+                        case 0: op = rv_op_wfi; break;

ERROR: trailing statements should be on next line
#1987: FILE: disas/riscv.c:1935:
+                case 288: op = rv_op_sfence_vma; break;

ERROR: trailing statements should be on next line
#1990: FILE: disas/riscv.c:1938:
+                    case 64: op = rv_op_hret; break;

ERROR: trailing statements should be on next line
#1995: FILE: disas/riscv.c:1943:
+                    case 64: op = rv_op_mret; break;

ERROR: trailing statements should be on next line
#2000: FILE: disas/riscv.c:1948:
+                    case 576: op = rv_op_dret; break;

ERROR: trailing statements should be on next line
#2005: FILE: disas/riscv.c:1953:
+            case 1: op = rv_op_csrrw; break;

ERROR: trailing statements should be on next line
#2006: FILE: disas/riscv.c:1954:
+            case 2: op = rv_op_csrrs; break;

ERROR: trailing statements should be on next line
#2007: FILE: disas/riscv.c:1955:
+            case 3: op = rv_op_csrrc; break;

ERROR: trailing statements should be on next line
#2008: FILE: disas/riscv.c:1956:
+            case 5: op = rv_op_csrrwi; break;

ERROR: trailing statements should be on next line
#2009: FILE: disas/riscv.c:1957:
+            case 6: op = rv_op_csrrsi; break;

ERROR: trailing statements should be on next line
#2010: FILE: disas/riscv.c:1958:
+            case 7: op = rv_op_csrrci; break;

WARNING: line over 80 characters
#2014: FILE: disas/riscv.c:1962:
+            switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {

ERROR: trailing statements should be on next line
#2015: FILE: disas/riscv.c:1963:
+            case 0: op = rv_op_addd; break;

ERROR: trailing statements should be on next line
#2016: FILE: disas/riscv.c:1964:
+            case 1: op = rv_op_slld; break;

ERROR: trailing statements should be on next line
#2017: FILE: disas/riscv.c:1965:
+            case 5: op = rv_op_srld; break;

ERROR: trailing statements should be on next line
#2018: FILE: disas/riscv.c:1966:
+            case 8: op = rv_op_muld; break;

ERROR: trailing statements should be on next line
#2019: FILE: disas/riscv.c:1967:
+            case 12: op = rv_op_divd; break;

ERROR: trailing statements should be on next line
#2020: FILE: disas/riscv.c:1968:
+            case 13: op = rv_op_divud; break;

ERROR: trailing statements should be on next line
#2021: FILE: disas/riscv.c:1969:
+            case 14: op = rv_op_remd; break;

ERROR: trailing statements should be on next line
#2022: FILE: disas/riscv.c:1970:
+            case 15: op = rv_op_remud; break;

ERROR: trailing statements should be on next line
#2023: FILE: disas/riscv.c:1971:
+            case 256: op = rv_op_subd; break;

ERROR: trailing statements should be on next line
#2024: FILE: disas/riscv.c:1972:
+            case 261: op = rv_op_srad; break;

ERROR: trailing statements should be on next line
#2787: FILE: disas/riscv.c:2735:
+        default: break;

ERROR: space prohibited between function name and open parenthesis '('
#3115: FILE: include/disas/bfd.h:432:
+int print_insn_riscv32          (bfd_vma, disassemble_info*);

ERROR: space prohibited between function name and open parenthesis '('
#3116: FILE: include/disas/bfd.h:433:
+int print_insn_riscv64          (bfd_vma, disassemble_info*);

total: 279 errors, 38 warnings, 3077 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 5/23: RISC-V CPU Helpers...
ERROR: return is not a function, parentheses are not required
#956: FILE: target/riscv/op_helper.c:385:
+        return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT

total: 1 errors, 0 warnings, 1186 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 6/23: Softfloat support for IEEE 754-201x minimumNumber/maximumNumber...
ERROR: spaces required around that '*' (ctx:WxV)
#85: FILE: fpu/softfloat.c:7773:
+                                 float_status *status)                  \
                                               ^

ERROR: spaces required around that '*' (ctx:WxV)
#91: FILE: fpu/softfloat.c:7779:
+                                 float_status *status)                  \
                                               ^

total: 2 errors, 0 warnings, 94 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 7/23: RISC-V FPU Support...
Checking PATCH 8/23: RISC-V GDB Stub...
Checking PATCH 9/23: RISC-V TCG Code Generation...
ERROR: spaces required around that ':' (ctx:VxE)
#635: FILE: target/riscv/translate.c:240:
+    CASE_OP_32_64(OPC_RISC_ADD):
                                ^

ERROR: spaces required around that ':' (ctx:VxE)
#638: FILE: target/riscv/translate.c:243:
+    CASE_OP_32_64(OPC_RISC_SUB):
                                ^

ERROR: spaces required around that ':' (ctx:VxE)
#692: FILE: target/riscv/translate.c:297:
+    CASE_OP_32_64(OPC_RISC_MUL):
                                ^

total: 3 errors, 0 warnings, 2336 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 10/23: RISC-V Physical Memory Protection...
Checking PATCH 11/23: RISC-V Linux User Emulation...
Checking PATCH 12/23: RISC-V HTIF Console...
Checking PATCH 13/23: RISC-V HART Array...
Checking PATCH 14/23: SiFive RISC-V CLINT Block...
Checking PATCH 15/23: SiFive RISC-V PLIC Block...
Checking PATCH 16/23: RISC-V Spike Machines...
Checking PATCH 17/23: RISC-V VirtIO Machine...
Checking PATCH 18/23: SiFive RISC-V UART Device...
Checking PATCH 19/23: SiFive RISC-V PRCI Block...
Checking PATCH 20/23: SiFive RISC-V Test Finisher...
Checking PATCH 21/23: SiFive Freedom E300 RISC-V Machine...
Checking PATCH 22/23: SiFive Freedom U500 RISC-V Machine...
Checking PATCH 23/23: RISC-V Build Infrastructure...
WARNING: line over 80 characters
#230: FILE: scripts/qemu-binfmt-conf.sh:103:
+riscv32_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00'

ERROR: line over 90 characters
#231: FILE: scripts/qemu-binfmt-conf.sh:104:
+riscv32_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'

WARNING: line over 80 characters
#234: FILE: scripts/qemu-binfmt-conf.sh:107:
+riscv64_magic='\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xf3\x00'

ERROR: line over 90 characters
#235: FILE: scripts/qemu-binfmt-conf.sh:108:
+riscv64_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'

total: 2 errors, 2 warnings, 156 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


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