From nobody Sun May 5 15:39:03 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1517778838386911.5371894778818; Sun, 4 Feb 2018 13:13:58 -0800 (PST) Received: from localhost ([::1]:40275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eiRbj-0004ka-AY for importer@patchew.org; Sun, 04 Feb 2018 16:13:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55808) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eiR6N-0002yl-V8 for qemu-devel@nongnu.org; Sun, 04 Feb 2018 15:41:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eiR6K-0003kh-1j for qemu-devel@nongnu.org; Sun, 04 Feb 2018 15:41:28 -0500 Received: from shattrath.sceen.net ([151.80.19.218]:52867 helo=mail.sceen.net) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eiR6J-0003k5-Qq for qemu-devel@nongnu.org; Sun, 04 Feb 2018 15:41:23 -0500 Received: by mail.sceen.net (Postfix, from userid 1000) id 737FF4035C; Sun, 4 Feb 2018 21:41:21 +0100 (CET) From: Richard Braun To: qemu-devel@nongnu.org Date: Sun, 4 Feb 2018 21:41:21 +0100 Message-Id: <1517776881-14115-1-git-send-email-rbraun@sceen.net> X-Mailer: git-send-email 2.1.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 151.80.19.218 X-Mailman-Approved-At: Sun, 04 Feb 2018 16:12:43 -0500 Subject: [Qemu-devel] [PATCH] hw/char/stm32f2xx_usart: improve TXE/TC bit handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Consider that data is always immediately sent. As a result, keep the SR_TXE and SR_TC bits always set. In addition, fix the reset value of the USART status register. Signed-off-by: Richard Braun --- hw/char/stm32f2xx_usart.c | 4 ---- include/hw/char/stm32f2xx_usart.h | 7 ++++++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 07b462d4b6..a914f98a2a 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -96,12 +96,10 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwad= dr addr, switch (addr) { case USART_SR: retvalue =3D s->usart_sr; - s->usart_sr &=3D ~USART_SR_TC; qemu_chr_fe_accept_input(&s->chr); return retvalue; case USART_DR: DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usar= t_dr); - s->usart_sr |=3D USART_SR_TXE; s->usart_sr &=3D ~USART_SR_RXNE; qemu_chr_fe_accept_input(&s->chr); qemu_set_irq(s->irq, 0); @@ -151,8 +149,6 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr = addr, /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); - s->usart_sr |=3D USART_SR_TC; - s->usart_sr &=3D ~USART_SR_TXE; } return; case USART_BRR: diff --git a/include/hw/char/stm32f2xx_usart.h b/include/hw/char/stm32f2xx_= usart.h index 9d03a7527c..bbba3965a1 100644 --- a/include/hw/char/stm32f2xx_usart.h +++ b/include/hw/char/stm32f2xx_usart.h @@ -37,7 +37,12 @@ #define USART_CR3 0x14 #define USART_GTPR 0x18 =20 -#define USART_SR_RESET 0x00C00000 +/* + * XXX The reset value mentioned in 24.6.1 Status register seems bogus. + * Looking at Table 98 USART register map and reset values, it seems it + * should be 0xc0, and that's how real hardware behaves. + */ +#define USART_SR_RESET (USART_SR_TXE | USART_SR_TC) =20 #define USART_SR_TXE (1 << 7) #define USART_SR_TC (1 << 6) --=20 2.11.0