From nobody Sat May 4 01:56:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512742580224411.7140072121523; Fri, 8 Dec 2017 06:16:20 -0800 (PST) Received: from localhost ([::1]:37477 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eNJRi-0008SA-Rj for importer@patchew.org; Fri, 08 Dec 2017 09:16:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eNJOk-0004iL-SY for qemu-devel@nongnu.org; Fri, 08 Dec 2017 09:13:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eNJOj-0001Tr-QU for qemu-devel@nongnu.org; Fri, 08 Dec 2017 09:13:06 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eNJOh-0001Lv-7f; Fri, 08 Dec 2017 09:13:03 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eNJOX-0000pn-UE; Fri, 08 Dec 2017 14:12:53 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 8 Dec 2017 14:12:52 +0000 Message-Id: <1512742372-31517-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] hw/intc/armv7m: Support byte and halfword accesses to CFSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andy Gross , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Configurable Fault Status Register for ARMv7M and v8M is supposed to be byte and halfword accessible, but we were only implementing word accesses. Add support for the other access sizes, which are used by the Zephyr RTOS. Signed-off-by: Peter Maydell Reported-by: Andy Gross Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/armv7m_nvic.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5d9c883..dc8e2f1 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -896,13 +896,6 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offs= et, MemTxAttrs attrs) val |=3D (1 << 8); } return val; - case 0xd28: /* Configurable Fault Status. */ - /* The BFSR bits [15:8] are shared between security states - * and we store them in the NS copy - */ - val =3D cpu->env.v7m.cfsr[attrs.secure]; - val |=3D cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; - return val; case 0xd2c: /* Hard Fault Status. */ return cpu->env.v7m.hfsr; case 0xd30: /* Debug Fault Status. */ @@ -1280,15 +1273,6 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, s->vectors[ARMV7M_EXCP_DEBUG].active =3D (value & (1 << 8)) !=3D 0; nvic_irq_update(s); break; - case 0xd28: /* Configurable Fault Status. */ - cpu->env.v7m.cfsr[attrs.secure] &=3D ~value; /* W1C */ - if (attrs.secure) { - /* The BFSR bits [15:8] are shared between security states - * and we store them in the NS copy. - */ - cpu->env.v7m.cfsr[M_REG_NS] &=3D ~(value & R_V7M_CFSR_BFSR_MAS= K); - } - break; case 0xd2c: /* Hard Fault Status. */ cpu->env.v7m.hfsr &=3D ~value; /* W1C */ break; @@ -1667,6 +1651,14 @@ static MemTxResult nvic_sysreg_read(void *opaque, hw= addr addr, val =3D deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank)); } break; + case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ + /* The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy + */ + val =3D s->cpu->env.v7m.cfsr[attrs.secure]; + val |=3D s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + val =3D extract32(val, (offset - 0xd28) * 8, size * 8); + break; case 0xfe0 ... 0xfff: /* ID. */ if (offset & 3) { val =3D 0; @@ -1765,6 +1757,20 @@ static MemTxResult nvic_sysreg_write(void *opaque, h= waddr addr, } nvic_irq_update(s); return MEMTX_OK; + case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ + /* All bits are W1C, so construct 32 bit value with 0s in + * the parts not written by the access size + */ + value <<=3D ((offset - 0xd28) * 8); + + s->cpu->env.v7m.cfsr[attrs.secure] &=3D ~value; + if (attrs.secure) { + /* The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy. + */ + s->cpu->env.v7m.cfsr[M_REG_NS] &=3D ~(value & R_V7M_CFSR_BFSR_= MASK); + } + return MEMTX_OK; } if (size =3D=3D 4) { nvic_writel(s, offset, value, attrs); --=20 2.7.4