From nobody Sat May 4 06:14:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512158553774720.178025773453; Fri, 1 Dec 2017 12:02:33 -0800 (PST) Received: from localhost ([::1]:60449 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eKrW0-0003G8-Tl for importer@patchew.org; Fri, 01 Dec 2017 15:02:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eKqPX-0004IZ-9V for qemu-devel@nongnu.org; Fri, 01 Dec 2017 13:51:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eKqPW-0006q6-ID for qemu-devel@nongnu.org; Fri, 01 Dec 2017 13:51:43 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38676) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eKqPU-0006nT-AZ; Fri, 01 Dec 2017 13:51:40 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eKqPR-0007Bs-RZ; Fri, 01 Dec 2017 18:51:37 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 1 Dec 2017 18:51:35 +0000 Message-Id: <1512154296-5652-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512154296-5652-1-git-send-email-peter.maydell@linaro.org> References: <1512154296-5652-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/2] nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Generalize nvic_sysreg_ns_ops so that we can pass it an arbitrary MemoryRegion which it will use as the underlying register implementation to apply the NS-alias behaviour to. We'll want this so we can do the same with systick. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/armv7m_nvic.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5d9c883..63f2743 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1786,10 +1786,12 @@ static MemTxResult nvic_sysreg_ns_write(void *opaqu= e, hwaddr addr, uint64_t value, unsigned size, MemTxAttrs attrs) { + MemoryRegion *mr =3D opaque; + if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return nvic_sysreg_write(opaque, addr, value, size, attrs); + return memory_region_dispatch_write(mr, addr, value, size, attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -1803,10 +1805,12 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque= , hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { + MemoryRegion *mr =3D opaque; + if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return nvic_sysreg_read(opaque, addr, data, size, attrs); + return memory_region_dispatch_read(mr, addr, data, size, attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2075,7 +2079,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) =20 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), - &nvic_sysreg_ns_ops, s, + &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_= mem); } --=20 2.7.4 From nobody Sat May 4 06:14:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1512160622457228.78285128048856; Fri, 1 Dec 2017 12:37:02 -0800 (PST) Received: from localhost ([::1]:60857 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eKs37-0000M2-6G for importer@patchew.org; Fri, 01 Dec 2017 15:36:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eKqqH-0004Ng-HL for qemu-devel@nongnu.org; Fri, 01 Dec 2017 14:19:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eKqqG-000327-Ac for qemu-devel@nongnu.org; Fri, 01 Dec 2017 14:19:21 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eKqqD-00030d-Es; Fri, 01 Dec 2017 14:19:17 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eKqPS-0007C5-Gc; Fri, 01 Dec 2017 18:51:38 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 1 Dec 2017 18:51:36 +0000 Message-Id: <1512154296-5652-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512154296-5652-1-git-send-email-peter.maydell@linaro.org> References: <1512154296-5652-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/2] nvic: Make systick banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the v8M security extension, there should be two systick devices, which use separate banked systick exceptions. The register interface is banked in the same way as for other banked registers, including the existence of an NS alias region for secure code to access the nonsecure timer. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/armv7m_nvic.h | 4 ++- hw/intc/armv7m_nvic.c | 81 ++++++++++++++++++++++++++++++++++++---= ---- 2 files changed, 72 insertions(+), 13 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index ac7997c..8bc2911 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -78,13 +78,15 @@ typedef struct NVICState { =20 MemoryRegion sysregmem; MemoryRegion sysreg_ns_mem; + MemoryRegion systickmem; + MemoryRegion systick_ns_mem; MemoryRegion container; =20 uint32_t num_irq; qemu_irq excpout; qemu_irq sysresetreq; =20 - SysTickState systick; + SysTickState systick[M_REG_NUM_BANKS]; } NVICState; =20 #endif diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63f2743..5cb44f4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1827,6 +1827,36 @@ static const MemoryRegionOps nvic_sysreg_ns_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + NVICState *s =3D opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); + return memory_region_dispatch_write(mr, addr, value, size, attrs); +} + +static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + NVICState *s =3D opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); + return memory_region_dispatch_read(mr, addr, data, size, attrs); +} + +static const MemoryRegionOps nvic_systick_ops =3D { + .read_with_attrs =3D nvic_systick_read, + .write_with_attrs =3D nvic_systick_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -2005,17 +2035,16 @@ static void nvic_systick_trigger(void *opaque, int = n, int level) /* SysTick just asked us to pend its exception. * (This is different from an external interrupt line's * behaviour.) - * TODO: when we implement the banked systicks we must make - * this pend the correct banked exception. + * n =3D=3D 0 : NonSecure systick + * n =3D=3D 1 : Secure systick */ - armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false); + armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, n); } } =20 static void armv7m_nvic_realize(DeviceState *dev, Error **errp) { NVICState *s =3D NVIC(dev); - SysBusDevice *systick_sbd; Error *err =3D NULL; int regionlen; =20 @@ -2032,15 +2061,30 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) /* include space for internal exception vectors */ s->num_irq +=3D NVIC_FIRST_IRQ; =20 - object_property_set_bool(OBJECT(&s->systick), true, "realized", &err); + object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true, + "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } - systick_sbd =3D SYS_BUS_DEVICE(&s->systick); - sysbus_connect_irq(systick_sbd, 0, + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, qdev_get_gpio_in_named(dev, "systick-trigger", 0)); =20 + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { + object_initialize(&s->systick[M_REG_S], sizeof(s->systick[M_REG_NS= ]), + TYPE_SYSTICK); + qdev_set_parent_bus(DEVICE(&s->systick[M_REG_S]), sysbus_get_defau= lt()); + + object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true, + "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, + qdev_get_gpio_in_named(dev, "systick-trigger", = 1)); + } + /* The NVIC and System Control Space (SCS) starts at 0xe000e000 * and looks like this: * 0x004 - ICTR @@ -2073,15 +2117,24 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); memory_region_add_subregion(&s->container, 0, &s->sysregmem); + + memory_region_init_io(&s->systickmem, OBJECT(s), + &nvic_systick_ops, s, + "nvic_systick", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0x10, - sysbus_mmio_get_region(systick_sbd= , 0), - 1); + &s->systickmem, 1); =20 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_= mem); + memory_region_init_io(&s->systick_ns_mem, OBJECT(s), + &nvic_sysreg_ns_ops, &s->systickmem, + "nvic_systick_ns", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0x20010, + &s->systick_ns_mem, 1); } =20 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); @@ -2099,12 +2152,16 @@ static void armv7m_nvic_instance_init(Object *obj) NVICState *nvic =3D NVIC(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 - object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK); - qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default()); + object_initialize(&nvic->systick[M_REG_NS], + sizeof(nvic->systick[M_REG_NS]), TYPE_SYSTICK); + qdev_set_parent_bus(DEVICE(&nvic->systick[M_REG_NS]), sysbus_get_defau= lt()); + /* We can't initialize the secure systick here, as we don't know + * yet if we need it. + */ =20 sysbus_init_irq(sbd, &nvic->excpout); qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); - qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", = 1); + qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", = 2); } =20 static void armv7m_nvic_class_init(ObjectClass *klass, void *data) --=20 2.7.4