From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511703801353967.6124724839167; Sun, 26 Nov 2017 05:43:21 -0800 (PST) Received: from localhost ([::1]:56763 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIxDH-00064P-3j for importer@patchew.org; Sun, 26 Nov 2017 08:43:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6C-0000Ql-4T for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx68-0006ck-Ta for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:56 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48795 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx68-0006cS-FN for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:52 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6A-00050e-0l; Sun, 26 Nov 2017 13:35:58 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:19 +0000 Message-Id: <1511703326-25325-2-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 1/8] sun4m: move sun4m_iommu.c from hw/dma to hw/sparc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This seems more appropriate and brings sun4m in line with the other architectures. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/dma/Makefile.objs | 1 - hw/dma/sun4m_iommu.c | 406 --------------------------------------------= --- hw/dma/trace-events | 10 -- hw/sparc/Makefile.objs | 2 +- hw/sparc/sun4m_iommu.c | 407 ++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/sparc/trace-events | 10 ++ 6 files changed, 418 insertions(+), 418 deletions(-) delete mode 100644 hw/dma/sun4m_iommu.c create mode 100644 hw/sparc/sun4m_iommu.c diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs index 087c8e6..0b3a009 100644 --- a/hw/dma/Makefile.objs +++ b/hw/dma/Makefile.objs @@ -8,7 +8,6 @@ common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axidma.o common-obj-$(CONFIG_ZYNQ_DEVCFG) +=3D xlnx-zynq-devcfg.o common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_dma.o common-obj-$(CONFIG_STP2000) +=3D sparc32_dma.o -common-obj-$(CONFIG_SUN4M) +=3D sun4m_iommu.o obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx_dpdma.o =20 obj-$(CONFIG_OMAP) +=3D omap_dma.o soc_dma.o diff --git a/hw/dma/sun4m_iommu.c b/hw/dma/sun4m_iommu.c deleted file mode 100644 index 30a05e8..0000000 --- a/hw/dma/sun4m_iommu.c +++ /dev/null @@ -1,406 +0,0 @@ -/* - * QEMU Sun4m iommu emulation - * - * Copyright (c) 2003-2005 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -#include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" -#include "hw/sysbus.h" -#include "exec/address-spaces.h" -#include "trace.h" - -/* - * I/O MMU used by Sun4m systems - * - * Chipset docs: - * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, - * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture= _edited2.pdf - */ - -#define IOMMU_CTRL (0x0000 >> 2) -#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ -#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ -#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ -#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ -#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ -#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ -#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ -#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ -#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ -#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ -#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ -#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ -#define IOMMU_CTRL_MASK 0x0000001d - -#define IOMMU_BASE (0x0004 >> 2) -#define IOMMU_BASE_MASK 0x07fffc00 - -#define IOMMU_TLBFLUSH (0x0014 >> 2) -#define IOMMU_TLBFLUSH_MASK 0xffffffff - -#define IOMMU_PGFLUSH (0x0018 >> 2) -#define IOMMU_PGFLUSH_MASK 0xffffffff - -#define IOMMU_AFSR (0x1000 >> 2) -#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ -#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after - transaction */ -#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than - 12.8 us. */ -#define IOMMU_AFSR_BE 0x10000000 /* Write access received error - acknowledge */ -#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing erro= r */ -#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ -#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by - hardware */ -#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ -#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress= */ -#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ -#define IOMMU_AFSR_MASK 0xff0fffff - -#define IOMMU_AFAR (0x1004 >> 2) - -#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ -#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ -#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ -#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ -#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ -#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ -#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ -#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ -#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ -#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ -#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ -#define IOMMU_AER_MASK 0x801f000f - -#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ -#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when - bypass enabled */ -#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ -#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ -#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses - produced by this device as pure - physical. */ -#define IOMMU_SBCFG_MASK 0x00010003 - -#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ -#define IOMMU_ARBEN_MASK 0x001f0000 -#define IOMMU_MID 0x00000008 - -#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ -#define IOMMU_MASK_ID_MASK 0x00ffffff - -#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ -#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ - -/* The format of an iopte in the page tables */ -#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12])= */ -#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or - Viking/MXCC) */ -#define IOPTE_WRITE 0x00000004 /* Writable */ -#define IOPTE_VALID 0x00000002 /* IOPTE is valid */ -#define IOPTE_WAZ 0x00000001 /* Write as zeros */ - -#define IOMMU_PAGE_SHIFT 12 -#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) -#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) - -static uint64_t iommu_mem_read(void *opaque, hwaddr addr, - unsigned size) -{ - IOMMUState *s =3D opaque; - hwaddr saddr; - uint32_t ret; - - saddr =3D addr >> 2; - switch (saddr) { - default: - ret =3D s->regs[saddr]; - break; - case IOMMU_AFAR: - case IOMMU_AFSR: - ret =3D s->regs[saddr]; - qemu_irq_lower(s->irq); - break; - } - trace_sun4m_iommu_mem_readl(saddr, ret); - return ret; -} - -static void iommu_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - IOMMUState *s =3D opaque; - hwaddr saddr; - - saddr =3D addr >> 2; - trace_sun4m_iommu_mem_writel(saddr, val); - switch (saddr) { - case IOMMU_CTRL: - switch (val & IOMMU_CTRL_RNGE) { - case IOMMU_RNGE_16MB: - s->iostart =3D 0xffffffffff000000ULL; - break; - case IOMMU_RNGE_32MB: - s->iostart =3D 0xfffffffffe000000ULL; - break; - case IOMMU_RNGE_64MB: - s->iostart =3D 0xfffffffffc000000ULL; - break; - case IOMMU_RNGE_128MB: - s->iostart =3D 0xfffffffff8000000ULL; - break; - case IOMMU_RNGE_256MB: - s->iostart =3D 0xfffffffff0000000ULL; - break; - case IOMMU_RNGE_512MB: - s->iostart =3D 0xffffffffe0000000ULL; - break; - case IOMMU_RNGE_1GB: - s->iostart =3D 0xffffffffc0000000ULL; - break; - default: - case IOMMU_RNGE_2GB: - s->iostart =3D 0xffffffff80000000ULL; - break; - } - trace_sun4m_iommu_mem_writel_ctrl(s->iostart); - s->regs[saddr] =3D ((val & IOMMU_CTRL_MASK) | s->version); - break; - case IOMMU_BASE: - s->regs[saddr] =3D val & IOMMU_BASE_MASK; - break; - case IOMMU_TLBFLUSH: - trace_sun4m_iommu_mem_writel_tlbflush(val); - s->regs[saddr] =3D val & IOMMU_TLBFLUSH_MASK; - break; - case IOMMU_PGFLUSH: - trace_sun4m_iommu_mem_writel_pgflush(val); - s->regs[saddr] =3D val & IOMMU_PGFLUSH_MASK; - break; - case IOMMU_AFAR: - s->regs[saddr] =3D val; - qemu_irq_lower(s->irq); - break; - case IOMMU_AER: - s->regs[saddr] =3D (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; - break; - case IOMMU_AFSR: - s->regs[saddr] =3D (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; - qemu_irq_lower(s->irq); - break; - case IOMMU_SBCFG0: - case IOMMU_SBCFG1: - case IOMMU_SBCFG2: - case IOMMU_SBCFG3: - s->regs[saddr] =3D val & IOMMU_SBCFG_MASK; - break; - case IOMMU_ARBEN: - // XXX implement SBus probing: fault when reading unmapped - // addresses, fault cause and address stored to MMU/IOMMU - s->regs[saddr] =3D (val & IOMMU_ARBEN_MASK) | IOMMU_MID; - break; - case IOMMU_MASK_ID: - s->regs[saddr] |=3D val & IOMMU_MASK_ID_MASK; - break; - default: - s->regs[saddr] =3D val; - break; - } -} - -static const MemoryRegionOps iommu_mem_ops =3D { - .read =3D iommu_mem_read, - .write =3D iommu_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, - }, -}; - -static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr) -{ - uint32_t ret; - hwaddr iopte; - hwaddr pa =3D addr; - - iopte =3D s->regs[IOMMU_BASE] << 4; - addr &=3D ~s->iostart; - iopte +=3D (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; - ret =3D address_space_ldl_be(&address_space_memory, iopte, - MEMTXATTRS_UNSPECIFIED, NULL); - trace_sun4m_iommu_page_get_flags(pa, iopte, ret); - return ret; -} - -static hwaddr iommu_translate_pa(hwaddr addr, - uint32_t pte) -{ - hwaddr pa; - - pa =3D ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); - trace_sun4m_iommu_translate_pa(addr, pa, pte); - return pa; -} - -static void iommu_bad_addr(IOMMUState *s, hwaddr addr, - int is_write) -{ - trace_sun4m_iommu_bad_addr(addr); - s->regs[IOMMU_AFSR] =3D IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RE= SV | - IOMMU_AFSR_FAV; - if (!is_write) - s->regs[IOMMU_AFSR] |=3D IOMMU_AFSR_RD; - s->regs[IOMMU_AFAR] =3D addr; - qemu_irq_raise(s->irq); -} - -/* Called from RCU critical section */ -static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, - hwaddr addr, - IOMMUAccessFlags flags) -{ - IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); - hwaddr page, pa; - int is_write =3D (flags & IOMMU_WO) ? 1 : 0; - uint32_t pte; - IOMMUTLBEntry ret =3D { - .target_as =3D &address_space_memory, - .iova =3D 0, - .translated_addr =3D 0, - .addr_mask =3D ~(hwaddr)0, - .perm =3D IOMMU_NONE, - }; - - page =3D addr & IOMMU_PAGE_MASK; - pte =3D iommu_page_get_flags(is, page); - if (!(pte & IOPTE_VALID)) { - iommu_bad_addr(is, page, is_write); - return ret; - } - - pa =3D iommu_translate_pa(addr, pte); - if (is_write && !(pte & IOPTE_WRITE)) { - iommu_bad_addr(is, page, is_write); - return ret; - } - - if (pte & IOPTE_WRITE) { - ret.perm =3D IOMMU_RW; - } else { - ret.perm =3D IOMMU_RO; - } - - ret.iova =3D page; - ret.translated_addr =3D pa; - ret.addr_mask =3D ~IOMMU_PAGE_MASK; - - return ret; -} - -static const VMStateDescription vmstate_iommu =3D { - .name =3D"iommu", - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS), - VMSTATE_UINT64(iostart, IOMMUState), - VMSTATE_END_OF_LIST() - } -}; - -static void iommu_reset(DeviceState *d) -{ - IOMMUState *s =3D SUN4M_IOMMU(d); - - memset(s->regs, 0, IOMMU_NREGS * 4); - s->iostart =3D 0; - s->regs[IOMMU_CTRL] =3D s->version; - s->regs[IOMMU_ARBEN] =3D IOMMU_MID; - s->regs[IOMMU_AFSR] =3D IOMMU_AFSR_RESV; - s->regs[IOMMU_AER] =3D IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; - s->regs[IOMMU_MASK_ID] =3D IOMMU_TS_MASK; -} - -static void iommu_init(Object *obj) -{ - IOMMUState *s =3D SUN4M_IOMMU(obj); - SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); - - memory_region_init_iommu(&s->iommu, sizeof(s->iommu), - TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev), - "iommu-sun4m", UINT64_MAX); - address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); - - sysbus_init_irq(dev, &s->irq); - - memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", - IOMMU_NREGS * sizeof(uint32_t)); - sysbus_init_mmio(dev, &s->iomem); -} - -static Property iommu_properties[] =3D { - DEFINE_PROP_UINT32("version", IOMMUState, version, 0), - DEFINE_PROP_END_OF_LIST(), -}; - -static void iommu_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->reset =3D iommu_reset; - dc->vmsd =3D &vmstate_iommu; - dc->props =3D iommu_properties; -} - -static const TypeInfo iommu_info =3D { - .name =3D TYPE_SUN4M_IOMMU, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(IOMMUState), - .instance_init =3D iommu_init, - .class_init =3D iommu_class_init, -}; - -static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void = *data) -{ - IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); - - imrc->translate =3D sun4m_translate_iommu; -} - -static const TypeInfo sun4m_iommu_memory_region_info =3D { - .parent =3D TYPE_IOMMU_MEMORY_REGION, - .name =3D TYPE_SUN4M_IOMMU_MEMORY_REGION, - .class_init =3D sun4m_iommu_memory_region_class_init, -}; - -static void iommu_register_types(void) -{ - type_register_static(&iommu_info); - type_register_static(&sun4m_iommu_memory_region_info); -} - -type_init(iommu_register_types) diff --git a/hw/dma/trace-events b/hw/dma/trace-events index 6b367f0..22f53d0 100644 --- a/hw/dma/trace-events +++ b/hw/dma/trace-events @@ -18,15 +18,5 @@ sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint= 32_t val) "write dmareg sparc32_dma_enable_raise(void) "Raise DMA enable" sparc32_dma_enable_lower(void) "Lower DMA enable" =20 -# hw/dma/sun4m_iommu.c -sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = =3D 0x%x" -sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"= ] =3D 0x%x" -sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart =3D 0x%"PRIx64 -sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush 0x%x" -sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush 0x%x" -sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get= flags addr 0x%"PRIx64" =3D> pte 0x%"PRIx64", *pte =3D 0x%x" -sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlat= e dva 0x%"PRIx64" =3D> pa 0x%"PRIx64" iopte =3D 0x%x" -sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 - # hw/dma/i8257.c i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered = DMA channel used nchan=3D%d dma_pos=3D%d dma_len=3D%d" diff --git a/hw/sparc/Makefile.objs b/hw/sparc/Makefile.objs index c987b5b..e2d0828 100644 --- a/hw/sparc/Makefile.objs +++ b/hw/sparc/Makefile.objs @@ -1 +1 @@ -obj-y +=3D sun4m.o leon3.o +obj-y +=3D sun4m_iommu.o sun4m.o leon3.o diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c new file mode 100644 index 0000000..72a9af5 --- /dev/null +++ b/hw/sparc/sun4m_iommu.c @@ -0,0 +1,407 @@ +/* + * QEMU Sun4m iommu emulation + * + * Copyright (c) 2003-2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sparc/sun4m.h" +#include "hw/sysbus.h" +#include "exec/address-spaces.h" +#include "trace.h" + +/* + * I/O MMU used by Sun4m systems + * + * Chipset docs: + * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, + * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture= _edited2.pdf + */ + +#define IOMMU_CTRL (0x0000 >> 2) +#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ +#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ +#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ +#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ +#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ +#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */ +#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */ +#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */ +#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */ +#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */ +#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */ +#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */ +#define IOMMU_CTRL_MASK 0x0000001d + +#define IOMMU_BASE (0x0004 >> 2) +#define IOMMU_BASE_MASK 0x07fffc00 + +#define IOMMU_TLBFLUSH (0x0014 >> 2) +#define IOMMU_TLBFLUSH_MASK 0xffffffff + +#define IOMMU_PGFLUSH (0x0018 >> 2) +#define IOMMU_PGFLUSH_MASK 0xffffffff + +#define IOMMU_AFSR (0x1000 >> 2) +#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ +#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after + transaction */ +#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than + 12.8 us. */ +#define IOMMU_AFSR_BE 0x10000000 /* Write access received error + acknowledge */ +#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing erro= r */ +#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ +#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by + hardware */ +#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ +#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress= */ +#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ +#define IOMMU_AFSR_MASK 0xff0fffff + +#define IOMMU_AFAR (0x1004 >> 2) + +#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ +#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ +#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ +#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ +#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ +#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ +#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ +#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ +#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ +#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ +#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ +#define IOMMU_AER_MASK 0x801f000f + +#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ +#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ +#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ +#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ +#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when + bypass enabled */ +#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ +#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ +#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses + produced by this device as pure + physical. */ +#define IOMMU_SBCFG_MASK 0x00010003 + +#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */ +#define IOMMU_ARBEN_MASK 0x001f0000 +#define IOMMU_MID 0x00000008 + +#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ +#define IOMMU_MASK_ID_MASK 0x00ffffff + +#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ +#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ + +/* The format of an iopte in the page tables */ +#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12])= */ +#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or + Viking/MXCC) */ +#define IOPTE_WRITE 0x00000004 /* Writable */ +#define IOPTE_VALID 0x00000002 /* IOPTE is valid */ +#define IOPTE_WAZ 0x00000001 /* Write as zeros */ + +#define IOMMU_PAGE_SHIFT 12 +#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) +#define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1)) + +static uint64_t iommu_mem_read(void *opaque, hwaddr addr, + unsigned size) +{ + IOMMUState *s =3D opaque; + hwaddr saddr; + uint32_t ret; + + saddr =3D addr >> 2; + switch (saddr) { + default: + ret =3D s->regs[saddr]; + break; + case IOMMU_AFAR: + case IOMMU_AFSR: + ret =3D s->regs[saddr]; + qemu_irq_lower(s->irq); + break; + } + trace_sun4m_iommu_mem_readl(saddr, ret); + return ret; +} + +static void iommu_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + IOMMUState *s =3D opaque; + hwaddr saddr; + + saddr =3D addr >> 2; + trace_sun4m_iommu_mem_writel(saddr, val); + switch (saddr) { + case IOMMU_CTRL: + switch (val & IOMMU_CTRL_RNGE) { + case IOMMU_RNGE_16MB: + s->iostart =3D 0xffffffffff000000ULL; + break; + case IOMMU_RNGE_32MB: + s->iostart =3D 0xfffffffffe000000ULL; + break; + case IOMMU_RNGE_64MB: + s->iostart =3D 0xfffffffffc000000ULL; + break; + case IOMMU_RNGE_128MB: + s->iostart =3D 0xfffffffff8000000ULL; + break; + case IOMMU_RNGE_256MB: + s->iostart =3D 0xfffffffff0000000ULL; + break; + case IOMMU_RNGE_512MB: + s->iostart =3D 0xffffffffe0000000ULL; + break; + case IOMMU_RNGE_1GB: + s->iostart =3D 0xffffffffc0000000ULL; + break; + default: + case IOMMU_RNGE_2GB: + s->iostart =3D 0xffffffff80000000ULL; + break; + } + trace_sun4m_iommu_mem_writel_ctrl(s->iostart); + s->regs[saddr] =3D ((val & IOMMU_CTRL_MASK) | s->version); + break; + case IOMMU_BASE: + s->regs[saddr] =3D val & IOMMU_BASE_MASK; + break; + case IOMMU_TLBFLUSH: + trace_sun4m_iommu_mem_writel_tlbflush(val); + s->regs[saddr] =3D val & IOMMU_TLBFLUSH_MASK; + break; + case IOMMU_PGFLUSH: + trace_sun4m_iommu_mem_writel_pgflush(val); + s->regs[saddr] =3D val & IOMMU_PGFLUSH_MASK; + break; + case IOMMU_AFAR: + s->regs[saddr] =3D val; + qemu_irq_lower(s->irq); + break; + case IOMMU_AER: + s->regs[saddr] =3D (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; + break; + case IOMMU_AFSR: + s->regs[saddr] =3D (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; + qemu_irq_lower(s->irq); + break; + case IOMMU_SBCFG0: + case IOMMU_SBCFG1: + case IOMMU_SBCFG2: + case IOMMU_SBCFG3: + s->regs[saddr] =3D val & IOMMU_SBCFG_MASK; + break; + case IOMMU_ARBEN: + /* XXX implement SBus probing: fault when reading unmapped + addresses, fault cause and address stored to MMU/IOMMU */ + s->regs[saddr] =3D (val & IOMMU_ARBEN_MASK) | IOMMU_MID; + break; + case IOMMU_MASK_ID: + s->regs[saddr] |=3D val & IOMMU_MASK_ID_MASK; + break; + default: + s->regs[saddr] =3D val; + break; + } +} + +static const MemoryRegionOps iommu_mem_ops =3D { + .read =3D iommu_mem_read, + .write =3D iommu_mem_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr) +{ + uint32_t ret; + hwaddr iopte; + hwaddr pa =3D addr; + + iopte =3D s->regs[IOMMU_BASE] << 4; + addr &=3D ~s->iostart; + iopte +=3D (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3; + ret =3D address_space_ldl_be(&address_space_memory, iopte, + MEMTXATTRS_UNSPECIFIED, NULL); + trace_sun4m_iommu_page_get_flags(pa, iopte, ret); + return ret; +} + +static hwaddr iommu_translate_pa(hwaddr addr, + uint32_t pte) +{ + hwaddr pa; + + pa =3D ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK); + trace_sun4m_iommu_translate_pa(addr, pa, pte); + return pa; +} + +static void iommu_bad_addr(IOMMUState *s, hwaddr addr, + int is_write) +{ + trace_sun4m_iommu_bad_addr(addr); + s->regs[IOMMU_AFSR] =3D IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RE= SV | + IOMMU_AFSR_FAV; + if (!is_write) { + s->regs[IOMMU_AFSR] |=3D IOMMU_AFSR_RD; + } + s->regs[IOMMU_AFAR] =3D addr; + qemu_irq_raise(s->irq); +} + +/* Called from RCU critical section */ +static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, + hwaddr addr, + IOMMUAccessFlags flags) +{ + IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); + hwaddr page, pa; + int is_write =3D (flags & IOMMU_WO) ? 1 : 0; + uint32_t pte; + IOMMUTLBEntry ret =3D { + .target_as =3D &address_space_memory, + .iova =3D 0, + .translated_addr =3D 0, + .addr_mask =3D ~(hwaddr)0, + .perm =3D IOMMU_NONE, + }; + + page =3D addr & IOMMU_PAGE_MASK; + pte =3D iommu_page_get_flags(is, page); + if (!(pte & IOPTE_VALID)) { + iommu_bad_addr(is, page, is_write); + return ret; + } + + pa =3D iommu_translate_pa(addr, pte); + if (is_write && !(pte & IOPTE_WRITE)) { + iommu_bad_addr(is, page, is_write); + return ret; + } + + if (pte & IOPTE_WRITE) { + ret.perm =3D IOMMU_RW; + } else { + ret.perm =3D IOMMU_RO; + } + + ret.iova =3D page; + ret.translated_addr =3D pa; + ret.addr_mask =3D ~IOMMU_PAGE_MASK; + + return ret; +} + +static const VMStateDescription vmstate_iommu =3D { + .name =3D "iommu", + .version_id =3D 2, + .minimum_version_id =3D 2, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS), + VMSTATE_UINT64(iostart, IOMMUState), + VMSTATE_END_OF_LIST() + } +}; + +static void iommu_reset(DeviceState *d) +{ + IOMMUState *s =3D SUN4M_IOMMU(d); + + memset(s->regs, 0, IOMMU_NREGS * 4); + s->iostart =3D 0; + s->regs[IOMMU_CTRL] =3D s->version; + s->regs[IOMMU_ARBEN] =3D IOMMU_MID; + s->regs[IOMMU_AFSR] =3D IOMMU_AFSR_RESV; + s->regs[IOMMU_AER] =3D IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; + s->regs[IOMMU_MASK_ID] =3D IOMMU_TS_MASK; +} + +static void iommu_init(Object *obj) +{ + IOMMUState *s =3D SUN4M_IOMMU(obj); + SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); + + memory_region_init_iommu(&s->iommu, sizeof(s->iommu), + TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev), + "iommu-sun4m", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); + + sysbus_init_irq(dev, &s->irq); + + memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", + IOMMU_NREGS * sizeof(uint32_t)); + sysbus_init_mmio(dev, &s->iomem); +} + +static Property iommu_properties[] =3D { + DEFINE_PROP_UINT32("version", IOMMUState, version, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void iommu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D iommu_reset; + dc->vmsd =3D &vmstate_iommu; + dc->props =3D iommu_properties; +} + +static const TypeInfo iommu_info =3D { + .name =3D TYPE_SUN4M_IOMMU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IOMMUState), + .instance_init =3D iommu_init, + .class_init =3D iommu_class_init, +}; + +static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void = *data) +{ + IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); + + imrc->translate =3D sun4m_translate_iommu; +} + +static const TypeInfo sun4m_iommu_memory_region_info =3D { + .parent =3D TYPE_IOMMU_MEMORY_REGION, + .name =3D TYPE_SUN4M_IOMMU_MEMORY_REGION, + .class_init =3D sun4m_iommu_memory_region_class_init, +}; + +static void iommu_register_types(void) +{ + type_register_static(&iommu_info); + type_register_static(&sun4m_iommu_memory_region_info); +} + +type_init(iommu_register_types) diff --git a/hw/sparc/trace-events b/hw/sparc/trace-events index efd765c..6e7259f 100644 --- a/hw/sparc/trace-events +++ b/hw/sparc/trace-events @@ -6,6 +6,16 @@ sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU I= RQ %d" sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d" sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d" =20 +# hw/sparc/sun4m_iommu.c +sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = =3D 0x%x" +sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"= ] =3D 0x%x" +sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart =3D 0x%"PRIx64 +sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush 0x%x" +sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush 0x%x" +sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get= flags addr 0x%"PRIx64" =3D> pte 0x%"PRIx64", *pte =3D 0x%x" +sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlat= e dva 0x%"PRIx64" =3D> pa 0x%"PRIx64" iopte =3D 0x%x" +sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64 + # hw/sparc/leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d" leon3_reset_irq(int intno) "Reset CPU IRQ %d" --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511703502654188.91015283798242; Sun, 26 Nov 2017 05:38:22 -0800 (PST) Received: from localhost ([::1]:56733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx8L-0002Br-9i for importer@patchew.org; Sun, 26 Nov 2017 08:38:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6B-0000Qh-OJ for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx6A-0006dL-1w for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:55 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48799 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx69-0006cw-SE for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:53 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6E-00050e-7k; Sun, 26 Nov 2017 13:35:59 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:20 +0000 Message-Id: <1511703326-25325-3-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 2/8] sun4m: move IOMMU declarations from sun4m.h to sun4m_iommu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also updating the relevant .c files as required. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/dma/sparc32_dma.c | 1 + hw/sparc/sun4m.c | 1 + hw/sparc/sun4m_iommu.c | 1 + include/hw/sparc/sun4m.h | 21 ----------------- include/hw/sparc/sun4m_iommu.h | 51 ++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 54 insertions(+), 21 deletions(-) create mode 100644 include/hw/sparc/sun4m_iommu.h diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index 01afb75..c04ad79 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -29,6 +29,7 @@ #include "hw/hw.h" #include "hw/sparc/sparc32_dma.h" #include "hw/sparc/sun4m.h" +#include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "sysemu/dma.h" #include "qapi/error.h" diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 24c2b8a..a3ba92f 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "qemu/timer.h" #include "hw/sparc/sun4m.h" +#include "hw/sparc/sun4m_iommu.h" #include "hw/timer/m48t59.h" #include "hw/sparc/sparc32_dma.h" #include "hw/block/fdc.h" diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 72a9af5..311c82d 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "hw/sparc/sun4m.h" +#include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" #include "trace.h" diff --git a/include/hw/sparc/sun4m.h b/include/hw/sparc/sun4m.h index c557b0d..9e06467 100644 --- a/include/hw/sparc/sun4m.h +++ b/include/hw/sparc/sun4m.h @@ -8,27 +8,6 @@ =20 /* Devices used by sparc32 system. */ =20 -/* iommu.c */ -#define TYPE_SUN4M_IOMMU "sun4m-iommu" -#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU) - -#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region" - -#define IOMMU_NREGS (4 * 4096 / 4) - -typedef struct IOMMUState { - SysBusDevice parent_obj; - - AddressSpace iommu_as; - IOMMUMemoryRegion iommu; - - MemoryRegion iomem; - uint32_t regs[IOMMU_NREGS]; - hwaddr iostart; - qemu_irq irq; - uint32_t version; -} IOMMUState; - /* sparc32_dma.c */ #include "hw/sparc/sparc32_dma.h" =20 diff --git a/include/hw/sparc/sun4m_iommu.h b/include/hw/sparc/sun4m_iommu.h new file mode 100644 index 0000000..938937eb --- /dev/null +++ b/include/hw/sparc/sun4m_iommu.h @@ -0,0 +1,51 @@ +/* + * QEMU Sun4m iommu emulation + * + * Copyright (c) 2003-2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef SUN4M_IOMMU_H +#define SUN4M_IOMMU_H + +#include "qemu-common.h" +#include "hw/sysbus.h" + +#define IOMMU_NREGS (4 * 4096 / 4) + +typedef struct IOMMUState { + SysBusDevice parent_obj; + + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + MemoryRegion iomem; + uint32_t regs[IOMMU_NREGS]; + hwaddr iostart; + qemu_irq irq; + uint32_t version; +} IOMMUState; + +#define TYPE_SUN4M_IOMMU "sun4m-iommu" +#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU) + +#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region" + +#endif --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511703635273523.8579066604586; Sun, 26 Nov 2017 05:40:35 -0800 (PST) Received: from localhost ([::1]:56746 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIxAY-0003qh-Cb for importer@patchew.org; Sun, 26 Nov 2017 08:40:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6A-0000QU-Rc for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx69-0006dD-RL for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:54 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48797 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx69-0006co-Lh for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:53 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6F-00050e-NF; Sun, 26 Nov 2017 13:36:00 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:21 +0000 Message-Id: <1511703326-25325-4-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 3/8] sun4m: remove include/hw/sparc/sun4m.h and all references to it X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With the previous commit there is now nothing left in sun4m.h so it can be removed, along with all remaining references to it. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/dma/sparc32_dma.c | 1 - hw/intc/slavio_intctl.c | 1 - hw/net/lance.c | 2 +- hw/sparc/sun4m.c | 1 - hw/sparc/sun4m_iommu.c | 1 - hw/timer/slavio_timer.c | 1 - include/hw/sparc/sun4m.h | 14 -------------- 7 files changed, 1 insertion(+), 20 deletions(-) delete mode 100644 include/hw/sparc/sun4m.h diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index c04ad79..7b00a27 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/sparc/sparc32_dma.h" -#include "hw/sparc/sun4m.h" #include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "sysemu/dma.h" diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index 84e0bee..817e026 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -23,7 +23,6 @@ */ =20 #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "monitor/monitor.h" #include "hw/sysbus.h" #include "hw/intc/intc.h" diff --git a/hw/net/lance.c b/hw/net/lance.c index 23929fd..0028bc5 100644 --- a/hw/net/lance.c +++ b/hw/net/lance.c @@ -40,7 +40,7 @@ #include "net/net.h" #include "qemu/timer.h" #include "qemu/sockets.h" -#include "hw/sparc/sun4m.h" +#include "hw/sparc/sparc32_dma.h" #include "hw/net/lance.h" #include "trace.h" #include "sysemu/sysemu.h" diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index a3ba92f..9723d6f 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -28,7 +28,6 @@ #include "hw/sysbus.h" #include "qemu/error-report.h" #include "qemu/timer.h" -#include "hw/sparc/sun4m.h" #include "hw/sparc/sun4m_iommu.h" #include "hw/timer/m48t59.h" #include "hw/sparc/sparc32_dma.h" diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 311c82d..b677601 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -23,7 +23,6 @@ */ =20 #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index a8cc9c0..4694b65 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -23,7 +23,6 @@ */ =20 #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "qemu/timer.h" #include "hw/ptimer.h" #include "hw/sysbus.h" diff --git a/include/hw/sparc/sun4m.h b/include/hw/sparc/sun4m.h deleted file mode 100644 index 9e06467..0000000 --- a/include/hw/sparc/sun4m.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef SUN4M_H -#define SUN4M_H - -#include "qemu-common.h" -#include "exec/hwaddr.h" -#include "qapi/qmp/types.h" -#include "hw/sysbus.h" - -/* Devices used by sparc32 system. */ - -/* sparc32_dma.c */ -#include "hw/sparc/sparc32_dma.h" - -#endif --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511703719179175.27995409369316; Sun, 26 Nov 2017 05:41:59 -0800 (PST) Received: from localhost ([::1]:56759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIxC2-0004uR-H5 for importer@patchew.org; Sun, 26 Nov 2017 08:41:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6B-0000Qi-QB for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx6A-0006dX-BC for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:55 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48802 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx6A-0006d2-2Q for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:54 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6H-00050e-2y; Sun, 26 Nov 2017 13:36:02 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:22 +0000 Message-Id: <1511703326-25325-5-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 4/8] apb: QOMify IOMMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is in preparation to split the IOMMU device out of the APB. As part of this commit we also enforce separation of the IOMMU and APB devices by using a QOM object link to pass the IOMMU reference and accessing the IOMMU regis= ters via a separate memory region mapped into the APB config space rather than directly. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 77 +++++++++++++++++++++++++++++++++--------= ---- hw/sparc64/sun4u.c | 7 ++++- include/hw/pci-host/apb.h | 8 ++++- 3 files changed, 70 insertions(+), 22 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 54ab899..7eb5ce0 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -36,6 +36,7 @@ #include "hw/pci-host/apb.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" +#include "qapi/error.h" #include "qemu/log.h" =20 /* debug APB */ @@ -250,8 +251,8 @@ static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryReg= ion *iommu, hwaddr addr, return ret; } =20 -static void iommu_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void iommu_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { IOMMUState *is =3D opaque; =20 @@ -295,7 +296,7 @@ static void iommu_config_write(void *opaque, hwaddr add= r, } } =20 -static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size) +static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) { IOMMUState *is =3D opaque; uint64_t val; @@ -344,7 +345,6 @@ static void apb_config_writel (void *opaque, hwaddr add= r, uint64_t val, unsigned size) { APBState *s =3D opaque; - IOMMUState *is =3D &s->iommu; =20 APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__,= addr, val); =20 @@ -352,9 +352,6 @@ static void apb_config_writel (void *opaque, hwaddr add= r, case 0x30 ... 0x4f: /* DMA error registers */ /* XXX: not implemented yet */ break; - case 0x200 ... 0x217: /* IOMMU */ - iommu_config_write(is, (addr & 0x1f), val, size); - break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { unsigned int ino =3D (addr & 0x3f) >> 3; @@ -426,7 +423,6 @@ static uint64_t apb_config_readl (void *opaque, hwaddr addr, unsigned size) { APBState *s =3D opaque; - IOMMUState *is =3D &s->iommu; uint32_t val; =20 switch (addr & 0xffff) { @@ -434,9 +430,6 @@ static uint64_t apb_config_readl (void *opaque, val =3D 0; /* XXX: not implemented yet */ break; - case 0x200 ... 0x217: /* IOMMU */ - val =3D iommu_config_read(is, (addr & 0x1f), size); - break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { val =3D s->pci_irq_map[(addr & 0x3f) >> 3]; @@ -641,7 +634,6 @@ static void pci_pbm_realize(DeviceState *dev, Error **e= rrp) PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); PCIDevice *pci_dev; - IOMMUState *is; =20 /* apb_config */ sysbus_mmio_map(sbd, 0, s->special_base); @@ -657,14 +649,9 @@ static void pci_pbm_realize(DeviceState *dev, Error **= errp) pci_create_simple(phb->bus, 0, "pbm-pci"); =20 /* APB IOMMU */ - is =3D &s->iommu; - memset(is, 0, sizeof(IOMMUState)); - - memory_region_init_iommu(&is->iommu, sizeof(is->iommu), - TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(dev), - "iommu-apb", UINT64_MAX); - address_space_init(&is->iommu_as, MEMORY_REGION(&is->iommu), "pbm-as"); - pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is); + memory_region_add_subregion_overlap(&s->apb_config, 0x200, + sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1= ); + pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu); =20 /* APB secondary busses */ pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, @@ -707,6 +694,12 @@ static void pci_pbm_init(Object *obj) s->irq_request =3D NO_IRQ_REQUEST; s->pci_irq_in =3D 0ULL; =20 + /* IOMMU */ + object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, + (Object **) &s->iommu, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + /* apb_config */ memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s, "apb-config", 0x10000); @@ -813,6 +806,49 @@ static const TypeInfo pbm_pci_bridge_info =3D { }, }; =20 +static const MemoryRegionOps iommu_mem_ops =3D { + .read =3D iommu_mem_read, + .write =3D iommu_mem_write, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void iommu_reset(DeviceState *d) +{ + IOMMUState *s =3D SUN4U_IOMMU(d); + + memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); +} + +static void iommu_init(Object *obj) +{ + IOMMUState *s =3D SUN4U_IOMMU(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_iommu(&s->iommu, sizeof(s->iommu), + TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), + "iommu-apb", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); + + memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", + IOMMU_NREGS * sizeof(uint64_t)); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void iommu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D iommu_reset; +} + +static const TypeInfo pbm_iommu_info =3D { + .name =3D TYPE_SUN4U_IOMMU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IOMMUState), + .instance_init =3D iommu_init, + .class_init =3D iommu_class_init, +}; + static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *d= ata) { IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); @@ -831,6 +867,7 @@ static void pbm_register_types(void) type_register_static(&pbm_host_info); type_register_static(&pbm_pci_host_info); type_register_static(&pbm_pci_bridge_info); + type_register_static(&pbm_iommu_info); type_register_static(&pbm_iommu_memory_region_info); } =20 diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 5d802bd..aaee3de 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -469,7 +469,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, PCIDevice *ebus, *pci_dev; SysBusDevice *s; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - DeviceState *dev; + DeviceState *iommu, *dev; FWCfgState *fw_cfg; NICInfo *nd; MACAddr macaddr; @@ -478,6 +478,10 @@ static void sun4uv_init(MemoryRegion *address_space_me= m, /* init CPUs */ cpu =3D sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); =20 + /* IOMMU */ + iommu =3D qdev_create(NULL, TYPE_SUN4U_IOMMU); + qdev_init_nofail(iommu); + /* set up devices */ ram_init(0, machine->ram_size); =20 @@ -487,6 +491,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, apb =3D APB_DEVICE(qdev_create(NULL, TYPE_APB)); qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); + object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_a= bort); qdev_init_nofail(DEVICE(apb)); =20 /* Wire up PCI interrupts to CPU */ diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 6194c8c..33dbc7a 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -44,12 +44,18 @@ #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL =20 typedef struct IOMMUState { + SysBusDevice parent_obj; + AddressSpace iommu_as; IOMMUMemoryRegion iommu; =20 + MemoryRegion iomem; uint64_t regs[IOMMU_NREGS]; } IOMMUState; =20 +#define TYPE_SUN4U_IOMMU "sun4u-iommu" +#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) + #define MAX_IVEC 0x40 =20 /* OBIO IVEC IRQs */ @@ -78,7 +84,7 @@ typedef struct APBState { MemoryRegion pci_mmio; MemoryRegion pci_ioport; uint64_t pci_irq_in; - IOMMUState iommu; + IOMMUState *iommu; PCIBridge *bridgeA; PCIBridge *bridgeB; uint32_t pci_control[16]; --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Sun, 26 Nov 2017 08:35:57 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6J-00050e-11; Sun, 26 Nov 2017 13:36:06 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:23 +0000 Message-Id: <1511703326-25325-6-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 5/8] sun4u: split IOMMU device out from apb.c to sun4u_iommu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" By separating the sun4u IOMMU device into new sun4u_iommu.c and sun4m_iommu= .h files we noticeably simplify apb.c whilst bringing sun4u in line with all t= he other IOMMU-supporting architectures. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 273 ------------------------------- hw/sparc64/Makefile.objs | 1 + hw/sparc64/sun4u.c | 1 + hw/sparc64/sun4u_iommu.c | 350 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci-host/apb.h | 57 +------ include/hw/sparc/sun4u_iommu.h | 50 ++++++ 6 files changed, 403 insertions(+), 329 deletions(-) create mode 100644 hw/sparc64/sun4u_iommu.c create mode 100644 include/hw/sparc/sun4u_iommu.h diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 7eb5ce0..516dc28 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -49,16 +49,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define APB_DPRINTF(fmt, ...) #endif =20 -/* debug IOMMU */ -//#define DEBUG_IOMMU - -#ifdef DEBUG_IOMMU -#define IOMMU_DPRINTF(fmt, ...) \ -do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) -#else -#define IOMMU_DPRINTF(fmt, ...) -#endif - /* * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", @@ -136,211 +126,6 @@ static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, v= oid *opaque, int devfn) return &is->iommu_as; } =20 -/* Called from RCU critical section */ -static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr = addr, - IOMMUAccessFlags flag) -{ - IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); - hwaddr baseaddr, offset; - uint64_t tte; - uint32_t tsbsize; - IOMMUTLBEntry ret =3D { - .target_as =3D &address_space_memory, - .iova =3D 0, - .translated_addr =3D 0, - .addr_mask =3D ~(hwaddr)0, - .perm =3D IOMMU_NONE, - }; - - if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { - /* IOMMU disabled, passthrough using standard 8K page */ - ret.iova =3D addr & IOMMU_PAGE_MASK_8K; - ret.translated_addr =3D addr; - ret.addr_mask =3D IOMMU_PAGE_MASK_8K; - ret.perm =3D IOMMU_RW; - - return ret; - } - - baseaddr =3D is->regs[IOMMU_BASE >> 3]; - tsbsize =3D (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; - - if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { - /* 64K */ - switch (tsbsize) { - case 0: - offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; - break; - case 1: - offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; - break; - case 2: - offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; - break; - case 3: - offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; - break; - case 4: - offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; - break; - case 5: - offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; - break; - default: - /* Not implemented, error */ - return ret; - } - } else { - /* 8K */ - switch (tsbsize) { - case 0: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10; - break; - case 1: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10; - break; - case 2: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10; - break; - case 3: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10; - break; - case 4: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10; - break; - case 5: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10; - break; - case 6: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10; - break; - case 7: - offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10; - break; - } - } - - tte =3D address_space_ldq_be(&address_space_memory, baseaddr + offset, - MEMTXATTRS_UNSPECIFIED, NULL); - - if (!(tte & IOMMU_TTE_DATA_V)) { - /* Invalid mapping */ - return ret; - } - - if (tte & IOMMU_TTE_DATA_W) { - /* Writeable */ - ret.perm =3D IOMMU_RW; - } else { - ret.perm =3D IOMMU_RO; - } - - /* Extract phys */ - if (tte & IOMMU_TTE_DATA_SIZE) { - /* 64K */ - ret.iova =3D addr & IOMMU_PAGE_MASK_64K; - ret.translated_addr =3D tte & IOMMU_TTE_PHYS_MASK_64K; - ret.addr_mask =3D (IOMMU_PAGE_SIZE_64K - 1); - } else { - /* 8K */ - ret.iova =3D addr & IOMMU_PAGE_MASK_8K; - ret.translated_addr =3D tte & IOMMU_TTE_PHYS_MASK_8K; - ret.addr_mask =3D (IOMMU_PAGE_SIZE_8K - 1); - } - - return ret; -} - -static void iommu_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - IOMMUState *is =3D opaque; - - IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 - " size: %d\n", addr, val, size); - - switch (addr) { - case IOMMU_CTRL: - if (size =3D=3D 4) { - is->regs[IOMMU_CTRL >> 3] &=3D 0xffffffffULL; - is->regs[IOMMU_CTRL >> 3] |=3D val << 32; - } else { - is->regs[IOMMU_CTRL >> 3] =3D val; - } - break; - case IOMMU_CTRL + 0x4: - is->regs[IOMMU_CTRL >> 3] &=3D 0xffffffff00000000ULL; - is->regs[IOMMU_CTRL >> 3] |=3D val & 0xffffffffULL; - break; - case IOMMU_BASE: - if (size =3D=3D 4) { - is->regs[IOMMU_BASE >> 3] &=3D 0xffffffffULL; - is->regs[IOMMU_BASE >> 3] |=3D val << 32; - } else { - is->regs[IOMMU_BASE >> 3] =3D val; - } - break; - case IOMMU_BASE + 0x4: - is->regs[IOMMU_BASE >> 3] &=3D 0xffffffff00000000ULL; - is->regs[IOMMU_BASE >> 3] |=3D val & 0xffffffffULL; - break; - case IOMMU_FLUSH: - case IOMMU_FLUSH + 0x4: - break; - default: - qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register write " - "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", - addr, size, val); - break; - } -} - -static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) -{ - IOMMUState *is =3D opaque; - uint64_t val; - - switch (addr) { - case IOMMU_CTRL: - if (size =3D=3D 4) { - val =3D is->regs[IOMMU_CTRL >> 3] >> 32; - } else { - val =3D is->regs[IOMMU_CTRL >> 3]; - } - break; - case IOMMU_CTRL + 0x4: - val =3D is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; - break; - case IOMMU_BASE: - if (size =3D=3D 4) { - val =3D is->regs[IOMMU_BASE >> 3] >> 32; - } else { - val =3D is->regs[IOMMU_BASE >> 3]; - } - break; - case IOMMU_BASE + 0x4: - val =3D is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; - break; - case IOMMU_FLUSH: - case IOMMU_FLUSH + 0x4: - val =3D 0; - break; - default: - qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register read " - "reg 0x%" HWADDR_PRIx " size 0x%x\n", - addr, size); - val =3D 0; - break; - } - - IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 - " size: %d\n", addr, val, size); - - return val; -} - static void apb_config_writel (void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -806,69 +591,11 @@ static const TypeInfo pbm_pci_bridge_info =3D { }, }; =20 -static const MemoryRegionOps iommu_mem_ops =3D { - .read =3D iommu_mem_read, - .write =3D iommu_mem_write, - .endianness =3D DEVICE_BIG_ENDIAN, -}; - -static void iommu_reset(DeviceState *d) -{ - IOMMUState *s =3D SUN4U_IOMMU(d); - - memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); -} - -static void iommu_init(Object *obj) -{ - IOMMUState *s =3D SUN4U_IOMMU(obj); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - - memory_region_init_iommu(&s->iommu, sizeof(s->iommu), - TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), - "iommu-apb", UINT64_MAX); - address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); - - memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", - IOMMU_NREGS * sizeof(uint64_t)); - sysbus_init_mmio(sbd, &s->iomem); -} - -static void iommu_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->reset =3D iommu_reset; -} - -static const TypeInfo pbm_iommu_info =3D { - .name =3D TYPE_SUN4U_IOMMU, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(IOMMUState), - .instance_init =3D iommu_init, - .class_init =3D iommu_class_init, -}; - -static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *d= ata) -{ - IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); - - imrc->translate =3D pbm_translate_iommu; -} - -static const TypeInfo pbm_iommu_memory_region_info =3D { - .parent =3D TYPE_IOMMU_MEMORY_REGION, - .name =3D TYPE_APB_IOMMU_MEMORY_REGION, - .class_init =3D pbm_iommu_memory_region_class_init, -}; - static void pbm_register_types(void) { type_register_static(&pbm_host_info); type_register_static(&pbm_pci_host_info); type_register_static(&pbm_pci_bridge_info); - type_register_static(&pbm_iommu_info); - type_register_static(&pbm_iommu_memory_region_info); } =20 type_init(pbm_register_types) diff --git a/hw/sparc64/Makefile.objs b/hw/sparc64/Makefile.objs index cf9de21..117e0ff 100644 --- a/hw/sparc64/Makefile.objs +++ b/hw/sparc64/Makefile.objs @@ -1,3 +1,4 @@ obj-y +=3D sparc64.o +obj-y +=3D sun4u_iommu.o obj-y +=3D sun4u.o obj-y +=3D niagara.o \ No newline at end of file diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index aaee3de..ec45ec2 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -29,6 +29,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pci_host.h" #include "hw/pci-host/apb.h" #include "hw/i386/pc.h" #include "hw/char/serial.h" diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c new file mode 100644 index 0000000..e5aa817 --- /dev/null +++ b/hw/sparc64/sun4u_iommu.c @@ -0,0 +1,350 @@ +/* + * QEMU sun4u IOMMU emulation + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/sparc/sun4u_iommu.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "qemu/log.h" + +/* debug IOMMU */ +//#define DEBUG_IOMMU + +#ifdef DEBUG_IOMMU +#define IOMMU_DPRINTF(fmt, ...) \ +do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) +#else +#define IOMMU_DPRINTF(fmt, ...) +#endif + + +#define IOMMU_PAGE_SIZE_8K (1ULL << 13) +#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) +#define IOMMU_PAGE_SIZE_64K (1ULL << 16) +#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) + +#define IOMMU_CTRL 0x0 +#define IOMMU_CTRL_TBW_SIZE (1ULL << 2) +#define IOMMU_CTRL_MMU_EN (1ULL) + +#define IOMMU_CTRL_TSB_SHIFT 16 + +#define IOMMU_BASE 0x8 +#define IOMMU_FLUSH 0x10 + +#define IOMMU_TTE_DATA_V (1ULL << 63) +#define IOMMU_TTE_DATA_SIZE (1ULL << 61) +#define IOMMU_TTE_DATA_W (1ULL << 1) + +#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL +#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL + +#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL + +#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL + + +/* Called from RCU critical section */ +static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr = addr, + IOMMUAccessFlags flag) +{ + IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); + hwaddr baseaddr, offset; + uint64_t tte; + uint32_t tsbsize; + IOMMUTLBEntry ret =3D { + .target_as =3D &address_space_memory, + .iova =3D 0, + .translated_addr =3D 0, + .addr_mask =3D ~(hwaddr)0, + .perm =3D IOMMU_NONE, + }; + + if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { + /* IOMMU disabled, passthrough using standard 8K page */ + ret.iova =3D addr & IOMMU_PAGE_MASK_8K; + ret.translated_addr =3D addr; + ret.addr_mask =3D IOMMU_PAGE_MASK_8K; + ret.perm =3D IOMMU_RW; + + return ret; + } + + baseaddr =3D is->regs[IOMMU_BASE >> 3]; + tsbsize =3D (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; + + if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { + /* 64K */ + switch (tsbsize) { + case 0: + offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; + break; + case 1: + offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; + break; + case 2: + offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; + break; + case 3: + offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; + break; + case 4: + offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; + break; + case 5: + offset =3D (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; + break; + default: + /* Not implemented, error */ + return ret; + } + } else { + /* 8K */ + switch (tsbsize) { + case 0: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10; + break; + case 1: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10; + break; + case 2: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10; + break; + case 3: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10; + break; + case 4: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10; + break; + case 5: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10; + break; + case 6: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10; + break; + case 7: + offset =3D (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10; + break; + } + } + + tte =3D address_space_ldq_be(&address_space_memory, baseaddr + offset, + MEMTXATTRS_UNSPECIFIED, NULL); + + if (!(tte & IOMMU_TTE_DATA_V)) { + /* Invalid mapping */ + return ret; + } + + if (tte & IOMMU_TTE_DATA_W) { + /* Writeable */ + ret.perm =3D IOMMU_RW; + } else { + ret.perm =3D IOMMU_RO; + } + + /* Extract phys */ + if (tte & IOMMU_TTE_DATA_SIZE) { + /* 64K */ + ret.iova =3D addr & IOMMU_PAGE_MASK_64K; + ret.translated_addr =3D tte & IOMMU_TTE_PHYS_MASK_64K; + ret.addr_mask =3D (IOMMU_PAGE_SIZE_64K - 1); + } else { + /* 8K */ + ret.iova =3D addr & IOMMU_PAGE_MASK_8K; + ret.translated_addr =3D tte & IOMMU_TTE_PHYS_MASK_8K; + ret.addr_mask =3D (IOMMU_PAGE_SIZE_8K - 1); + } + + return ret; +} + +static void iommu_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + IOMMUState *is =3D opaque; + + IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 + " size: %d\n", addr, val, size); + + switch (addr) { + case IOMMU_CTRL: + if (size =3D=3D 4) { + is->regs[IOMMU_CTRL >> 3] &=3D 0xffffffffULL; + is->regs[IOMMU_CTRL >> 3] |=3D val << 32; + } else { + is->regs[IOMMU_CTRL >> 3] =3D val; + } + break; + case IOMMU_CTRL + 0x4: + is->regs[IOMMU_CTRL >> 3] &=3D 0xffffffff00000000ULL; + is->regs[IOMMU_CTRL >> 3] |=3D val & 0xffffffffULL; + break; + case IOMMU_BASE: + if (size =3D=3D 4) { + is->regs[IOMMU_BASE >> 3] &=3D 0xffffffffULL; + is->regs[IOMMU_BASE >> 3] |=3D val << 32; + } else { + is->regs[IOMMU_BASE >> 3] =3D val; + } + break; + case IOMMU_BASE + 0x4: + is->regs[IOMMU_BASE >> 3] &=3D 0xffffffff00000000ULL; + is->regs[IOMMU_BASE >> 3] |=3D val & 0xffffffffULL; + break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + break; + default: + qemu_log_mask(LOG_UNIMP, + "apb iommu: Unimplemented register write " + "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", + addr, size, val); + break; + } +} + +static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + IOMMUState *is =3D opaque; + uint64_t val; + + switch (addr) { + case IOMMU_CTRL: + if (size =3D=3D 4) { + val =3D is->regs[IOMMU_CTRL >> 3] >> 32; + } else { + val =3D is->regs[IOMMU_CTRL >> 3]; + } + break; + case IOMMU_CTRL + 0x4: + val =3D is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; + break; + case IOMMU_BASE: + if (size =3D=3D 4) { + val =3D is->regs[IOMMU_BASE >> 3] >> 32; + } else { + val =3D is->regs[IOMMU_BASE >> 3]; + } + break; + case IOMMU_BASE + 0x4: + val =3D is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; + break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + val =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, + "apb iommu: Unimplemented register read " + "reg 0x%" HWADDR_PRIx " size 0x%x\n", + addr, size); + val =3D 0; + break; + } + + IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 + " size: %d\n", addr, val, size); + + return val; +} + +static const MemoryRegionOps iommu_mem_ops =3D { + .read =3D iommu_mem_read, + .write =3D iommu_mem_write, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static void iommu_reset(DeviceState *d) +{ + IOMMUState *s =3D SUN4U_IOMMU(d); + + memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); +} + +static void iommu_init(Object *obj) +{ + IOMMUState *s =3D SUN4U_IOMMU(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_iommu(&s->iommu, sizeof(s->iommu), + TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), + "iommu-apb", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); + + memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", + IOMMU_NREGS * sizeof(uint64_t)); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void iommu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D iommu_reset; +} + +static const TypeInfo pbm_iommu_info =3D { + .name =3D TYPE_SUN4U_IOMMU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IOMMUState), + .instance_init =3D iommu_init, + .class_init =3D iommu_class_init, +}; + +static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *d= ata) +{ + IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); + + imrc->translate =3D pbm_translate_iommu; +} + +static const TypeInfo pbm_iommu_memory_region_info =3D { + .parent =3D TYPE_IOMMU_MEMORY_REGION, + .name =3D TYPE_APB_IOMMU_MEMORY_REGION, + .class_init =3D pbm_iommu_memory_region_class_init, +}; + +static void pbm_register_types(void) +{ + type_register_static(&pbm_iommu_info); + type_register_static(&pbm_iommu_memory_region_info); +} + +type_init(pbm_register_types) diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 33dbc7a..604d899 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -1,60 +1,7 @@ #ifndef PCI_HOST_APB_H #define PCI_HOST_APB_H =20 -#include "qemu-common.h" -#include "hw/pci/pci_host.h" - -#define IOMMU_NREGS 3 - -#define IOMMU_PAGE_SIZE_8K (1ULL << 13) -#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) -#define IOMMU_PAGE_SIZE_64K (1ULL << 16) -#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) - -#define IOMMU_CTRL 0x0 -#define IOMMU_CTRL_TBW_SIZE (1ULL << 2) -#define IOMMU_CTRL_MMU_EN (1ULL) - -#define IOMMU_CTRL_TSB_SHIFT 16 - -#define IOMMU_BASE 0x8 -#define IOMMU_FLUSH 0x10 - -#define IOMMU_TTE_DATA_V (1ULL << 63) -#define IOMMU_TTE_DATA_SIZE (1ULL << 61) -#define IOMMU_TTE_DATA_W (1ULL << 1) - -#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL -#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL - -#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL - -#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL - -typedef struct IOMMUState { - SysBusDevice parent_obj; - - AddressSpace iommu_as; - IOMMUMemoryRegion iommu; - - MemoryRegion iomem; - uint64_t regs[IOMMU_NREGS]; -} IOMMUState; - -#define TYPE_SUN4U_IOMMU "sun4u-iommu" -#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) +#include "hw/sparc/sun4u_iommu.h" =20 #define MAX_IVEC 0x40 =20 @@ -72,8 +19,6 @@ typedef struct IOMMUState { #define APB_DEVICE(obj) \ OBJECT_CHECK(APBState, (obj), TYPE_APB) =20 -#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" - typedef struct APBState { PCIHostState parent_obj; =20 diff --git a/include/hw/sparc/sun4u_iommu.h b/include/hw/sparc/sun4u_iommu.h new file mode 100644 index 0000000..bc4506b --- /dev/null +++ b/include/hw/sparc/sun4u_iommu.h @@ -0,0 +1,50 @@ +/* + * QEMU sun4u IOMMU emulation + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef SUN4U_IOMMU_H +#define SUN4U_IOMMU_H + +#include "qemu-common.h" +#include "hw/sysbus.h" + +#define IOMMU_NREGS 3 + +typedef struct IOMMUState { + SysBusDevice parent_obj; + + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + MemoryRegion iomem; + uint64_t regs[IOMMU_NREGS]; +} IOMMUState; + +#define TYPE_SUN4U_IOMMU "sun4u-iommu" +#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) + +#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" + +#endif --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511703638068305.6173150473659; Sun, 26 Nov 2017 05:40:38 -0800 (PST) Received: from localhost ([::1]:56751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIxAh-00041F-CN for importer@patchew.org; Sun, 26 Nov 2017 08:40:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6J-0000U5-4G for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx6F-0006gM-5M for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:03 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48808 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx6E-0006g4-UV for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:35:59 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6M-00050e-GR; Sun, 26 Nov 2017 13:36:07 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:24 +0000 Message-Id: <1511703326-25325-7-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 6/8] sun4u_iommu: update to reflect IOMMU is no longer part of the APB device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc64/sun4u_iommu.c | 35 ++++++++++++++++++----------------- include/hw/sparc/sun4u_iommu.h | 2 +- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index e5aa817..612fec4 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -81,8 +81,9 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) =20 =20 /* Called from RCU critical section */ -static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr = addr, - IOMMUAccessFlags flag) +static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, + hwaddr addr, + IOMMUAccessFlags flag) { IOMMUState *is =3D container_of(iommu, IOMMUState, iommu); hwaddr baseaddr, offset; @@ -233,7 +234,7 @@ static void iommu_mem_write(void *opaque, hwaddr addr, break; default: qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register write " + "sun4u-iommu: Unimplemented register write " "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", addr, size, val); break; @@ -272,7 +273,7 @@ static uint64_t iommu_mem_read(void *opaque, hwaddr add= r, unsigned size) break; default: qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register read " + "sun4u-iommu: Unimplemented register read " "reg 0x%" HWADDR_PRIx " size 0x%x\n", addr, size); val =3D 0; @@ -304,9 +305,9 @@ static void iommu_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 memory_region_init_iommu(&s->iommu, sizeof(s->iommu), - TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), - "iommu-apb", UINT64_MAX); - address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); + TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s), + "iommu-sun4u", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); =20 memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", IOMMU_NREGS * sizeof(uint64_t)); @@ -320,7 +321,7 @@ static void iommu_class_init(ObjectClass *klass, void *= data) dc->reset =3D iommu_reset; } =20 -static const TypeInfo pbm_iommu_info =3D { +static const TypeInfo iommu_info =3D { .name =3D TYPE_SUN4U_IOMMU, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(IOMMUState), @@ -328,23 +329,23 @@ static const TypeInfo pbm_iommu_info =3D { .class_init =3D iommu_class_init, }; =20 -static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *d= ata) +static void sun4u_iommu_memory_region_class_init(ObjectClass *klass, void = *data) { IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); =20 - imrc->translate =3D pbm_translate_iommu; + imrc->translate =3D sun4u_translate_iommu; } =20 -static const TypeInfo pbm_iommu_memory_region_info =3D { +static const TypeInfo sun4u_iommu_memory_region_info =3D { .parent =3D TYPE_IOMMU_MEMORY_REGION, - .name =3D TYPE_APB_IOMMU_MEMORY_REGION, - .class_init =3D pbm_iommu_memory_region_class_init, + .name =3D TYPE_SUN4U_IOMMU_MEMORY_REGION, + .class_init =3D sun4u_iommu_memory_region_class_init, }; =20 -static void pbm_register_types(void) +static void iommu_register_types(void) { - type_register_static(&pbm_iommu_info); - type_register_static(&pbm_iommu_memory_region_info); + type_register_static(&iommu_info); + type_register_static(&sun4u_iommu_memory_region_info); } =20 -type_init(pbm_register_types) +type_init(iommu_register_types) diff --git a/include/hw/sparc/sun4u_iommu.h b/include/hw/sparc/sun4u_iommu.h index bc4506b..a760172 100644 --- a/include/hw/sparc/sun4u_iommu.h +++ b/include/hw/sparc/sun4u_iommu.h @@ -45,6 +45,6 @@ typedef struct IOMMUState { #define TYPE_SUN4U_IOMMU "sun4u-iommu" #define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) =20 -#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" +#define TYPE_SUN4U_IOMMU_MEMORY_REGION "sun4u-iommu-memory-region" =20 #endif --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511703507518516.7278012192907; Sun, 26 Nov 2017 05:38:27 -0800 (PST) Received: from localhost ([::1]:56734 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx8U-0002IH-Pe for importer@patchew.org; Sun, 26 Nov 2017 08:38:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34153) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6J-0000U0-3m for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx6G-0006gv-Sb for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:03 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48810 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx6G-0006gc-Ll for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:00 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6N-00050e-UK; Sun, 26 Nov 2017 13:36:09 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:25 +0000 Message-Id: <1511703326-25325-8-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 7/8] sun4u_iommu: convert from IOMMU_DPRINTF to trace-events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc64/sun4u_iommu.c | 17 +++-------------- hw/sparc64/trace-events | 4 ++++ 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index 612fec4..51fbc39 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -30,16 +30,7 @@ #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" - -/* debug IOMMU */ -//#define DEBUG_IOMMU - -#ifdef DEBUG_IOMMU -#define IOMMU_DPRINTF(fmt, ...) \ -do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) -#else -#define IOMMU_DPRINTF(fmt, ...) -#endif +#include "trace.h" =20 =20 #define IOMMU_PAGE_SIZE_8K (1ULL << 13) @@ -201,8 +192,7 @@ static void iommu_mem_write(void *opaque, hwaddr addr, { IOMMUState *is =3D opaque; =20 - IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 - " size: %d\n", addr, val, size); + trace_sun4u_iommu_mem_write(addr, val, size); =20 switch (addr) { case IOMMU_CTRL: @@ -280,8 +270,7 @@ static uint64_t iommu_mem_read(void *opaque, hwaddr add= r, unsigned size) break; } =20 - IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 - " size: %d\n", addr, val, size); + trace_sun4u_iommu_mem_read(addr, val, size); =20 return val; } diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index 04d80b7..052352f 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -2,3 +2,7 @@ =20 # hw/sparc64/sun4u.c ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d" + +# hw/sparc64/sun4u_iommu.c +sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRI= x64" val: 0x%"PRIx64" size: %d" +sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PR= Ix64" val: 0x%"PRIx64" size: %d" --=20 1.7.10.4 From nobody Sun Apr 28 05:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151170387437651.99278861709513; Sun, 26 Nov 2017 05:44:34 -0800 (PST) Received: from localhost ([::1]:56767 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIxEN-0006eg-Oy for importer@patchew.org; Sun, 26 Nov 2017 08:44:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eIx6J-0000U3-3x for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eIx6H-0006hr-Px for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:03 -0500 Received: from chuckie.co.uk ([82.165.15.123]:48813 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eIx6H-0006gz-JG for qemu-devel@nongnu.org; Sun, 26 Nov 2017 08:36:01 -0500 Received: from host86-189-155-83.range86-189.btcentralplus.com ([86.189.155.83] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1eIx6P-00050e-L9; Sun, 26 Nov 2017 13:36:10 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Sun, 26 Nov 2017 13:35:26 +0000 Message-Id: <1511703326-25325-9-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1511703326-25325-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.189.155.83 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 8/8] sun4u_iommu: add trace event for IOMMU translations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc64/sun4u_iommu.c | 2 ++ hw/sparc64/trace-events | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index 51fbc39..4cf8e69 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -184,6 +184,8 @@ static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryR= egion *iommu, ret.addr_mask =3D (IOMMU_PAGE_SIZE_8K - 1); } =20 + trace_sun4u_iommu_translate(ret.iova, ret.translated_addr, tte); + return ret; } =20 diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index 052352f..2ee2d75 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -6,3 +6,4 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d leve= l %d" # hw/sparc64/sun4u_iommu.c sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRI= x64" val: 0x%"PRIx64" size: %d" sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PR= Ix64" val: 0x%"PRIx64" size: %d" +sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "x= late 0x%"PRIx64" =3D> pa 0x%"PRIx64" tte: 0x%"PRIx64 --=20 1.7.10.4