From nobody Wed May 1 17:17:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511199576605245.45158973096795; Mon, 20 Nov 2017 09:39:36 -0800 (PST) Received: from localhost ([::1]:58586 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq2P-0000r6-QR for importer@patchew.org; Mon, 20 Nov 2017 12:39:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq0h-0008HK-7N for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGq0f-0006Id-Sm for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:31 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38456) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGq0f-0006HX-Lb for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:29 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eGq0c-0006Md-7R for qemu-devel@nongnu.org; Mon, 20 Nov 2017 17:37:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 17:37:20 +0000 Message-Id: <1511199444-17922-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> References: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/5] target/arm: Report GICv3 sysregs present in ID registers if needed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The CPU ID registers ID_AA64PFR0_EL1, ID_PFR1_EL1 and ID_PFR1 have a field for reporting presence of GICv3 system registers. We need to report this field correctly in order for Xen to work as a guest inside QEMU emulation. We mustn't incorrectly claim the sysregs exist when they don't, though, or Linux will crash. Unfortunately the way we've designed the GICv3 emulation in QEMU puts the system registers as part of the GICv3 device, which may be created after the CPU proper has been realized. This means that we don't know at the point when we define the ID registers what the correct value is. Handle this by switching them to calling a function at runtime to read the value, where we can fill in the GIC field appropriately. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Stefano Stabellini Message-id: 1510066898-3725-1-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f61fb3e..35c5bd6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4549,6 +4549,33 @@ static void define_debug_regs(ARMCPU *cpu) } } =20 +/* We don't know until after realize whether there's a GICv3 + * attached, and that is what registers the gicv3 sysregs. + * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 + * at runtime. + */ +static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint64_t pfr1 =3D cpu->id_pfr1; + + if (env->gicv3state) { + pfr1 |=3D 1 << 28; + } + return pfr1; +} + +static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint64_t pfr0 =3D cpu->id_aa64pfr0; + + if (env->gicv3state) { + pfr0 |=3D 1 << 24; + } + return pfr0; +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -4573,10 +4600,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_pfr0 }, + /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know + * the value of the GIC field until after we define these regs. + */ { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_pfr1 }, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + .readfn =3D id_pfr1_read, + .writefn =3D arm_cp_write_ignore }, { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -4692,10 +4723,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] =3D { + /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't + * know the right value for the GIC field until after we + * define these regs. + */ { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64pfr0 }, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + .readfn =3D id_aa64pfr0_read, + .writefn =3D arm_cp_write_ignore }, { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.7.4 From nobody Wed May 1 17:17:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511199578292836.4827405206274; Mon, 20 Nov 2017 09:39:38 -0800 (PST) Received: from localhost ([::1]:58584 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq2K-0000oP-5I for importer@patchew.org; Mon, 20 Nov 2017 12:39:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37465) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq0f-0008Gk-CT for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGq0e-0006Hs-Ke for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:29 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38454) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGq0e-0006H1-DG for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:28 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eGq0d-0006N8-1q for qemu-devel@nongnu.org; Mon, 20 Nov 2017 17:37:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 17:37:21 +0000 Message-Id: <1511199444-17922-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> References: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/5] nvic: Fix ARMv7M MPU_RBAR reads X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Fix an incorrect mask expression in the handling of v7M MPU_RBAR reads that meant that we would always report the ADDR field as zero. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-id: 1509732813-22957-1-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index be46639..5d9c883 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) if (region >=3D cpu->pmsav7_dregion) { return 0; } - return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); + return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf); } case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ --=20 2.7.4 From nobody Wed May 1 17:17:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511199687676327.3987655778267; Mon, 20 Nov 2017 09:41:27 -0800 (PST) Received: from localhost ([::1]:58600 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq4K-0002TK-TE for importer@patchew.org; Mon, 20 Nov 2017 12:41:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq0f-0008Gt-Tl for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGq0e-0006I6-V4 for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:29 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38456) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGq0e-0006HX-N4 for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:28 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eGq0d-0006Ne-Li for qemu-devel@nongnu.org; Mon, 20 Nov 2017 17:37:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 17:37:22 +0000 Message-Id: <1511199444-17922-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> References: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/5] arm: check regime, not current state, for ATS write PAR format X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In do_ats_write(), rather than using extended_addresses_enabled() to decide whether the value we get back from get_phys_addr() is a 64-bit format PAR or a 32-bit one, use arm_s1_regime_using_lpae_format(). This is not really the correct answer, because the PAR format depends on the AT instruction being used, not just on the translation regime. However getting this correct requires a significant refactoring, so that get_phys_addr() returns raw information about the fault which the caller can then assemble into a suitable FSR/PAR/syndrome for its purposes, rather than get_phys_addr() returning a pre-formatted FSR. However this change at least improves the situation by making the PAR work correctly for address translation operations done at AArch64 EL2 on the EL2 translation regime. In particular, this is necessary for Xen to be able to run in our emulation, so this seems like a safer interim fix given that we are in freeze. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Benn=C3=A9e Tested-by: Stefano Stabellini Message-id: 1509719814-6191-1-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 35c5bd6..91a9300 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2169,7 +2169,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, =20 ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, &prot, &page_size, &fsr, &fi, &cacheattrs); - if (extended_addresses_enabled(env)) { + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { /* fsr is a DFSR/IFSR value for the long descriptor * translation table format, but with WnR always clear. * Convert it to a 64-bit PAR. --=20 2.7.4 From nobody Wed May 1 17:17:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511199686677657.4528852499036; Mon, 20 Nov 2017 09:41:26 -0800 (PST) Received: from localhost ([::1]:58601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq4K-0002TQ-Ue for importer@patchew.org; Mon, 20 Nov 2017 12:41:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq0g-0008HH-Qb for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGq0f-0006IQ-K7 for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:30 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38454) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGq0f-0006H1-Bf for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:29 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eGq0e-0006Nv-Am for qemu-devel@nongnu.org; Mon, 20 Nov 2017 17:37:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 17:37:23 +0000 Message-Id: <1511199444-17922-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> References: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/5] hw/arm/aspeed: Unlock SCU when running kernel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Joel Stanley The ASPEED hardware contains a lock register for the SCU that disables any writes to the SCU when it is locked. The machine comes up with the lock enabled, but on all known hardware u-boot will unlock it and leave it unlocked when loading the kernel. This means the kernel expects the SCU to be unlocked. When booting from an emulated ROM the normal u-boot unlock path is executed. Things don't go well when booting using the -kernel command line, as u-boot does not run first. Change behaviour so that when a kernel is passed to the machine, set the reset value of the SCU to be unlocked. Signed-off-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Message-id: 20171114122018.12204-1-joel@jms.id.au Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_scu.h | 3 +++ hw/arm/aspeed.c | 9 +++++++++ hw/arm/aspeed_soc.c | 2 ++ hw/misc/aspeed_scu.c | 5 +++-- 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index bd4ac01..d70cc0a 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -29,6 +29,7 @@ typedef struct AspeedSCUState { uint32_t silicon_rev; uint32_t hw_strap1; uint32_t hw_strap2; + uint32_t hw_prot_key; } AspeedSCUState; =20 #define AST2400_A0_SILICON_REV 0x02000303U @@ -38,6 +39,8 @@ typedef struct AspeedSCUState { =20 extern bool is_supported_silicon_rev(uint32_t silicon_rev); =20 +#define ASPEED_SCU_PROT_KEY 0x1688A8A8 + /* * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions * were added. diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index ab895ad..7088c90 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -186,6 +186,15 @@ static void aspeed_board_init(MachineState *machine, &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", &error_abort); + if (machine->kernel_filename) { + /* + * When booting with a -kernel command line there is no u-boot + * that runs to unlock the SCU. In this case set the default to + * be unlocked as the kernel expects + */ + object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY, + "hw-prot-key", &error_abort); + } object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); =20 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 5aa3d2d..c83b7e2 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -154,6 +154,8 @@ static void aspeed_soc_init(Object *obj) "hw-strap1", &error_abort); object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); + object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), + "hw-prot-key", &error_abort); =20 object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 95022d3..74537ce 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -85,7 +85,6 @@ #define BMC_REV TO_REG(0x19C) #define BMC_DEV_ID TO_REG(0x1A4) =20 -#define PROT_KEY_UNLOCK 0x1688A8A8 #define SCU_IO_REGION_SIZE 0x1000 =20 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] =3D { @@ -192,7 +191,7 @@ static void aspeed_scu_write(void *opaque, hwaddr offse= t, uint64_t data, } =20 if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && - s->regs[PROT_KEY] !=3D PROT_KEY_UNLOCK) { + s->regs[PROT_KEY] !=3D ASPEED_SCU_PROT_KEY) { qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); return; } @@ -246,6 +245,7 @@ static void aspeed_scu_reset(DeviceState *dev) s->regs[SILICON_REV] =3D s->silicon_rev; s->regs[HW_STRAP1] =3D s->hw_strap1; s->regs[HW_STRAP2] =3D s->hw_strap2; + s->regs[PROT_KEY] =3D s->hw_prot_key; } =20 static uint32_t aspeed_silicon_revs[] =3D { @@ -299,6 +299,7 @@ static Property aspeed_scu_properties[] =3D { DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0), DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), + DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.7.4 From nobody Wed May 1 17:17:59 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1511199799272584.966239234287; Mon, 20 Nov 2017 09:43:19 -0800 (PST) Received: from localhost ([::1]:58609 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq69-0003jf-BQ for importer@patchew.org; Mon, 20 Nov 2017 12:43:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eGq0h-0008HS-DA for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eGq0g-0006Iv-6L for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:31 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eGq0f-0006IH-V8 for qemu-devel@nongnu.org; Mon, 20 Nov 2017 12:37:30 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eGq0e-0006OP-UC for qemu-devel@nongnu.org; Mon, 20 Nov 2017 17:37:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 20 Nov 2017 17:37:24 +0000 Message-Id: <1511199444-17922-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> References: <1511199444-17922-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/5] hw/arm: Silence xlnx-ep108 deprecation warning during tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Thomas Huth The new deprecation warning for the xlnx-ep108 machine also pops up during "make check" which is kind of confusing. Silence it if testing mode is enabled. Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Acked-by: Wei Huang Message-id: 1510846183-756-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 9631a53..bbe7d04 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -24,6 +24,7 @@ #include "qemu/error-report.h" #include "exec/address-spaces.h" #include "qemu/log.h" +#include "sysemu/qtest.h" =20 typedef struct XlnxZCU102 { MachineState parent_obj; @@ -164,8 +165,10 @@ static void xlnx_ep108_init(MachineState *machine) { XlnxZCU102 *s =3D EP108_MACHINE(machine); =20 - info_report("The Xilinx EP108 machine is deprecated, please use the " - "ZCU102 machine instead. It has the same features supporte= d."); + if (!qtest_enabled()) { + info_report("The Xilinx EP108 machine is deprecated, please use th= e " + "ZCU102 machine (which has the same features) instead.= "); + } =20 xlnx_zynqmp_init(s, machine); } --=20 2.7.4