From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668949353581.7540250234961; Sun, 17 Sep 2017 10:22:29 -0700 (PDT) Received: from localhost ([::1]:33118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdH0-0002f4-N0 for importer@patchew.org; Sun, 17 Sep 2017 13:22:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAy-00065N-Lx for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAt-0006A8-NI for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:12 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39948 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAt-00068u-GF; Sun, 17 Sep 2017 13:16:07 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAr-0005RD-5L; Sun, 17 Sep 2017 18:16:06 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:41 +0100 Message-Id: <1505668548-16616-2-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 1/8] ppc: QOMify g3beige machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/mac_oldworld.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index fcac399..5d1171d 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -380,8 +380,10 @@ static int heathrow_kvm_type(const char *arg) return 2; } =20 -static void heathrow_machine_init(MachineClass *mc) +static void heathrow_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "Heathrow based PowerMAC"; mc->init =3D ppc_heathrow_init; mc->block_default_type =3D IF_IDE; @@ -394,4 +396,15 @@ static void heathrow_machine_init(MachineClass *mc) mc->kvm_type =3D heathrow_kvm_type; } =20 -DEFINE_MACHINE("g3beige", heathrow_machine_init) +static const TypeInfo ppc_heathrow_machine_info =3D { + .name =3D MACHINE_TYPE_NAME("g3beige"), + .parent =3D TYPE_MACHINE, + .class_init =3D heathrow_class_init +}; + +static void ppc_heathrow_register_types(void) +{ + type_register_static(&ppc_heathrow_machine_info); +} + +type_init(ppc_heathrow_register_types); --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505669035147766.7415009937846; Sun, 17 Sep 2017 10:23:55 -0700 (PDT) Received: from localhost ([::1]:33127 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdIQ-0003kR-AO for importer@patchew.org; Sun, 17 Sep 2017 13:23:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAy-00065M-Lz for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAt-0006AZ-R3 for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:12 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39955 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAt-00069Y-Jn; Sun, 17 Sep 2017 13:16:07 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAs-0005RD-Bc; Sun, 17 Sep 2017 18:16:07 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:42 +0100 Message-Id: <1505668548-16616-3-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 2/8] ppc/mac: Advertise a high clock frequency for NewWorld Macs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt We use 900Mhz, otherwise MacOS X 10.5 refuses to install. Signed-off-by: Benjamin Herrenschmidt --- hw/ppc/mac_newworld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index d466634..c581d96 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -77,7 +77,7 @@ #define MAX_IDE_BUS 2 #define CFG_ADDR 0xf0000510 #define TBFREQ (100UL * 1000UL * 1000UL) -#define CLOCKFREQ (266UL * 1000UL * 1000UL) +#define CLOCKFREQ (900UL * 1000UL * 1000UL) #define BUSFREQ (100UL * 1000UL * 1000UL) =20 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668695681659.3715714878671; Sun, 17 Sep 2017 10:18:15 -0700 (PDT) Received: from localhost ([::1]:33095 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdCw-0007YX-PW for importer@patchew.org; Sun, 17 Sep 2017 13:18:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAy-00065O-MT for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAt-0006AC-NS for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:12 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39954 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAt-00069H-GJ; Sun, 17 Sep 2017 13:16:07 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAt-0005RD-Ju; Sun, 17 Sep 2017 18:16:08 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:43 +0100 Message-Id: <1505668548-16616-4-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 3/8] ppc/ide/macio: Add missing registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt The timing register exists on all variants of MacIO IDE, we just store and return its value. The interrupts register only exists on KeyLargo but it doesn't hurt to have it. The lack of this register causes MacOS X to hangs under some circumstances. Both are 32-bit only. The HW might support smaller access sizes but no known OS uses them. Because the core IDE subsystem doesn't provide us with a way to query the main (level) interrupt state, nor do we have a way to know that DBDMA issued a (edge) interrupt, we reflect both through a private pair of qirq's in order to maintain the register state. Signed-off-by: Benjamin Herrenschmidt --- hw/ide/macio.c | 44 +++++++++++++++++++++++++++++++++++++++++--- hw/ppc/mac.h | 6 +++++- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 9742c00..db5db39 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -331,6 +331,12 @@ static void pmac_ide_writel (void *opaque, val =3D bswap32(val); if (addr =3D=3D 0) { ide_data_writel(&d->bus, 0, val); + } else if (addr =3D=3D 0x20) { + d->timing_reg =3D val; + } else if (addr =3D=3D 0x30) { + if (val & 0x80000000u) { + d->irq_reg &=3D 0x7fffffff; + } } } =20 @@ -342,6 +348,17 @@ static uint32_t pmac_ide_readl (void *opaque,hwaddr ad= dr) addr =3D (addr & 0xFFF) >> 4; if (addr =3D=3D 0) { retval =3D ide_data_readl(&d->bus, 0); + } else if (addr =3D=3D 0x20) { + retval =3D d->timing_reg; + } else if (addr =3D=3D 0x30) { + /* This is an interrupt state register that only exists + * in the KeyLargo and later variants. Bit 0x8000_0000 + * latches the DMA interrupt and has to be written to + * clear. Bit 0x4000_0000 is an image of the disk + * interrupt. MacOS X relies on this and will hang if + * we don't provide at least the disk interrupt + */ + retval =3D d->irq_reg; } else { retval =3D 0xFFFFFFFF; } @@ -426,13 +443,32 @@ static void macio_ide_realizefn(DeviceState *dev, Err= or **errp) { MACIOIDEState *s =3D MACIO_IDE(dev); =20 - ide_init2(&s->bus, s->irq); + ide_init2(&s->bus, s->ide_irq); =20 /* Register DMA callbacks */ s->dma.ops =3D &dbdma_ops; s->bus.dma =3D &s->dma; } =20 +static void pmac_ide_irq(void *opaque, int n, int level) +{ + MACIOIDEState *s =3D opaque; + uint32_t mask =3D 0x80000000u >> n; + + /* We need to reflect the IRQ state in the irq register */ + if (level) { + s->irq_reg |=3D mask; + } else { + s->irq_reg &=3D ~mask; + } + + if (n) { + qemu_set_irq(s->real_ide_irq, level); + } else { + qemu_set_irq(s->real_dma_irq, level); + } +} + static void macio_ide_initfn(Object *obj) { SysBusDevice *d =3D SYS_BUS_DEVICE(obj); @@ -441,8 +477,10 @@ static void macio_ide_initfn(Object *obj) ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x10= 00); sysbus_init_mmio(d, &s->mem); - sysbus_init_irq(d, &s->irq); - sysbus_init_irq(d, &s->dma_irq); + sysbus_init_irq(d, &s->real_ide_irq); + sysbus_init_irq(d, &s->real_dma_irq); + s->dma_irq =3D qemu_allocate_irq(pmac_ide_irq, s, 0); + s->ide_irq =3D qemu_allocate_irq(pmac_ide_irq, s, 1); } =20 static void macio_ide_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 20cbddb..300fc8a 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -132,7 +132,9 @@ typedef struct MACIOIDEState { SysBusDevice parent_obj; /*< public >*/ =20 - qemu_irq irq; + qemu_irq real_ide_irq; + qemu_irq real_dma_irq; + qemu_irq ide_irq; qemu_irq dma_irq; =20 MemoryRegion mem; @@ -140,6 +142,8 @@ typedef struct MACIOIDEState { IDEDMA dma; void *dbdma; bool dma_active; + uint32_t timing_reg; + uint32_t irq_reg; } MACIOIDEState; =20 void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table); --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668844199720.0317055460384; Sun, 17 Sep 2017 10:20:44 -0700 (PDT) Received: from localhost ([::1]:33113 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdFL-0001KO-6W for importer@patchew.org; Sun, 17 Sep 2017 13:20:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAy-00065L-La for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAt-0006A9-My for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:12 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39951 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAt-000695-GO; Sun, 17 Sep 2017 13:16:07 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAv-0005RD-63; Sun, 17 Sep 2017 18:16:10 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:44 +0100 Message-Id: <1505668548-16616-5-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 4/8] macio: convert pmac_ide_ops from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland --- hw/ide/macio.c | 154 +++++++++++++++++++++-------------------------------= ---- 1 file changed, 56 insertions(+), 98 deletions(-) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index db5db39..428fbfc 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -255,131 +255,89 @@ static void pmac_ide_flush(DBDMA_io *io) } =20 /* PowerMac IDE memory IO */ -static void pmac_ide_writeb (void *opaque, - hwaddr addr, uint32_t val) +static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size) { MACIOIDEState *d =3D opaque; + uint64_t retval; + addr =3D (addr & 0xfff) >> 4; =20 - addr =3D (addr & 0xFFF) >> 4; switch (addr) { - case 1 ... 7: - ide_ioport_write(&d->bus, addr, val); - break; - case 8: - case 22: - ide_cmd_write(&d->bus, 0, val); - break; - default: + case 0x0: + if (size =3D=3D 2) { + retval =3D ide_data_readw(&d->bus, 0); + } else if (size =3D=3D 4) { + retval =3D ide_data_readl(&d->bus, 0); + } else { + retval =3D 0xffffffff; + } break; - } -} - -static uint32_t pmac_ide_readb (void *opaque,hwaddr addr) -{ - uint8_t retval; - MACIOIDEState *d =3D opaque; - - addr =3D (addr & 0xFFF) >> 4; - switch (addr) { - case 1 ... 7: + case 0x1 ... 0x7: retval =3D ide_ioport_read(&d->bus, addr); break; - case 8: - case 22: + case 0x8: + case 0x16: retval =3D ide_status_read(&d->bus, 0); break; + case 0x20: + retval =3D d->timing_reg; + break; + case 0x30: + /* This is an interrupt state register that only exists + * in the KeyLargo and later variants. Bit 0x8000_0000 + * latches the DMA interrupt and has to be written to + * clear. Bit 0x4000_0000 is an image of the disk + * interrupt. MacOS X relies on this and will hang if + * we don't provide at least the disk interrupt + */ + retval =3D d->irq_reg; + break; default: - retval =3D 0xFF; + retval =3D 0xffffffff; break; } - return retval; -} - -static void pmac_ide_writew (void *opaque, - hwaddr addr, uint32_t val) -{ - MACIOIDEState *d =3D opaque; - - addr =3D (addr & 0xFFF) >> 4; - val =3D bswap16(val); - if (addr =3D=3D 0) { - ide_data_writew(&d->bus, 0, val); - } -} =20 -static uint32_t pmac_ide_readw (void *opaque,hwaddr addr) -{ - uint16_t retval; - MACIOIDEState *d =3D opaque; - - addr =3D (addr & 0xFFF) >> 4; - if (addr =3D=3D 0) { - retval =3D ide_data_readw(&d->bus, 0); - } else { - retval =3D 0xFFFF; - } - retval =3D bswap16(retval); return retval; } =20 -static void pmac_ide_writel (void *opaque, - hwaddr addr, uint32_t val) + +static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { MACIOIDEState *d =3D opaque; + addr =3D (addr & 0xfff) >> 4; =20 - addr =3D (addr & 0xFFF) >> 4; - val =3D bswap32(val); - if (addr =3D=3D 0) { - ide_data_writel(&d->bus, 0, val); - } else if (addr =3D=3D 0x20) { + switch (addr) { + case 0x0: + if (size =3D=3D 2) { + ide_data_writew(&d->bus, 0, val); + } else if (size =3D=3D 4) { + ide_data_writel(&d->bus, 0, val); + } + break; + case 0x1 ... 0x7: + ide_ioport_write(&d->bus, addr, val); + break; + case 0x8: + case 0x16: + ide_cmd_write(&d->bus, 0, val); + break; + case 0x20: d->timing_reg =3D val; - } else if (addr =3D=3D 0x30) { + break; + case 0x30: if (val & 0x80000000u) { d->irq_reg &=3D 0x7fffffff; } + break; } } =20 -static uint32_t pmac_ide_readl (void *opaque,hwaddr addr) -{ - uint32_t retval; - MACIOIDEState *d =3D opaque; - - addr =3D (addr & 0xFFF) >> 4; - if (addr =3D=3D 0) { - retval =3D ide_data_readl(&d->bus, 0); - } else if (addr =3D=3D 0x20) { - retval =3D d->timing_reg; - } else if (addr =3D=3D 0x30) { - /* This is an interrupt state register that only exists - * in the KeyLargo and later variants. Bit 0x8000_0000 - * latches the DMA interrupt and has to be written to - * clear. Bit 0x4000_0000 is an image of the disk - * interrupt. MacOS X relies on this and will hang if - * we don't provide at least the disk interrupt - */ - retval =3D d->irq_reg; - } else { - retval =3D 0xFFFFFFFF; - } - retval =3D bswap32(retval); - return retval; -} - static const MemoryRegionOps pmac_ide_ops =3D { - .old_mmio =3D { - .write =3D { - pmac_ide_writeb, - pmac_ide_writew, - pmac_ide_writel, - }, - .read =3D { - pmac_ide_readb, - pmac_ide_readw, - pmac_ide_readl, - }, - }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .read =3D pmac_ide_read, + .write =3D pmac_ide_write, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static const VMStateDescription vmstate_pmac =3D { --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668698298981.5803643104801; Sun, 17 Sep 2017 10:18:18 -0700 (PDT) Received: from localhost ([::1]:33096 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdCz-0007b1-FR for importer@patchew.org; Sun, 17 Sep 2017 13:18:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdAz-00065S-U2 for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAv-0006BY-ME for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:13 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39964 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAv-0006Aw-B9; Sun, 17 Sep 2017 13:16:09 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAw-0005RD-M5; Sun, 17 Sep 2017 18:16:12 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:45 +0100 Message-Id: <1505668548-16616-6-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 5/8] ppc/mac: More rework of the DBDMA emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt This completely reworks the handling of the control register according to my understanding of the HW and the spec. It should (hopefully ... still testing) fix a number of issues most notably cases of MacOS hanging. Also update dbdma_unassigned_rw() and dbdma_unassigned_flush() to have the expected behaviour now that flush is handled slightly differently. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/mac_dbdma.c | 191 +++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 139 insertions(+), 52 deletions(-) diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index 15452b9..3fe5073 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -96,9 +96,8 @@ static void dbdma_cmdptr_load(DBDMA_channel *ch) =20 static void dbdma_cmdptr_save(DBDMA_channel *ch) { - DBDMA_DPRINTFCH(ch, "dbdma_cmdptr_save 0x%08x\n", - ch->regs[DBDMA_CMDPTR_LO]); - DBDMA_DPRINTFCH(ch, "xfer_status 0x%08x res_count 0x%04x\n", + DBDMA_DPRINTFCH(ch, "-> update 0x%08x stat=3D0x%08x, res=3D0x%04x\n", + ch->regs[DBDMA_CMDPTR_LO], le16_to_cpu(ch->current.xfer_status), le16_to_cpu(ch->current.res_count)); dma_memory_write(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], @@ -166,15 +165,14 @@ static int conditional_wait(DBDMA_channel *ch) uint16_t sel_mask, sel_value; uint32_t status; int cond; - - DBDMA_DPRINTFCH(ch, "conditional_wait\n"); + int res =3D 0; =20 wait =3D le16_to_cpu(current->command) & WAIT_MASK; - switch(wait) { case WAIT_NEVER: /* don't wait */ return 0; case WAIT_ALWAYS: /* always wait */ + DBDMA_DPRINTFCH(ch, " [WAIT_ALWAYS]\n"); return 1; } =20 @@ -187,15 +185,19 @@ static int conditional_wait(DBDMA_channel *ch) =20 switch(wait) { case WAIT_IFSET: /* wait if condition bit is 1 */ - if (cond) - return 1; - return 0; + if (cond) { + res =3D 1; + } + DBDMA_DPRINTFCH(ch, " [WAIT_IFSET=3D%d]\n", res); + break; case WAIT_IFCLR: /* wait if condition bit is 0 */ - if (!cond) - return 1; - return 0; + if (!cond) { + res =3D 1; + } + DBDMA_DPRINTFCH(ch, " [WAIT_IFCLR=3D%d]\n", res); + break; } - return 0; + return res; } =20 static void next(DBDMA_channel *ch) @@ -226,8 +228,6 @@ static void conditional_branch(DBDMA_channel *ch) uint32_t status; int cond; =20 - DBDMA_DPRINTFCH(ch, "conditional_branch\n"); - /* check if we must branch */ =20 br =3D le16_to_cpu(current->command) & BR_MASK; @@ -237,6 +237,7 @@ static void conditional_branch(DBDMA_channel *ch) next(ch); return; case BR_ALWAYS: /* always branch */ + DBDMA_DPRINTFCH(ch, " [BR_ALWAYS]\n"); branch(ch); return; } @@ -250,16 +251,22 @@ static void conditional_branch(DBDMA_channel *ch) =20 switch(br) { case BR_IFSET: /* branch if condition bit is 1 */ - if (cond) + if (cond) { + DBDMA_DPRINTFCH(ch, " [BR_IFSET =3D 1]\n"); branch(ch); - else + } else { + DBDMA_DPRINTFCH(ch, " [BR_IFSET =3D 0]\n"); next(ch); + } return; case BR_IFCLR: /* branch if condition bit is 0 */ - if (!cond) + if (!cond) { + DBDMA_DPRINTFCH(ch, " [BR_IFCLR =3D 1]\n"); branch(ch); - else + } else { + DBDMA_DPRINTFCH(ch, " [BR_IFCLR =3D 0]\n"); next(ch); + } return; } } @@ -428,7 +435,7 @@ wait: =20 static void stop(DBDMA_channel *ch) { - ch->regs[DBDMA_STATUS] &=3D ~(ACTIVE|DEAD|FLUSH); + ch->regs[DBDMA_STATUS] &=3D ~(ACTIVE); =20 /* the stop command does not increment command pointer */ } @@ -471,18 +478,22 @@ static void channel_run(DBDMA_channel *ch) =20 switch (cmd) { case OUTPUT_MORE: + DBDMA_DPRINTFCH(ch, "* OUTPUT_MORE *\n"); start_output(ch, key, phy_addr, req_count, 0); return; =20 case OUTPUT_LAST: + DBDMA_DPRINTFCH(ch, "* OUTPUT_LAST *\n"); start_output(ch, key, phy_addr, req_count, 1); return; =20 case INPUT_MORE: + DBDMA_DPRINTFCH(ch, "* INPUT_MORE *\n"); start_input(ch, key, phy_addr, req_count, 0); return; =20 case INPUT_LAST: + DBDMA_DPRINTFCH(ch, "* INPUT_LAST *\n"); start_input(ch, key, phy_addr, req_count, 1); return; } @@ -508,10 +519,12 @@ static void channel_run(DBDMA_channel *ch) =20 switch (cmd) { case LOAD_WORD: + DBDMA_DPRINTFCH(ch, "* LOAD_WORD *\n"); load_word(ch, key, phy_addr, req_count); return; =20 case STORE_WORD: + DBDMA_DPRINTFCH(ch, "* STORE_WORD *\n"); store_word(ch, key, phy_addr, req_count); return; } @@ -562,43 +575,117 @@ void DBDMA_register_channel(void *dbdma, int nchan, = qemu_irq irq, ch->io.opaque =3D opaque; } =20 -static void -dbdma_control_write(DBDMA_channel *ch) +static void dbdma_control_write(DBDMA_channel *ch) { uint16_t mask, value; uint32_t status; + bool do_flush =3D false; =20 mask =3D (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff; value =3D ch->regs[DBDMA_CONTROL] & 0xffff; =20 - value &=3D (RUN | PAUSE | FLUSH | WAKE | DEVSTAT); - + /* This is the status register which we'll update + * appropriately and store back + */ status =3D ch->regs[DBDMA_STATUS]; =20 - status =3D (value & mask) | (status & ~mask); + /* RUN and PAUSE are bits under SW control only + * FLUSH and WAKE are set by SW and cleared by HW + * DEAD, ACTIVE and BT are only under HW control + * + * We handle ACTIVE separately at the end of the + * logic to ensure all cases are covered. + */ =20 - if (status & WAKE) - status |=3D ACTIVE; - if (status & RUN) { - status |=3D ACTIVE; - status &=3D ~DEAD; + /* Setting RUN will tentatively activate the channel + */ + if ((mask & RUN) && (value & RUN)) { + status |=3D RUN; + DBDMA_DPRINTFCH(ch, " Setting RUN !\n"); + } + + /* Clearing RUN 1->0 will stop the channel */ + if ((mask & RUN) && !(value & RUN)) { + /* This has the side effect of clearing the DEAD bit */ + status &=3D ~(DEAD | RUN); + DBDMA_DPRINTFCH(ch, " Clearing RUN !\n"); + } + + /* Setting WAKE wakes up an idle channel if it's running + * + * Note: The doc doesn't say so but assume that only works + * on a channel whose RUN bit is set. + * + * We set WAKE in status, it's not terribly useful as it will + * be cleared on the next command fetch but it seems to mimmic + * the HW behaviour and is useful for the way we handle + * ACTIVE further down. + */ + if ((mask & WAKE) && (value & WAKE) && (status & RUN)) { + status |=3D WAKE; + DBDMA_DPRINTFCH(ch, " Setting WAKE !\n"); + } + + /* PAUSE being set will deactivate (or prevent activation) + * of the channel. We just copy it over for now, ACTIVE will + * be re-evaluated later. + */ + if (mask & PAUSE) { + status =3D (status & ~PAUSE) | (value & PAUSE); + DBDMA_DPRINTFCH(ch, " %sing PAUSE !\n", + (value & PAUSE) ? "sett" : "clear"); + } + + /* FLUSH is its own thing */ + if ((mask & FLUSH) && (value & FLUSH)) { + DBDMA_DPRINTFCH(ch, " Setting FLUSH !\n"); + /* We set flush directly in the status register, we do *NOT* + * set it in "status" so that it gets naturally cleared when + * we update the status register further down. That way it + * will be set only during the HW flush operation so it is + * visible to any completions happening during that time. + */ + ch->regs[DBDMA_STATUS] |=3D FLUSH; + do_flush =3D true; } - if (status & PAUSE) + + /* If either RUN or PAUSE is clear, so should ACTIVE be, + * otherwise, ACTIVE will be set if we modified RUN, PAUSE or + * set WAKE. That means that PAUSE was just cleared, RUN was + * just set or WAKE was just set. + */ + if ((status & PAUSE) || !(status & RUN)) { status &=3D ~ACTIVE; - if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) { - /* RUN is cleared */ - status &=3D ~(ACTIVE|DEAD); + DBDMA_DPRINTFCH(ch, " -> ACTIVE down !\n"); + + /* We stopped processing, we want the underlying HW command + * to complete *before* we clear the ACTIVE bit. Otherwise + * we can get into a situation where the command status will + * have RUN or ACTIVE not set which is going to confuse the + * MacOS driver. + */ + do_flush =3D true; + } else if (mask & (RUN | PAUSE)) { + status |=3D ACTIVE; + DBDMA_DPRINTFCH(ch, " -> ACTIVE up !\n"); + } else if ((mask & WAKE) && (value & WAKE)) { + status |=3D ACTIVE; + DBDMA_DPRINTFCH(ch, " -> ACTIVE up !\n"); } =20 - if ((status & FLUSH) && ch->flush) { + DBDMA_DPRINTFCH(ch, " new status=3D0x%08x\n", status); + + /* If we need to flush the underlying HW, do it now, this happens + * both on FLUSH commands and when stopping the channel for safety. + */ + if (do_flush && ch->flush) { ch->flush(&ch->io); - status &=3D ~FLUSH; } =20 - DBDMA_DPRINTFCH(ch, " status 0x%08x\n", status); - + /* Finally update the status register image */ ch->regs[DBDMA_STATUS] =3D status; =20 + /* If active, make sure the BH gets to run */ if (status & ACTIVE) { DBDMA_kick(dbdma_from_ch(ch)); } @@ -666,13 +753,9 @@ static uint64_t dbdma_read(void *opaque, hwaddr addr, =20 value =3D ch->regs[reg]; =20 - DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " =3D> 0x%08x\n", addr, = value); - DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", - (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); - switch(reg) { case DBDMA_CONTROL: - value =3D 0; + value =3D ch->regs[DBDMA_STATUS]; break; case DBDMA_STATUS: case DBDMA_CMDPTR_LO: @@ -698,6 +781,10 @@ static uint64_t dbdma_read(void *opaque, hwaddr addr, break; } =20 + DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " =3D> 0x%08x\n", addr, = value); + DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", + (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); + return value; } =20 @@ -776,28 +863,28 @@ static void dbdma_reset(void *opaque) static void dbdma_unassigned_rw(DBDMA_io *io) { DBDMA_channel *ch =3D io->channel; - qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", - __func__, ch->channel); - ch->io.processing =3D false; -} - -static void dbdma_unassigned_flush(DBDMA_io *io) -{ - DBDMA_channel *ch =3D io->channel; dbdma_cmd *current =3D &ch->current; uint16_t cmd; qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", __func__, ch->channel); + ch->io.processing =3D false; =20 cmd =3D le16_to_cpu(current->command) & COMMAND_MASK; if (cmd =3D=3D OUTPUT_MORE || cmd =3D=3D OUTPUT_LAST || cmd =3D=3D INPUT_MORE || cmd =3D=3D INPUT_LAST) { - current->xfer_status =3D cpu_to_le16(ch->regs[DBDMA_STATUS] | FLUS= H); + current->xfer_status =3D cpu_to_le16(ch->regs[DBDMA_STATUS]); current->res_count =3D cpu_to_le16(io->len); dbdma_cmdptr_save(ch); } } =20 +static void dbdma_unassigned_flush(DBDMA_io *io) +{ + DBDMA_channel *ch =3D io->channel; + qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", + __func__, ch->channel); +} + void* DBDMA_init (MemoryRegion **dbdma_mem) { DBDMAState *s; --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668844527856.7158122801; Sun, 17 Sep 2017 10:20:44 -0700 (PDT) Received: from localhost ([::1]:33114 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdFL-0001MC-MD for importer@patchew.org; Sun, 17 Sep 2017 13:20:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdB0-00065i-Q6 for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAx-0006CL-2B for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39969 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAw-0006Bt-RI; Sun, 17 Sep 2017 13:16:10 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdAy-0005RD-VA; Sun, 17 Sep 2017 18:16:14 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:46 +0100 Message-Id: <1505668548-16616-7-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 6/8] ppc: Fix OpenPIC model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt Apple uses an IBM MPIC2A without timers, it has 64 sources. Signed-off-by: Benjamin Herrenschmidt --- hw/intc/openpic.c | 35 +++++++++++++++++++++++++++++++++++ hw/ppc/mac_newworld.c | 2 +- include/hw/ppc/openpic.h | 1 + 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 9dd285b..10d6e87 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -92,6 +92,16 @@ static int get_current_cpu(void); #define RAVEN_MAX_TMR OPENPIC_MAX_TMR #define RAVEN_MAX_IPI OPENPIC_MAX_IPI =20 +/* KeyLargo */ +#define KEYLARGO_MAX_CPU 4 +#define KEYLARGO_MAX_EXT 64 +#define KEYLARGO_MAX_IPI 4 +#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) +#define KEYLARGO_MAX_TMR 0 +#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ +/* Timers don't exist but this makes the code happy... */ +#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) + /* Interrupt definitions */ #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ @@ -120,6 +130,7 @@ static FslMpicInfo fsl_mpic_42 =3D { #define VID_REVISION_1_3 3 =20 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ +#define VIR_MPIC2A 0x00004614 /* IBM MPIC-2A */ =20 #define GCR_RESET 0x80000000 #define GCR_MODE_PASS 0x00000000 @@ -329,6 +340,8 @@ typedef struct OpenPICState { uint32_t nb_cpus; /* Timer registers */ OpenPICTimer timers[OPENPIC_MAX_TMR]; + uint32_t max_tmr; + /* Shared MSI registers */ OpenPICMSI msi[MAX_MSI]; uint32_t max_irq; @@ -1717,6 +1730,28 @@ static void openpic_realize(DeviceState *dev, Error = **errp) =20 map_list(opp, list_le, &list_count); break; + + case OPENPIC_MODEL_KEYLARGO: + opp->nb_irqs =3D KEYLARGO_MAX_EXT; + opp->vid =3D VID_REVISION_1_2; + opp->vir =3D VIR_GENERIC; + opp->vector_mask =3D 0xFF; + opp->tfrr_reset =3D 4160000; + opp->ivpr_reset =3D IVPR_MASK_MASK | IVPR_MODE_MASK; + opp->idr_reset =3D 0; + opp->max_irq =3D KEYLARGO_MAX_IRQ; + opp->irq_ipi0 =3D KEYLARGO_IPI_IRQ; + opp->irq_tim0 =3D KEYLARGO_TMR_IRQ; + opp->brr1 =3D -1; + opp->mpic_mode_mask =3D GCR_MODE_MIXED; + + if (opp->nb_cpus !=3D 1) { + error_setg(errp, "Only UP supported today"); + return; + } + + map_list(opp, list_le, &list_count); + break; } =20 for (i =3D 0; i < opp->nb_cpus; i++) { diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index c581d96..62bd8d3 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -351,7 +351,7 @@ static void ppc_core99_init(MachineState *machine) pic =3D g_new0(qemu_irq, 64); =20 dev =3D qdev_create(NULL, TYPE_OPENPIC); - qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); + qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_KEYLARGO); qdev_init_nofail(dev); s =3D SYS_BUS_DEVICE(dev); pic_mem =3D s->mmio[0].memory; diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h index 6137e2d..e55ce54 100644 --- a/include/hw/ppc/openpic.h +++ b/include/hw/ppc/openpic.h @@ -20,6 +20,7 @@ enum { #define OPENPIC_MODEL_RAVEN 0 #define OPENPIC_MODEL_FSL_MPIC_20 1 #define OPENPIC_MODEL_FSL_MPIC_42 2 +#define OPENPIC_MODEL_KEYLARGO 3 =20 #define OPENPIC_MAX_SRC 256 #define OPENPIC_MAX_TMR 4 --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668693223804.197621289345; Sun, 17 Sep 2017 10:18:13 -0700 (PDT) Received: from localhost ([::1]:33094 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdCu-0007Ww-6M for importer@patchew.org; Sun, 17 Sep 2017 13:18:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45725) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdB0-00065W-Mi for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAy-0006DI-9e for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39973 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAy-0006Cm-2x; Sun, 17 Sep 2017 13:16:12 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdB0-0005RD-Ga; Sun, 17 Sep 2017 18:16:15 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:47 +0100 Message-Id: <1505668548-16616-8-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 7/8] openpic: add missing timer fields to vmstate_openpic_timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Observation of the code shows indicates that several timer fields are missing from the migration stream. Signed-off-by: Mark Cave-Ayland --- hw/intc/openpic.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 10d6e87..debfcbf 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -1570,11 +1570,14 @@ static const VMStateDescription vmstate_openpic_irq= source =3D { =20 static const VMStateDescription vmstate_openpic_timer =3D { .name =3D "openpic_timer", - .version_id =3D 0, - .minimum_version_id =3D 0, + .version_id =3D 1, + .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT32(tccr, OpenPICTimer), VMSTATE_UINT32(tbcr, OpenPICTimer), + VMSTATE_BOOL(qemu_timer_active, OpenPICTimer), + VMSTATE_TIMER_PTR(qemu_timer, OpenPICTimer), + VMSTATE_UINT64(origin_time, OpenPICTimer), VMSTATE_END_OF_LIST() } }; @@ -1620,7 +1623,7 @@ static const VMStateDescription vmstate_openpic =3D { VMSTATE_UINT32_EQUAL(nb_cpus, OpenPICState, NULL), VMSTATE_STRUCT_VARRAY_UINT32(dst, OpenPICState, nb_cpus, 0, vmstate_openpic_irqdest, IRQDest), - VMSTATE_STRUCT_ARRAY(timers, OpenPICState, OPENPIC_MAX_TMR, 0, + VMSTATE_STRUCT_ARRAY(timers, OpenPICState, OPENPIC_MAX_TMR, 1, vmstate_openpic_timer, OpenPICTimer), VMSTATE_STRUCT_ARRAY(msi, OpenPICState, MAX_MSI, 0, vmstate_openpic_msi, OpenPICMSI), --=20 1.7.10.4 From nobody Sun Apr 28 03:03:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505668949781922.7910524270941; Sun, 17 Sep 2017 10:22:29 -0700 (PDT) Received: from localhost ([::1]:33119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdH1-0002hO-3C for importer@patchew.org; Sun, 17 Sep 2017 13:22:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtdB1-00065r-1V for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtdAz-0006Eo-QY for qemu-devel@nongnu.org; Sun, 17 Sep 2017 13:16:14 -0400 Received: from chuckie.co.uk ([82.165.15.123]:39977 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dtdAz-0006EG-JS; Sun, 17 Sep 2017 13:16:13 -0400 Received: from host109-151-159-252.range109-151.btcentralplus.com ([109.151.159.252] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dtdB1-0005RD-Om; Sun, 17 Sep 2017 18:16:17 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org Date: Sun, 17 Sep 2017 18:15:48 +0100 Message-Id: <1505668548-16616-9-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1505668548-16616-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.159.252 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 8/8] openpic: Fix problem when IRQ transitions from edge to level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt Some interrupts get triggered before the OS has setup the right interrupt type. If an edge interrupt is latched that way, not delivered (still masked), then the interrupt is changed to level and isn't asserted anymore, it will be stuck "pending", causing an interrupt flood. This can happen with the PMU GPIO interrupt for example. There are a few other corner cases like this, so let's keep track of the input "level" so we can properly re-evaluate when the trigger type changes. Signed-off-by: Benjamin Herrenschmidt --- hw/intc/openpic.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index debfcbf..34749f8 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -236,6 +236,7 @@ typedef struct IRQSource { int last_cpu; int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ int pending; /* TRUE if IRQ is pending */ + int cur_level; /* Cache current level */ IRQType type; bool level:1; /* level-triggered */ bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ @@ -552,14 +553,26 @@ static void openpic_set_irq(void *opaque, int n_IRQ, = int level) } =20 src =3D &opp->src[n_IRQ]; - DPRINTF("openpic: set irq %d =3D %d ivpr=3D0x%08x\n", - n_IRQ, level, src->ivpr); + DPRINTF("openpic: set irq %d =3D %d ivpr=3D0x%08x (l=3D%d,cl=3D%d)\n", + n_IRQ, level, src->ivpr, src->level, src->cur_level); + + /* Keep track of the current input level in order to properly deal + * with the configuration of the source changing from edge to level + * after it's been latched. Otherwise the interrupt can get stuck. + */ + src->cur_level =3D level; + if (src->level) { - /* level-sensitive irq */ src->pending =3D level; openpic_update_irq(opp, n_IRQ); } else { - /* edge-sensitive irq */ + /* edge-sensitive irq + * + * In an ideal world we would only set pending on an "edge", ie + * if level is set and src->cur_level as clear. However that would + * require all the devices to properly send "pulses" rather than + * just "raise" which isn't the case today. + */ if (level) { src->pending =3D 1; openpic_update_irq(opp, n_IRQ); @@ -676,6 +689,13 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp= , int n_IRQ, uint32_t val) switch (opp->src[n_IRQ].type) { case IRQ_TYPE_NORMAL: opp->src[n_IRQ].level =3D !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MAS= K); + + /* If we switched to level we need to re-evaluate "pending" based + * on the actual input state. + */ + if (opp->src[n_IRQ].level) { + opp->src[n_IRQ].pending =3D opp->src[n_IRQ].cur_level; + } break; =20 case IRQ_TYPE_FSLINT: @@ -687,6 +707,7 @@ static inline void write_IRQreg_ivpr(OpenPICState *opp,= int n_IRQ, uint32_t val) break; } =20 + /* Re-evaluate a level irq */ openpic_update_irq(opp, n_IRQ); DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, opp->src[n_IRQ].ivpr); @@ -1232,7 +1253,7 @@ static uint32_t openpic_iack(OpenPICState *opp, IRQDe= st *dst, int cpu) } =20 if (!src->level) { - /* edge-sensitive IRQ */ + /* edge-sensitive IRQ or level dropped */ src->ivpr &=3D ~IVPR_ACTIVITY_MASK; src->pending =3D 0; IRQ_resetbit(&dst->raised, irq); @@ -1564,6 +1585,7 @@ static const VMStateDescription vmstate_openpic_irqso= urce =3D { VMSTATE_UINT32(destmask, IRQSource), VMSTATE_INT32(last_cpu, IRQSource), VMSTATE_INT32(pending, IRQSource), + VMSTATE_INT32(cur_level, IRQSource), VMSTATE_END_OF_LIST() } }; --=20 1.7.10.4