From nobody Mon Apr 29 17:16:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503065073028808.5127783798067; Fri, 18 Aug 2017 07:04:33 -0700 (PDT) Received: from localhost ([::1]:55964 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diht1-0005hL-L0 for importer@patchew.org; Fri, 18 Aug 2017 10:04:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51554) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqe-00048N-Hq for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqd-0008WU-1F for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:04 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2235) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqV-0008OJ-Mg; Fri, 18 Aug 2017 10:01:56 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74410; Fri, 18 Aug 2017 22:00:48 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:12 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:42 +0800 Message-ID: <1503066227-18251-2-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F310.0190, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d6bd547ab7138c2865427ea05fc33ed4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 1/6] ACPI: add APEI/HEST/CPER structures and macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" (1) Add related APEI/HEST table structures and macros, these definition refer to ACPI 6.1 and UEFI 2.6 spec. (2) Add generic error status block and CPER memory section definition, user space only handle memory section errors. Signed-off-by: Dongjiu Geng --- include/hw/acpi/acpi-defs.h | 193 ++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 193 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 72be675..3b4bad7 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -297,6 +297,44 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicT= able; #define ACPI_APIC_GENERIC_TRANSLATOR 15 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserve= d */ =20 +/* UEFI Spec 2.6, "N.2.5 Memory Error Section */ +#define UEFI_CPER_MEM_VALID_ERROR_STATUS 0x0001 +#define UEFI_CPER_MEM_VALID_PA 0x0002 +#define UEFI_CPER_MEM_VALID_PA_MASK 0x0004 +#define UEFI_CPER_MEM_VALID_NODE 0x0008 +#define UEFI_CPER_MEM_VALID_CARD 0x0010 +#define UEFI_CPER_MEM_VALID_MODULE 0x0020 +#define UEFI_CPER_MEM_VALID_BANK 0x0040 +#define UEFI_CPER_MEM_VALID_DEVICE 0x0080 +#define UEFI_CPER_MEM_VALID_ROW 0x0100 +#define UEFI_CPER_MEM_VALID_COLUMN 0x0200 +#define UEFI_CPER_MEM_VALID_BIT_POSITION 0x0400 +#define UEFI_CPER_MEM_VALID_REQUESTOR 0x0800 +#define UEFI_CPER_MEM_VALID_RESPONDER 0x1000 +#define UEFI_CPER_MEM_VALID_TARGET 0x2000 +#define UEFI_CPER_MEM_VALID_ERROR_TYPE 0x4000 +#define UEFI_CPER_MEM_VALID_RANK_NUMBER 0x8000 +#define UEFI_CPER_MEM_VALID_CARD_HANDLE 0x10000 +#define UEFI_CPER_MEM_VALID_MODULE_HANDLE 0x20000 +#define UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC 3 + +/* From the ACPI 6.1 spec, "18.3.2.9 Hardware Error Notification" */ + +enum AcpiHestNotifyType { + ACPI_HEST_NOTIFY_POLLED =3D 0, + ACPI_HEST_NOTIFY_EXTERNAL =3D 1, + ACPI_HEST_NOTIFY_LOCAL =3D 2, + ACPI_HEST_NOTIFY_SCI =3D 3, + ACPI_HEST_NOTIFY_NMI =3D 4, + ACPI_HEST_NOTIFY_CMCI =3D 5, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_MCE =3D 6, /* ACPI 5.0 */ + ACPI_HEST_NOTIFY_GPIO =3D 7, /* ACPI 6.0 */ + ACPI_HEST_NOTIFY_SEA =3D 8, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_SEI =3D 9, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_GSIV =3D 10, /* ACPI 6.1 */ + ACPI_HEST_NOTIFY_RESERVED =3D 11 /* 11 and greater are reserved */ +}; + /* * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) */ @@ -474,6 +512,161 @@ struct AcpiSystemResourceAffinityTable { } QEMU_PACKED; typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityT= able; =20 +/* Hardware Error Notification, from the ACPI 6.1 + * spec, "18.3.2.9 Hardware Error Notification" + */ +struct AcpiHestNotify { + uint8_t type; + uint8_t length; + uint16_t config_write_enable; + uint32_t poll_interval; + uint32_t vector; + uint32_t polling_threshold_value; + uint32_t polling_threshold_window; + uint32_t error_threshold_value; + uint32_t error_threshold_window; +} QEMU_PACKED; +typedef struct AcpiHestNotify AcpiHestNotify; + +/* From ACPI 6.1, sections "18.3.2.1 IA-32 Architecture Machine + * Check Exception" through "18.3.2.8 Generic Hardware Error Source versio= n 2". + */ +enum AcpiHestSourceType { + ACPI_HEST_SOURCE_IA32_CHECK =3D 0, + ACPI_HEST_SOURCE_IA32_CORRECTED_CHECK =3D 1, + ACPI_HEST_SOURCE_IA32_NMI =3D 2, + ACPI_HEST_SOURCE_AER_ROOT_PORT =3D 6, + ACPI_HEST_SOURCE_AER_ENDPOINT =3D 7, + ACPI_HEST_SOURCE_AER_BRIDGE =3D 8, + ACPI_HEST_SOURCE_GENERIC_ERROR =3D 9, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2 =3D 10, + ACPI_HEST_SOURCE_RESERVED =3D 11 /* 11 and greater are reserved */ +}; + +/* Block status bitmasks from ACPI 6.1, "18.3.2.7.1 Generic Error Data" */ +#define ACPI_GEBS_UNCORRECTABLE (1) +#define ACPI_GEBS_CORRECTABLE (1 << 1) +#define ACPI_GEBS_MULTIPLE_UNCORRECTABLE (1 << 2) +#define ACPI_GEBS_MULTIPLE_CORRECTABLE (1 << 3) +/* 10 bits, error data entry count */ +#define ACPI_GEBS_ERROR_ENTRY_COUNT (0x3FF << 4) + +/* Generic Hardware Error Source Structure, refer to ACPI 6.1 + * "18.3.2.7 Generic Hardware Error Source". in this struct the + * "type" field has to be ACPI_HEST_SOURCE_GENERIC_ERROR + */ + +struct AcpiGenericHardwareErrorSource { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSource AcpiGenericHardwareErrorSour= ce; + +/* Generic Hardware Error Source, version 2, ACPI 6.1, "18.3.2.8 Generic + * Hardware Error Source version 2", in this struct the "type" field has to + * be ACPI_HEST_SOURCE_GENERIC_ERROR_V2 + */ +struct AcpiGenericHardwareErrorSourceV2 { + uint16_t type; + uint16_t source_id; + uint16_t related_source_id; + uint8_t flags; + uint8_t enabled; + uint32_t number_of_records; + uint32_t max_sections_per_record; + uint32_t max_raw_data_length; + struct AcpiGenericAddress error_status_address; + struct AcpiHestNotify notify; + uint32_t error_status_block_length; + struct AcpiGenericAddress read_ack_register; + uint64_t read_ack_preserve; + uint64_t read_ack_write; +} QEMU_PACKED; +typedef struct AcpiGenericHardwareErrorSourceV2 + AcpiGenericHardwareErrorSourceV2; + +/* Generic Error Status block, from ACPI 6.1, + * "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorStatus { + /* It is a bitmask composed of ACPI_GEBS_xxx macros */ + uint32_t block_status; + uint32_t raw_data_offset; + uint32_t raw_data_length; + uint32_t data_length; + uint32_t error_severity; +} QEMU_PACKED; +typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus; + +enum AcpiGenericErrorSeverity { + ACPI_CPER_SEV_RECOVERABLE, + ACPI_CPER_SEV_FATAL, + ACPI_CPER_SEV_CORRECTED, + ACPI_CPER_SEV_NONE, +}; + +/* Generic Error Data entry, revision number is 0x0300, + * ACPI 6.1, "18.3.2.7.1 Generic Error Data" + */ +struct AcpiGenericErrorData { + uint8_t section_type_le[16]; + /* The "error_severity" fields that they take their + * values from AcpiGenericErrorSeverity + */ + uint32_t error_severity; + uint16_t revision; + uint8_t validation_bits; + uint8_t flags; + uint32_t error_data_length; + uint8_t fru_id[16]; + uint8_t fru_text[20]; + uint64_t time_stamp; +} QEMU_PACKED; +typedef struct AcpiGenericErrorData AcpiGenericErrorData; + +/* From UEFI 2.6, "N.2.5 Memory Error Section" */ +struct UefiCperSecMemErr { + uint64_t validation_bits; + uint64_t error_status; + uint64_t physical_addr; + uint64_t physical_addr_mask; + uint16_t node; + uint16_t card; + uint16_t module; + uint16_t bank; + uint16_t device; + uint16_t row; + uint16_t column; + uint16_t bit_pos; + uint64_t requestor_id; + uint64_t responder_id; + uint64_t target_id; + uint8_t error_type; + uint8_t reserved; + uint16_t rank; + uint16_t mem_array_handle; /* card handle in UEFI 2.4 */ + uint16_t mem_dev_handle; /* module handle in UEFI 2.4 */ +} QEMU_PACKED; +typedef struct UefiCperSecMemErr UefiCperSecMemErr; + +/* + * HEST Description Table + */ +struct AcpiHardwareErrorSourceTable { + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ + uint32_t error_source_count; +} QEMU_PACKED; +typedef struct AcpiHardwareErrorSourceTable AcpiHardwareErrorSourceTable; + #define ACPI_SRAT_PROCESSOR_APIC 0 #define ACPI_SRAT_MEMORY 1 #define ACPI_SRAT_PROCESSOR_x2APIC 2 --=20 1.8.3.1 From nobody Mon Apr 29 17:16:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503065273628183.20290886904934; Fri, 18 Aug 2017 07:07:53 -0700 (PDT) Received: from localhost ([::1]:56005 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihwG-0000Bh-8Y for importer@patchew.org; Fri, 18 Aug 2017 10:07:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihr8-0004XE-Ag for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihr1-0000Ju-4q for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:34 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2240) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqm-0000AZ-Tc; Fri, 18 Aug 2017 10:02:14 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74384; Fri, 18 Aug 2017 22:00:42 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:12 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:43 +0800 Message-ID: <1503066227-18251-3-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F30C.0131, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: fae2e80c8e9eb9944b27414a5d5592e6 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 2/6] ACPI: Add APEI GHES Table Generation support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This implements APEI GHES Table by passing the error CPER info to the guest via a fw_cfg_blob. After a CPER info is recorded, an SEA(Synchronous External Abort)/SEI(SError Interrupt) exception will be injected into the guest OS. Below is the table layout, the max number of error soure is 11, which is classified by notification type. etc/acpi/tables etc/hardware_errors =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +--------------------------+ +------------------+ | | HEST | | address | = +--------------+ | +--------------------------+ | registers | = | Error Status | | | GHES0 | | +----------------+ = | Data Block 0 | | +--------------------------+ +--------->| |status_address0 |-------------= >| +------------+ | | ................. | | | +----------------+ = | | CPER | | | error_status_address-----+-+ +------->| |status_address1 |----------+ = | | CPER | | | ................. | | | +----------------+ | = | | .... | | | read_ack_register--------+-+ | | ............. | | = | | CPER | | | read_ack_preserve | | | +------------------+ | = | +-+------------+ | | read_ack_write | | | +----->| |status_address10|--------+ | = | Error Status | + +--------------------------+ | | | | +----------------+ | | = | Data Block 1 | | | GHES1 | +-+-+----->| | ack_value0 | | +--= >| +------------+ + +--------------------------+ | | | +----------------+ | = | | CPER | | | ................. | | | +--->| | ack_value1 | | = | | CPER | | | error_status_address-----+---+ | | | +----------------+ | = | | .... | | | ................. | | | | | ............. | | = | | CPER | | | read_ack_register--------+-----+-+ | +----------------+ | = +-+------------+ | | read_ack_preserve | | +->| | ack_value10 | | = | |.......... | | | read_ack_write | | | | +----------------+ | = | +------------+ + +--------------------------| | | | = | Error Status | | | ............... | | | | = | Data Block 10| + +--------------------------+ | | +----= >| +------------+ | | GHES10 | | | = | | CPER | + +--------------------------+ | | = | | CPER | | | ................. | | | = | | .... | | | error_status_address-----+-----+ | = | | CPER | | | ................. | | = +-+------------+ | | read_ack_register--------+---------+ | | read_ack_preserve | | | read_ack_write | + +--------------------------+ For GHESv2 error source, the OSPM must acknowledges the error via Read Ack = register. so user space must check the ack value to avoid read-write race condition. Signed-off-by: Dongjiu Geng --- hw/acpi/aml-build.c | 2 + hw/acpi/hest_ghes.c | 345 ++++++++++++++++++++++++++++++++++++++++= ++++ hw/arm/virt-acpi-build.c | 6 + include/hw/acpi/aml-build.h | 1 + include/hw/acpi/hest_ghes.h | 47 ++++++ 5 files changed, 401 insertions(+) create mode 100644 hw/acpi/hest_ghes.c create mode 100644 include/hw/acpi/hest_ghes.h diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 36a6cc4..6849e5f 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables) tables->table_data =3D g_array_new(false, true /* clear */, 1); tables->tcpalog =3D g_array_new(false, true /* clear */, 1); tables->vmgenid =3D g_array_new(false, true /* clear */, 1); + tables->hardware_errors =3D g_array_new(false, true /* clear */, 1); tables->linker =3D bios_linker_loader_init(); } =20 @@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *table= s, bool mfre) g_array_free(tables->table_data, true); g_array_free(tables->tcpalog, mfre); g_array_free(tables->vmgenid, mfre); + g_array_free(tables->hardware_errors, mfre); } =20 /* Build rsdt table */ diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c new file mode 100644 index 0000000..ff6b5ef --- /dev/null +++ b/hw/acpi/hest_ghes.c @@ -0,0 +1,345 @@ +/* + * APEI GHES table Generation + * + * Copyright (C) 2017 huawei. + * + * Author: Dongjiu Geng + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qmp-commands.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" +#include "hw/acpi/hest_ghes.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +/* The structure that stands for the layout + * GHES_ERRORS_FW_CFG_FILE fw_cfg blob + * + * etc/hardware_errors + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * +------------------+ + * | address | +--------------+ + * | registers | | Error Status | + * | +----------------+ | Data Block 0 | + * | |status_address0 |------------->| +------------+ + * | +----------------+ | | CPER | + * | |status_address1 |----------+ | | CPER | + * | +----------------+ | | | .... | + * | |............. | | | | CPER | + * | +----------------+ | | +------------+ + * | |status_address10|-----+ | | Error Status | + * | +----------------+ | | | Data Block 1 | + * | |ack_value0 | | +-->| +------------+ + * | +----------------+ | | | CPER | + * | |ack_value1 | | | | CPER | + * | +----------------+ | | | .... | + * | | ............. | | | | CPER | + * | +----------------+ | +-+------------+ + * | |ack_value10 | | | |.......... | + * | +----------------+ | | +------------+ + * | | Error Status | + * | | Data Block10 | + * +------->+------------+ + * | | CPER | + * | | CPER | + * | | .... | + * | | CPER | + * +-+------------+ + */ +struct hardware_errors_buffer { + /* Generic Error Status Block register */ + uint64_t gesb_address[GHES_ACPI_HEST_NOTIFY_RESERVED]; + uint64_t ack_value[GHES_ACPI_HEST_NOTIFY_RESERVED]; + char gesb[GHES_MAX_RAW_DATA_LENGTH][GHES_ACPI_HEST_NOTIFY_RESERVED]; +}; + +static int ghes_record_cper(uint64_t error_block_address, + uint64_t error_physical_addr) +{ + AcpiGenericErrorStatus block; + AcpiGenericErrorData *gdata; + UefiCperSecMemErr *mem_err; + uint64_t current_block_length; + unsigned char *buffer; + /* memory section */ + char mem_section_id_le[] =3D {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE, + 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C, + 0x83, 0xB1}; + + cpu_physical_memory_read(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Get the current generic error status block length */ + current_block_length =3D sizeof(AcpiGenericErrorStatus) + + le32_to_cpu(block.data_length); + + /* If the Generic Error Status Block is NULL, update + * the block header + */ + if (!block.block_status) { + block.block_status =3D ACPI_GEBS_UNCORRECTABLE; + block.error_severity =3D ACPI_CPER_SEV_RECOVERABLE; + } + + block.data_length +=3D cpu_to_le32(sizeof(AcpiGenericErrorData)); + block.data_length +=3D cpu_to_le32(sizeof(UefiCperSecMemErr)); + + /* check whether it runs out of the preallocated memory */ + if ((le32_to_cpu(block.data_length) + sizeof(AcpiGenericErrorStatus)) > + GHES_MAX_RAW_DATA_LENGTH) { + error_report("Record CPER out of boundary!!!"); + return GHES_CPER_FAIL; + } + + /* Write back the Generic Error Status Block to guest memory */ + cpu_physical_memory_write(error_block_address, &block, + sizeof(AcpiGenericErrorStatus)); + + /* Fill in Generic Error Data Entry */ + buffer =3D g_malloc0(sizeof(AcpiGenericErrorData) + + sizeof(UefiCperSecMemErr)); + + + memset(buffer, 0, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMem= Err)); + gdata =3D (AcpiGenericErrorData *)buffer; + + /* Memory section */ + memcpy(&(gdata->section_type_le), &mem_section_id_le, + sizeof(mem_section_id_le)); + + /* error severity is recoverable */ + gdata->error_severity =3D ACPI_CPER_SEV_RECOVERABLE; + gdata->revision =3D 0x300; /* the revision number is 0x300 */ + gdata->error_data_length =3D cpu_to_le32(sizeof(UefiCperSecMemErr)); + + mem_err =3D (UefiCperSecMemErr *) (gdata + 1); + + /* User space only handle the memory section CPER */ + + /* Hard code to Multi-bit ECC error */ + mem_err->validation_bits |=3D cpu_to_le32(UEFI_CPER_MEM_VALID_ERROR_TY= PE); + mem_err->error_type =3D cpu_to_le32(UEFI_CPER_MEM_ERROR_TYPE_MULTI_ECC= ); + + /* Record the physical address at which the memory error occurred */ + mem_err->validation_bits |=3D cpu_to_le32(UEFI_CPER_MEM_VALID_PA); + mem_err->physical_addr =3D cpu_to_le32(error_physical_addr); + + /* Write back the Generic Error Data Entry to guest memory */ + cpu_physical_memory_write(error_block_address + current_block_length, + buffer, sizeof(AcpiGenericErrorData) + sizeof(UefiCperSecMemErr)); + + g_free(buffer); + return GHES_CPER_OK; +} + +static void +build_address(GArray *table_data, BIOSLinker *linker, + uint32_t dst_patched_offset, uint32_t src_offset, + uint8_t address_space_id , uint8_t register_bit_width, + uint8_t register_bit_offset, uint8_t access_size) +{ + uint32_t address_size =3D sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + /* Address space */ + build_append_int_noprefix(table_data, address_space_id, 1); + /* register bit width */ + build_append_int_noprefix(table_data, register_bit_width, 1); + /* register bit offset */ + build_append_int_noprefix(table_data, register_bit_offset, 1); + /* access size */ + build_append_int_noprefix(table_data, access_size, 1); + acpi_data_push(table_data, address_size); + + /* Patch address of ERRORS fw_cfg blob into the TABLE fw_cfg blob so O= SPM + * can retrieve and read it. the address size is 64 bits. + */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, dst_patched_offset, sizeof(uint64_t), + GHES_ERRORS_FW_CFG_FILE, src_offset); +} + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker) +{ + uint32_t ghes_start =3D table_data->len; + uint32_t address_size, error_status_address_offset; + uint32_t read_ack_register_offset, i; + + address_size =3D sizeof(struct AcpiGenericAddress) - + offsetof(struct AcpiGenericAddress, address); + + error_status_address_offset =3D ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, error_status_address) + + offsetof(struct AcpiGenericAddress, address); + + read_ack_register_offset =3D ghes_start + + sizeof(AcpiHardwareErrorSourceTable) + + offsetof(AcpiGenericHardwareErrorSourceV2, read_ack_register) + + offsetof(struct AcpiGenericAddress, address); + + acpi_data_push(hardware_error, + offsetof(struct hardware_errors_buffer, ack_value)); + for (i =3D 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Initialize read ack register */ + build_append_int_noprefix((void *)hardware_error, 1, 8); + + /* Reserved the total size for ERRORS fw_cfg blob + */ + acpi_data_push(hardware_error, sizeof(struct hardware_errors_buffer)); + + /* Allocate guest memory for the Data fw_cfg blob */ + bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_err= or, + 1, false); + /* Reserve table header size */ + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + build_append_int_noprefix(table_data, GHES_ACPI_HEST_NOTIFY_RESERVED, = 4); + + for (i =3D 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) { + build_append_int_noprefix(table_data, + ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */ + /* source id */ + build_append_int_noprefix(table_data, cpu_to_le16(i), 2); + /* related source id */ + build_append_int_noprefix(table_data, 0xffff, 2); + build_append_int_noprefix(table_data, 0, 1); /* flags */ + + /* Currently only enable SEA notification type to avoid the kernel + * warning, reserve the space for other notification error source + */ + if (i =3D=3D ACPI_HEST_NOTIFY_SEA) { + build_append_int_noprefix(table_data, 1, 1); /* enabled */ + } else { + build_append_int_noprefix(table_data, 0, 1); /* enabled */ + } + + /* The number of error status block per generic hardware error sou= rce */ + build_append_int_noprefix(table_data, 1, 4); + /* Max sections per record */ + build_append_int_noprefix(table_data, 1, 4); + /* Max raw data length */ + build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4); + + /* Build error status address*/ + build_address(table_data, linker, error_status_address_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), i * address_size, + AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */); + + /* Hardware error notification structure */ + build_append_int_noprefix(table_data, i, 1); /* type */ + /* length */ + build_append_int_noprefix(table_data, sizeof(AcpiHestNotify), 1); + build_append_int_noprefix(table_data, 0, 26); + + /* Error Status Block Length */ + build_append_int_noprefix(table_data, + cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4); + + /* Build read ack register */ + build_address(table_data, linker, read_ack_register_offset + i * + sizeof(AcpiGenericHardwareErrorSourceV2), + offsetof(struct hardware_errors_buffer, ack_value) + + i * address_size, AML_SYSTEM_MEMORY, 0x40, 0, + 4 /* QWord access */); + + /* Read ack preserve */ + build_append_int_noprefix(table_data, cpu_to_le64(0xfffffffe), 8); + + /* Read ack write */ + build_append_int_noprefix(table_data, cpu_to_le64(0x1), 8); + } + + for (i =3D 0; i < GHES_ACPI_HEST_NOTIFY_RESERVED; i++) + /* Patch address of generic error status block into + * the address register so OSPM can retrieve and read it. + */ + bios_linker_loader_add_pointer(linker, + GHES_ERRORS_FW_CFG_FILE, address_size * i, address_size, + GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb) + + i * GHES_MAX_RAW_DATA_LENGTH); + + /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob + * so QEMU can write the ERRORS there. The address is expected to be + * < 4GB, but write 64 bits anyway. + */ + bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE, + 0, address_size, GHES_ERRORS_FW_CFG_FILE, + offsetof(struct hardware_errors_buffer, gesb)); + + build_header(linker, table_data, + (void *)(table_data->data + ghes_start), "HEST", + table_data->len - ghes_start, 1, NULL, "GHES"); +} + +static GhesState ges; +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error) +{ + + size_t request_block_size =3D sizeof(uint64_t) + GHES_MAX_RAW_DATA_LEN= GTH; + size_t size =3D GHES_ACPI_HEST_NOTIFY_RESERVED * request_block_size; + + /* Create a read-only fw_cfg file for GHES */ + fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data, + size); + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, + &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false); +} + +bool ghes_update_guest(uint32_t notify, uint64_t physical_address) +{ + uint64_t error_block_addr; + uint64_t ack_value_addr, ack_value =3D 0; + int loop =3D 0, ack_value_size; + bool ret =3D GHES_CPER_FAIL; + + ack_value_size =3D (offsetof(struct hardware_errors_buffer, gesb) - + offsetof(struct hardware_errors_buffer, ack_value)) / + GHES_ACPI_HEST_NOTIFY_RESERVED; + + if (physical_address && notify < GHES_ACPI_HEST_NOTIFY_RESERVED) { + error_block_addr =3D ges.ghes_addr_le + notify * GHES_MAX_RAW_DATA= _LENGTH; + error_block_addr =3D le32_to_cpu(error_block_addr); + + ack_value_addr =3D ges.ghes_addr_le - + (GHES_ACPI_HEST_NOTIFY_RESERVED - notify) * ack_value_size; +retry: + cpu_physical_memory_read(ack_value_addr, &ack_value, ack_value_siz= e); + if (!ack_value) { + if (loop < 3) { + usleep(100 * 1000); + loop++; + goto retry; + } else { + error_report("Last time OSPM does not acknowledge the erro= r," + " record CPER failed this time, set the ack value to" + " avoid blocking next time CPER record! exit"); + ack_value =3D 1; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + return ret; + } + } else { + /* A zero value in ghes_addr means that BIOS has not yet writt= en + * the address + */ + if (error_block_addr) { + ack_value =3D 0; + cpu_physical_memory_write(ack_value_addr, + &ack_value, ack_value_size); + ret =3D ghes_record_cper(error_block_addr, physical_addres= s); + } + } + } + return ret; +} diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3d78ff6..def1ec1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -45,6 +45,7 @@ #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "kvm_arm.h" +#include "hw/acpi/hest_ghes.h" =20 #define ARM_SPI_BASE 32 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -771,6 +772,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) acpi_add_table(table_offsets, tables_blob); build_spcr(tables_blob, tables->linker, vms); =20 + acpi_add_table(table_offsets, tables_blob); + ghes_build_acpi(tables_blob, tables->hardware_errors, tables->linker); + if (nb_numa_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, vms); @@ -887,6 +891,8 @@ void virt_acpi_setup(VirtMachineState *vms) fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->d= ata, acpi_data_len(tables.tcpalog)); =20 + ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors); + build_state->rsdp_mr =3D acpi_add_rom_blob(build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); =20 diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 88d0738..7f7b55c 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -211,6 +211,7 @@ struct AcpiBuildTables { GArray *rsdp; GArray *tcpalog; GArray *vmgenid; + GArray *hardware_errors; BIOSLinker *linker; } AcpiBuildTables; =20 diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h new file mode 100644 index 0000000..0772756 --- /dev/null +++ b/include/hw/acpi/hest_ghes.h @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Authors: + * Dongjiu Geng + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef ACPI_GHES_H +#define ACPI_GHES_H + +#include "hw/acpi/bios-linker-loader.h" + +#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors" +#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" + +#define GHES_GAS_ADDRESS_OFFSET 4 +#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20 +#define GHES_NOTIFICATION_STRUCTURE 32 + +#define GHES_CPER_OK 1 +#define GHES_CPER_FAIL 0 + +#define GHES_ACPI_HEST_NOTIFY_RESERVED 11 +/* The max size in Bytes for one error block */ +#define GHES_MAX_RAW_DATA_LENGTH 0x1000 + + +typedef struct GhesState { + uint64_t ghes_addr_le; +} GhesState; + +void ghes_build_acpi(GArray *table_data, GArray *hardware_error, + BIOSLinker *linker); +void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors); +bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr); +#endif --=20 1.8.3.1 From nobody Mon Apr 29 17:16:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503065092965761.7242456679681; Fri, 18 Aug 2017 07:04:52 -0700 (PDT) Received: from localhost ([::1]:55966 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihtL-0005y8-Oa for importer@patchew.org; Fri, 18 Aug 2017 10:04:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqe-00048B-6B for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqd-00005B-94 for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:04 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2236) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqW-0008QT-Tv; Fri, 18 Aug 2017 10:01:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74401; Fri, 18 Aug 2017 22:00:47 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:13 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:44 +0800 Message-ID: <1503066227-18251-4-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F30F.0212, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 42727865dfb62d32f4afad31125f8e15 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 3/6] ACPI: build and enable APEI GHES in the Makefile and configuration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CONFIG_ACPI_APEI configuration in the Makefile and enable it in the arm-softmmu.mak Signed-off-by: Dongjiu Geng --- default-configs/arm-softmmu.mak | 1 + hw/acpi/Makefile.objs | 1 + 2 files changed, 2 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index bbdd3c1..c362113 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -129,3 +129,4 @@ CONFIG_ACPI=3Dy CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_GPIO_KEY=3Dy +CONFIG_ACPI_APEI=3Dy diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs index 11c35bc..bafb148 100644 --- a/hw/acpi/Makefile.objs +++ b/hw/acpi/Makefile.objs @@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) +=3D memory_hotplu= g.o common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) +=3D cpu.o common-obj-$(CONFIG_ACPI_NVDIMM) +=3D nvdimm.o common-obj-$(CONFIG_ACPI_VMGENID) +=3D vmgenid.o +common-obj-$(CONFIG_ACPI_APEI) +=3D hest_ghes.o common-obj-$(call lnot,$(CONFIG_ACPI_X86)) +=3D acpi-stub.o =20 common-obj-y +=3D acpi_interface.o --=20 1.8.3.1 From nobody Mon Apr 29 17:16:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Fri, 18 Aug 2017 10:01:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74404; Fri, 18 Aug 2017 22:00:47 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:13 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:45 +0800 Message-ID: <1503066227-18251-5-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F30F.02DB, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 888d5f8d1e081f94f5dc4a02f078723a X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 4/6] target-arm: kvm64: detect guest RAS EXTENSION feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" check if kvm supports guest RAS EXTENSION. if so, set corresponding feature bit for vcpu. Signed-off-by: Dongjiu Geng --- linux-headers/linux/kvm.h | 1 + target/arm/cpu.h | 3 +++ target/arm/kvm64.c | 8 ++++++++ 3 files changed, 12 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 7971a4f..2aa176e 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -929,6 +929,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SMT_POSSIBLE 147 #define KVM_CAP_HYPERV_SYNIC2 148 #define KVM_CAP_HYPERV_VP_INDEX 149 +#define KVM_CAP_ARM_RAS_EXTENSION 150 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64a..6b0961b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -611,6 +611,8 @@ struct ARMCPU { =20 /* CPU has memory protection unit */ bool has_mpu; + /* CPU has ras extension unit */ + bool has_ras_extension; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; =20 @@ -1229,6 +1231,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_RAS_EXTENSION, /*has RAS extension support */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index a16abc8..0781367 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -518,6 +518,14 @@ int kvm_arch_init_vcpu(CPUState *cs) unset_feature(&env->features, ARM_FEATURE_PMU); } =20 + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_RAS_EXTENSION)) { + cpu->has_ras_extension =3D true; + set_feature(&env->features, ARM_FEATURE_RAS_EXTENSION); + } else { + cpu->has_ras_extension =3D false; + unset_feature(&env->features, ARM_FEATURE_RAS_EXTENSION); + } + /* Do KVM_ARM_VCPU_INIT ioctl */ ret =3D kvm_arm_vcpu_init(cs); if (ret) { --=20 1.8.3.1 From nobody Mon Apr 29 17:16:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503065402467664.1119477622835; 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Fri, 18 Aug 2017 22:00:13 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:46 +0800 Message-ID: <1503066227-18251-6-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.5996F310.00E0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: dbca42ab5aec7b3a3582b2370f2434d9 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 5/6] target-arm: kvm64: handle SIGBUS signal for synchronous External Abort X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SIGBUS signal handler. In this handler, it checks the exception type, translates the host VA which is delivered by host or KVM to guest PA, then fills this PA to CPER, finally injects a Error to guest OS through KVM. Add synchronous external abort injection logic, setup spsr_elx, esr_elx, PSTATE, far_elx, elr_elx etc, when switch to guest OS, it will jump to the synchronous external abort vector table entry. Signed-off-by: Dongjiu Geng Signed-off-by: Quanming Wu --- include/sysemu/kvm.h | 2 +- linux-headers/asm-arm64/kvm.h | 5 ++ target/arm/internals.h | 13 ++++ target/arm/kvm.c | 34 ++++++++++ target/arm/kvm64.c | 150 ++++++++++++++++++++++++++++++++++++++= ++++ target/arm/kvm_arm.h | 1 + 6 files changed, 204 insertions(+), 1 deletion(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 3a458f5..90c1605 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -361,7 +361,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id); /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */ unsigned long kvm_arch_vcpu_id(CPUState *cpu); =20 -#ifdef TARGET_I386 +#if defined(TARGET_I386) || defined(TARGET_AARCH64) #define KVM_HAVE_MCE_INJECTION 1 void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); #endif diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index d254700..5909c30 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -181,6 +181,11 @@ struct kvm_arch_memory_slot { #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 =20 +/* AArch64 fault registers */ +#define KVM_REG_ARM64_FAULT (0x0014 << KVM_REG_ARM_COPROC_SHIF= T) +#define KVM_REG_ARM64_FAULT_ESR_EC (0) +#define KVM_REG_ARM64_FAULT_FAR (1) + #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ KVM_REG_ARM64_SYSREG_ ## n ## _MASK) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f6efef..fc0ad6d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -235,6 +235,19 @@ enum arm_exception_class { #define ARM_EL_ISV_SHIFT 24 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) +#define ARM_EL_EC_MASK ((0x3F) << ARM_EL_EC_SHIFT) +#define ARM_EL_FSC_TYPE (0x3C) + +#define FSC_SEA (0x10) +#define FSC_SEA_TTW0 (0x14) +#define FSC_SEA_TTW1 (0x15) +#define FSC_SEA_TTW2 (0x16) +#define FSC_SEA_TTW3 (0x17) +#define FSC_SECC (0x18) +#define FSC_SECC_TTW0 (0x1c) +#define FSC_SECC_TTW1 (0x1d) +#define FSC_SECC_TTW2 (0x1e) +#define FSC_SECC_TTW3 (0x1f) =20 /* Utility functions for constructing various kinds of syndrome value. * Note that in general we follow the AArch64 syndrome values; in a diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7c17f0d..2e1716a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -129,6 +129,39 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } =20 +typedef struct HWPoisonPage { + ram_addr_t ram_addr; + QLIST_ENTRY(HWPoisonPage) list; +} HWPoisonPage; + +static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =3D + QLIST_HEAD_INITIALIZER(hwpoison_page_list); + +static void kvm_unpoison_all(void *param) +{ + HWPoisonPage *page, *next_page; + + QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { + QLIST_REMOVE(page, list); + qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); + g_free(page); + } +} + +void kvm_hwpoison_page_add(ram_addr_t ram_addr) +{ + HWPoisonPage *page; + + QLIST_FOREACH(page, &hwpoison_page_list, list) { + if (page->ram_addr =3D=3D ram_addr) { + return; + } + } + page =3D g_new(HWPoisonPage, 1); + page->ram_addr =3D ram_addr; + QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); +} + static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data) { ARMHostCPUClass *ahcc =3D ARM_HOST_CPU_CLASS(oc); @@ -182,6 +215,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 cap_has_mp_state =3D kvm_check_extension(s, KVM_CAP_MP_STATE); =20 + qemu_register_reset(kvm_unpoison_all, NULL); type_register_static(&host_arm_cpu_type_info); =20 return 0; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0781367..d3bdab2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -27,6 +27,8 @@ #include "kvm_arm.h" #include "internals.h" #include "hw/arm/arm.h" +#include "hw/acpi/acpi-defs.h" +#include "hw/acpi/hest_ghes.h" =20 static bool have_guest_debug; =20 @@ -590,6 +592,79 @@ int kvm_arm_cpreg_level(uint64_t regidx) return KVM_PUT_RUNTIME_STATE; } =20 +static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t fieldoffset) +{ + int i; + + for (i =3D 0; i < cpu->cpreg_array_len; i++) { + uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + const ARMCPRegInfo *ri; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + if (!ri) { + continue; + } + + if (ri->type & ARM_CP_NO_RAW) { + continue; + } + + if (ri->fieldoffset =3D=3D fieldoffset) { + cpu->cpreg_values[i] =3D read_raw_cp_reg(&cpu->env, ri); + return 0; + } + } + return -EINVAL; +} + +/* Inject synchronous external abort */ +static int kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu =3D ARM_CPU(c); + CPUARMState *env =3D &cpu->env; + unsigned long cpsr =3D pstate_read(env); + uint32_t esr =3D 0; + int ret; + + c->exception_index =3D EXCP_DATA_ABORT; + /* Inject the exception to El1 */ + env->exception.target_el =3D 1; + CPUClass *cc =3D CPU_GET_CLASS(c); + + esr |=3D (EC_DATAABORT << ARM_EL_EC_SHIFT); + /* This exception syndrome includes {I,D}FSC in the bits [5:0] + */ + esr |=3D (env->exception.syndrome & 0x3f); + + /* This exception is EL0 or EL1 fault. */ + if ((cpsr & 0xf) =3D=3D PSTATE_MODE_EL0t) { + esr |=3D (EC_INSNABORT << ARM_EL_EC_SHIFT); + } else { + esr |=3D (EC_INSNABORT_SAME_EL << ARM_EL_EC_SHIFT); + } + + /* In the aarch64, there is only 32-bit instruction*/ + esr |=3D ARM_EL_IL; + env->exception.syndrome =3D esr; + cc->do_interrupt(c); + + /* set ESR_EL1 */ + ret =3D kvm_arm_cpreg_value(cpu, offsetof(CPUARMState, cp15.esr_el[1])= ); + + if (ret) { + fprintf(stderr, "<%s> failed to set esr_el1\n", __func__); + abort(); + } + + /* set FAR_EL1 */ + ret =3D kvm_arm_cpreg_value(cpu, offsetof(CPUARMState, cp15.far_el[1])= ); + if (ret) { + fprintf(stderr, "<%s> failed to set far_el1\n", __func__); + abort(); + } + + return 0; +} + #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) =20 @@ -599,6 +674,9 @@ int kvm_arm_cpreg_level(uint64_t regidx) #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) =20 +#define AARCH64_FAULT_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ + KVM_REG_ARM64_FAULT | (x)) + int kvm_arch_put_registers(CPUState *cs, int level) { struct kvm_one_reg reg; @@ -873,6 +951,22 @@ int kvm_arch_get_registers(CPUState *cs) } vfp_set_fpcr(env, fpr); =20 + if (is_a64(env)) { + reg.id =3D AARCH64_FAULT_REG(KVM_REG_ARM64_FAULT_ESR_EC); + reg.addr =3D (uintptr_t)(&env->exception.syndrome); + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } + + reg.id =3D AARCH64_FAULT_REG(KVM_REG_ARM64_FAULT_FAR); + reg.addr =3D (uintptr_t)(&env->exception.vaddress); + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + if (ret) { + return ret; + } + } + if (!write_kvmstate_to_list(cpu)) { return EINVAL; } @@ -887,6 +981,62 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 +static bool is_abort_sea(unsigned long syndrome) +{ + unsigned long fault_status; + uint8_t ec =3D ((syndrome & ARM_EL_EC_MASK) >> ARM_EL_EC_SHIFT); + if ((ec !=3D EC_INSNABORT) && (ec !=3D EC_DATAABORT)) { + return false; + } + + fault_status =3D syndrome & ARM_EL_FSC_TYPE; + switch (fault_status) { + case FSC_SEA: + case FSC_SEA_TTW0: + case FSC_SEA_TTW1: + case FSC_SEA_TTW2: + case FSC_SEA_TTW3: + case FSC_SECC: + case FSC_SECC_TTW0: + case FSC_SECC_TTW1: + case FSC_SECC_TTW2: + case FSC_SECC_TTW3: + return true; + default: + return false; + } +} + +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + ARMCPU *cpu =3D ARM_CPU(c); + CPUARMState *env =3D &cpu->env; + assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); + if (addr) { + ram_addr =3D qemu_ram_addr_from_host(addr); + if (ram_addr !=3D RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { + kvm_cpu_synchronize_state(c); + kvm_hwpoison_page_add(ram_addr); + if (is_abort_sea(env->exception.syndrome)) { + ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr); + kvm_inject_arm_sea(c); + } + return; + } + fprintf(stderr, "Hardware memory error for memory used by " + "QEMU itself instead of guest system!\n"); + } + + if (code =3D=3D BUS_MCEERR_AR) { + fprintf(stderr, "Hardware memory error!\n"); + exit(1); + } +} + /* C6.6.29 BRK instruction */ static const uint32_t brk_insn =3D 0xd4200000; =20 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 633d088..7cdde97 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -288,4 +288,5 @@ static inline const char *its_class_name(void) } } =20 +void kvm_hwpoison_page_add(ram_addr_t ram_addr); #endif --=20 1.8.3.1 From nobody Mon Apr 29 17:16:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150306523377153.817105111815636; Fri, 18 Aug 2017 07:07:13 -0700 (PDT) Received: from localhost ([::1]:56002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihvc-000878-HG for importer@patchew.org; Fri, 18 Aug 2017 10:07:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51637) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dihqm-0004CY-LT for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dihqg-00007p-T3 for qemu-devel@nongnu.org; Fri, 18 Aug 2017 10:02:12 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2237) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dihqY-0008RQ-HQ; Fri, 18 Aug 2017 10:01:59 -0400 Received: from 172.30.72.58 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DFM74412; Fri, 18 Aug 2017 22:00:48 +0800 (CST) Received: from linux.huawei.com (10.67.187.203) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Fri, 18 Aug 2017 22:00:14 +0800 From: Dongjiu Geng To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 18 Aug 2017 22:23:47 +0800 Message-ID: <1503066227-18251-7-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> References: <1503066227-18251-1-git-send-email-gengdongjiu@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.187.203] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0207.5996F310.019D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a2fc3c2d8f4dd5ae8c41d992041e0951 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 45.249.212.191 Subject: [Qemu-devel] [PATCH v11 6/6] target-arm: kvm64: Handle SError interrupt for the guest OS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhengqiang10@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, linuxarm@huawei.com, gengdongjiu@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When guest OS happens SError interrupt(SEI), it will trap to host. Host firstly calls memory failure to deal with this error and decide whether it needs to deliver SIGBUS signal to userspace. The advantage that using signal to notify is that it can make the notification method is general, non-KVM user can also use it. when userspace gets this signal and knows this is SError interrupt, it will translate the delivered host VA to PA and record this PA to GHES. Because ARMv8.2 adds an extension to RAS to allow system software insert implicit Error Synchronization Barrier operations to isolate the error and allow passes specified syndrome to guest OS, so after record the CPER, user space calls IOCTL to pass a specified syndrome to KVM, then switch to guest OS, guest OS can use the recorded CPER record and syndrome information to do the recovery. The steps are shown below: 1. translate the host VA to guest OS PA and record this error PA to HEST ta= ble. 2. set specified virtual SError syndrome and pass the value to KVM. Signed-off-by: Dongjiu Geng Signed-off-by: Quanming Wu --- linux-headers/linux/kvm.h | 1 + target/arm/internals.h | 1 + target/arm/kvm64.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 2aa176e..10dfcab 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1356,6 +1356,7 @@ struct kvm_s390_ucas_mapping { /* Available with KVM_CAP_S390_CMMA_MIGRATION */ #define KVM_S390_GET_CMMA_BITS _IOWR(KVMIO, 0xb8, struct kvm_s390_cmm= a_log) #define KVM_S390_SET_CMMA_BITS _IOW(KVMIO, 0xb9, struct kvm_s390_cmma= _log) +#define KVM_ARM_SEI _IO(KVMIO, 0xb10) =20 #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) diff --git a/target/arm/internals.h b/target/arm/internals.h index fc0ad6d..18b1cbc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -237,6 +237,7 @@ enum arm_exception_class { #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) #define ARM_EL_EC_MASK ((0x3F) << ARM_EL_EC_SHIFT) #define ARM_EL_FSC_TYPE (0x3C) +#define ARM_EL_ISS_MASK ((1 << ARM_EL_IL_SHIFT) - 1) =20 #define FSC_SEA (0x10) #define FSC_SEA_TTW0 (0x14) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d3bdab2..b84cb49 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -616,6 +616,22 @@ static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t = fieldoffset) return -EINVAL; } =20 +static int kvm_inject_arm_sei(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + unsigned long syndrome =3D env->exception.vaddress; + /* set virtual SError syndrome */ + if (arm_feature(env, ARM_FEATURE_RAS_EXTENSION)) { + syndrome =3D syndrome & ARM_EL_ISS_MASK; + } else { + syndrome =3D 0; + } + + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_SEI, &syndrome); +} + /* Inject synchronous external abort */ static int kvm_inject_arm_sea(CPUState *c) { @@ -1007,6 +1023,15 @@ static bool is_abort_sea(unsigned long syndrome) } } =20 +static bool is_abort_sei(unsigned long syndrome) +{ + uint8_t ec =3D ((syndrome & ARM_EL_EC_MASK) >> ARM_EL_EC_SHIFT); + if ((ec !=3D EC_SERROR)) + return false; + else + return true; +} + void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) { ram_addr_t ram_addr; @@ -1024,6 +1049,9 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, v= oid *addr) if (is_abort_sea(env->exception.syndrome)) { ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr); kvm_inject_arm_sea(c); + } else if (is_abort_sei(env->exception.syndrome)) { + ghes_update_guest(ACPI_HEST_NOTIFY_SEI, paddr); + kvm_inject_arm_sei(c); } return; } --=20 1.8.3.1