From nobody Fri May 3 20:56:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502812679101166.5901924210424; Tue, 15 Aug 2017 08:57:59 -0700 (PDT) Received: from localhost ([::1]:43498 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dheE9-0006i3-Kv for importer@patchew.org; Tue, 15 Aug 2017 11:57:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhd5c-0006oW-GU for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:45:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dhd5X-00051o-Ho for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:45:04 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:60947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dhd5X-0004zJ-BT for qemu-devel@nongnu.org; Tue, 15 Aug 2017 10:44:59 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id D5BF21E6E1AD3; Tue, 15 Aug 2017 15:44:49 +0100 (IST) Received: from mredfearn-linux.le.imgtec.org (10.150.130.83) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Tue, 15 Aug 2017 15:44:52 +0100 From: Matt Redfearn To: "Michael S . Tsirkin" , Marcel Apfelbaum Date: Tue, 15 Aug 2017 15:44:17 +0100 Message-ID: <1502808257-17395-1-git-send-email-matt.redfearn@imgtec.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.150.130.83] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 X-Mailman-Approved-At: Tue, 15 Aug 2017 11:56:42 -0400 Subject: [Qemu-devel] [PATCH] PCI: PCIe access should always be little endian X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Matt Redfearn , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PCIe busses are always little endian, so set the endianness of the memory region to little endian rather than native such that operations work as expected on big endian targets. Signed-off-by: Matt Redfearn Reviewed-by: Marcel Apfelbaum --- hw/pci/pcie_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index dcebf57ed45e..553db56778b6 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, static const MemoryRegionOps pcie_mmcfg_ops =3D { .read =3D pcie_mmcfg_data_read, .write =3D pcie_mmcfg_data_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static void pcie_host_init(Object *obj) --=20 2.7.4