From nobody Mon May 6 23:15:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502333973128545.593577495303; Wed, 9 Aug 2017 19:59:33 -0700 (PDT) Received: from localhost ([::1]:50754 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfdh5-0003uq-Uo for importer@patchew.org; Wed, 09 Aug 2017 22:59:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfdfi-000392-M3 for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfdfe-0002cC-Ry for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:06 -0400 Received: from mga07.intel.com ([134.134.136.100]:53881) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfdfe-0002aX-JL for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:02 -0400 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP; 09 Aug 2017 19:58:01 -0700 Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.141]) by orsmga004.jf.intel.com with ESMTP; 09 Aug 2017 19:57:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,349,1498546800"; d="scan'208";a="117462840" From: Lan Tianyu To: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org Date: Wed, 9 Aug 2017 16:51:20 -0400 Message-Id: <1502311882-11038-2-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1502311882-11038-1-git-send-email-tianyu.lan@intel.com> References: <1502311882-11038-1-git-send-email-tianyu.lan@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.100 Subject: [Qemu-devel] [PATCH V2 1/3] i386/msi: Correct mask of destination ID in MSI address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , kevin.tian@intel.com, sstabellini@kernel.org, ehabkost@redhat.com, mst@redhat.com, marcel@redhat.com, anthony.perard@citrix.com, pbonzini@redhat.com, Chao Gao , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chao Gao According to SDM 10.11.1, only [19:12] bits of MSI address are Destination ID, change the mask to avoid ambiguity for VT-d spec has used the bit 4 to indicate a remappable interrupt request. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu Reviewed-by: Anthony PERARD Reviewed-by: Peter Xu --- include/hw/i386/apic-msidef.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/i386/apic-msidef.h b/include/hw/i386/apic-msidef.h index 8b4d4cc..420b411 100644 --- a/include/hw/i386/apic-msidef.h +++ b/include/hw/i386/apic-msidef.h @@ -26,6 +26,6 @@ =20 #define MSI_ADDR_DEST_ID_SHIFT 12 #define MSI_ADDR_DEST_IDX_SHIFT 4 -#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 +#define MSI_ADDR_DEST_ID_MASK 0x000ff000 =20 #endif /* HW_APIC_MSIDEF_H */ --=20 1.8.3.1 From nobody Mon May 6 23:15:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502334079905740.0547894398621; Wed, 9 Aug 2017 20:01:19 -0700 (PDT) Received: from localhost ([::1]:50766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfdio-0005Lm-NQ for importer@patchew.org; Wed, 09 Aug 2017 23:01:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfdfl-0003At-S3 for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfdfi-0002eU-0T for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:09 -0400 Received: from mga09.intel.com ([134.134.136.24]:2418) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfdfh-0002dc-L3 for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:05 -0400 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2017 19:58:04 -0700 Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.141]) by fmsmga005.fm.intel.com with ESMTP; 09 Aug 2017 19:58:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,349,1498546800"; d="scan'208";a="137770638" From: Lan Tianyu To: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org Date: Wed, 9 Aug 2017 16:51:21 -0400 Message-Id: <1502311882-11038-3-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1502311882-11038-1-git-send-email-tianyu.lan@intel.com> References: <1502311882-11038-1-git-send-email-tianyu.lan@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Subject: [Qemu-devel] [PATCH V2 2/3] xen-pt: bind/unbind interrupt remapping format MSI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , kevin.tian@intel.com, sstabellini@kernel.org, ehabkost@redhat.com, mst@redhat.com, marcel@redhat.com, anthony.perard@citrix.com, pbonzini@redhat.com, Chao Gao , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chao Gao If a vIOMMU is exposed to guest, guest will configure the msi to remapping format. The original code isn't suitable to the new format. A new pair bind/unbind interfaces are added for this usage. This patch recognizes this case and uses new interfaces to bind/unbind msi. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu Reviewed-by: Anthony PERARD --- configure | 4 +++- hw/xen/xen_pt_msi.c | 50 ++++++++++++++++++++++++++++++++-------= ---- include/hw/i386/apic-msidef.h | 1 + include/hw/xen/xen_common.h | 25 ++++++++++++++++++++++ 4 files changed, 66 insertions(+), 14 deletions(-) diff --git a/configure b/configure index dd73cce..92b56d3 100755 --- a/configure +++ b/configure @@ -2108,13 +2108,15 @@ EOF elif cat > $TMPC < #include int main(void) { + xc_interface *xc =3D NULL; xenforeignmemory_handle *xfmem; =20 xfmem =3D xenforeignmemory_open(0, 0); xenforeignmemory_map2(xfmem, 0, 0, 0, 0, 0, 0, 0); - + xc_domain_update_msi_irq_remapping(xc, 0, 0, 0, 0, 0, 0); return 0; } EOF diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c index ff9a79f..5c5d15a 100644 --- a/hw/xen/xen_pt_msi.c +++ b/hw/xen/xen_pt_msi.c @@ -163,16 +163,23 @@ static int msi_msix_update(XenPCIPassthroughState *s, int rc =3D 0; uint64_t table_addr =3D 0; =20 - XEN_PT_LOG(d, "Updating MSI%s with pirq %d gvec %#x gflags %#x" - " (entry: %#x)\n", - is_msix ? "-X" : "", pirq, gvec, gflags, msix_entry); - if (is_msix) { table_addr =3D s->msix->mmio_base_addr; } =20 - rc =3D xc_domain_update_msi_irq(xen_xc, xen_domid, gvec, - pirq, gflags, table_addr); + if (addr & MSI_ADDR_IF_MASK) { + XEN_PT_LOG(d, "Updating MSI%s with addr %#" PRIx64 " data %#x\n", + is_msix ? "-X" : "", addr, data); + rc =3D xc_domain_update_msi_irq_remapping(xen_xc, xen_domid, pirq, + d->devfn, data, addr, table_a= ddr); + } else { + XEN_PT_LOG(d, "Updating MSI%s with pirq %d gvec %#x gflags %#x" + " (entry: %#x)\n", + is_msix ? "-X" : "", pirq, gvec, gflags, msix_entry); + + rc =3D xc_domain_update_msi_irq(xen_xc, xen_domid, gvec, + pirq, gflags, table_addr); + } =20 if (rc) { XEN_PT_ERR(d, "Updating of MSI%s failed. (err: %d)\n", @@ -204,13 +211,30 @@ static int msi_msix_disable(XenPCIPassthroughState *s, } =20 if (is_binded) { - XEN_PT_LOG(d, "Unbind MSI%s with pirq %d, gvec %#x\n", - is_msix ? "-X" : "", pirq, gvec); - rc =3D xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec, pirq, gfl= ags); - if (rc) { - XEN_PT_ERR(d, "Unbinding of MSI%s failed. (err: %d, pirq: %d, = gvec: %#x)\n", - is_msix ? "-X" : "", errno, pirq, gvec); - return rc; + if (addr & MSI_ADDR_IF_MASK) { + XEN_PT_LOG(d, "Unbinding of MSI%s . ( pirq: %d, data: %x, " + "addr: %#" PRIx64 ")\n", + is_msix ? "-X" : "", pirq, data, addr); + rc =3D xc_domain_unbind_msi_irq_remapping(xen_xc, xen_domid, p= irq, + d->devfn, data, addr); + if (rc) { + XEN_PT_ERR(d, "Unbinding of MSI%s . (error: %d, pirq: %d, " + "data: %x, addr: %#" PRIx64 ")\n", + is_msix ? "-X" : "", rc, pirq, data, addr); + return rc; + } + + } else { + XEN_PT_LOG(d, "Unbind MSI%s with pirq %d, gvec %#x\n", + is_msix ? "-X" : "", pirq, gvec); + rc =3D xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec, + pirq, gflags); + if (rc) { + XEN_PT_ERR(d, "Unbinding of MSI%s failed. (err: %d, pirq: = %d, " + "gvec: %#x)\n", + is_msix ? "-X" : "", errno, pirq, gvec); + return rc; + } } } =20 diff --git a/include/hw/i386/apic-msidef.h b/include/hw/i386/apic-msidef.h index 420b411..a2b52d9 100644 --- a/include/hw/i386/apic-msidef.h +++ b/include/hw/i386/apic-msidef.h @@ -27,5 +27,6 @@ #define MSI_ADDR_DEST_ID_SHIFT 12 #define MSI_ADDR_DEST_IDX_SHIFT 4 #define MSI_ADDR_DEST_ID_MASK 0x000ff000 +#define MSI_ADDR_IF_MASK 0x00000010 =20 #endif /* HW_APIC_MSIDEF_H */ diff --git a/include/hw/xen/xen_common.h b/include/hw/xen/xen_common.h index 86c7f26..454ab6d 100644 --- a/include/hw/xen/xen_common.h +++ b/include/hw/xen/xen_common.h @@ -680,4 +680,29 @@ static inline int xengnttab_grant_copy(xengnttab_handl= e *xgt, uint32_t count, } #endif =20 +/* Xen before 4.10 */ +#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 41000 + +static inline int xc_domain_update_msi_irq_remapping(xc_interface *xc, + uint32_t domid, + uint32_t pirq, + uint32_t source_id, + uint32_t data, + uint64_t addr, + uint64_t gtable) +{ + return -ENOSYS; +} + +static inline int xc_domain_unbind_msi_irq_remapping(xc_interface *xc, + uint32_t domid, + uint32_t pirq, + uint32_t source_id, + uint32_t data, + uint64_t addr) +{ + return -ENOSYS; +} +#endif + #endif /* QEMU_HW_XEN_COMMON_H */ --=20 1.8.3.1 From nobody Mon May 6 23:15:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502334074957445.8447508841963; Wed, 9 Aug 2017 20:01:14 -0700 (PDT) Received: from localhost ([::1]:50765 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfdij-0005HG-NM for importer@patchew.org; Wed, 09 Aug 2017 23:01:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfdfo-0003DR-Rk for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfdfk-0002gT-Uj for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:12 -0400 Received: from mga03.intel.com ([134.134.136.65]:63975) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfdfk-0002ff-Kj for qemu-devel@nongnu.org; Wed, 09 Aug 2017 22:58:08 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2017 19:58:07 -0700 Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.141]) by FMSMGA003.fm.intel.com with ESMTP; 09 Aug 2017 19:58:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,349,1498546800"; d="scan'208";a="888416534" From: Lan Tianyu To: xen-devel@lists.xenproject.org, qemu-devel@nongnu.org Date: Wed, 9 Aug 2017 16:51:22 -0400 Message-Id: <1502311882-11038-4-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1502311882-11038-1-git-send-email-tianyu.lan@intel.com> References: <1502311882-11038-1-git-send-email-tianyu.lan@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH V2 3/3] msi: Handle remappable format interrupt request X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , kevin.tian@intel.com, sstabellini@kernel.org, ehabkost@redhat.com, mst@redhat.com, marcel@redhat.com, anthony.perard@citrix.com, pbonzini@redhat.com, Chao Gao , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chao Gao According to VT-d spec Interrupt Remapping and Interrupt Posting -> Interrupt Remapping -> Interrupt Request Formats On Intel 64 Platforms, fields of MSI data register have changed. This patch avoids wrongly regarding a remappable format interrupt request as an interrupt binded with an event channel. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu Acked-by: Anthony PERARD --- hw/i386/xen/xen-hvm.c | 8 +++++++- hw/pci/msi.c | 5 +++-- hw/pci/msix.c | 4 +++- hw/xen/xen_pt_msi.c | 2 +- include/hw/xen/xen.h | 2 +- stubs/xen-hvm.c | 2 +- 6 files changed, 16 insertions(+), 7 deletions(-) diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index d9ccd5d..cbbce73 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -145,8 +145,14 @@ void xen_piix_pci_write_config_client(uint32_t address= , uint32_t val, int len) } } =20 -int xen_is_pirq_msi(uint32_t msi_data) +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data) { + /* If the MSI address is configured in remapping format, the MSI will = not + * be remapped into a pirq. + */ + if (msi_addr_lo & MSI_ADDR_IF_MASK) { + return 0; + } /* If vector is 0, the msi is remapped into a pirq, passed as * dest_id. */ diff --git a/hw/pci/msi.c b/hw/pci/msi.c index 5e05ce5..d05c876 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -289,7 +289,7 @@ void msi_reset(PCIDevice *dev) static bool msi_is_masked(const PCIDevice *dev, unsigned int vector) { uint16_t flags =3D pci_get_word(dev->config + msi_flags_off(dev)); - uint32_t mask, data; + uint32_t mask, data, addr_lo; bool msi64bit =3D flags & PCI_MSI_FLAGS_64BIT; assert(vector < PCI_MSI_VECTORS_MAX); =20 @@ -298,7 +298,8 @@ static bool msi_is_masked(const PCIDevice *dev, unsigne= d int vector) } =20 data =3D pci_get_word(dev->config + msi_data_off(dev, msi64bit)); - if (xen_is_pirq_msi(data)) { + addr_lo =3D pci_get_long(dev->config + msi_address_lo_off(dev)); + if (xen_is_pirq_msi(addr_lo, data)) { return false; } =20 diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 5078d3d..65cf00c 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -83,9 +83,11 @@ static bool msix_vector_masked(PCIDevice *dev, unsigned = int vector, bool fmask) { unsigned offset =3D vector * PCI_MSIX_ENTRY_SIZE; uint8_t *data =3D &dev->msix_table[offset + PCI_MSIX_ENTRY_DATA]; + uint8_t *addr_lo =3D &dev->msix_table[offset + PCI_MSIX_ENTRY_LOWER_AD= DR]; /* MSIs on Xen can be remapped into pirqs. In those cases, masking * and unmasking go through the PV evtchn path. */ - if (xen_enabled() && xen_is_pirq_msi(pci_get_long(data))) { + if (xen_enabled() && xen_is_pirq_msi(pci_get_long(addr_lo), + pci_get_long(data))) { return false; } return fmask || dev->msix_table[offset + PCI_MSIX_ENTRY_VECTOR_CTRL] & diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c index 5c5d15a..82e13b2 100644 --- a/hw/xen/xen_pt_msi.c +++ b/hw/xen/xen_pt_msi.c @@ -114,7 +114,7 @@ static int msi_msix_setup(XenPCIPassthroughState *s, =20 assert((!is_msix && msix_entry =3D=3D 0) || is_msix); =20 - if (xen_is_pirq_msi(data)) { + if (xen_is_pirq_msi(addr, data)) { *ppirq =3D msi_ext_dest_id(addr >> 32) | msi_dest_id(addr); if (!*ppirq) { /* this probably identifies an misconfiguration of the guest, diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h index 7efcdaa..0d6c83e 100644 --- a/include/hw/xen/xen.h +++ b/include/hw/xen/xen.h @@ -34,7 +34,7 @@ int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num= ); void xen_piix3_set_irq(void *opaque, int irq_num, int level); void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int = len); void xen_hvm_inject_msi(uint64_t addr, uint32_t data); -int xen_is_pirq_msi(uint32_t msi_data); +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data); =20 qemu_irq *xen_interrupt_controller_init(void); =20 diff --git a/stubs/xen-hvm.c b/stubs/xen-hvm.c index 3ca6c51..aeb1592 100644 --- a/stubs/xen-hvm.c +++ b/stubs/xen-hvm.c @@ -31,7 +31,7 @@ void xen_hvm_inject_msi(uint64_t addr, uint32_t data) { } =20 -int xen_is_pirq_msi(uint32_t msi_data) +int xen_is_pirq_msi(uint32_t msi_addr_lo, uint32_t msi_data) { return 0; } --=20 1.8.3.1