From nobody Fri May 3 19:55:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502196228029758.6322369791733; Tue, 8 Aug 2017 05:43:48 -0700 (PDT) Received: from localhost ([::1]:42436 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df3rO-00020S-Cm for importer@patchew.org; Tue, 08 Aug 2017 08:43:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1df3qc-0001gq-DS for qemu-devel@nongnu.org; Tue, 08 Aug 2017 08:42:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1df3qb-0000GZ-0T for qemu-devel@nongnu.org; Tue, 08 Aug 2017 08:42:58 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36816) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1df3qa-0000Fb-O0 for qemu-devel@nongnu.org; Tue, 08 Aug 2017 08:42:56 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1df3qX-0006TY-Em; Tue, 08 Aug 2017 13:42:53 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 8 Aug 2017 13:42:52 +0100 Message-Id: <1502196172-13818-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] target/alpha: Switch to do_transaction_failed() hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Switch the alpha target from the old unassigned_access hook to the new do_transaction_failed hook. This allows us to resolve a ??? in the old hook implementation. The only part of the alpha target that does physical memory accesses is reading the page table -- add a TODO comment there to the effect that we should handle bus faults on page table walks. (Since the palcode doesn't actually do anything useful on a bus fault anyway it's a bit moot for now.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Based-on: 1501867249-1924-1-git-send-email-peter.maydell@linaro.org This patch sits on top of the series adding the new hook. The comment in the page walk code could probably be rephrased by somebody who knows what the palcode behaviour in the busfault-on-table-walk case is. This patch isn't really tested (just 'make check' and checking that qemu-system-alpha can start up). --- target/alpha/cpu.h | 8 +++++--- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 8 ++++++++ target/alpha/mem_helper.c | 19 ++++++++++--------- 4 files changed, 24 insertions(+), 13 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e95be2b..389e1a4 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -488,9 +488,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_= t val); uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); #ifndef CONFIG_USER_ONLY -QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int unused, unsigned size); +void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retad= dr); #endif =20 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 76150f4..4d49fd0 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -307,7 +307,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault =3D alpha_cpu_handle_mmu_fault; #else - cc->do_unassigned_access =3D alpha_cpu_unassigned_access; + cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 34121f4..36407f7 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -163,6 +163,14 @@ static int get_physical_address(CPUAlphaState *env, ta= rget_ulong addr, =20 pt =3D env->ptbr; =20 + /* TODO: rather than using ldq_phys() to read the page table we should + * use address_space_ldq() so that we can handle the case when + * the page table read gives a bus fault, rather than ignoring it. + * For the existing code the zero data that ldq_phys will return for + * an access to invalid memory will result in our treating the page + * table as invalid, which may even be the right behaviour. + */ + /* L1 page table read. */ index =3D (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff; L1pte =3D ldq_phys(cs->as, pt + index*8); diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 78a7d45..3c06baa 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -49,22 +49,23 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, cpu_loop_exit(cs); } =20 -void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size) +void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retad= dr) { AlphaCPU *cpu =3D ALPHA_CPU(cs); CPUAlphaState *env =3D &cpu->env; =20 + if (retaddr) { + cpu_restore_state(cs, retaddr); + } + env->trap_arg0 =3D addr; - env->trap_arg1 =3D is_write ? 1 : 0; + env->trap_arg1 =3D access_type =3D=3D MMU_DATA_STORE ? 1 : 0; cs->exception_index =3D EXCP_MCHK; env->error_code =3D 0; - - /* ??? We should cpu_restore_state to the faulting insn, but this hook - does not have access to the retaddr value from the original helper. - It's all moot until the QEMU PALcode grows an MCHK handler. */ - cpu_loop_exit(cs); } =20 --=20 2.7.4