1. Patchew
  2. QEMU
  3. View series

[Qemu-devel] [PATCH] target-mips: apply CP0.PageMask before writing into TLB entry

Yongbok Kim posted 1 patch 6 years, 8 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1501682311-16370-1-git-send-email-yongbok.kim@imgtec.com
Test FreeBSD passed
Test checkpatch passed
Test docker passed
Test s390x passed
target/mips/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
[Qemu-devel] [PATCH] target-mips: apply CP0.PageMask before writing into TLB entry
Posted by Yongbok Kim 6 years, 8 months ago 
From: Leon Alrae <leon.alrae@imgtec.com>

PFN0 and PFN1 have to be masked out with PageMask_Mask.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
[Yongbok Kim:
  Added commit message]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
 target/mips/op_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 526f8e4..320f2b0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -2008,6 +2008,7 @@ static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
 {
     r4k_tlb_t *tlb;
+    uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
 
     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
     tlb = &env->tlb->mmu.r4k.tlb[idx];
@@ -2028,13 +2029,13 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx)
     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
-    tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
+    tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
-    tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
+    tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
 }
 
 void r4k_helper_tlbinv(CPUMIPSState *env)
-- 
2.7.4
Re: [Qemu-devel] [PATCH] target-mips: apply CP0.PageMask before writing into TLB entry
Posted by Philippe Mathieu-Daudé 6 years, 8 months ago 
Hi Leon,

On 08/02/2017 10:58 AM, Yongbok Kim wrote:
> From: Leon Alrae <leon.alrae@imgtec.com>
> 
> PFN0 and PFN1 have to be masked out with PageMask_Mask.
> 
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
> [Yongbok Kim:
>    Added commit message]
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
>   target/mips/op_helper.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 526f8e4..320f2b0 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -2008,6 +2008,7 @@ static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
>   static void r4k_fill_tlb(CPUMIPSState *env, int idx)
>   {
>       r4k_tlb_t *tlb;
> +    uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
>   
>       /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
>       tlb = &env->tlb->mmu.r4k.tlb[idx];
> @@ -2028,13 +2029,13 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx)
>       tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
>       tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
>       tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
> -    tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
> +    tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
>       tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
>       tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
>       tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
>       tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
>       tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
> -    tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
> +    tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
>   }
>   
>   void r4k_helper_tlbinv(CPUMIPSState *env)
> 

What about refactoring get_tlb_pfn_from_entrylo(uint64_t entrylo) -> 
r4k_get_tlb_pfn_from_entrylo(uint64_t entrylo, uint64_t pagemask) to 
directly masked pfn?

Regards,

Phil.
Re: [Qemu-devel] [PATCH] target-mips: apply CP0.PageMask before writing into TLB entry
Posted by Yongbok Kim 6 years, 8 months ago 

On 02/08/2017 19:56, Philippe Mathieu-Daudé wrote:
> Hi Leon,
> 
> On 08/02/2017 10:58 AM, Yongbok Kim wrote:
>> From: Leon Alrae <leon.alrae@imgtec.com>
>>
>> PFN0 and PFN1 have to be masked out with PageMask_Mask.
>>
>> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
>> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
>> [Yongbok Kim:
>>    Added commit message]
>> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
>> ---
>>   target/mips/op_helper.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
>> index 526f8e4..320f2b0 100644
>> --- a/target/mips/op_helper.c
>> +++ b/target/mips/op_helper.c
>> @@ -2008,6 +2008,7 @@ static inline uint64_t
>> get_tlb_pfn_from_entrylo(uint64_t entrylo)
>>   static void r4k_fill_tlb(CPUMIPSState *env, int idx)
>>   {
>>       r4k_tlb_t *tlb;
>> +    uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
>>         /* XXX: detect conflicting TLBs and raise a MCHECK exception when
>> needed */
>>       tlb = &env->tlb->mmu.r4k.tlb[idx];
>> @@ -2028,13 +2029,13 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx)
>>       tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
>>       tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
>>       tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
>> -    tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
>> +    tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask)
>> << 12;
>>       tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
>>       tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
>>       tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
>>       tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
>>       tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
>> -    tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
>> +    tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask)
>> << 12;
>>   }
>>     void r4k_helper_tlbinv(CPUMIPSState *env)
>>
> 
> What about refactoring get_tlb_pfn_from_entrylo(uint64_t entrylo) ->
> r4k_get_tlb_pfn_from_entrylo(uint64_t entrylo, uint64_t pagemask) to
> directly masked pfn?
> 
> Regards,
> 
> Phil.

Hi Phil,

Leon left Imagination a year ago and this patch is one of his remainders.
I agree to refactor the inline function but it is paired with other inline
function get_entrylo_pfn_from_tlb(). I will send another patch for both of
them but it should be after 2.10.

Regards,
Yongbok

Patchew 2.1-devel-0870f84

© 2016 - 2024 Red Hat, Inc.