From nobody Thu May 2 23:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150115339823829.879759012963746; Thu, 27 Jul 2017 04:03:18 -0700 (PDT) Received: from localhost ([::1]:42261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagZU-0000cL-Sr for importer@patchew.org; Thu, 27 Jul 2017 07:03:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40155) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagVq-0006N4-43 for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dagVp-0000QZ-C7 for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dagVm-0008P0-Uk; Thu, 27 Jul 2017 06:59:23 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVb-0003lV-L1; Thu, 27 Jul 2017 11:59:11 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 27 Jul 2017 11:59:06 +0100 Message-Id: <1501153150-19984-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.10 1/5] target/arm: Don't do MPU lookups for addresses in M profile PPB region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The M profile PMSAv7 specification says that if the address being looked up is in the PPB region (0xe0000000 - 0xe00fffff) then we do not use the MPU regions but always use the default memory map. Implement this (we were previously behaving like an R profile PMSAv7, which does not special case this). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ed32c5..ceef225 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8244,6 +8244,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } } =20 +static inline bool is_ppb_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile PPB region 0xe0000000 - 0xe00ff= fff */ + return arm_feature(env, ARM_FEATURE_M) && + extract32(address, 20, 12) =3D=3D 0xe00; +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fs= r) @@ -8255,7 +8262,15 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, *phys_ptr =3D address; *prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx) || + is_ppb_region(env, address)) { + /* MPU disabled or M profile PPB access: use default memory map. + * The other case which uses the default memory map in the + * v7M ARM ARM pseudocode is exception vector reads from the vector + * table. In QEMU those accesses are done in arm_v7m_load_vector(), + * which always does a direct read using address_space_ldl(), rath= er + * than going via this function, so we don't need to check that he= re. + */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { --=20 2.7.4 From nobody Thu May 2 23:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501153405692598.5888511720411; Thu, 27 Jul 2017 04:03:25 -0700 (PDT) Received: from localhost ([::1]:42262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagZd-0000hV-2z for importer@patchew.org; Thu, 27 Jul 2017 07:03:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagVp-0006Kj-6u for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dagVo-0000P3-DP for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dagVm-0008P0-4e; Thu, 27 Jul 2017 06:59:22 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVc-0003lk-9W; Thu, 27 Jul 2017 11:59:12 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 27 Jul 2017 11:59:07 +0100 Message-Id: <1501153150-19984-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.10 2/5] target/arm: Don't allow guest to make System space executable for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For an M profile v7PMSA, the system space (0xe0000000 - 0xffffffff) can never be executable, even if the guest tries to set the MPU registers up that way. Enforce this restriction. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ceef225..169c361 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8251,6 +8251,14 @@ static inline bool is_ppb_region(CPUARMState *env, u= int32_t address) extract32(address, 20, 12) =3D=3D 0xe00; } =20 +static inline bool is_system_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile system region + * 0xe0000000 - 0xffffffff + */ + return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) = =3D=3D 0x7; +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fs= r) @@ -8354,6 +8362,12 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* a MPU hit! */ uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); + uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); + + if (is_system_region(env, address)) { + /* System space is always execute never */ + xn =3D 1; + } =20 if (is_user) { /* User mode AP bit decoding */ switch (ap) { @@ -8394,7 +8408,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, } =20 /* execute never */ - if (env->pmsav7.dracr[n] & (1 << 12)) { + if (xn) { *prot &=3D ~PAGE_EXEC; } } --=20 2.7.4 From nobody Thu May 2 23:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501153411180357.44665061651983; Thu, 27 Jul 2017 04:03:31 -0700 (PDT) Received: from localhost ([::1]:42263 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagZi-0000lT-Sj for importer@patchew.org; Thu, 27 Jul 2017 07:03:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagVo-0006Jp-Qp for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dagVn-0000N2-LO for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dagVl-0008P0-Al; Thu, 27 Jul 2017 06:59:21 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVc-0003lx-OO; Thu, 27 Jul 2017 11:59:12 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 27 Jul 2017 11:59:08 +0100 Message-Id: <1501153150-19984-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.10 3/5] target/arm: Rename cp15.c6_rgnr to pmsav7.rnr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Almost all of the PMSAv7 state is in the pmsav7 substruct of the ARM CPU state structure. The exception is the region number register, which is in cp15.c6_rgnr. This exception is a bit odd for M profile, which otherwise generally does not store state in the cp15 substruct. Rename cp15.c6_rgnr to pmsav7.rnr accordingly. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/armv7m_nvic.c | 14 +++++++------- target/arm/cpu.h | 3 +-- target/arm/helper.c | 6 +++--- target/arm/machine.c | 2 +- 4 files changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 26a4b2d..323e2d4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -536,13 +536,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set) case 0xd94: /* MPU_CTRL */ return cpu->env.v7m.mpu_ctrl; case 0xd98: /* MPU_RNR */ - return cpu->env.cp15.c6_rgnr; + return cpu->env.pmsav7.rnr; case 0xd9c: /* MPU_RBAR */ case 0xda4: /* MPU_RBAR_A1 */ case 0xdac: /* MPU_RBAR_A2 */ case 0xdb4: /* MPU_RBAR_A3 */ { - int region =3D cpu->env.cp15.c6_rgnr; + int region =3D cpu->env.pmsav7.rnr; =20 if (region >=3D cpu->pmsav7_dregion) { return 0; @@ -554,7 +554,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t) case 0xdb0: /* MPU_RASR_A2 */ case 0xdb8: /* MPU_RASR_A3 */ { - int region =3D cpu->env.cp15.c6_rgnr; + int region =3D cpu->env.pmsav7.rnr; =20 if (region >=3D cpu->pmsav7_dregion) { return 0; @@ -681,7 +681,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) PRIu32 "/%" PRIu32 "\n", value, cpu->pmsav7_dregion); } else { - cpu->env.cp15.c6_rgnr =3D value; + cpu->env.pmsav7.rnr =3D value; } break; case 0xd9c: /* MPU_RBAR */ @@ -702,9 +702,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) region, cpu->pmsav7_dregion); return; } - cpu->env.cp15.c6_rgnr =3D region; + cpu->env.pmsav7.rnr =3D region; } else { - region =3D cpu->env.cp15.c6_rgnr; + region =3D cpu->env.pmsav7.rnr; } =20 if (region >=3D cpu->pmsav7_dregion) { @@ -720,7 +720,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) case 0xdb0: /* MPU_RASR_A2 */ case 0xdb8: /* MPU_RASR_A3 */ { - int region =3D cpu->env.cp15.c6_rgnr; + int region =3D cpu->env.pmsav7.rnr; =20 if (region >=3D cpu->pmsav7_dregion) { return; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 102c58a..b39d64a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -305,8 +305,6 @@ typedef struct CPUARMState { uint64_t par_el[4]; }; =20 - uint32_t c6_rgnr; - uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ @@ -519,6 +517,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; + uint32_t rnr; } pmsav7; =20 void *nvic; diff --git a/target/arm/helper.c b/target/arm/helper.c index 169c361..63187de 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const A= RMCPRegInfo *ri) return 0; } =20 - u32p +=3D env->cp15.c6_rgnr; + u32p +=3D env->pmsav7.rnr; return *u32p; } =20 @@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMC= PRegInfo *ri, return; } =20 - u32p +=3D env->cp15.c6_rgnr; + u32p +=3D env->pmsav7.rnr; tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ *u32p =3D value; } @@ -2447,7 +2447,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_rgnr), + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr), .writefn =3D pmsav7_rgnr_write }, REGINFO_SENTINEL }; diff --git a/target/arm/machine.c b/target/arm/machine.c index 1a40469..93c1a78 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -151,7 +151,7 @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, = int version_id) { ARMCPU *cpu =3D opaque; =20 - return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion; + return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; } =20 static const VMStateDescription vmstate_pmsav7 =3D { --=20 2.7.4 From nobody Thu May 2 23:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501153264611657.8475304155749; Thu, 27 Jul 2017 04:01:04 -0700 (PDT) Received: from localhost ([::1]:42251 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagXO-0007Qw-Fq for importer@patchew.org; Thu, 27 Jul 2017 07:01:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40104) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagVo-0006J6-13 for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dagVn-0000Lc-1e for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dagVk-0008P0-H2; Thu, 27 Jul 2017 06:59:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVd-0003mN-9k; Thu, 27 Jul 2017 11:59:13 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 27 Jul 2017 11:59:09 +0100 Message-Id: <1501153150-19984-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.10 4/5] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When the PMSAv7 implementation was originally added it was for R profile CPUs only, and reset was handled using the cpreg .resetfn hooks. Unfortunately for M profile cores this doesn't work, because they do not register any cpregs. Move the reset handling into arm_cpu_reset(), where it will work for both R profile and M profile cores. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++---------------- 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 96d1f84..05c038b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -232,6 +232,20 @@ static void arm_cpu_reset(CPUState *s) =20 env->vfp.xregs[ARM_VFP_FPEXC] =3D 0; #endif + + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V7)) { + if (cpu->pmsav7_dregion > 0) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } + env->pmsav7.rnr =3D 0; + } + set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); diff --git a/target/arm/helper.c b/target/arm/helper.c index 63187de..a9247e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2404,18 +2404,6 @@ static void pmsav7_write(CPUARMState *env, const ARM= CPRegInfo *ri, *u32p =3D value; } =20 -static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); -} - static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2433,22 +2421,30 @@ static void pmsav7_rgnr_write(CPUARMState *env, con= st ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { + /* Reset for all these registers is handled in arm_cpu_reset(), + * because the PMSAv7 is also used by M-profile CPUs, which do + * not register cpregs but still need the state to be reset. + */ { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr), - .writefn =3D pmsav7_rgnr_write }, + .writefn =3D pmsav7_rgnr_write, + .resetfn =3D arm_cp_reset_ignore }, REGINFO_SENTINEL }; =20 --=20 2.7.4 From nobody Thu May 2 23:44:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501153273972797.8691699216845; Thu, 27 Jul 2017 04:01:13 -0700 (PDT) Received: from localhost ([::1]:42254 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagXV-0007Wt-LA for importer@patchew.org; Thu, 27 Jul 2017 07:01:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dagVm-0006Hi-Jg for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dagVl-0000I4-U9 for qemu-devel@nongnu.org; Thu, 27 Jul 2017 06:59:22 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37719) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dagVj-0008P0-OF; Thu, 27 Jul 2017 06:59:19 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dagVd-0003ml-Pd; Thu, 27 Jul 2017 11:59:13 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 27 Jul 2017 11:59:10 +0100 Message-Id: <1501153150-19984-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> References: <1501153150-19984-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH for-2.10 5/5] target/arm: Migrate MPU_RNR register state for M profile cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The PMSAv7 region number register is migrated for R profile cores using the cpreg scheme, but M profile doesn't use cpregs, and so we weren't migrating the MPU_RNR register state at all. Fix that by adding a migration subsection for the M profile case. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/machine.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/machine.c b/target/arm/machine.c index 93c1a78..1f66da4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -171,6 +171,29 @@ static const VMStateDescription vmstate_pmsav7 =3D { } }; =20 +static bool pmsav7_rnr_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + /* For R profile cores pmsav7.rnr is migrated via the cpreg + * "RGNR" definition in helper.h. For M profile we have to + * migrate it separately. + */ + return arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav7_rnr =3D { + .name =3D "cpu/pmsav7-rnr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav7_rnr_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -377,6 +400,11 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_iwmmxt, &vmstate_m, &vmstate_thumb2ee, + /* pmsav7_rnr must come before pmsav7 so that we have the + * region number before we test it in the VMSTATE_VALIDATE + * in vmstate_pmsav7. + */ + &vmstate_pmsav7_rnr, &vmstate_pmsav7, NULL } --=20 2.7.4