From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520621823785.2040401814518; Wed, 19 Jul 2017 20:17:01 -0700 (PDT) Received: from localhost ([::1]:35827 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1xT-0007Ir-Vs for importer@patchew.org; Wed, 19 Jul 2017 23:17:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016M-Al for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qI-0005oc-Vq for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:51259) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qI-0005nh-Ne for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:34 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 90B9320A52; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:31 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 562F3241E0; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=buHV2ud6KIgEkQM wGqy38a8ZRqf0F8XaW5hA3j+ERtU=; b=GoozZCiWdPlcX4C3n64UxzJ5z9u/fwz hTXzeCvpJXEwNw6fVwfrrEK4C4CMSvrBAkdGTK28zcjEXZc7QfSBA0ShH3p+PRx6 zp6XzFKl67/jhE/JPd259CViNv63JffLuJJa2sB/q2xEjd5D42ja6D6osrm5WlR2 8X5varJ4FPEc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=buHV2ud6KIgEkQMwGqy38a8ZRqf0F8XaW5hA3j+ERtU=; b=LGJYAzd7 z9+RN7iPG45kL/x7c4OEOlUNklQKCt45TSEsZQJAv0cbbaAFhIx15q9V7Ykb3JH1 QHzsETexkQqhRHapEcf9yAnF1a+dwnZEOp8Q4mvmAuI+8V7v+GBzUeFLvSvjWtVc uzcOZh/cYyNsM0X6AYI2HEOLthbWia+cjC0lL0V8Hu0mJa1eQ6SOG3ruYoXn5Mbn eZ/dlJngPWdmoLiMHBpePpe2aEeIBuCpZp9VTbASGyimjK5y45UxDUyjngINx4jq uQ9ts0TYsWJgj42GZzlSk4jRDHUF+FP9wufG8EN2+n9+XRnjJR1zuNfa1NzV4CHD xaPeDLJ4TM5pFA== X-ME-Sender: X-Sasl-enc: sYjNICbeHO9o/DHUcTfDmtigq10WvGBDl5IaYj5oZ46Q 1500520171 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:47 -0400 Message-Id: <1500520169-23367-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 01/43] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Note that this change also requires updating the accessors to tlb_flush_count to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f8..e43ff83 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f94178..c91db21 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 85635ae..9377110 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_f= unc fn, } } =20 -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count =3D 0; + + CPU_FOREACH(cpu) { + CPUArchState *env =3D cpu->env_ptr; + + count +=3D atomic_read(&env->tlb_flush_count); + } + return count; +} =20 /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } =20 assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 tb_lock(); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 090ebad..3ee69e5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1916,7 +1916,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 tb_unlock(); --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520633295514.4043702433551; Wed, 19 Jul 2017 20:17:13 -0700 (PDT) Received: from localhost ([::1]:35828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1xX-0007LI-Cd for importer@patchew.org; Wed, 19 Jul 2017 23:17:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016H-9a for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qI-0005oW-Vk for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:34925) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qI-0005no-NE for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:34 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id BB9AA20736; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:31 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 843A27E322; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=N5tnzqG6f0zZxfu 55la5g3tuJZuEilKtjuICpak3PCY=; b=JXBqPWISSXlEr2VwzTWt5pvPTeEM2Wy 4bWISt5i+Xclkm3vXi83hV0VN2lP7oH6B+Fn4cfs4FZE5D3r0rE2Q57Wqvkk/D1w HLnxn+sI29IYfLGaDhCZ9mM18pFETcw+RhnZWiTKPF6oHzOJ7g2lu+v8BV/ez7Nf TmzZarxzGw98= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=N5tnzqG6f0zZxfu55la5g3tuJZuEilKtjuICpak3PCY=; b=gX5h0ZXz MSiVCMiT+ZwxzoMhgwDCqEMWhGeTDAmnRt6K/fAvlIi4/rzeCWTFGkeJ/pjNj/hY b6ucEeq4EiYcXcOzRLlbAyZvG7jOIwAqIAhETID8KFXKPfqpPhjyPwMGHIuAucSm JbSuAfCKBmZ0OhkKvG9z9zN/BIaxLd7sHi4/vaRysfS7sZXMpgtSS+D1xuXMmyJ2 cxaKkm4PVmMrutQ3VwCPhscq2BXtVHU3XQyuGfRB6l9p8Povc7cmjyVhWX7RUA2/ +X1iVj8oSJ/dE/FsKzsDh+d1rxnUH8BKfeXnh/v6WdzVKcuaSDX0aPVqEtTNVh87 Re21kgfhr1fZHg== X-ME-Sender: X-Sasl-enc: sYjbJDTRH/Zr9D3GYCvDmtigq10WvGBDl5IaYj5oZ46Q 1500520171 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:48 -0400 Message-Id: <1500520169-23367-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 02/43] tcg: fix corruption of code_time profiling counter upon tb_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Whenever there is an overflow in code_gen_buffer (e.g. we run out of space in it and have to flush it), the code_time profiling counter ends up with an invalid value (that is, code_time -=3D profile_getclock(), without later on getting +=3D profile_getclock() due to the goto). Fix it by using the ti variable, so that we only update code_time when there is no overflow. Note that in case there is an overflow we fail to account for the elapsed coding time, but this is quite rare so we can probably live with it. "info jit" before/after, roughly at the same time during debian-arm bootup: - before: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 998 JIT cycles -615191529184601 (-256329.804 s at 2.4 GHz) translated TBs 302310 (aborted=3D0 0.0%) avg ops/TB 48.4 max=3D438 deleted ops/TB 8.54 avg temps/TB 32.31 max=3D38 avg host code/TB 361.5 avg search data/TB 24.5 cycles/op -42014693.0 cycles/in byte -121444900.2 cycles/out byte -5629031.1 cycles/search byte -83114481.0 gen_interm time -0.0% gen_code time 100.0% optim./code time -0.0% liveness/code time -0.0% cpu_restore count 6236 avg cycles 110.4 - after: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 1010 JIT cycles 1996899624 (0.832 s at 2.4 GHz) translated TBs 297961 (aborted=3D0 0.0%) avg ops/TB 48.5 max=3D438 deleted ops/TB 8.56 avg temps/TB 32.31 max=3D38 avg host code/TB 361.8 avg search data/TB 24.5 cycles/op 138.2 cycles/in byte 398.4 cycles/out byte 18.5 cycles/search byte 273.1 gen_interm time 14.0% gen_code time 86.0% optim./code time 19.4% liveness/code time 10.3% cpu_restore count 6372 avg cycles 111.0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3ee69e5..63f8538 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1300,7 +1300,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; tcg_ctx.interm_time +=3D profile_getclock() - ti; - tcg_ctx.code_time -=3D profile_getclock(); + ti =3D profile_getclock(); #endif =20 /* ??? Overflow could be handled better here. In particular, we @@ -1318,7 +1318,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock(); + tcg_ctx.code_time +=3D profile_getclock() - ti; tcg_ctx.code_in_len +=3D tb->size; tcg_ctx.code_out_len +=3D gen_code_size; tcg_ctx.search_out_len +=3D search_size; --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520937164632.4871264312574; Wed, 19 Jul 2017 20:22:17 -0700 (PDT) Received: from localhost ([::1]:35848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY22V-0004pd-Uq for importer@patchew.org; Wed, 19 Jul 2017 23:22:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60150) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016P-CF for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qI-0005oM-UT for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39539) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qI-0005nv-Kh for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:34 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id E8F70208C3; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:31 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B16E2240AF; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=R11 +bn/vtG7XjxdNSbNM1EI7K2cs1NN0kofjtwEn+x8=; b=pK56tojrkhKyUJqWzAk ZCznhTuqAgtUvNImbmyeTXs7Yt7umL7lUk38t8cKZ7RrRoasY9Pcci27BqV2kUVP QeiEh3NOIAGH5zs0LgWqYLt+KFFTMom9OVQP5j2EWIseQL9xNrmxh2ETyDrVyUdn MkoiOmBLLSwCuOnX/TpLYnCA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=R11+bn/vtG7XjxdNSbNM1EI7K2cs1NN0kofjtwEn+ x8=; b=kndhctpn2BrkaUnd23wcX5KSDEaoX/BPmRzDGWpw52kw6yQ/uAu7fB3z6 n1Llzzfn0AmjL2Uy5KaEo5JQdVji/nRgOepT4ixpdEkcmuZPfJv4JgqH+Z0i8A0n l2YkKWI/is8bSZKwiLslUEWGgtJ41961IkQw2T9OE51UmpzUffcTdlZXTQajltJN JRh8JgUEjmqYzeQxfk9bZB+DtRo72irOzpgOQ6MehRHOhWl6kUQSsfQC20ERTxFW edJMCtJmgo87VCENv6jzQPv3AIVlVIx7Ch2SakVQALwgu/ZkGfwxiOMEMgXH1jzl vfsB9SbIVLvFuyoITyD4nKdefdvfg== X-ME-Sender: X-Sasl-enc: sYjXIjnVDuJ36yHZcCfDmtigq10WvGBDl5IaYj5oZ46Q 1500520171 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:49 -0400 Message-Id: <1500520169-23367-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 03/43] exec-all: fix typos in TranslationBlock's documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 87b1b74..69c1b36 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -370,7 +370,7 @@ struct TranslationBlock { /* The following data are used to directly call another TB from * the code of this one. This can be done either by emitting direct or * indirect native jump instructions. These jumps are reset so that th= e TB - * just continue its execution. The TB can be linked to another one by + * just continues its execution. The TB can be linked to another one by * setting one of the jump targets (or patching the jump instruction).= Only * two of such jumps are supported. */ @@ -381,7 +381,7 @@ struct TranslationBlock { #else uintptr_t jmp_target_addr[2]; /* target address for indirect jump */ #endif - /* Each TB has an assosiated circular list of TBs jumping to this one. + /* Each TB has an associated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. * Since each TB can have two jumps, it can participate in two lists. --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520297082263.30403589184107; Wed, 19 Jul 2017 20:11:37 -0700 (PDT) Received: from localhost ([::1]:35804 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1sE-0002Vr-P8 for importer@patchew.org; Wed, 19 Jul 2017 23:11:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016R-CR for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005oq-1z for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52129) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qI-0005nx-Pc for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:34 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2184020A3B; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:32 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id DF3837E322; Wed, 19 Jul 2017 23:09:31 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=NTmtzjRpKNYDuaU ZrGg/+ukEM6vlK1wMdSRtET/xq0o=; b=gsyYeyFvZp3esujNy4DCXXy0Z4u6h0s ihbnHjlI8Z08+LMZgxyzSe+9Hj6aMdmJjX/OqHILk67zAW7xcRb8aQC3/lU9iliA 3XUmUGgkURjPa7Yybl0esMK8QDlnY4zwA1BeMwauQrpZmgV7LU6ABlaY3CNchsLA r7oG5ylUndyw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=NTmtzjRpKNYDuaUZrGg/+ukEM6vlK1wMdSRtET/xq0o=; b=Zxe2WmM5 qLGAnluRVXxHlH0O6+vj+PxpNLH8jZB2tFKz80/9EN8I2Sb3j6TxPiprGakvArHm SUknHuC1aT3fyJ7Ore9q6/CW0frnm7WbZqPR43z4H5M1vXnQpdeX2Wd2BKDnmSa8 wQl0y20tmYD+z/1QS8vRbVCgsELUsWnye0hG1DyA5W7P+dfNf9UqnTPR88UcTqed +Y70ge4l6d78cqcLmraTpOgd38/NmAmyW17HojnI1YwVNrtIEYkotJUPOnIdVN7A uqGtN/7vDkiLP7vAnLB/LcD614LOF1ADL78U7YOvyOzIw+EUgndINppc1kgxMJvu lslyAaKf1gIFSg== X-ME-Sender: X-Sasl-enc: sYjKOS7IAOlj4y7LeS3Dmtigq10WvGBDl5IaYj5oZ46Q 1500520171 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:50 -0400 Message-Id: <1500520169-23367-5-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 04/43] translate-all: make have_tb_lock static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 It is only used by this object, and it's not exported to any other. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 63f8538..a124181 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -139,7 +139,7 @@ TCGContext tcg_ctx; bool parallel_cpus; =20 /* translation block context */ -__thread int have_tb_lock; +static __thread int have_tb_lock; =20 static void page_table_config_init(void) { --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520293798233.77852869333276; Wed, 19 Jul 2017 20:11:33 -0700 (PDT) Received: from localhost ([::1]:35803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1sB-0002SW-4n for importer@patchew.org; Wed, 19 Jul 2017 23:11:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016J-9u for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pW-CC for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:54327) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005oJ-6g for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 521BC20A41; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:32 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 1A302240AF; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=JIq a/+T4t+RWZYCulKxJhNxL6q/Vpw+eIq7ABMSghn0=; b=VpARny90oc4HwI7zizq /ZFPuCGkSlxMzXfAgTItb4bYJrQdl5d9HpTAv2UUOMYiGXRRRtTC4qpPXXqnsBbl Eheg0kCAWofALk5gBSmpTFu/OxZRFZ812Rik6JXd9k7Su+A5prSJKaBSnUXnReKt Fwd8bUg65N8RFt3MdVsjR4dg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=JIqa/+T4t+RWZYCulKxJhNxL6q/Vpw+eIq7ABMSgh n0=; b=IqDrHEYtrXG+G03TyIPoRsenDeIlGmRmsw++jZzgrxBqXOmYvQPDg/btM +DvviqD2rPJm1WO+RirAcE0EjJcbydpmBRDl4WTGFHhyrF/7dfn8Bl2BGtI9de5P bRMsobf9hPmDT/9+LmeY9zcnayEU0/5sfwghAlmMi6wm8O3yFLJfhafd5peR3kPA t9SWB00MLOVkfcH8mTK1kbNLUodfx/J7Sjke//vW/PrW8QtzgEZzgKMWvU1EixcW XErEnFNrMnJUsNF/4t03gQyklSedMaamYGtMGMBXOqhKgSzbSoKMyOBTCTM8Ag6C gdFZfPgmpGxMEOcqdfhGfPhwFJjuw== X-ME-Sender: X-Sasl-enc: BsgdHjC/NhozkF57Wu9rjWmtegvdMYVGlUPO0wKg5tDM 1500520172 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:51 -0400 Message-Id: <1500520169-23367-6-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 05/43] cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reusing the have_tb_lock name, which is also defined in translate-all.c, makes code reviewing unnecessarily harder. Avoid potential confusion by renaming the local have_tb_lock variable to something else. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/cpu-exec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d84b01d..c4c289b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -337,7 +337,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - bool have_tb_lock =3D false; + bool acquired_tb_lock =3D false; =20 /* we record a subset of the CPU state. It will always be the same before a given translated block @@ -356,7 +356,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, */ mmap_lock(); tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; =20 /* There's a chance that our desired tb has been translated wh= ile * taking the locks so we check again inside the lock. @@ -384,15 +384,15 @@ static inline TranslationBlock *tb_find(CPUState *cpu, #endif /* See if we can patch the calling TB. */ if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - if (!have_tb_lock) { + if (!acquired_tb_lock) { tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; } if (!tb->invalid) { tb_add_jump(last_tb, tb_exit, tb); } } - if (have_tb_lock) { + if (acquired_tb_lock) { tb_unlock(); } return tb; --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052030585428.736640911205313; Wed, 19 Jul 2017 20:11:45 -0700 (PDT) Received: from localhost ([::1]:35806 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1sO-0002dy-1M for importer@patchew.org; Wed, 19 Jul 2017 23:11:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60144) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016O-Bx for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pc-EO for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40929) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005oH-6n for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7D30220A42; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:32 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 447A37E322; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=HzhQbOk6ZtSYR/J fQiZvnrr5stExrz/79eIhjlu0Uwk=; b=JJBqbwVznBIlWaSIyWTBvipeDUn6CO8 1IjHZgR4MwL56i7atFRGogCH5K3J9kUv4vZLgFiUSvORmMhRh+iNhrs0H/DtmxOK yND9I4xJUweVn0OPimSMX36oIqSg3/gCyn7Q7gxdfCsYJjnNIyWVz11dv/t4SMp9 +Hwu8S/5iAfI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=HzhQbOk6ZtSYR/JfQiZvnrr5stExrz/79eIhjlu0Uwk=; b=fWxIBDIU X2p5wb2x7U18D34/CpyHcItOSYJbGh79kp7VUC1m2JbRXzYULE9p75vZGuUwieSo 2YCLEc6CPMGrA+KHG7JNl2wNTC861OqLGFDnP4kDLpbkO+KyKK7NDeh1XSl7K8zk rzjXY8bYn5TERZAo5GW02Ltjxk4DIeyvEkYLNQxE6r4t/LshMJKIo8/oW/uIMN+h /++O2CK390Pzhg3za/cW5jSKDKhIEH5fjQqfRXdBDYspaDj7/8BeGEdna/HYjm4K 3+bpYCl/yOtS569bb18J2ry2S9AhY7qkPNuYWE7X7QAbZJ7k3VRk5E46zkdYKCwE I4SJaHDGPqLMEw== X-ME-Sender: X-Sasl-enc: BsgTFymmOB4+gVdiTfJrjWmtegvdMYVGlUPO0wKg5tDM 1500520172 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:52 -0400 Message-Id: <1500520169-23367-7-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 06/43] tcg/i386: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 01e3b4e..06df01a 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2514,7 +2514,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return NULL; } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_RBP, TCG_REG_RBX, --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520454797882.734258233636; Wed, 19 Jul 2017 20:14:14 -0700 (PDT) Received: from localhost ([::1]:35811 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1uk-0004rW-6g for importer@patchew.org; Wed, 19 Jul 2017 23:14:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016K-Aj for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005py-Gk for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:55275) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005og-9x for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id A988B20A5B; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:32 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 7238A240AF; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=c0XyXNQgWv6N5nU vxoYlEDaZqby1EMzQFqFeac8obO0=; b=MCxglllY2Bp/FRu/DJe3ffawSLGLuui 3EAiDr8PXj6lUtfQlZ1qARmmdrsz5nTFWdmqDlLDjCbce54mkf8+K07rBMk/Uenk /EquEmZBy3RddQPh9Q8g4vWZQ1lfFlmOZ6G7DIjhnDnNWlPpGozdjWhUr+zXXncl nHw0N5y+qoRc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=c0XyXNQgWv6N5nUvxoYlEDaZqby1EMzQFqFeac8obO0=; b=VJHkGbU8 tTPLr0rMajs+wI3ngfymfaXn/sWPfdABcDxVxIqpiUnIj/iPNCr8UBrlKoZUHy3Q q8rnR5NacLfHnc2QbEpeMKi8baAz2jGptw4lSYnoXxJVP+ghrhOQ0B0B9+QxVUms SN4l2evjRxUStpBCIWFiF5WdO6iPGgAnH5UJWdqV+9q5nIgnjD5ndHmE8bidfs41 brb1/oZJIAY0KmTGrxkf1I/5QkMVVBy+UvHpwPTpBHFoPxQW8NQpzFlcyZDCqJ4B bTOcuLSpfSJXKFhtku2tK/MPVL8c6phvaAW2U2fHRnY9ycHco3qsAn1MbiQGupK2 N3HI916DoC4/kg== X-ME-Sender: X-Sasl-enc: BsgTAiClPggtlEV6XulrjWmtegvdMYVGlUPO0wKg5tDM 1500520172 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:53 -0400 Message-Id: <1500520169-23367-8-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 07/43] tcg/mips: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 85756b8..56db228 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2323,7 +2323,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return NULL; } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S0, /* used for the global env (TCG_AREG0) */ TCG_REG_S1, TCG_REG_S2, --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520459744313.3422048502946; Wed, 19 Jul 2017 20:14:19 -0700 (PDT) Received: from localhost ([::1]:35813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1uq-0004wp-Gt for importer@patchew.org; Wed, 19 Jul 2017 23:14:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016I-AS for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pn-Ge for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:51183) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005oK-6p for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D6CCD20A72; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:32 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 9C7227E057; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=dWe tRz/6fkaaBXN8CZ0OiY+uvh9SALHVgmcsaAS2Q7o=; b=jB8pQd1xyUh4lSWfG3n mOXzYspREvMhKUYnne1CBH8v/af/4FmluB6v7nq6d/F3RzKyD2gqQZIH8HLvDBK6 WP9agMbEsEJIvTMHjgpkZn913jWBicAecjRWCB/9xYl4ViQjbPGaadc3XGZk+bj0 U+4n7YRLpExWFQWyHsQg0d2M= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=dWetRz/6fkaaBXN8CZ0OiY+uvh9SALHVgmcsaAS2Q 7o=; b=c6y4176sNMuoFyGAgE5/aHoMXVH2E+Qhc/HiGWA5APl6i7TgdXNtkdIho lSYzrBWwCUA34mNC7cLe+LZ+Lu/6TNtrMil9WW3s/9e7KznTq2tfi/5G4iia46yy hR9gF2TkzmiHvbRdJYgZFagafedN7/sQdTMuVIkMd1kSoZoT0q2xGu7nSAj3bxkk c/jGsUfBHS5iZwivPzSXaA6F10BQJ/SIQw4nm4eRKvmycbQKCJejUA3fN/iJSdPq JlitocnfB7G/God/KkOnMqjl6ZqCUgFn2aPf5jahDtUnDcdm+y8uwGVXOc0GwLsZ wPCYsW44XHMWWRSPMFy/xAtoP6QMw== X-ME-Sender: X-Sasl-enc: BsgbADOiKhIiglJmUe1rjWmtegvdMYVGlUPO0wKg5tDM 1500520172 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:54 -0400 Message-Id: <1500520169-23367-9-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 08/43] tcg: remove addr argument from lookup_tb_ptr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg-op.h | 4 ++-- tcg/tcg-runtime.h | 2 +- target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 5 +---- target/hppa/translate.c | 6 +++--- target/i386/translate.c | 17 +++++------------ target/mips/translate.c | 4 ++-- target/s390x/translate.c | 2 +- target/sh4/translate.c | 4 ++-- tcg/tcg-op.c | 4 ++-- tcg/tcg-runtime.c | 20 ++++++++++---------- 12 files changed, 32 insertions(+), 42 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f..18d01b2 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -797,7 +797,7 @@ static inline void tcg_gen_exit_tb(uintptr_t val) void tcg_gen_goto_tb(unsigned idx); =20 /** - * tcg_gen_lookup_and_goto_ptr() - look up a TB and jump to it if valid + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if v= alid * @addr: Guest address of the target TB * * If the TB is not valid, jump to the epilogue. @@ -805,7 +805,7 @@ void tcg_gen_goto_tb(unsigned idx); * This operation is optional. If the TCG backend does not implement goto_= ptr, * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argume= nt. */ -void tcg_gen_lookup_and_goto_ptr(TCGv addr); +void tcg_gen_lookup_and_goto_ptr(void); =20 #if TARGET_LONG_BITS =3D=3D 32 #define tcg_temp_new() tcg_temp_new_i32() diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h index c41d38a..1df17d0 100644 --- a/tcg/tcg-runtime.h +++ b/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i6= 4) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) =20 -DEF_HELPER_FLAGS_2(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env, tl) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) =20 DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 90e6d52..9e98312 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3073,7 +3073,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) /* FALLTHRU */ case EXIT_PC_UPDATED: if (!use_exit_tb(&ctx)) { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; } /* FALLTHRU */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3fa3902..818d7eb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -379,7 +379,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) } else if (s->singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); s->is_jmp =3D DISAS_TB_JUMP; } } @@ -11366,7 +11366,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Transla= tionBlock *tb) gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; case DISAS_TB_JUMP: case DISAS_EXC: diff --git a/target/arm/translate.c b/target/arm/translate.c index e27736c..964b627 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4152,10 +4152,7 @@ static inline bool use_goto_tb(DisasContext *s, targ= et_ulong dest) =20 static void gen_goto_ptr(void) { - TCGv addr =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, cpu_R[15]); - tcg_gen_lookup_and_goto_ptr(addr); - tcg_temp_free(addr); + tcg_gen_lookup_and_goto_ptr(); } =20 /* This will end the TB but doesn't guarantee we'll return to diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e10abc5..91053e2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -517,7 +517,7 @@ static void gen_goto_tb(DisasContext *ctx, int which, if (ctx->singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -1527,7 +1527,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv = dest, if (link !=3D 0) { tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, NO_EXIT); } else { cond_prep(&ctx->null_cond); @@ -3885,7 +3885,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct = TranslationBlock *tb) if (ctx.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/i386/translate.c b/target/i386/translate.c index ed3b896..291c577 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -2511,7 +2511,7 @@ static void gen_bnd_jmp(DisasContext *s) If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of S->TF. This is used by the syscall/sysret insns. */ static void -do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) +do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) { gen_update_cc_op(s); =20 @@ -2532,12 +2532,8 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) tcg_gen_exit_tb(0); } else if (s->tf) { gen_helper_single_step(cpu_env); - } else if (!TCGV_IS_UNUSED(jr)) { - TCGv vaddr =3D tcg_temp_new(); - - tcg_gen_add_tl(vaddr, jr, cpu_seg_base[R_CS]); - tcg_gen_lookup_and_goto_ptr(vaddr); - tcg_temp_free(vaddr); + } else if (jr) { + tcg_gen_lookup_and_goto_ptr(); } else { tcg_gen_exit_tb(0); } @@ -2547,10 +2543,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) static inline void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf) { - TCGv unused; - - TCGV_UNUSED(unused); - do_gen_eob_worker(s, inhibit, recheck_tf, unused); + do_gen_eob_worker(s, inhibit, recheck_tf, false); } =20 /* End of block. @@ -2569,7 +2562,7 @@ static void gen_eob(DisasContext *s) /* Jump to register */ static void gen_jr(DisasContext *s, TCGv dest) { - do_gen_eob_worker(s, false, false, dest); + do_gen_eob_worker(s, false, false, true); } =20 /* generate a jump to eip. No segment change must happen before as a diff --git a/target/mips/translate.c b/target/mips/translate.c index fe44f2f..28c9fbd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4233,7 +4233,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int= n, target_ulong dest) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); } } =20 @@ -10731,7 +10731,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); break; default: fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 1dffcee..be1a04d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5948,7 +5948,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) } else if (use_exit_tb(&dc) || status =3D=3D EXIT_PC_STALE_NOCHAIN= ) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(psw_addr); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 498bb99..2a206af 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -261,7 +261,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -278,7 +278,7 @@ static void gen_jump(DisasContext * ctx) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673e..205d07f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2587,11 +2587,11 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 -void tcg_gen_lookup_and_goto_ptr(TCGv addr) +void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env, addr); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 3e23649..e85a042 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -144,33 +144,33 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } =20 -void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) +void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, addr_hash; + uint32_t flags, hash; =20 - addr_hash =3D tb_jmp_cache_hash_func(addr); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[addr_hash]); cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + hash =3D tb_jmp_cache_hash_func(pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); =20 if (unlikely(!(tb - && tb->pc =3D=3D addr + && tb->pc =3D=3D pc && tb->cs_base =3D=3D cs_base && tb->flags =3D=3D flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, addr, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); if (!tb) { return tcg_ctx.code_gen_epilogue; } - atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); + atomic_set(&cpu->tb_jmp_cache[hash], tb); } =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, addr, + qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, addr, - lookup_symbol(addr)); + tb->tc_ptr, cpu->cpu_index, pc, + lookup_symbol(pc)); return tb->tc_ptr; } =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521238432636.6867595423096; Wed, 19 Jul 2017 20:27:18 -0700 (PDT) Received: from localhost ([::1]:35873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY27Q-0001ln-DJ for importer@patchew.org; Wed, 19 Jul 2017 23:27:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60261) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qP-00016k-56 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005q7-Jl for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:41 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:33405) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005oj-90 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 18AAC20AB4; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:33 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C8EE0240AF; Wed, 19 Jul 2017 23:09:32 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=A4F R/yabXutX/OiY2VOdWmYvP0jequC6Rn4U8gy7s8g=; b=HycZqcYZdlWQIIzP3I0 7J+arpZ/8bHUCBbEkD2P8jbT5ju6dAEwnUNhRGjd3di9aqKJpmI9oyjySGcUOhwo 41KdNmBcCtLGJO+WK5BZTNv++JKzrWJpD5smwKWDjCTk/kdTAdGTG6qY0+sWJi0s uAZgnMtPT0TrlYilH+EM18R4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=A4FR/yabXutX/OiY2VOdWmYvP0jequC6Rn4U8gy7s 8g=; b=SiKOX5g/L3gsbd+MRuEfntufvCvY8TBhKMjt8M/wpgH40ht8Y5BbjZHVC l6kImtIYcT+JWWVvbx+C5dsjG6eZVMyRM+C0LCQSj73ulM953zN+goNSkpc8qbK3 dZuq+WPOjnE6fhLzF7NZW9BziUwDEo0n0saBkmbB7ET7h9RFl7+F2OJ6M877bV/c OKgTIzEnloGhBuAT8PDoPtheypJ1lBwK+8YG43ym23m/jRTsPvFdISXaeg2Plk+5 /Kg29Vxiob9iW8SBMdVdSDu8NA0hNEfRUr4aV698+d9sj8OZ8WdJ3iVdaoJ0zYI8 yZ+j21v9WpjmfPrVUDO28mgm2m7Og== X-ME-Sender: X-Sasl-enc: BsgQBie5PB8ghUF4RexrjWmtegvdMYVGlUPO0wKg5tDM 1500520172 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:55 -0400 Message-Id: <1500520169-23367-10-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 09/43] tcg: consolidate TB lookups in tb_lookup__cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This avoids duplicating code. cpu_exec_step will also use the new common function once we integrate parallel_cpus into tb->cflags. Note that in this commit we also fix a race, described by Richard Henderson during review. Think of this scenario with threads A and B: (A) Lookup succeeds for TB in hash without tb_lock (B) Sets the TB's tb->invalid flag (B) Removes the TB from tb_htable (B) Clears all CPU's tb_jmp_cache (A) Store TB into local tb_jmp_cache Given that order of events, (A) will keep executing that invalid TB until another flush of its tb_jmp_cache happens, which in theory might never happ= en. We can fix this by checking the tb->invalid flag every time we look up a TB from tb_jmp_cache, so that in the above scenario, next time we try to find that TB in tb_jmp_cache, we won't, and will therefore be forced to look it up in tb_htable. Performance-wise, I measured a small improvement when booting debian-arm. Note that inlining pays off: Performance counter stats for 'taskset -c 0 qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Djessie.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): Before: 18714.917392 task-clock # 0.952 CPUs utilized = ( +- 0.95% ) 23,142 context-switches # 0.001 M/sec = ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 10,558 page-faults # 0.001 M/sec = ( +- 0.95% ) 53,957,727,252 cycles # 2.883 GHz = ( +- 0.91% ) [83.33%] 24,440,599,852 stalled-cycles-frontend # 45.30% frontend cycles idl= e ( +- 1.20% ) [83.33%] 16,495,714,424 stalled-cycles-backend # 30.57% backend cycles idl= e ( +- 0.95% ) [66.66%] 76,267,572,582 instructions # 1.41 insns per cycle # 0.32 stalled cycles per = insn ( +- 0.87% ) [83.34%] 12,692,186,323 branches # 678.186 M/sec = ( +- 0.92% ) [83.35%] 263,486,879 branch-misses # 2.08% of all branches = ( +- 0.73% ) [83.34%] 19.648474449 seconds time elapsed = ( +- 0.82% ) After, w/ inline (this patch): 18471.376627 task-clock # 0.955 CPUs utilized = ( +- 0.96% ) 23,048 context-switches # 0.001 M/sec = ( +- 0.48% ) 1 CPU-migrations # 0.000 M/sec 10,708 page-faults # 0.001 M/sec = ( +- 0.81% ) 53,208,990,796 cycles # 2.881 GHz = ( +- 0.98% ) [83.34%] 23,941,071,673 stalled-cycles-frontend # 44.99% frontend cycles idl= e ( +- 0.95% ) [83.34%] 16,161,773,848 stalled-cycles-backend # 30.37% backend cycles idl= e ( +- 0.76% ) [66.67%] 75,786,269,766 instructions # 1.42 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.24% ) [83.34%] 12,573,617,143 branches # 680.708 M/sec = ( +- 1.34% ) [83.33%] 260,235,550 branch-misses # 2.07% of all branches = ( +- 0.66% ) [83.33%] 19.340502161 seconds time elapsed = ( +- 0.56% ) After, w/o inline: 18791.253967 task-clock # 0.954 CPUs utilized = ( +- 0.78% ) 23,230 context-switches # 0.001 M/sec = ( +- 0.42% ) 1 CPU-migrations # 0.000 M/sec 10,563 page-faults # 0.001 M/sec = ( +- 1.27% ) 54,168,674,622 cycles # 2.883 GHz = ( +- 0.80% ) [83.34%] 24,244,712,629 stalled-cycles-frontend # 44.76% frontend cycles idl= e ( +- 1.37% ) [83.33%] 16,288,648,572 stalled-cycles-backend # 30.07% backend cycles idl= e ( +- 0.95% ) [66.66%] 77,659,755,503 instructions # 1.43 insns per cycle # 0.31 stalled cycles per = insn ( +- 0.97% ) [83.34%] 12,922,780,045 branches # 687.702 M/sec = ( +- 1.06% ) [83.34%] 261,962,386 branch-misses # 2.03% of all branches = ( +- 0.71% ) [83.35%] 19.700174670 seconds time elapsed = ( +- 0.56% ) Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/tb-lookup.h | 49 ++++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/cpu-exec.c | 47 ++++++++++++++++++--------------------------= -- tcg/tcg-runtime.c | 24 ++++++------------------ 3 files changed, 73 insertions(+), 47 deletions(-) create mode 100644 include/exec/tb-lookup.h diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h new file mode 100644 index 0000000..9d32cb0 --- /dev/null +++ b/include/exec/tb-lookup.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017, Emilio G. Cota + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef EXEC_TB_LOOKUP_H +#define EXEC_TB_LOOKUP_H + +#include "qemu/osdep.h" + +#ifdef NEED_CPU_H +#include "cpu.h" +#else +#include "exec/poison.h" +#endif + +#include "exec/exec-all.h" +#include "exec/tb-hash.h" + +/* Might cause an exception, so have a longjmp destination ready */ +static inline TranslationBlock * +tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, + uint32_t *flags) +{ + CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; + TranslationBlock *tb; + uint32_t hash; + + cpu_get_tb_cpu_state(env, pc, cs_base, flags); + hash =3D tb_jmp_cache_hash_func(*pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); + if (likely(tb && + tb->pc =3D=3D *pc && + tb->cs_base =3D=3D *cs_base && + tb->flags =3D=3D *flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && + !atomic_read(&tb->invalid))) { + return tb; + } + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + if (tb =3D=3D NULL) { + return NULL; + } + atomic_set(&cpu->tb_jmp_cache[hash], tb); + return tb; +} + +#endif /* EXEC_TB_LOOKUP_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c4c289b..5d2ee5b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "qemu/rcu.h" #include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "exec/log.h" #include "qemu/main-loop.h" #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) @@ -333,43 +334,31 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) { - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; =20 - /* we record a subset of the CPU state. It will - always be the same before a given translated block - is executed. */ - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]); - if (unlikely(!tb || tb->pc !=3D pc || tb->cs_base !=3D cs_base || - tb->flags !=3D flags || - tb->trace_vcpu_dstate !=3D *cpu->trace_dstate)) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - - /* mmap_lock is needed by tb_gen_code, and mmap_lock must be - * taken outside tb_lock. As system emulation is currently - * single threaded the locks are NOPs. - */ - mmap_lock(); - tb_lock(); - acquired_tb_lock =3D true; - - /* There's a chance that our desired tb has been translated wh= ile - * taking the locks so we check again inside the lock. - */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - /* if no translated code available, then translate it now = */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); - } + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + /* mmap_lock is needed by tb_gen_code, and mmap_lock must be + * taken outside tb_lock. As system emulation is currently + * single threaded the locks are NOPs. + */ + mmap_lock(); + tb_lock(); + acquired_tb_lock =3D true; =20 - mmap_unlock(); + /* There's a chance that our desired tb has been translated while + * taking the locks so we check again inside the lock. + */ + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + if (likely(tb =3D=3D NULL)) { + /* if no translated code available, then translate it now */ + tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); } =20 + mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup = */ atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); } diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index e85a042..7100339 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -27,7 +27,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" =20 @@ -149,24 +149,12 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, hash; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - hash =3D tb_jmp_cache_hash_func(pc); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); - - if (unlikely(!(tb - && tb->pc =3D=3D pc - && tb->cs_base =3D=3D cs_base - && tb->flags =3D=3D flags - && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - return tcg_ctx.code_gen_epilogue; - } - atomic_set(&cpu->tb_jmp_cache[hash], tb); - } + uint32_t flags; =20 + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + return tcg_ctx.code_gen_epilogue; + } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", tb->tc_ptr, cpu->cpu_index, pc, --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520773335295.7754400896479; Wed, 19 Jul 2017 20:19:33 -0700 (PDT) Received: from localhost ([::1]:35834 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1zu-0001b7-Hg for importer@patchew.org; Wed, 19 Jul 2017 23:19:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60138) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016L-AJ for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pE-9d for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40689) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005oS-5o for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2DF4420A91; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:33 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 06EAE7E057; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=uno MtqEKp39cVnG3/JhHCdMOyijXg2GJJSRS7ZN3luU=; b=QClnmYDrOIkR0XoBbFU PRsDbLiVU6cRrRvBPJtMzemaEJUyYYaBORyURNCW6kJizUVvq+NS4NPUX6cRPR71 80oVk9buG6lvRvzj55CF2VsR3ftjcnQ7r1GCBmGkaqertFBoFsY4rPj51ZSSXDEv P8AsY1D8HMbMIT6mkx0ycsSQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=unoMtqEKp39cVnG3/JhHCdMOyijXg2GJJSRS7ZN3l uU=; b=j5rfRfNcR7XrJEKOwRR1ZsvKpOJc0cj1TzDzLpCfAas3KSLvdbqH8V02+ eGAj6jtBOme3E9tcgNPAbSepkrfTfFqtF7pX0jSxpBHqZ2/KtJ11BId6b4O09p+A aGDDA3el899dE5X+3qlJx/Rbl3OjbV3wXLq81QuR3bkcBXoJ72x7wmIgBVxdLQZw goLvlJPBWJjAIUSx57tHS5q8sW1YbGzj/A6pl11uutIu6rquvGLwZky23F6Cgfl1 PXAqrKzbRXfeBCi1o1JqobZM1j8PaKeQ0e1Cbu3sxS92yS0IB2Up2fXldSOQomVp aw4Fw9Sks78eK+NmXQgMTViVF6cdQ== X-ME-Sender: X-Sasl-enc: u8it2ZIqiyJ2A9RZmpD23Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:56 -0400 Message-Id: <1500520169-23367-11-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 10/43] exec-all: bring tb->invalid into tb->cflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This gets rid of a hole in struct TranslationBlock. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 3 +-- include/exec/tb-lookup.h | 2 +- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 3 +-- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 69c1b36..256b9a6 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -352,12 +352,11 @@ struct TranslationBlock { #define CF_NOCACHE 0x10000 /* To be freed after execution */ #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ +#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - uint16_t invalid; - void *tc_ptr; /* pointer to the translated code */ uint8_t *tc_search; /* pointer to search data */ /* original tb when cflags has CF_NOCACHE */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 9d32cb0..436b6d5 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -35,7 +35,7 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, tar= get_ulong *cs_base, tb->cs_base =3D=3D *cs_base && tb->flags =3D=3D *flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - !atomic_read(&tb->invalid))) { + !(atomic_read(&tb->cflags) & CF_INVALID))) { return tb; } tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5d2ee5b..fae8c40 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -294,7 +294,7 @@ static bool tb_cmp(const void *p, const void *d) tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && - !atomic_read(&tb->invalid)) { + !(atomic_read(&tb->cflags) & CF_INVALID)) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { return true; @@ -377,7 +377,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, tb_lock(); acquired_tb_lock =3D true; } - if (!tb->invalid) { + if (!(tb->cflags & CF_INVALID)) { tb_add_jump(last_tb, tb_exit, tb); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a124181..7ef4f19 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1073,7 +1073,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) =20 assert_tb_locked(); =20 - atomic_set(&tb->invalid, true); + atomic_set(&tb->cflags, tb->cflags | CF_INVALID); =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); @@ -1269,7 +1269,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tb->invalid =3D false; =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521663555655.4459624673468; Wed, 19 Jul 2017 20:34:23 -0700 (PDT) Received: from localhost ([::1]:35904 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2EH-0007cO-Iy for importer@patchew.org; Wed, 19 Jul 2017 23:34:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016a-KI for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qT-Oa for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:34261) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005op-Dm for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7279920A89; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:33 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 2F72F240AF; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Vf7 2wNA7NeIwFbAL2qf/a5R1aYCPcUU9qIubHOY02TY=; b=Mi/TV5/9Gjr+oQJ1b2i JSniqH/OR8IayaBqF+R0C+Zv4/FBZYhXDr11BCFN1ZTLebBWeriqcB/5fhF7htT6 aGaZe0l4YS98HR1koTMCSPQlx8DKGIgO4DwxT/+GWtg4B9wFOR/2KMZTmLMIr0Xk gK1Yanqfe34cWhMgRCBn0O68= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=Vf72wNA7NeIwFbAL2qf/a5R1aYCPcUU9qIubHOY02 TY=; b=BH7T7atKVovBqZv5RdXbf0Q8uu7SNNhxFmDTLLm1EwRtG9uUy6L2aFNK8 zIiOVQ6XucCLzg1lHC7Fs8Msneu2/AhdKJvRtHxCuIsqS9UajlUOrsVtAddu1w6V kzc8po6AiKCXD1ZaE/XPXWACKXVfpuG4tjFOMpKWrHY0GGUeISqamnTvrUxGy/Eb tbzlu/G7cpcYEtQ3/XBqPPj13l8Sfl3U/sfCdo58IQ48B+pY+5hiCOOSrqzof5aZ fxm5oozFrhTgUIjrlKHaa5pj0BlCQ9CetxZsEv32Way/5BkX9VZcM187wIxBbLYw 9VYDH56FX6J2im7SEM2m4gUnlmoug== X-ME-Sender: X-Sasl-enc: u8i2zJ0ohjRuH8BChJr23Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:57 -0400 Message-Id: <1500520169-23367-12-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 11/43] tcg: define CF_PARALLEL and use it for TB hashing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will enable us to decouple code translation from the value of parallel_cpus at any given time. It will also help us minimize TB flushes when generating code via EXCP_ATOMIC. Note that the declaration of parallel_cpus is brought to exec-all.h to be able to define there the "curr_cflags" inline. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 20 +++++++++++++++++++- include/exec/tb-hash-xx.h | 9 ++++++--- include/exec/tb-hash.h | 4 ++-- include/exec/tb-lookup.h | 6 +++--- tcg/tcg.h | 1 - accel/tcg/cpu-exec.c | 45 +++++++++++++++++++++++--------------------= -- accel/tcg/translate-all.c | 13 +++++++++---- exec.c | 2 +- tcg/tcg-runtime.c | 2 +- tests/qht-bench.c | 2 +- 10 files changed, 65 insertions(+), 39 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 256b9a6..0af0485 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -353,6 +353,9 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ #define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ +#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */ +/* cflags' mask for hashing/comparison */ +#define CF_HASH_MASK (CF_PARALLEL) =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; @@ -396,11 +399,26 @@ struct TranslationBlock { uintptr_t jmp_list_first; }; =20 +extern bool parallel_cpus; + +/* Hide the atomic_read to make code a little easier on the eyes */ +static inline uint32_t tb_cflags(const TranslationBlock *tb) +{ + return atomic_read(&tb->cflags); +} + +/* current cflags for hashing/comparison */ +static inline uint32_t curr_cflags(void) +{ + return parallel_cpus ? CF_PARALLEL : 0; +} + void tb_free(TranslationBlock *tb); void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags); + target_ulong cs_base, uint32_t flags, + uint32_t cf_mask); =20 #if defined(USE_DIRECT_JUMP) =20 diff --git a/include/exec/tb-hash-xx.h b/include/exec/tb-hash-xx.h index 6cd3022..747a9a6 100644 --- a/include/exec/tb-hash-xx.h +++ b/include/exec/tb-hash-xx.h @@ -48,8 +48,8 @@ * xxhash32, customized for input variables that are not guaranteed to be * contiguous in memory. */ -static inline -uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f) +static inline uint32_t +tb_hash_func7(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f, uint32_t g) { uint32_t v1 =3D TB_HASH_XX_SEED + PRIME32_1 + PRIME32_2; uint32_t v2 =3D TB_HASH_XX_SEED + PRIME32_2; @@ -78,7 +78,7 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t= e, uint32_t f) v4 *=3D PRIME32_1; =20 h32 =3D rol32(v1, 1) + rol32(v2, 7) + rol32(v3, 12) + rol32(v4, 18); - h32 +=3D 24; + h32 +=3D 28; =20 h32 +=3D e * PRIME32_3; h32 =3D rol32(h32, 17) * PRIME32_4; @@ -86,6 +86,9 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t= e, uint32_t f) h32 +=3D f * PRIME32_3; h32 =3D rol32(h32, 17) * PRIME32_4; =20 + h32 +=3D g * PRIME32_3; + h32 =3D rol32(h32, 17) * PRIME32_4; + h32 ^=3D h32 >> 15; h32 *=3D PRIME32_2; h32 ^=3D h32 >> 13; diff --git a/include/exec/tb-hash.h b/include/exec/tb-hash.h index 17b5ee0..0526c4f 100644 --- a/include/exec/tb-hash.h +++ b/include/exec/tb-hash.h @@ -59,9 +59,9 @@ static inline unsigned int tb_jmp_cache_hash_func(target_= ulong pc) =20 static inline uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t fl= ags, - uint32_t trace_vcpu_dstate) + uint32_t cf_mask, uint32_t trace_vcpu_dstate) { - return tb_hash_func6(phys_pc, pc, flags, trace_vcpu_dstate); + return tb_hash_func7(phys_pc, pc, flags, cf_mask, trace_vcpu_dstate); } =20 #endif diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 436b6d5..2961385 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -21,7 +21,7 @@ /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock * tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, - uint32_t *flags) + uint32_t *flags, uint32_t cf_mask) { CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; @@ -35,10 +35,10 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, t= arget_ulong *cs_base, tb->cs_base =3D=3D *cs_base && tb->flags =3D=3D *flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - !(atomic_read(&tb->cflags) & CF_INVALID))) { + (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) =3D=3D cf_mas= k)) { return tb; } - tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask); if (tb =3D=3D NULL) { return NULL; } diff --git a/tcg/tcg.h b/tcg/tcg.h index da78721..96872f8 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -730,7 +730,6 @@ struct TCGContext { }; =20 extern TCGContext tcg_ctx; -extern bool parallel_cpus; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index fae8c40..b71e015 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -207,7 +207,8 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, tb_lock(); tb =3D tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, max_cycles | CF_NOCACHE - | (ignore_icount ? CF_IGNORE_ICOUNT : 0)); + | (ignore_icount ? CF_IGNORE_ICOUNT : 0) + | curr_cflags()); tb->orig_tb =3D orig_tb; tb_unlock(); =20 @@ -225,31 +226,27 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, static void cpu_exec_step(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; + uint32_t cflags =3D 1 | CF_IGNORE_ICOUNT; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { - mmap_lock(); - tb_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, - 1 | CF_NOCACHE | CF_IGNORE_ICOUNT); - tb->orig_tb =3D NULL; - tb_unlock(); - mmap_unlock(); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, + cflags & CF_HASH_MASK); + if (tb =3D=3D NULL) { + mmap_lock(); + tb_lock(); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb_unlock(); + mmap_unlock(); + } =20 cc->cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb_nocache(tb, pc); + trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); - - tb_lock(); - tb_phys_invalidate(tb, -1); - tb_free(tb); - tb_unlock(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -281,6 +278,7 @@ struct tb_desc { CPUArchState *env; tb_page_addr_t phys_page1; uint32_t flags; + uint32_t cf_mask; uint32_t trace_vcpu_dstate; }; =20 @@ -294,7 +292,7 @@ static bool tb_cmp(const void *p, const void *d) tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && - !(atomic_read(&tb->cflags) & CF_INVALID)) { + (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) =3D=3D desc->cf_mask= ) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { return true; @@ -313,7 +311,8 @@ static bool tb_cmp(const void *p, const void *d) } =20 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags) + target_ulong cs_base, uint32_t flags, + uint32_t cf_mask) { tb_page_addr_t phys_pc; struct tb_desc desc; @@ -322,11 +321,12 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, tar= get_ulong pc, desc.env =3D (CPUArchState *)cpu->env_ptr; desc.cs_base =3D cs_base; desc.flags =3D flags; + desc.cf_mask =3D cf_mask; desc.trace_vcpu_dstate =3D *cpu->trace_dstate; desc.pc =3D pc; phys_pc =3D get_page_addr_code(desc.env, pc); desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; - h =3D tb_hash_func(phys_pc, pc, flags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); } =20 @@ -338,8 +338,9 @@ static inline TranslationBlock *tb_find(CPUState *cpu, target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; + uint32_t cf_mask =3D curr_cflags(); =20 - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); if (tb =3D=3D NULL) { /* mmap_lock is needed by tb_gen_code, and mmap_lock must be * taken outside tb_lock. As system emulation is currently @@ -352,10 +353,10 @@ static inline TranslationBlock *tb_find(CPUState *cpu, /* There's a chance that our desired tb has been translated while * taking the locks so we check again inside the lock. */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); if (likely(tb =3D=3D NULL)) { /* if no translated code available, then translate it now */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cf_mask); } =20 mmap_unlock(); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7ef4f19..600c0a1 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1077,7 +1077,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, + tb->trace_vcpu_dstate); qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); =20 /* remove the TB from the page list */ @@ -1222,7 +1223,8 @@ static void tb_link_page(TranslationBlock *tb, tb_pag= e_addr_t phys_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, + tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 #ifdef DEBUG_TB_CHECK @@ -1503,7 +1505,8 @@ void tb_invalidate_phys_page_range(tb_page_addr_t sta= rt, tb_page_addr_t end, /* we generate a block containing just the instruction modifying the memory. It will ensure that it cannot modify itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, + 1 | curr_cflags()); cpu_loop_exit_noexc(cpu); } #endif @@ -1621,7 +1624,8 @@ static bool tb_invalidate_phys_page(tb_page_addr_t ad= dr, uintptr_t pc) /* we generate a block containing just the instruction modifying the memory. It will ensure that it cannot modify itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, + 1 | curr_cflags()); /* tb_lock will be reset after cpu_loop_exit_noexc longjmps * back into the cpu_exec loop. */ return true; @@ -1765,6 +1769,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) } =20 cflags =3D n | CF_LAST_IO; + cflags |=3D curr_cflags(); pc =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; diff --git a/exec.c b/exec.c index 01ac21e..94b0f3e 100644 --- a/exec.c +++ b/exec.c @@ -2433,7 +2433,7 @@ static void check_watchpoint(int offset, int len, Mem= TxAttrs attrs, int flags) cpu_loop_exit(cpu); } else { cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); + tb_gen_code(cpu, pc, cs_base, cpu_flags, 1 | curr_cfla= gs()); cpu_loop_exit_noexc(cpu); } } diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 7100339..4f873a9 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -151,7 +151,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) target_ulong cs_base, pc; uint32_t flags; =20 - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb =3D=3D NULL) { return tcg_ctx.code_gen_epilogue; } diff --git a/tests/qht-bench.c b/tests/qht-bench.c index 11c1cec..4cabdfd 100644 --- a/tests/qht-bench.c +++ b/tests/qht-bench.c @@ -103,7 +103,7 @@ static bool is_equal(const void *obj, const void *userp) =20 static inline uint32_t h(unsigned long v) { - return tb_hash_func6(v, 0, 0, 0); + return tb_hash_func7(v, 0, 0, 0, 0); } =20 /* --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521668843241.26498655284286; Wed, 19 Jul 2017 20:34:28 -0700 (PDT) Received: from localhost ([::1]:35905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2EM-0007fh-Mf for importer@patchew.org; Wed, 19 Jul 2017 23:34:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qV-0001DJ-Uh for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qa-Pm for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:37951) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005or-BT for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id AF32620866; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:33 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 655BA7E1FC; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=WJn Mx/0kuiW2mvoE02CInZ5h/j1WjfTnrBa9VQM6wkc=; b=nLF4kOSCDd3oNFgU0gC pO3Xxh+Fu6DI2AQXULNvBz8TRvSR/RhD4OKBMidnJHGQrPiOeB2d1iAWs2/4UCRx ZAUVt+LtlsOHZAQ7TW8+CkFqgG6lpmPo+osN3VkAtCAUHvYLrmWfSCsWunIwjPZv Fg20MorB+vHO/9fa/QxzVgOQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=WJnMx/0kuiW2mvoE02CInZ5h/j1WjfTnrBa9VQM6w kc=; b=VWLIPw1VE2MkswfjGrs/qE1qWwctIQ2YmEDD0aLLfsbgdhnuScIIgkqJU WdsH9yCON27t1SechAf8huaw21LYdfP5Sc3ZcOUfJ4ncmGoOJz7kEKiu6O1XG/lE wyezW8Ims/7YsGtsjPK1IiiIdwtriKc7FftP0NyGMEPCCGpPyc0sUMo1MNpjIv/d IjszRNbAPfLBUPTuhnJ9ukSPKrHhf54dXd5Gm5zLUe3oZdU3necMMyUjb2UdvgIZ BMfJVLRjO2xHuEkrtV9lAnlSVYF5CXFqpmCO5mTxaJfDqJW+limDfGQdFhlCdoEx nLbpo8HVs5vafUA8s8PGN6DsB4piQ== X-ME-Sender: X-Sasl-enc: u8i7wYI2nilgA9xHj4L23Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:58 -0400 Message-Id: <1500520169-23367-13-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 12/43] tcg: convert tb->cflags reads to tb_cflags(tb) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=3D$(git grep 'tb->cflags' target include/exec/gen-icount.h | \ cut -f 1 -d':' | sort | uniq) perl -pi -e 's/([^>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z]*)->tb->cflags/tb_cflags($1->tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/gen-icount.h | 8 +++---- target/alpha/translate.c | 12 +++++----- target/arm/translate-a64.c | 13 +++++----- target/arm/translate.c | 10 ++++---- target/cris/translate.c | 6 ++--- target/hppa/translate.c | 8 +++---- target/i386/translate.c | 55 ++++++++++++++++++++++-----------------= ---- target/lm32/translate.c | 14 +++++------ target/m68k/translate.c | 6 ++--- target/microblaze/translate.c | 6 ++--- target/mips/translate.c | 26 ++++++++++---------- target/moxie/translate.c | 2 +- target/nios2/translate.c | 6 ++--- target/openrisc/translate.c | 6 ++--- target/ppc/translate.c | 6 ++--- target/ppc/translate_init.c | 32 ++++++++++++------------- target/s390x/translate.c | 8 +++---- target/sh4/translate.c | 6 ++--- target/sparc/translate.c | 6 ++--- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 6 ++--- target/xtensa/translate.c | 28 +++++++++++----------- 23 files changed, 138 insertions(+), 136 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9b3cb14..48b566c 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -13,7 +13,7 @@ static inline void gen_tb_start(TranslationBlock *tb) TCGv_i32 count, imm; =20 exitreq_label =3D gen_new_label(); - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { count =3D tcg_temp_local_new_i32(); } else { count =3D tcg_temp_new_i32(); @@ -22,7 +22,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_ld_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { imm =3D tcg_temp_new_i32(); /* We emit a movi with a dummy immediate argument. Keep the insn i= ndex * of the movi so that we later (when we know the actual insn coun= t) @@ -36,7 +36,7 @@ static inline void gen_tb_start(TranslationBlock *tb) =20 tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx.tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } @@ -46,7 +46,7 @@ static inline void gen_tb_start(TranslationBlock *tb) =20 static inline void gen_tb_end(TranslationBlock *tb, int num_insns) { - if (tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know * the actual insn count. */ tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 9e98312..f97a8e5 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -484,9 +484,9 @@ static bool in_superpage(DisasContext *ctx, int64_t add= r) =20 static bool use_exit_tb(DisasContext *ctx) { - return ((ctx->tb->cflags & CF_LAST_IO) + return (tb_cflags(ctx->tb) & CF_LAST_IO) || ctx->singlestep_enabled - || singlestep); + || singlestep; } =20 static bool use_goto_tb(DisasContext *ctx, uint64_t dest) @@ -2430,7 +2430,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) case 0xC000: /* RPCC */ va =3D dest_gpr(ctx, ra); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); gen_helper_load_pcc(va, cpu_env); gen_io_end(); @@ -2998,7 +2998,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) TCGV_UNUSED_I64(ctx.lit); =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -3028,7 +3028,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.pc +=3D 4; break; } - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } insn =3D cpu_ldl_code(env, ctx.pc); @@ -3053,7 +3053,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) } } while (ret =3D=3D NO_EXIT); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 818d7eb..685f1b0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -348,7 +348,8 @@ static inline bool use_goto_tb(DisasContext *s, int n, = uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_= IO)) { + if (s->singlestep_enabled || s->ss_active || + (tb_cflags(s->tb) & CF_LAST_IO)) { return false; } =20 @@ -1559,7 +1560,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((tb_cflags(s->tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } =20 @@ -1590,7 +1591,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((tb_cflags(s->tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->is_jmp =3D DISAS_UPDATE; @@ -11258,7 +11259,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Transla= tionBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -11299,7 +11300,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Transla= tionBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -11340,7 +11341,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Transla= tionBlock *tb) dc->pc < next_page_start && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 964b627..ccfb428 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7655,7 +7655,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((tb_cflags(s->tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } =20 @@ -7746,7 +7746,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((tb_cflags(s->tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); gen_lookup_tb(s); @@ -11876,7 +11876,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) cpu_M0 =3D tcg_temp_new_i64(); next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -11971,7 +11971,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -12041,7 +12041,7 @@ void gen_intermediate_code(CPUARMState *env, Transl= ationBlock *tb) !end_of_page && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ diff --git a/target/cris/translate.c b/target/cris/translate.c index 0ee05ca..1703d91 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3137,7 +3137,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -3167,7 +3167,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } dc->clear_x =3D 1; @@ -3240,7 +3240,7 @@ void gen_intermediate_code(CPUCRISState *env, struct = TranslationBlock *tb) =20 npc =3D dc->pc; =20 - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); /* Force an update if the per-tb cpu state has changed. */ if (dc->is_jmp =3D=3D DISAS_NEXT diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 91053e2..1effe82 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -487,7 +487,7 @@ static ExitStatus gen_illegal(DisasContext *ctx) static bool use_goto_tb(DisasContext *ctx, target_ulong dest) { /* Suppress goto_tb in the case of single-steping and IO. */ - if ((ctx->tb->cflags & CF_LAST_IO) || ctx->singlestep_enabled) { + if ((tb_cflags(ctx->tb) & CF_LAST_IO) || ctx->singlestep_enabled) { return false; } return true; @@ -3762,7 +3762,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct = TranslationBlock *tb) /* Compute the maximum number of insns to execute, as bounded by (1) icount, (2) single-stepping, (3) branch delay slots, or (4) the number of insns remaining on the current page. */ - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -3792,7 +3792,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct = TranslationBlock *tb) ret =3D gen_excp(&ctx, EXCP_DEBUG); break; } - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -3868,7 +3868,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct = TranslationBlock *tb) } } while (ret =3D=3D NO_EXIT); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/i386/translate.c b/target/i386/translate.c index 291c577..f046ffa 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -1119,7 +1119,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) =20 static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1134,14 +1134,14 @@ static inline void gen_ins(DisasContext *s, TCGMemO= p ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); } } =20 static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1154,7 +1154,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -6299,7 +6299,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6314,7 +6314,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base= ); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6330,14 +6330,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6351,14 +6351,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6369,14 +6369,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6389,14 +6389,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7104,11 +7104,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7563,11 +7563,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7932,24 +7932,24 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg= )); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(s->tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8431,7 +8431,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) record/replay modes and there will always be an additional step for ecx=3D0 when icount is enabled. */ - dc->repz_opt =3D !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt =3D !dc->jmp_opt && !(tb_cflags(tb) & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8454,7 +8454,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) dc->is_jmp =3D DISAS_NEXT; pc_ptr =3D pc_start; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -8479,7 +8479,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) pc_ptr +=3D 1; goto done_generating; } - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -8504,7 +8504,7 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - if ((tb->cflags & CF_USE_ICOUNT) + if ((tb_cflags(tb) & CF_USE_ICOUNT) && ((pc_ptr & TARGET_PAGE_MASK) !=3D ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MA= SK) || (pc_ptr & ~TARGET_PAGE_MASK) =3D=3D 0)) { @@ -8526,8 +8526,9 @@ void gen_intermediate_code(CPUX86State *env, Translat= ionBlock *tb) break; } } - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); + } done_generating: gen_tb_end(tb, num_insns); =20 diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 692882f..3597c61 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -874,24 +874,24 @@ static void dec_wcsr(DisasContext *dc) break; case CSR_IM: /* mark as an io operation because it could cause an interrupt */ - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_im(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp =3D DISAS_UPDATE; break; case CSR_IP: /* mark as an io operation because it could cause an interrupt */ - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wcsr_ip(cpu_env, cpu_R[dc->r1]); tcg_gen_movi_tl(cpu_pc, dc->pc + 4); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } dc->is_jmp =3D DISAS_UPDATE; @@ -1072,7 +1072,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1100,7 +1100,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -1113,7 +1113,7 @@ void gen_intermediate_code(CPULM32State *env, struct = TranslationBlock *tb) && (dc->pc < next_page_start) && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3a519b7..188520b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5544,7 +5544,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) dc->done_mac =3D 0; dc->writeback_mask =3D 0; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -5570,7 +5570,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -5582,7 +5582,7 @@ void gen_intermediate_code(CPUM68KState *env, Transla= tionBlock *tb) (pc_offset) < (TARGET_PAGE_SIZE - 32) && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); if (unlikely(cs->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index cb65d1e..4cd184e 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1660,7 +1660,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1695,7 +1695,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) /* Pretty disas. */ LOG_DIS("%8.8x:\t", dc->pc); =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -1757,7 +1757,7 @@ void gen_intermediate_code(CPUMBState *env, struct Tr= anslationBlock *tb) npc =3D dc->jmp_pc; } =20 - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); /* Force an update if the per-tb cpu state has changed. */ if (dc->is_jmp =3D=3D DISAS_NEXT diff --git a/target/mips/translate.c b/target/mips/translate.c index 28c9fbd..f839a2b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5238,11 +5238,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -5642,7 +5642,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) if (sel !=3D 0) check_insn(ctx, ISA_MIPS32); =20 - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } =20 @@ -6291,7 +6291,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) trace_mips_translate_c0("mtc0", rn, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); ctx->bstate =3D BS_STOP; } @@ -6551,11 +6551,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -6942,7 +6942,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) if (sel !=3D 0) check_insn(ctx, ISA_MIPS64); =20 - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } =20 @@ -7259,11 +7259,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) save_cpu_state(ctx, 1); /* Mark as an IO operation because we may trigger a software interrupt. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mtc0_cause(cpu_env, arg); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Stop translation as we may have triggered an intetrupt */ @@ -7589,7 +7589,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) trace_mips_translate_c0("dmtc0", rn, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); ctx->bstate =3D BS_STOP; } @@ -19937,7 +19937,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) ctx.default_tcg_memop_mask =3D (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -19963,7 +19963,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) goto done_generating; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -20024,7 +20024,7 @@ void gen_intermediate_code(CPUMIPSState *env, struc= t TranslationBlock *tb) if (singlestep) break; } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } if (cs->singlestep_enabled && ctx.bstate !=3D BS_BRANCH) { diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 0660b44..f61aa2d 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -838,7 +838,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct T= ranslationBlock *tb) ctx.singlestep_enabled =3D 0; ctx.bstate =3D BS_NONE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2f3c2e5..e74e070 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -822,7 +822,7 @@ void gen_intermediate_code(CPUNios2State *env, Translat= ionBlock *tb) max_insns =3D 1; } else { int page_insns =3D (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)= ) / 4; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -849,7 +849,7 @@ void gen_intermediate_code(CPUNios2State *env, Translat= ionBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -866,7 +866,7 @@ void gen_intermediate_code(CPUNios2State *env, Translat= ionBlock *tb) !tcg_op_buf_full() && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e49518e..347790c 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1540,7 +1540,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) =20 next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; =20 if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -1583,7 +1583,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } disas_openrisc_insn(dc, cpu); @@ -1606,7 +1606,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, str= uct TranslationBlock *tb) && (dc->pc < next_page_start) && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c0cd64d..e146aa3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7275,7 +7275,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) msr_se =3D 1; #endif num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -7303,7 +7303,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) LOG_DISAS("----------------\n"); LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", ctx.nip, ctx.mem_idx, (int)msr_ir); - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) gen_io_start(); if (unlikely(need_byteswap(&ctx))) { ctx.opcode =3D bswap32(cpu_ldl_code(env, ctx.nip)); @@ -7384,7 +7384,7 @@ void gen_intermediate_code(CPUPPCState *env, struct T= ranslationBlock *tb) exit(1); } } - if (tb->cflags & CF_LAST_IO) + if (tb_cflags(tb) & CF_LAST_IO) gen_io_end(); if (ctx.exception =3D=3D POWERPC_EXCP_NONE) { gen_goto_tb(&ctx, 0, ctx.nip); diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index b325c2c..2e902fc 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -175,11 +175,11 @@ static void spr_write_ureg(DisasContext *ctx, int spr= n, int gprn) #if !defined(CONFIG_USER_ONLY) static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -187,11 +187,11 @@ static void spr_read_decr(DisasContext *ctx, int gprn= , int sprn) =20 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -202,11 +202,11 @@ static void spr_write_decr(DisasContext *ctx, int spr= n, int gprn) /* Time base */ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -214,11 +214,11 @@ static void spr_read_tbl(DisasContext *ctx, int gprn,= int sprn) =20 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -239,11 +239,11 @@ static void spr_read_atbu(DisasContext *ctx, int gprn= , int sprn) #if !defined(CONFIG_USER_ONLY) static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -251,11 +251,11 @@ static void spr_write_tbl(DisasContext *ctx, int sprn= , int gprn) =20 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -283,11 +283,11 @@ static void spr_read_purr(DisasContext *ctx, int gprn= , int sprn) /* HDECR */ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } @@ -295,11 +295,11 @@ static void spr_read_hdecr(DisasContext *ctx, int gpr= n, int sprn) =20 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) { - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_stop_exception(ctx); } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index be1a04d..0d5d623 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -612,7 +612,7 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_exit_tb(DisasContext *s) { return (s->singlestep_enabled || - (s->tb->cflags & CF_LAST_IO) || + (tb_cflags(s->tb) & CF_LAST_IO) || (s->tb->flags & FLAG_MASK_PER)); } =20 @@ -5880,7 +5880,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -5905,7 +5905,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -5924,7 +5924,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) } } while (status =3D=3D NO_EXIT); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 2a206af..9fcaefd 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2256,7 +2256,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) (ctx.tbflags & (1 << SR_RB))) * 0x10; ctx.fbank =3D ctx.tbflags & FPSCR_FR ? 0x10 : 0; =20 - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -2300,7 +2300,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) break; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -2308,7 +2308,7 @@ void gen_intermediate_code(CPUSH4State * env, struct = TranslationBlock *tb) decode_opc(&ctx); ctx.pc +=3D 2; } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index aa6734d..39d8494 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5781,7 +5781,7 @@ void gen_intermediate_code(CPUSPARCState * env, Trans= lationBlock * tb) #endif =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -5810,7 +5810,7 @@ void gen_intermediate_code(CPUSPARCState * env, Trans= lationBlock * tb) goto exit_gen_loop; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -5837,7 +5837,7 @@ void gen_intermediate_code(CPUSPARCState * env, Trans= lationBlock * tb) num_insns < max_insns); =20 exit_gen_loop: - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } if (!dc->is_br) { diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ff2ef7b..33be670 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2379,7 +2379,7 @@ void gen_intermediate_code(CPUTLGState *env, struct T= ranslationBlock *tb) uint64_t pc_start =3D tb->pc; uint64_t next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; int num_insns =3D 0; - int max_insns =3D tb->cflags & CF_COUNT_MASK; + int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; =20 dc->pc =3D pc_start; dc->mmuidx =3D 0; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ddd2dd0..3d8448c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8791,7 +8791,7 @@ void gen_intermediate_code(CPUTriCoreState *env, stru= ct TranslationBlock *tb) int num_insns, max_insns; =20 num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 666a201..4cede72 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -1896,7 +1896,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) cpu_F1d =3D tcg_temp_new_i64(); next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -1929,7 +1929,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) goto done_generating; } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -1954,7 +1954,7 @@ void gen_intermediate_code(CPUUniCore32State *env, Tr= anslationBlock *tb) dc->pc < next_page_start && num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 2630024..3ded61b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -513,12 +513,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t s= r, unsigned access) =20 static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) { - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(d, cpu_SR[sr]); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); return true; } @@ -698,11 +698,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32= _t sr, TCGv_i32 v) =20 static void gen_check_interrupts(DisasContext *dc) { - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_check_interrupts(cpu_env); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -756,11 +756,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr,= TCGv_i32 v) =20 static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) { - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wsr_ccount(cpu_env, v); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); return true; @@ -797,11 +797,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32= _t sr, TCGv_i32 v) =20 tcg_gen_mov_i32(cpu_SR[sr], v); tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccompare(cpu_env, tmp); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); ret =3D true; @@ -896,11 +896,11 @@ static void gen_waiti(DisasContext *dc, uint32_t imm4) TCGv_i32 pc =3D tcg_const_i32(dc->next_pc); TCGv_i32 intlevel =3D tcg_const_i32(imm4); =20 - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_waiti(cpu_env, pc, intlevel); - if (dc->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { gen_io_end(); } tcg_temp_free(pc); @@ -3123,7 +3123,7 @@ void gen_intermediate_code(CPUXtensaState *env, Trans= lationBlock *tb) CPUState *cs =3D CPU(cpu); DisasContext dc; int insn_count =3D 0; - int max_insns =3D tb->cflags & CF_COUNT_MASK; + int max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; uint32_t pc_start =3D tb->pc; uint32_t next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; @@ -3159,7 +3159,7 @@ void gen_intermediate_code(CPUXtensaState *env, Trans= lationBlock *tb) =20 gen_tb_start(tb); =20 - if ((tb->cflags & CF_USE_ICOUNT) && + if ((tb_cflags(tb) & CF_USE_ICOUNT) && (tb->flags & XTENSA_TBFLAG_YIELD)) { tcg_gen_insn_start(dc.pc); ++insn_count; @@ -3191,7 +3191,7 @@ void gen_intermediate_code(CPUXtensaState *env, Trans= lationBlock *tb) break; } =20 - if (insn_count =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (insn_count =3D=3D max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } =20 @@ -3232,7 +3232,7 @@ done: tcg_temp_free(dc.next_icount); } =20 - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052078635737.83624945530187; Wed, 19 Jul 2017 20:19:46 -0700 (PDT) Received: from localhost ([::1]:35836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY208-0001jY-IU for importer@patchew.org; Wed, 19 Jul 2017 23:19:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016Q-CQ for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pr-HX for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40143) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005od-7f for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D1B9320A5D; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:33 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 94BC3240AF; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=XLG X7+ueAlf3sv88oU1zL+yCry8RTn251OXHxfYcG3Q=; b=n0kZ40kXO9VWm/8hKqf Y4erSuVK1qXr+XN35FWEe0oDQlJulWckxgn8oRfVLVzKpLGEP7hD7dYC8UaKvg0S NTuANMVIijKeWd9YHK7BH553FBvyah8fqN5spyuKKvG/sEJiuS1docu61PhFaaNe Q04DTK/59kU+RGr1LqAM+v18= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=XLGX7+ueAlf3sv88oU1zL+yCry8RTn251OXHxfYcG 3Q=; b=EMv4Q0Sx4J9lPb+JcCbBj/KAxWLrnn5itSyUVsxMwuvo/AM5UKaUYhXq+ 3jEuVEspFZHGUZTQ9uxPTNaTJDy+ByZ6m42JrchqIr2w0wB9FbNRO4H2CHcdGuMq 28fc7V+yVPBRbboLpOs7J/34GQIwVeFCXBjIsQX9xDPx3qZuZXCxBPznz4wzeTxu k0tlAJe9J3Z49BOcJn9V5jc86xchR91g6gtHzlExoSQtHQRZRmqR74jOlKjFxk1g B3MTPHiDIrB6mbeGFlJR7ujVjTC4RkDp041yJoQ5hbrPDJmuGnCrd2Ps4uU+CIBw 8Sn+w+LR5tmmsHmwF6n/vtOzQyaEQ== X-ME-Sender: X-Sasl-enc: u8i+05w2jyl+C91ElZX23Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:59 -0400 Message-Id: <1500520169-23367-14-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 13/43] target/arm: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/arm/helper-a64.h | 4 ++++ target/arm/helper-a64.c | 38 ++++++++++++++++++++++++++++++++------ target/arm/op_helper.c | 7 ------- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ target/arm/translate.c | 9 +++++++-- 5 files changed, 68 insertions(+), 21 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba..85d8674 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -43,4 +43,8 @@ DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32= , f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82c..d0e435c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -430,8 +430,9 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, = uint32_t bytes) } =20 /* Returns 0 on success; 1 otherwise. */ -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -440,7 +441,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -484,8 +485,21 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env,= uint64_t addr, return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true); +} + +static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -494,7 +508,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -537,3 +551,15 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env,= uint64_t addr, =20 return !success; } + +uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true); +} diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..a28f254 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -450,13 +450,6 @@ void HELPER(yield)(CPUARMState *env) ARMCPU *cpu =3D arm_env_get_cpu(env); CPUState *cs =3D CPU(cpu); =20 - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - g_assert(!parallel_cpus); - /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the * top level loop so that a more deserving VCPU has a chance to run. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 685f1b0..5e775bd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1334,13 +1334,18 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 3: /* WFI */ s->is_jmp =3D DISAS_WFI; return; + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* YIELD */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { s->is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { s->is_jmp =3D DISAS_WFE; } return; @@ -1918,11 +1923,25 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } } } else { TCGv_i64 val =3D cpu_reg(s, rt); diff --git a/target/arm/translate.c b/target/arm/translate.c index ccfb428..bd0ef58 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4497,8 +4497,13 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* yield */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->is_jmp =3D DISAS_YIELD; } @@ -4508,7 +4513,7 @@ static void gen_nop_hint(DisasContext *s, int val) s->is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->is_jmp =3D DISAS_WFE; } --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520789014155.9808281268081; Wed, 19 Jul 2017 20:19:49 -0700 (PDT) Received: from localhost ([::1]:35837 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY20A-0001m4-UC for importer@patchew.org; Wed, 19 Jul 2017 23:19:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60214) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016X-0j for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005q2-Ig for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:36545) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005p0-B0 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 0CD1A20A61; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:34 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C2DDC7E057; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=CBh IBhZuRS6o66eEaMB/Zywq1FNwGxcEvxNnpfbFroo=; b=qyjL/APC3BWihfRCps1 X+icn44c/BEaM14+cso1YWOHdke9p7mGNyy4bSK5tj2voXiEmQ9A0IRLLWSjkT6j xbSS6GR1UUfgwB7ZgZ4PDkjKLEiIbCkNclV+TXEW9RRtWA8hK8M/cGzIFz0uJre1 S/TAoE22zpYTRBYsKUi6aZUs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=CBhIBhZuRS6o66eEaMB/Zywq1FNwGxcEvxNnpfbFr oo=; b=Er2cBG5rCYQ1+UZZkT+xbx1QsZvGdHAwEy3ZDiCwYI1nlkklHFFgzZWxI D6aADmqFaHQ+SzFjS3DbmWXievZBW7+sX48bjI/Ec1ifb7A0PbntSj5+26VGOWRo j+3JqEj5E20rd9vYrToZE8NCrZ/4VfGptboL12jnQyzP6aC+xaxWTh93B+OOCTIp xBOQMKiw62kmr1TC+lW8cLzlaMmb2+bGdPOk+PIYH676YbM0jPMCPHun2J+6CDzv keHMAEct4zBtyHuFZrb5Gea2qM/KVJ8ehZZzyTiFfrqn9PeMtAZKQL+b5XOHg5mS si/TJAAOLeXgak3o8NUYbp0ldfcJA== X-ME-Sender: X-Sasl-enc: u8iyzI09jTV0CM1KioX23Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:00 -0400 Message-Id: <1500520169-23367-15-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 14/43] target/hppa: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++---- target/hppa/translate.c | 12 ++++++++++-- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 789f07f..0a6b900 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -3,7 +3,9 @@ DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) =20 DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index c05c0d5..3104404 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -76,7 +76,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, #endif } =20 -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, + bool parallel) { uintptr_t ra =3D GETPC(); =20 @@ -89,7 +90,7 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr,= target_ulong val) break; case 1: /* The 3 byte store must appear atomic. */ - if (parallel_cpus) { + if (parallel) { atomic_store_3(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); @@ -102,14 +103,26 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong a= ddr, target_ulong val) } } =20 -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +{ + do_stby_b(env, addr, val, false); +} + +void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, + target_ulong val) +{ + do_stby_b(env, addr, val, true); +} + +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong v= al, + bool parallel) { uintptr_t ra =3D GETPC(); =20 switch (addr & 3) { case 3: /* The 3 byte store must appear atomic. */ - if (parallel_cpus) { + if (parallel) { atomic_store_3(env, addr - 3, val, 0xffffff00u, ra); } else { cpu_stw_data_ra(env, addr - 3, val >> 16, ra); @@ -132,6 +145,17 @@ void HELPER(stby_e)(CPUHPPAState *env, target_ulong ad= dr, target_ulong val) } } =20 +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +{ + do_stby_e(env, addr, val, false); +} + +void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, + target_ulong val) +{ + do_stby_e(env, addr, val, true); +} + target_ulong HELPER(probe_r)(target_ulong addr) { return page_check_range(addr, 1, PAGE_READ); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1effe82..66aa11d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2309,9 +2309,17 @@ static ExitStatus trans_stby(DisasContext *ctx, uint= 32_t insn, val =3D load_gpr(ctx, rt); =20 if (a) { - gen_helper_stby_e(cpu_env, addr, val); + if (tb_cflags(ctx->tb) & CF_PARALLEL) { + gen_helper_stby_e_parallel(cpu_env, addr, val); + } else { + gen_helper_stby_e(cpu_env, addr, val); + } } else { - gen_helper_stby_b(cpu_env, addr, val); + if (tb_cflags(ctx->tb) & CF_PARALLEL) { + gen_helper_stby_b_parallel(cpu_env, addr, val); + } else { + gen_helper_stby_b(cpu_env, addr, val); + } } =20 if (m) { --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520457416686.8664275970393; Wed, 19 Jul 2017 20:14:17 -0700 (PDT) Received: from localhost ([::1]:35812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1uo-0004uk-Hf for importer@patchew.org; Wed, 19 Jul 2017 23:14:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016T-Iy for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qH-Mk for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:36491) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pC-Ft for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2DEC320B0A; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:34 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id EF475241E0; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=EaC MjZmhDnwuq1WDA0LL5VYEajUKjM5YKRawTQUAeXk=; b=wwsa5ox+L2FS9JZ/cgZ qJUtvdpgZ7ZXx3OTaKVEeTgS9/A5RBJWv3swqhHf9sTXfXMzeOVVcBjoD2pxT6H8 DPn1Cx2zmHFPO6+bTifR4hNR5++c5ZoAj6uceo5nx9c8CR6GS/YdR5FwokNBXZOZ 1echtPUnrNjI09WRXwLc2KMY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=EaCMjZmhDnwuq1WDA0LL5VYEajUKjM5YKRawTQUAe Xk=; b=Ka7gZqGzPH1b73mtqBKaMwTOnq3Gc4plIPl1SFfaVXTFlBV3OCaRMBW4O haFGxXVOlJMYgu1zzZUl72JocK44qtKu2zYx6H8E5Q+0sO5Mk5eRJ24dWNcEdA8o 2O/BrAjnenfjmgby0dOrkvR2CnVck8U5cf2UABN3ToRhNQNHUQnvLrkRSsC8MHRd C7QUD4vAmgeayGS40dkQP1/9jFiXFMYeukBLX3K52bnQLrmuTc4DsP++nWffXnNU RyFzY5VQ0xtk16bj52Y2ysk9l+BCM/PI+M2oFEvNMNq6+86q0xH0GwrKttDZqBJ1 VpNYKeF8UCv38xWZK2QDlbSiB4lQA== X-ME-Sender: X-Sasl-enc: u8i8yYo2mCBtHMJZnY723Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:01 -0400 Message-Id: <1500520169-23367-16-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 15/43] target/i386: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/i386/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index f046ffa..0f38a48 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -5263,7 +5263,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) goto illegal_op; gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && parallel_cpus) { + if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->tb) & CF_PARALL= EL)) { gen_helper_cmpxchg16b(cpu_env, cpu_A0); } else { gen_helper_cmpxchg16b_unlocked(cpu_env, cpu_A0); @@ -5274,7 +5274,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, if (!(s->cpuid_features & CPUID_CX8)) goto illegal_op; gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && parallel_cpus) { + if ((s->prefix & PREFIX_LOCK) && (tb_cflags(s->tb) & CF_PARALL= EL)) { gen_helper_cmpxchg8b(cpu_env, cpu_A0); } else { gen_helper_cmpxchg8b_unlocked(cpu_env, cpu_A0); --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520621468623.024535132678; Wed, 19 Jul 2017 20:17:01 -0700 (PDT) Received: from localhost ([::1]:35826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1xO-0007Eg-T1 for importer@patchew.org; Wed, 19 Jul 2017 23:16:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qN-00016W-PL for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qi-P1 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52893) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pB-J4 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 5F5E520A34; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:34 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 1CEFA7E057; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=3vL GUSXCOkh02Kxufvk3b7KaAQRWCXK7oTell2YQ6KM=; b=lpSwXYwhYlNltMcLjto uW16y7WF2yozBmZcDSkt428AvBuWaDm6Jqn3LCDjOtbWCN0qPdzWJ8/ch0964r/C 3ep1vC/oMN5GR1O7nk6YhLAufLooW36lIHrcTG9EmftI2CAO8FyWRvG5zO5ANJLG YMFZN4wIfcpZpWFvCzdFDMLs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=3vLGUSXCOkh02Kxufvk3b7KaAQRWCXK7oTell2YQ6 KM=; b=qrwvAOQEQvPCkRDhax7FJtLpeXqSIZpmWGFpGjfX5483D5Ed5jf2tKQYU DfgXwM1GKorj8HxkhdAwXcxlgBycRwTVnZYX2n+t+fwFz+N5N4/qktjbmAp9oyFE PiiEHO/rpW5udV1MFnUbCUZE0fQTa5RgEIXsJeXF7eOSuQsO1owPPLIfHXAwzqz2 AX2fb99oyGOOY70DJ1/14VyCaVcKz9lNeXzeFSlfOWGbAjwcfupp8ppuqJFUJCZG pmgBewr5e81PjB7qKjgMinewgMfETBfrHQ3gwmRAcf58zvCCwB/jyAMYMG78OySH Edwmd5mlDqbEId3OEmJwAGLn0tGEA== X-ME-Sender: X-Sasl-enc: W2+njPwfNltbiTci8MtpwML6KaLTk+nBUBJOmrlX2jh0 1500520174 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:02 -0400 Message-Id: <1500520169-23367-17-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 16/43] target/m68k: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/m68k/helper.h | 1 + target/m68k/op_helper.c | 33 ++++++++++++++++++++------------- target/m68k/translate.c | 12 ++++++++++-- 3 files changed, 31 insertions(+), 15 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 475a1f2..eebe52d 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -11,6 +11,7 @@ DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) DEF_HELPER_4(cas2w, void, env, i32, i32, i32) DEF_HELPER_4(cas2l, void, env, i32, i32, i32) +DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) =20 #define dh_alias_fp ptr #define dh_ctype_fp FPReg * diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 7b5126c..6308951 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -361,6 +361,7 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int re= gr, int32_t den) env->dregs[numr] =3D quot; } =20 +/* We're executing in a serial context -- no need to be atomic. */ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) { uint32_t Dc1 =3D extract32(regs, 9, 3); @@ -374,17 +375,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2) int16_t l1, l2; uintptr_t ra =3D GETPC(); =20 - if (parallel_cpus) { - /* Tell the main loop we need to serialize this insn. */ - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } else { - /* We're executing in a serial context -- no need to be atomic. */ - l1 =3D cpu_lduw_data_ra(env, a1, ra); - l2 =3D cpu_lduw_data_ra(env, a2, ra); - if (l1 =3D=3D c1 && l2 =3D=3D c2) { - cpu_stw_data_ra(env, a1, u1, ra); - cpu_stw_data_ra(env, a2, u2, ra); - } + l1 =3D cpu_lduw_data_ra(env, a1, ra); + l2 =3D cpu_lduw_data_ra(env, a2, ra); + if (l1 =3D=3D c1 && l2 =3D=3D c2) { + cpu_stw_data_ra(env, a1, u1, ra); + cpu_stw_data_ra(env, a2, u2, ra); } =20 if (c1 !=3D l1) { @@ -399,7 +394,8 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, ui= nt32_t a1, uint32_t a2) env->dregs[Dc2] =3D deposit32(env->dregs[Dc2], 0, 16, l2); } =20 -void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32= _t a2, + bool parallel) { uint32_t Dc1 =3D extract32(regs, 9, 3); uint32_t Dc2 =3D extract32(regs, 6, 3); @@ -416,7 +412,7 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, ui= nt32_t a1, uint32_t a2) TCGMemOpIdx oi; #endif =20 - if (parallel_cpus) { + if (parallel) { /* We're executing in a parallel context -- must be atomic. */ #ifdef CONFIG_ATOMIC64 uint64_t c, u, l; @@ -470,6 +466,17 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, u= int32_t a1, uint32_t a2) env->dregs[Dc2] =3D l2; } =20 +void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +{ + do_cas2l(env, regs, a1, a2, false); +} + +void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1, + uint32_t a2) +{ + do_cas2l(env, regs, a1, a2, true); +} + struct bf_data { uint32_t addr; uint32_t bofs; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 188520b..65044be 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2308,7 +2308,11 @@ DISAS_INSN(cas2w) (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2w(cpu_env, regs, addr1, addr2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_exit_atomic(cpu_env); + } else { + gen_helper_cas2w(cpu_env, regs, addr1, addr2); + } tcg_temp_free(regs); =20 /* Note that cas2w also assigned to env->cc_op. */ @@ -2354,7 +2358,11 @@ DISAS_INSN(cas2l) (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2l(cpu_env, regs, addr1, addr2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2); + } else { + gen_helper_cas2l(cpu_env, regs, addr1, addr2); + } tcg_temp_free(regs); =20 /* Note that cas2l also assigned to env->cc_op. */ --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052177738124.614998575008258; Wed, 19 Jul 2017 20:36:17 -0700 (PDT) Received: from localhost ([::1]:35918 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2G7-0000bk-K0 for importer@patchew.org; Wed, 19 Jul 2017 23:36:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qQ-00016q-A1 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qy-SQ for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:47257) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pN-LB for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id A3DA520B44; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:34 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 514FB241E0; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=/54 Aoh7vScrYmivCBmWl6xVtXPS1A/bDm5F//Kbl7KM=; b=JKukJ6oppjgI4C1p5XU R6sMa838LBTz4irnS2qwIeBbHOt6ZozS+Zj+w/vs5WzZdSFXKqe2CfqmDRKN9R/2 mrqZrtT2oBgjCHRNG2zkTFY3UZj1BKjQ6zvwNMmWN+UYHfspGIC+ce8I0JH5ddVJ i1R3zBft+n6w/oBb5sWTWdLY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=/54Aoh7vScrYmivCBmWl6xVtXPS1A/bDm5F//Kbl7 KM=; b=rMYIZdPNPL9AvTds/BSK2GApwaT3fcq6dtvT0vyCfzRhIxo0LEzbiU8WO Ax1HZmGDzo3OTaZSyHUil8MuyOwk6bew93noQzT8rqxdttBuNoQK+qyZfmRE7zrx FQgYYNCnaMf4aNKR0taxGI9gGf7bEUOoPEviQ/UzBcJH7EgV22s9MYcta1Q6voH0 BccstLdiQUiLbfP8gOnh0ebdXarIRC9ss/WBrI0hUbDjwqTizDzlQiDY4/zVR3RT rS2Wbx628FU6TX5/jGNMDxCiNp1uOO7Gzc71m0GHyKScBBRbblfzQyj9GEZOznVk 2edaMbVLzQ9ykLO7k8r1ITGpoxfMQ== X-ME-Sender: X-Sasl-enc: W2+1jPwWLUZagjEk8MJpwML6KaLTk+nBUBJOmrlX2jh0 1500520174 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:03 -0400 Message-Id: <1500520169-23367-18-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 17/43] target/s390x: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/s390x/helper.h | 4 +++ target/s390x/mem_helper.c | 80 +++++++++++++++++++++++++++++++++++++------= ---- target/s390x/translate.c | 26 ++++++++++++--- 3 files changed, 88 insertions(+), 22 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 4b02907..84a4597 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -34,7 +34,9 @@ DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i64, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) +DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) +DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) @@ -107,7 +109,9 @@ DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) DEF_HELPER_2(stfle, i32, env, i64) DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lpq_parallel, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(stpq_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i64) DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) DEF_HELPER_4(cu12, i32, env, i32, i32, i32) DEF_HELPER_4(cu14, i32, env, i32, i32, i32) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index cdc78aa..74a2157 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1363,8 +1363,8 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1= , uint32_t r2, return cc; } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) +static void do_cdsg(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3, bool parallel) { uintptr_t ra =3D GETPC(); Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); @@ -1372,7 +1372,7 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, Int128 oldv; bool fail; =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -1404,7 +1404,20 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 -uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64= _t a2) +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + do_cdsg(env, addr, r1, r3, false); +} + +void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + do_cdsg(env, addr, r1, r3, true); +} + +static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, + uint64_t a2, bool parallel) { #if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) uint32_t mem_idx =3D cpu_mmu_index(env, false); @@ -1440,7 +1453,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) the complete operation is not. Therefore we do not need to assert = serial context in order to implement this. That said, restart early if we= can't support either operation that is supposed to be atomic. */ - if (parallel_cpus) { + if (parallel) { int mask =3D 0; #if !defined(CONFIG_ATOMIC64) mask =3D -8; @@ -1464,7 +1477,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) uint32_t cv =3D env->regs[r3]; uint32_t ov; =20 - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_USER_ONLY uint32_t *haddr =3D g2h(a1); ov =3D atomic_cmpxchg__nocheck(haddr, cv, nv); @@ -1487,7 +1500,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) uint64_t cv =3D env->regs[r3]; uint64_t ov; =20 - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_ATOMIC64 # ifdef CONFIG_USER_ONLY uint64_t *haddr =3D g2h(a1); @@ -1497,7 +1510,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) ov =3D helper_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, = ra); # endif #else - /* Note that we asserted !parallel_cpus above. */ + /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { @@ -1517,13 +1530,13 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t = r3, uint64_t a1, uint64_t a2) Int128 cv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; =20 - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_ATOMIC128 TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); cc =3D !int128_eq(ov, cv); #else - /* Note that we asserted !parallel_cpus above. */ + /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { @@ -1567,13 +1580,13 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t = r3, uint64_t a1, uint64_t a2) cpu_stq_data_ra(env, a2, svh, ra); break; case 4: - if (parallel_cpus) { + if (parallel) { #ifdef CONFIG_ATOMIC128 TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); Int128 sv =3D int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); #else - /* Note that we asserted !parallel_cpus above. */ + /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { @@ -1593,6 +1606,17 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r= 3, uint64_t a1, uint64_t a2) g_assert_not_reached(); } =20 +uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64= _t a2) +{ + return do_csst(env, r3, a1, a2, false); +} + +uint32_t HELPER(csst_parallel)(CPUS390XState *env, uint32_t r3, uint64_t a= 1, + uint64_t a2) +{ + return do_csst(env, r3, a1, a2, true); +} + #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { @@ -2035,12 +2059,12 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) #endif =20 /* load pair from quadword */ -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) +static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -2061,13 +2085,23 @@ uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t a= ddr) return hi; } =20 +uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) +{ + return do_lpq(env, addr, false); +} + +uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) +{ + return do_lpq(env, addr, true); +} + /* store pair to quadword */ -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) +static void do_stpq(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high, bool parallel) { uintptr_t ra =3D GETPC(); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -2085,6 +2119,18 @@ void HELPER(stpq)(CPUS390XState *env, uint64_t addr, } } =20 +void HELPER(stpq)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + do_stpq(env, addr, low, high, false); +} + +void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + do_stpq(env, addr, low, high, true); +} + /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 0d5d623..ea8a90a 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2024,7 +2024,11 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps = *o) addr =3D get_address(s, 0, b2, d2); t_r1 =3D tcg_const_i32(r1); t_r3 =3D tcg_const_i32(r3); - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); + } else { + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + } tcg_temp_free_i64(addr); tcg_temp_free_i32(t_r1); tcg_temp_free_i32(t_r3); @@ -2038,7 +2042,11 @@ static ExitStatus op_csst(DisasContext *s, DisasOps = *o) int r3 =3D get_field(s->fields, r3); TCGv_i32 t_r3 =3D tcg_const_i32(r3); =20 - gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->in1, o->in2); + } else { + gen_helper_csst(cc_op, cpu_env, t_r3, o->in1, o->in2); + } tcg_temp_free_i32(t_r3); =20 set_cc_static(s); @@ -2943,7 +2951,7 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o) TCGMemOp mop =3D s->insn->data; =20 /* In a parallel context, stop the world and single step. */ - if (parallel_cpus) { + if (tb_cflags(s->tb) & CF_PARALLEL) { potential_page_fault(s); gen_exception(EXCP_ATOMIC); return EXIT_NORETURN; @@ -2964,7 +2972,11 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *= o) =20 static ExitStatus op_lpq(DisasContext *s, DisasOps *o) { - gen_helper_lpq(o->out, cpu_env, o->in2); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_lpq_parallel(o->out, cpu_env, o->in2); + } else { + gen_helper_lpq(o->out, cpu_env, o->in2); + } return_low128(o->out2); return NO_EXIT; } @@ -4281,7 +4293,11 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps = *o) =20 static ExitStatus op_stpq(DisasContext *s, DisasOps *o) { - gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); + } else { + gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + } return NO_EXIT; } =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521092983881.4286197890183; Wed, 19 Jul 2017 20:24:52 -0700 (PDT) Received: from localhost ([::1]:35860 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY254-0007cs-P3 for importer@patchew.org; Wed, 19 Jul 2017 23:24:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60175) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qN-00016U-1A for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qm-Ps for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:45613) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pM-IA for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C3AC120B0C; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:34 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 88C527E057; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=PqL qPp9zolJ+WMjjUPyXVjFYWsimZFTTr7StYGUanRE=; b=Md5Ghl2KUAdZ2xkYJlD +UihzN/6aIVOr2tzOkwk04PhKoJWLxN7O9frxBjjp2AsQiptbKsOYt5O12RmR6Fb gqDFo1G36L1eA0hnxpJ29aUf5cKs5UMJ/e13A/LS6mnXflnqd/R+lbtmoIo0Xm0o FKwXVkhIfYBbMPNe94cmLp5s= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=PqLqPp9zolJ+WMjjUPyXVjFYWsimZFTTr7StYGUan RE=; b=FwsLL8LK+sjXv8uCqc9RigvBP4HPnO9r+JBYn3mHr5ZhS08x/HG+hvz7v wrby2SUmhpJelK8CVzPtBp452IP5bkFaNS/QlLX0Pw6Tk6ov++oKx87UjPFkh6jV IvsviYHt+DItRQ8mEuKge90pfcWeq++/hckpDV4l16I49lFjx+/DU6Uw86Qw38It 7Bog/EQy7p27GTdezChgTRl+EpHItwSzBERZUS8eWt61mGqEXFVzsb31dzPv1u7H ouAC2aU377mVDFZ5n3ry7yHatckMp84dPz/vWaq7weMswsvjZ4zP28qDKiR9nK9l f/06qP53IJX9wusq4BBApincDTwaw== X-ME-Sender: X-Sasl-enc: W2+9kPwfL0RIiCwl+clpwML6KaLTk+nBUBJOmrlX2jh0 1500520174 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:04 -0400 Message-Id: <1500520169-23367-19-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 18/43] target/sh4: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/sh4/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9fcaefd..52fabb3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -528,7 +528,7 @@ static void _decode_opc(DisasContext * ctx) /* Detect the start of a gUSA region. If so, update envflags and end the TB. This will allow us to see the end of the region (stored in R0) in the next TB. */ - if (B11_8 =3D=3D 15 && B7_0s < 0 && parallel_cpus) { + if (B11_8 =3D=3D 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARAL= LEL)) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); ctx->bstate =3D BS_STOP; } --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520611443535.5369121776409; Wed, 19 Jul 2017 20:16:51 -0700 (PDT) Received: from localhost ([::1]:35825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1xJ-00079h-1y for importer@patchew.org; Wed, 19 Jul 2017 23:16:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016S-Cn for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qX-P9 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:41237) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pP-If for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id EE37C20B4F; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:34 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B3AD9241E0; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=sXe uE/HxFFdvXaSTovakUXIrEP5dRC9CGAd0klUP888=; b=h5V7CmtrWb/lfzPVgOW x3wdQi2b1Gmwnwl0mGWSVLiJw2N5qsRIhlgMTQy0H3EeKWnOTiR4lD23Su7w7xmg ZWYTrh0+RSWPpRbVXoxBq1jQ/XVNGlEVZ6MhG9SdGqiT3u/1F7OZJIIXtuAYh/ns oEtrVUir81+viixoGSLCKQ0A= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=sXeuE/HxFFdvXaSTovakUXIrEP5dRC9CGAd0klUP8 88=; b=A1W8domb6CON+EXI+jQo3c7DBemTON3vE91j3JPJ+TwelJZH2+Dpl3lrN 5ys7sUCbIp3GjQQGt3Ucmcar+ZAS3Z7Herr5J7R/zdPWXLYQSqwzToe39FaQMe9Z Wfi8lAXIB6Rp8jH5REGJgX4OoKYU3hSa/KMOSeV7KEXWKwW57IIYCouaasbpojXW eUUA2NRVMXW38wWa71vpTSz1CQUlo1u2iPwaqMzUZLIyJOElnG1dsScmGkiom9On +MqketgIi6pcX4SctVJhXTusK1oEF1N+VOJZ5UKpphWBln6K+JUROjhqkWaP79nt d1H5ywLKsAEeL0yoWWRROPAfkJXWg== X-ME-Sender: X-Sasl-enc: W2+mkf0EM1dZnTcr8c1pwML6KaLTk+nBUBJOmrlX2jh0 1500520174 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:05 -0400 Message-Id: <1500520169-23367-20-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 19/43] target/sparc: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 39d8494..768ce68 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2450,7 +2450,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst= , TCGv addr, int insn) default: /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ - if (parallel_cpus) { + if (tb_cflags(dc->tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { TCGv_i32 r_asi =3D tcg_const_i32(da.asi); --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520944321189.61391506492964; Wed, 19 Jul 2017 20:22:24 -0700 (PDT) Received: from localhost ([::1]:35850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY22g-00052y-IM for importer@patchew.org; Wed, 19 Jul 2017 23:22:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qN-00016V-5B for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qv-R7 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40131) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pO-Jl for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2E8F820B50; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id E15B37E057; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=0J/ gSaSYrTzVwre/A1lgzU2x4Qb/KiCcXMpXc4/SU8g=; b=f0v0XOIltCp2CWHv//8 U/wcKiFy3QeVX9dm1xrMv3D5oBFSqNH0i6H2V0jaGI/WIu0HYlEeejmXVBPM9yFL AwyTJAObVLK5gZRIemj0F4eyW/JWdITY7bmeVzirofKktIzQD4evsmX6CMtFq9hO utgX6h8/4H7po63EQRQ/Ktxc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=0J/gSaSYrTzVwre/A1lgzU2x4Qb/KiCcXMpXc4/SU 8g=; b=DOCPxUaHiWOsA7haRRWqLRQPOMwJOgbTJjq4De8tcpv9HDdmkPaY1HSBo l1lbUUjocxIONmsR88BauoXpM5Rw0IAxe4MbzKvHOtcudbNq5J5KhUPn4m/gXxpc mOR4QWpR2ti0+5UoHBrc/RvT8E5neLxKe/9JNnZ3wWecdY5ilCUh/5ITL0Izl2R/ 2nVOV7VtqhQPXDHLhzOQUqzNZCkcpPX9tGlXV7g+JeV+Hg+pbz24Lrn+LOHenMrv 0fNIga6dCVpBhOxkIEInT7kyZitH6H1SZ4eHbPWdkg7wnsxXgob0fX1NWWcYeXUf 1PvCMJ9cJqQAzPeK9vm3r/OToNglw== X-ME-Sender: X-Sasl-enc: W2+vgeAMLE5GmT01/tRpwML6KaLTk+nBUBJOmrlX2jh0 1500520174 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:06 -0400 Message-Id: <1500520169-23367-21-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 20/43] tcg: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a bit to TCGContext, storing there whether CF_PARALLEL is set before translating every TB. Most architectures have <=3D 32 registers, which results in a 4-byte hole in TCGContext. Use this hole for the bit we need, which we store in a bool. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 1 + accel/tcg/translate-all.c | 1 + tcg/tcg-op.c | 10 +++++----- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 96872f8..9b6dade 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,6 +656,7 @@ struct TCGContext { uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_J= UMP */ =20 TCGRegSet reserved_regs; + bool cf_parallel; /* whether CF_PARALLEL is set in tb->cflags */ intptr_t current_frame_offset; intptr_t frame_start; intptr_t frame_end; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 600c0a1..645bc70 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1271,6 +1271,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; + tcg_ctx.cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 205d07f..ef420d4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -150,7 +150,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg= a1, TCGArg a2, =20 void tcg_gen_mb(TCGBar mb_type) { - if (parallel_cpus) { + if (tcg_ctx.cf_parallel) { tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); } } @@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!parallel_cpus) { + if (!tcg_ctx.cf_parallel) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!parallel_cpus) { + if (!tcg_ctx.cf_parallel) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.cf_parallel) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.cf_parallel) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520935548415.44915085903915; Wed, 19 Jul 2017 20:22:15 -0700 (PDT) Received: from localhost ([::1]:35849 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY22X-0004ri-Q2 for importer@patchew.org; Wed, 19 Jul 2017 23:22:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016Y-AP for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005r4-Sx for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:33885) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pk-Nv for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 5793120B52; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 1B604241E0; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=k+b TzhZBey2LiM9kFswUkkZ8GYJVyHRbUTIpeuPQ5kc=; b=jQiYA01ME6j9mHtLO0+ eSKSAaLzW+jr9iUKgRSFoPbSbttgNdYcNc6+syqzOxv6sgkTBrWeZhlurNF8mrXm 1gPeCNbNOO83IinB2qpiUz5dMK20uVuiRNqII3IPRfFVlq0Ll6fIfr1pa2zbin+B 9/o22n+GfFtee1CYWiXsTDCE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=k+bTzhZBey2LiM9kFswUkkZ8GYJVyHRbUTIpeuPQ5 kc=; b=TWvOfgJRAlZa0W9OQvkHPdd9MWYTbo2RCPiirIu9NTGGQcm88z9lZjSBZ kuXKgLieCPZzGLz4ZhsnvcHo3NtFoRM2h69Cpqcity2pos6dd9IkUAyesP7zkF/0 RNZRGrujLnD1zIkzxEgnwukKbEEJ2pdn921ch4K9dVI8OkTcGc9jOGn1Oz9GOUPR 4oTxsnCPFUJTfxNO1VQeM/npzgvum+54foG91qGuf15JhDmsLVw7ShOe6YMliscU bX9tKL23405WK3zcVR5rWUwQvHM/T/R2p3MGwlO49bOaPKtg6q2y8fHxzj3JN9Ew CSNgSRVmp1/5Dj4tizTuXuIy+o3BQ== X-ME-Sender: X-Sasl-enc: 92pBxn/aufqbBEVKI0RItYbRtUP9JetTkbvaXY2bZn9p 1500520175 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:07 -0400 Message-Id: <1500520169-23367-22-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 21/43] cpu-exec: lookup/generate TB outside exclusive region during step_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that all code generation has been converted to check CF_PARALLEL, we can generate !CF_PARALLEL code without having yet set !parallel_cpus -- and therefore without having to be in the exclusive region during cpu_exec_step_atomic. While at it, merge cpu_exec_step into cpu_exec_step_atomic. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/cpu-exec.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b71e015..526cab3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -223,30 +223,40 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, } #endif =20 -static void cpu_exec_step(CPUState *cpu) +void cpu_exec_step_atomic(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; uint32_t cflags =3D 1 | CF_IGNORE_ICOUNT; + uint32_t cf_mask =3D cflags & CF_HASH_MASK; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, - cflags & CF_HASH_MASK); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); if (tb =3D=3D NULL) { mmap_lock(); tb_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); + if (likely(tb =3D=3D NULL)) { + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + } tb_unlock(); mmap_unlock(); } =20 + start_exclusive(); + + /* Since we got here, we know that parallel_cpus must be true. */ + parallel_cpus =3D false; cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); + parallel_cpus =3D true; + + end_exclusive(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -260,18 +270,6 @@ static void cpu_exec_step(CPUState *cpu) } } =20 -void cpu_exec_step_atomic(CPUState *cpu) -{ - start_exclusive(); - - /* Since we got here, we know that parallel_cpus must be true. */ - parallel_cpus =3D false; - cpu_exec_step(cpu); - parallel_cpus =3D true; - - end_exclusive(); -} - struct tb_desc { target_ulong pc; target_ulong cs_base; --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520778347944.2091193117393; Wed, 19 Jul 2017 20:19:38 -0700 (PDT) Received: from localhost ([::1]:35835 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY200-0001eC-Bd for importer@patchew.org; Wed, 19 Jul 2017 23:19:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60246) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016Z-Fw for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005rA-VY for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:34291) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005q8-Qz for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 8719F20B55; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 47DD07E057; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=gkZX3r3TtbUCEIM GZn5uDrCPZy2nfuOHPtlbXu1KZ8E=; b=hFafAtFVTX4MSfSKcB3P2YQiXTQ2+XH /K4zeUJCZiQFj54xPugPNneLxZdhwoMvvluvLGfLOrGQlWt0X2P7n8uqHmQm7O2v MY42UzVyey3Fq8SZ3VKSSPdko2RSHCbXxmG6/Nhekvn2rqU0wJRqE3fLeeSYKySR aX0u54HRCxkw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=gkZX3r3TtbUCEIMGZn5uDrCPZy2nfuOHPtlbXu1KZ8E=; b=noxho2/B 1PH9BThLVoqeh03osfLoGpW+TJu4Bd6W5LCqUYJ6mKLt3weAt9AyD4Ff1ANN770Y h/Caxh18DEe33ISd02KKmiQKT36etEyVHiTo1QeT4UmNvHRQXekjhb27jmwpoxUB l7TgbpmfA0IsV1ViE9qT0jxVtNm8il00OBGj+kwaBRo9b0uB3X5epzllvUqdNVW4 5AhOTDGYaMwn/61XtzUn/qM14AVoI++OyvfOsXaj+Xs6/wmx0nwafcN0NL69cTq5 28VFsf+9aaH5L+b+SXYq8l6OqpwmVp6m0uoHnltYzaqnBuDbT8ai2pLTHrgI1CAG BzTXaSDiZX3yZg== X-ME-Sender: X-Sasl-enc: 92pZyHXPu/WADF5dL0dItYbRtUP9JetTkbvaXY2bZn9p 1500520175 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:08 -0400 Message-Id: <1500520169-23367-23-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 22/43] translate-all: define and use DEBUG_TB_FLUSH_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This gets rid of some ifdef checks while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 645bc70..c1cd258 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_FLUSH +#define DEBUG_TB_FLUSH_GATE 1 +#else +#define DEBUG_TB_FLUSH_GATE 0 +#endif + #if !defined(CONFIG_USER_ONLY) /* TB consistency checks only implemented for usermode emulation. */ #undef DEBUG_TB_CHECK @@ -899,13 +905,13 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) goto done; } =20 -#if defined(DEBUG_TB_FLUSH) - printf("qemu: flush code_size=3D%ld nb_tbs=3D%d avg_tb_size=3D%ld\n", - (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer= )) / - tcg_ctx.tb_ctx.nb_tbs : 0); -#endif + if (DEBUG_TB_FLUSH_GATE) { + printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, + tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / + tcg_ctx.tb_ctx.nb_tbs : 0); + } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521385042662.554179926241; Wed, 19 Jul 2017 20:29:45 -0700 (PDT) Received: from localhost ([::1]:35880 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY29n-0003oI-78 for importer@patchew.org; Wed, 19 Jul 2017 23:29:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016c-Qk for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qK-0005rJ-3T for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52761) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qh-Vr for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:36 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B2AE420B57; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 779A4247A2; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=6F5ADrdg11ovYFR hrvcWdGz2AUji7liiFFA68U/9o9E=; b=edRrZXUBZrXqh+DwulWZ0mn/q7C1iL/ DiSpY7F/4SVhs5Vt5+YCi5fkVzxHbOO7FB4oMQMyGk76MMCJzcIAw2L7ripO0aHd JFHwBuDY2ssOUHFCsHta6TfAB2gOM1Q7B19Xg1zK/PUtDOyFSxB2LQWcFrEEfZ+B EP9P6pRrKynI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=6F5ADrdg11ovYFRhrvcWdGz2AUji7liiFFA68U/9o9E=; b=K4gRqPiT MA64UlNnQ08rJfGYFsSvscLOVruE09wMyGrlPeSOW4EODEtTX/lBC168oZreX+D+ +W/JdPgaT/uOSgeWc6OgYTmWlBi73/kdDF1V8a1WQsGyg1CLQW84NgF/ikcemfuh Uv+A9LUh/3mqtnb1ioVajo1QFHsDy4nJ758kz7bgQR/e/PdyaPGupt2QQcz9bVse fJR5ramoeDIFdB/vOGvFqwbPc1P71XRMEhCIFJSJ37DmtzP4xneyc/F/E+cwLG9C XaWb3N1XDMXA3yG8qz14qiSDiX09hDSUtQ64w5kyzdvx3kwwCMEiRlz3joXo6yXx jvSfboafbtl+Jw== X-ME-Sender: X-Sasl-enc: 92pH02HWvuOGBldJL1JItYbRtUP9JetTkbvaXY2bZn9p 1500520175 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:09 -0400 Message-Id: <1500520169-23367-24-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 23/43] exec-all: introduce TB_PAGE_ADDR_FMT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 And fix the following warning when DEBUG_TB_INVALIDATE is enabled in translate-all.c: CC mipsn32-linux-user/accel/tcg/translate-all.o /data/src/qemu/accel/tcg/translate-all.c: In function =E2=80=98tb_alloc_pag= e=E2=80=99: /data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format =E2=80=98%l= x=E2=80=99 expects argument of type =E2=80=98long unsigned int=E2=80=99, bu= t argument 2 has type =E2=80=98tb_page_addr_t {aka unsigned int}=E2=80=99 [= -Werror=3Dformat=3D] printf("protecting code page: 0x" TARGET_FMT_lx "\n", ^ cc1: all warnings being treated as errors /data/src/qemu/rules.mak:66: recipe for target 'accel/tcg/translate-all.o' = failed make[1]: *** [accel/tcg/translate-all.o] Error 1 Makefile:328: recipe for target 'subdir-mipsn32-linux-user' failed make: *** [subdir-mipsn32-linux-user] Error 2 cota@flamenco:/data/src/qemu/build ((18f3fe1...) *$)$ Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 2 ++ accel/tcg/translate-all.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 0af0485..00f7da8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,10 @@ type. */ #if defined(CONFIG_USER_ONLY) typedef abi_ulong tb_page_addr_t; +#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx #else typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif =20 /* DisasContext is_jmp field values diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c1cd258..c4c23f9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1194,8 +1194,7 @@ static inline void tb_alloc_page(TranslationBlock *tb, mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); #ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TARGET_FMT_lx "\n", - page_addr); + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); #endif } #else --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520944311728.3160580226565; Wed, 19 Jul 2017 20:22:24 -0700 (PDT) Received: from localhost ([::1]:35851 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY22g-000533-HT for importer@patchew.org; Wed, 19 Jul 2017 23:22:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016b-MI for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qK-0005rV-F1 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40609) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qK-0005rF-BI for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:36 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id DCE0B20B47; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id A1E897E057; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=HXxjbuIWIlcA0xs QnraW5WBYr6O/p3NUktuPkLpL4ds=; b=t/Fj8oQaqLEt7cYW4lM87Qb3l1+kYcH NnJux4algZGIipPrYmD5/lDa68orTieu03Vd8inIiY8sqMC6oCog97X9MOqvsUir iExyVzSyJr07yDFS6Ss7r9IO48cWHgD2dy/yZxh7OoFfUR8ih97+A9Fm7nJ+FA1w BoBpdVCM64cg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=HXxjbuIWIlcA0xsQnraW5WBYr6O/p3NUktuPkLpL4ds=; b=peL0mncg EtK2rxH1d1FskKZPiXqifbSzaiJl42VnzanpUKY+4NUMVFUvgJpQl5HyD4FqKc90 GW8jEv2MtfH0SI6AVtHeiwVnNvac0+kwnYN8GHYZ4NbeWR1+oQ/ZKS8kFncHl2hI RGN2i7H7y0VoLoQHK7PyosXzSQZLAXjQWiuHclAbqXyR1VU3BpRzLUYf3Pow5d20 cdtAiJsU+2EqacQuKhcqfT8XnETysrs0au10KytEo/ZPkUgUkI2Am2MFn6ObQC2x W2dKpavinKF0Vpma+oJeWrEjkFL8dGinIZ8XH0mEyI5hvKFEIp1QTg9PT5rcIxBP 3y5ji+0wwE4t+w== X-ME-Sender: X-Sasl-enc: 92pC33PGsfWbH0NJL1tItYbRtUP9JetTkbvaXY2bZn9p 1500520175 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:10 -0400 Message-Id: <1500520169-23367-25-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 24/43] translate-all: define and use DEBUG_TB_INVALIDATE_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This gets rid of an ifdef check while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c4c23f9..962e9b3 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_INVALIDATE +#define DEBUG_TB_INVALIDATE_GATE 1 +#else +#define DEBUG_TB_INVALIDATE_GATE 0 +#endif + #ifdef DEBUG_TB_FLUSH #define DEBUG_TB_FLUSH_GATE 1 #else @@ -1193,9 +1199,9 @@ static inline void tb_alloc_page(TranslationBlock *tb, } mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); -#ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); -#endif + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); + } } #else /* if some code is already present, then the pages are already --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521235890590.8776457506409; Wed, 19 Jul 2017 20:27:15 -0700 (PDT) Received: from localhost ([::1]:35872 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY27N-0001iR-Fn for importer@patchew.org; Wed, 19 Jul 2017 23:27:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60255) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016d-Sj for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qK-0005rl-MR for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:53141) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qK-0005rN-Hv for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:36 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 163F120B60; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:36 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id CB8E27E1FC; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=4RqHB0RIQFkzwFB Dx5XEefWF/+3hmBu3BYpSeaEGKtI=; b=g/ild8y5VU7qrHYNleggKN/ZE/DTKp3 hTdW46Nx2jnjHwpRwm/qy8n44rDF7TS0qysrZ7tFdDM2tn39E71NHZHOXfW38CSj 5PYswUZdmIeoKjl6IV+ZD/oXBiQhUg2FWkC2DyXsIUyMNy8jBnKNS7hhAde0OAyX 60fZj9g5beWU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=4RqHB0RIQFkzwFBDx5XEefWF/+3hmBu3BYpSeaEGKtI=; b=foEBgj1M H4g79FY+WJtXF/VqxNMvvQR55cBapcgKrS8IVnoFlk7AmSihOhszSUPXxElupWrQ y5qfLUDKdlZI5z6uwOKqIxu8vqOu6hcKTCT4f1/SnbTCskhzp55edNkWDPHOhS7l 3e5vuCH55oTPbEFvPe/+AGw+YiTRCj5vu5pEkuBl6x0e1rJVYzGwVUUOjUPJP2Ta gtjcZQs+dlwe++65n/HHXIrnM69naw0me+JYcPN/12McyhNjE1XG2bbaECZ0OXHO vEF3FtOPwqNZmCdpjK2/9+bjn1f2COcMjWqzHyh98B4I8q4m75pCVnUZrYN/W+cF nSrhTUzQgkj4vg== X-ME-Sender: X-Sasl-enc: 92pHy3XXoPaAHlxKKE1ItYbRtUP9JetTkbvaXY2bZn9p 1500520175 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:11 -0400 Message-Id: <1500520169-23367-26-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 25/43] translate-all: define and use DEBUG_TB_CHECK_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This prevents bit rot by ensuring the debug code is compiled when building a user-mode target. Unfortunately the helpers are user-mode-only so we cannot fully get rid of the ifdef checks. Add a comment to explain this. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 962e9b3..845585b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -82,6 +82,12 @@ #undef DEBUG_TB_CHECK #endif =20 +#ifdef DEBUG_TB_CHECK +#define DEBUG_TB_CHECK_GATE 1 +#else +#define DEBUG_TB_CHECK_GATE 0 +#endif + /* Access to the various translations structures need to be serialised via= locks * for consistency. This is automatic for SoftMMU based system * emulation due to its single threaded nature. In user-mode emulation @@ -950,7 +956,13 @@ void tb_flush(CPUState *cpu) } } =20 -#ifdef DEBUG_TB_CHECK +/* + * Formerly ifdef DEBUG_TB_CHECK. These debug functions are user-mode-only, + * so in order to prevent bit rot we compile them unconditionally in user-= mode, + * and let the optimizer get rid of them by wrapping their user-only calle= rs + * with if (DEBUG_TB_CHECK_GATE). + */ +#ifdef CONFIG_USER_ONLY =20 static void do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp) @@ -994,7 +1006,7 @@ static void tb_page_check(void) qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); } =20 -#endif +#endif /* CONFIG_USER_ONLY */ =20 static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock= *tb) { @@ -1238,8 +1250,10 @@ static void tb_link_page(TranslationBlock *tb, tb_pa= ge_addr_t phys_pc, tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 -#ifdef DEBUG_TB_CHECK - tb_page_check(); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_page_check(); + } #endif } =20 @@ -2209,8 +2223,10 @@ int page_unprotect(target_ulong address, uintptr_t p= c) /* and since the content will be modified, we must invalidate the corresponding translated code. */ current_tb_invalidated |=3D tb_invalidate_phys_page(addr, pc); -#ifdef DEBUG_TB_CHECK - tb_invalidate_check(addr); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_invalidate_check(addr); + } #endif } mprotect((void *)g2h(host_start), qemu_host_page_size, --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052124541166.59160785482709; Wed, 19 Jul 2017 20:27:25 -0700 (PDT) Received: from localhost ([::1]:35874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY27X-0001q7-Fi for importer@patchew.org; Wed, 19 Jul 2017 23:27:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qQ-00017h-Vf for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qK-0005rr-Rg for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:37221) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qK-0005rP-Mn for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:36 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 4221E20736; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:36 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 057657E322; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=cDu hyRf2C29bRA4XaIqPL2DT2JpfC6HhMSSU9RSMYmg=; b=kg1qUWmfal3QJJ8nw7z fodNSTPUn7nZ3Sg5WCiBWM7bt96JONTVlp8vXtPiz8ubip0P5/Sb0VkLeKf2zM7m lJPz0ZBJezpUAI1Y9Xri++s0nsoWbbXM6VesxDd+9uk3UHBXF3hBBxbTejatpiZq ybASBoXeIW3B48xrh3qPz1D4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=cDuhyRf2C29bRA4XaIqPL2DT2JpfC6HhMSSU9RSMY mg=; b=eZ6Jk9VgOH3jdUb5uggPxqxfPovYY+0b9f9wu1+L7Z0K6rAwbsyVluaJm 7OdcDDF3KQcG9upEo3ptUUx90en6m2GqTpoboBD/ZeqLVIlytjzkqOo3ElFbQMg9 VvmyWJMxanm82Acj/zfjQBekF5+7keFKdR9hOHEMiMcEGy8YKzSEJ0kzERWr4pqj DHtiArLB+8N+PRr0jXAdMqzUwW3aVOANvAqm30XvFBCChY6yKJV/6WRoPiGql4Ir +w86JWQ2VDC62AyBZHFePsLQCZTCNSDmdFnqxyUxztx0D7fpsOlLcdVCfaDf/P4u oul6m9hbwOMrve/2tDgGrYe8+rBQA== X-ME-Sender: X-Sasl-enc: +6wrNMdVkit+nOoH0P88FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:12 -0400 Message-Id: <1500520169-23367-27-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 26/43] exec-all: extract tb->tc_* into a separate struct tc_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In preparation for adding tc.size to be able to keep track of TB's using the binary search tree implementation from glib. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 20 ++++++++++++++------ accel/tcg/cpu-exec.c | 6 +++--- accel/tcg/translate-all.c | 20 ++++++++++---------- tcg/tcg-runtime.c | 4 ++-- tcg/tcg.c | 4 ++-- 5 files changed, 31 insertions(+), 23 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 00f7da8..bc4f41c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -341,6 +341,14 @@ static inline void tb_invalidate_phys_addr(AddressSpac= e *as, hwaddr addr) #define USE_DIRECT_JUMP #endif =20 +/* + * Translation Cache-related fields of a TB. + */ +struct tb_tc { + void *ptr; /* pointer to the translated code */ + uint8_t *search; /* pointer to search data */ +}; + struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -362,8 +370,8 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - void *tc_ptr; /* pointer to the translated code */ - uint8_t *tc_search; /* pointer to search data */ + struct tb_tc tc; + /* original tb when cflags has CF_NOCACHE */ struct TranslationBlock *orig_tb; /* first and second physical page containing code. The lower bit @@ -462,7 +470,7 @@ static inline void tb_set_jmp_target(TranslationBlock *= tb, int n, uintptr_t addr) { uint16_t offset =3D tb->jmp_insn_offset[n]; - tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); + tb_set_jmp_target1((uintptr_t)(tb->tc.ptr + offset), addr); } =20 #else @@ -489,11 +497,11 @@ static inline void tb_add_jump(TranslationBlock *tb, = int n, qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); + tb->tc.ptr, tb->pc, n, + tb_next->tc.ptr, tb_next->pc); =20 /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); =20 /* add in TB jmp circular list */ tb->jmp_list_next[n] =3D tb_next->jmp_list_first; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 526cab3..cb1e6d3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -143,11 +143,11 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *= cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr =3D itb->tc_ptr; + uint8_t *tb_ptr =3D itb->tc.ptr; =20 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %p [%d: " TARGET_FMT_lx "] %s\n", - itb->tc_ptr, cpu->cpu_index, itb->pc, + itb->tc.ptr, cpu->cpu_index, itb->pc, lookup_symbol(itb->pc)); =20 #if defined(DEBUG_DISAS) @@ -179,7 +179,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc_ptr, last_tb->pc, + last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); if (cc->synchronize_from_tb) { cc->synchronize_from_tb(cpu, last_tb); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 845585b..0a2eb86 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -260,7 +260,7 @@ static target_long decode_sleb128(uint8_t **pp) which comes from the host pc of the end of the code implementing the in= sn. =20 Each line of the table is encoded as sleb128 deltas from the previous - line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }. + line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. That is, the first column is seeded with the guest pc, the last column with the host pc, and the middle columns with zeros. */ =20 @@ -270,7 +270,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) uint8_t *p =3D block; int i, j, n; =20 - tb->tc_search =3D block; + tb->tc.search =3D block; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { target_ulong prev; @@ -305,9 +305,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uintptr_t searched_pc) { target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; - uintptr_t host_pc =3D (uintptr_t)tb->tc_ptr; + uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; - uint8_t *p =3D tb->tc_search; + uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER int64_t ti =3D profile_getclock(); @@ -858,7 +858,7 @@ void tb_free(TranslationBlock *tb) tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); =20 - tcg_ctx.code_gen_ptr =3D tb->tc_ptr - struct_size; + tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; tcg_ctx.tb_ctx.nb_tbs--; } } @@ -1059,7 +1059,7 @@ static inline void tb_remove_from_jmp_list(Translatio= nBlock *tb, int n) another TB */ static inline void tb_reset_jump(TranslationBlock *tb, int n) { - uintptr_t addr =3D (uintptr_t)(tb->tc_ptr + tb->jmp_reset_offset[n]); + uintptr_t addr =3D (uintptr_t)(tb->tc.ptr + tb->jmp_reset_offset[n]); tb_set_jmp_target(tb, n, addr); } =20 @@ -1290,7 +1290,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 gen_code_buf =3D tcg_ctx.code_gen_ptr; - tb->tc_ptr =3D gen_code_buf; + tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; @@ -1310,7 +1310,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_intermediate_code(env, tb); tcg_ctx.cpu =3D NULL; =20 - trace_translate_block(tb, tb->pc, tb->tc_ptr); + trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1356,7 +1356,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(tb->pc)) { qemu_log_lock(); qemu_log("OUT: [size=3D%d]\n", gen_code_size); - log_disas(tb->tc_ptr, gen_code_size); + log_disas(tb->tc.ptr, gen_code_size); qemu_log("\n"); qemu_log_flush(); qemu_log_unlock(); @@ -1684,7 +1684,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) while (m_min <=3D m_max) { m =3D (m_min + m_max) >> 1; tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc_ptr; + v =3D (uintptr_t)tb->tc.ptr; if (v =3D=3D tc_ptr) { return tb; } else if (tc_ptr < v) { diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 4f873a9..9a87616 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -157,9 +157,9 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, pc, + tb->tc.ptr, cpu->cpu_index, pc, lookup_symbol(pc)); - return tb->tc_ptr; + return tb->tc.ptr; } =20 void HELPER(exit_atomic)(CPUArchState *env) diff --git a/tcg/tcg.c b/tcg/tcg.c index 3559829..28c1b94 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2616,8 +2616,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 tcg_reg_alloc_start(s); =20 - s->code_buf =3D tb->tc_ptr; - s->code_ptr =3D tb->tc_ptr; + s->code_buf =3D tb->tc.ptr; + s->code_ptr =3D tb->tc.ptr; =20 tcg_out_tb_init(s); =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500522076276125.37292331441927; Wed, 19 Jul 2017 20:41:16 -0700 (PDT) Received: from localhost ([::1]:35936 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2Kw-0003yE-30 for importer@patchew.org; Wed, 19 Jul 2017 23:41:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qS-00019G-Gk for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qK-0005s5-Vp for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:41703) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qK-0005rd-Rr for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:36 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7B52320B69; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:36 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 3367C241E0; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=kLB 9ic3LCU35nbsMj2dOeb157T++vqJOKagl1w+J2Iw=; b=bGoawOmP7IhbIsTlqfJ yhIt4C3taEGLicRNWDgbrmPYfR91NPDyUnpE4IBI6MTNrP2i8tJpF3Y63lHEqwEf s5HiQ22RdLvSevjmTRUKiw527mBS2cpyN3R/BzTXCaIAfW7sza3fKUWgbxiqgTMm wH8G4LzRx0X6yzLoVFaf4eGM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=kLB9ic3LCU35nbsMj2dOeb157T++vqJOKagl1w+J2 Iw=; b=Rp143co5sHbo4AtO31gJQwve8Au5Y7+W1JL2Ab9AlCpBKJRFThyYzaR6c +a32sJA4y4EXuKdOsKuGMjeFBb6XGNtROYXX5I+Fb6aFTYBMTyf1NbnFqSwlGNsr U2QkexiYFPiT1+4e0Poz0HH0c0wWPklsKVz0rXho/IYiDsgaak1dFxHCN0q4Zi7+ IfI0mR0QR/rfdOxr11rbOGw+k9h6s7xaIpcHlS4j+sKzVHi+zTuqU7c7l6CPI9HI mvi4zYPBYjhDcEinKKeY3SKjv5V+RMDYnnOG9YHyh25Yl27p12ajbNCs/wF8TU2I ijyPILQuaibRZHZimpwYLArmu5ADg== X-ME-Sender: X-Sasl-enc: +6whNc5PhzBrmvkX0eg8FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:13 -0400 Message-Id: <1500520169-23367-28-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 27/43] translate-all: use a binary search tree to track TBs in TBContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a prerequisite for supporting multiple TCG contexts, since we will have threads generating code in separate regions of code_gen_buffer. For this we need a new field (.size) in struct tb_tc to keep track of the size of the translated code. This field uses a size_t to avoid adding a hole to the struct, although really an unsigned int would have been enough. The comparison function we use is optimized for the common case: insertions. Profiling shows that upon booting debian-arm, 98% of comparisons are between existing tb's (i.e. a->size and b->size are both !0), which happens during insertions (and removals, but those are rare). The remaining cases are lookups. From reading the glib sources we see that the first key is always the lookup key. However, the code does not assume this to always be the case because this behaviour is not guaranteed in the glib docs. However, we embed this knowledge in the code as a branch hint for the compiler. Note that tb_free does not free space in the code_gen_buffer anymore, since we cannot easily know whether the tb is the last one inserted in code_gen_buffer. The next patch in this series renames tb_free to tb_remove to reflect this. Performance-wise, lookups in tb_find_pc are the same as before: O(log n). However, insertions are O(log n) instead of O(1), which results in a small slowdown when booting debian-arm: Performance counter stats for 'build/arm-softmmu/qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Dimg/arm/jessie-arm32.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel img/arm/aarch32-current-linux-kernel-only.img \ -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): - Before: 8048.598422 task-clock (msec) # 0.931 CPUs utilized = ( +- 0.28% ) 16,974 context-switches # 0.002 M/sec = ( +- 0.12% ) 0 cpu-migrations # 0.000 K/sec 10,125 page-faults # 0.001 M/sec = ( +- 1.23% ) 35,144,901,879 cycles # 4.367 GHz = ( +- 0.14% ) stalled-cycles-frontend stalled-cycles-backend 65,758,252,643 instructions # 1.87 insns per cycl= e ( +- 0.33% ) 10,871,298,668 branches # 1350.707 M/sec = ( +- 0.41% ) 192,322,212 branch-misses # 1.77% of all branche= s ( +- 0.32% ) 8.640869419 seconds time elapsed = ( +- 0.57% ) - After: 8146.242027 task-clock (msec) # 0.923 CPUs utilized = ( +- 1.23% ) 17,016 context-switches # 0.002 M/sec = ( +- 0.40% ) 0 cpu-migrations # 0.000 K/sec 18,769 page-faults # 0.002 M/sec = ( +- 0.45% ) 35,660,956,120 cycles # 4.378 GHz = ( +- 1.22% ) stalled-cycles-frontend stalled-cycles-backend 65,095,366,607 instructions # 1.83 insns per cycl= e ( +- 1.73% ) 10,803,480,261 branches # 1326.192 M/sec = ( +- 1.95% ) 195,601,289 branch-misses # 1.81% of all branche= s ( +- 0.39% ) 8.828660235 seconds time elapsed = ( +- 0.38% ) Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 5 ++ include/exec/tb-context.h | 4 +- accel/tcg/translate-all.c | 217 ++++++++++++++++++++++++------------------= ---- 3 files changed, 118 insertions(+), 108 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bc4f41c..eb3eb7b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -343,10 +343,15 @@ static inline void tb_invalidate_phys_addr(AddressSpa= ce *as, hwaddr addr) =20 /* * Translation Cache-related fields of a TB. + * This struct exists just for convenience; we keep track of TB's in a bin= ary + * search tree, and the only fields needed to compare TB's in the tree are + * @ptr and @size. @search is brought here for consistency, since it is al= so + * a TC-related field. */ struct tb_tc { void *ptr; /* pointer to the translated code */ uint8_t *search; /* pointer to search data */ + size_t size; }; =20 struct TranslationBlock { diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index 25c2afe..1fa8dcc 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -31,10 +31,8 @@ typedef struct TBContext TBContext; =20 struct TBContext { =20 - TranslationBlock **tbs; + GTree *tb_tree; struct qht htable; - size_t tbs_size; - int nb_tbs; /* any access to the tbs or the page table must use this lock */ QemuMutex tb_lock; =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 0a2eb86..cb71aef 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -776,6 +776,48 @@ static inline void *alloc_code_gen_buffer(void) } #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ =20 +/* compare a pointer @ptr and a tb_tc @s */ +static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) +{ + if (ptr >=3D s->ptr + s->size) { + return 1; + } else if (ptr < s->ptr) { + return -1; + } + return 0; +} + +static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) +{ + const struct tb_tc *a =3D ap; + const struct tb_tc *b =3D bp; + + /* + * When both sizes are set, we know this isn't a lookup and therefore + * the two buffers are non-overlapping. + * This is the most likely case: every TB must be inserted; lookups + * are a lot less frequent. + */ + if (likely(a->size && b->size)) { + /* a->ptr =3D=3D b->ptr would mean the buffers overlap */ + g_assert(a->ptr !=3D b->ptr); + + if (a->ptr > b->ptr) { + return 1; + } + return -1; + } + /* + * All lookups have either .size field set to 0. + * From the glib sources we see that @ap is always the lookup key. How= ever + * the docs provide no guarantee, so we just mark this case as likely. + */ + if (likely(a->size =3D=3D 0)) { + return ptr_cmp_tb_tc(a->ptr, b); + } + return ptr_cmp_tb_tc(b->ptr, a); +} + static inline void code_gen_alloc(size_t tb_size) { tcg_ctx.code_gen_buffer_size =3D size_code_gen_buffer(tb_size); @@ -784,15 +826,7 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } - - /* size this conservatively -- realloc later if needed */ - tcg_ctx.tb_ctx.tbs_size =3D - tcg_ctx.code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE / 8; - if (unlikely(!tcg_ctx.tb_ctx.tbs_size)) { - tcg_ctx.tb_ctx.tbs_size =3D 64 * 1024; - } - tcg_ctx.tb_ctx.tbs =3D g_new(TranslationBlock *, tcg_ctx.tb_ctx.tbs_si= ze); - + tcg_ctx.tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); } =20 @@ -829,7 +863,6 @@ void tcg_exec_init(unsigned long tb_size) static TranslationBlock *tb_alloc(target_ulong pc) { TranslationBlock *tb; - TBContext *ctx; =20 assert_tb_locked(); =20 @@ -837,12 +870,6 @@ static TranslationBlock *tb_alloc(target_ulong pc) if (unlikely(tb =3D=3D NULL)) { return NULL; } - ctx =3D &tcg_ctx.tb_ctx; - if (unlikely(ctx->nb_tbs =3D=3D ctx->tbs_size)) { - ctx->tbs_size *=3D 2; - ctx->tbs =3D g_renew(TranslationBlock *, ctx->tbs, ctx->tbs_size); - } - ctx->tbs[ctx->nb_tbs++] =3D tb; return tb; } =20 @@ -851,16 +878,7 @@ void tb_free(TranslationBlock *tb) { assert_tb_locked(); =20 - /* In practice this is mostly used for single use temporary TB - Ignore the hard cases and just back up if this TB happens to - be the last one generated. */ - if (tcg_ctx.tb_ctx.nb_tbs > 0 && - tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { - size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); - - tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; - tcg_ctx.tb_ctx.nb_tbs--; - } + g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc); } =20 static inline void invalidate_page_bitmap(PageDesc *p) @@ -918,11 +936,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) } =20 if (DEBUG_TB_FLUSH_GATE) { - printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / - tcg_ctx.tb_ctx.nb_tbs : 0); + size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + + printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%td= \n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs := 0); } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { @@ -933,7 +952,10 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data= tb_flush_count) cpu_tb_jmp_cache_clear(cpu); } =20 - tcg_ctx.tb_ctx.nb_tbs =3D 0; + /* Increment the refcount first so that destroy acts as a reset */ + g_tree_ref(tcg_ctx.tb_ctx.tb_tree); + g_tree_destroy(tcg_ctx.tb_ctx.tb_tree); + qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 @@ -1343,6 +1365,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (unlikely(search_size < 0)) { goto buffer_overflow; } + tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER tcg_ctx.code_time +=3D profile_getclock() - ti; @@ -1393,6 +1416,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * through the physical hash table and physical page list. */ tb_link_page(tb, phys_pc, phys_page2); + g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb); return tb; } =20 @@ -1663,37 +1687,16 @@ static bool tb_invalidate_phys_page(tb_page_addr_t = addr, uintptr_t pc) } #endif =20 -/* find the TB 'tb' such that tb[0].tc_ptr <=3D tc_ptr < - tb[1].tc_ptr. Return NULL if not found */ +/* + * Find the TB 'tb' such that + * tb->tc.ptr <=3D tc_ptr < tb->tc.ptr + tb->tc.size + * Return NULL if not found. + */ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) { - int m_min, m_max, m; - uintptr_t v; - TranslationBlock *tb; + struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 - if (tcg_ctx.tb_ctx.nb_tbs <=3D 0) { - return NULL; - } - if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || - tc_ptr >=3D (uintptr_t)tcg_ctx.code_gen_ptr) { - return NULL; - } - /* binary search (cf Knuth) */ - m_min =3D 0; - m_max =3D tcg_ctx.tb_ctx.nb_tbs - 1; - while (m_min <=3D m_max) { - m =3D (m_min + m_max) >> 1; - tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc.ptr; - if (v =3D=3D tc_ptr) { - return tb; - } else if (tc_ptr < v) { - m_max =3D m - 1; - } else { - m_min =3D m + 1; - } - } - return tcg_ctx.tb_ctx.tbs[m_max]; + return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1879,63 +1882,67 @@ static void print_qht_statistics(FILE *f, fprintf_f= unction cpu_fprintf, g_free(hgram); } =20 +struct tb_tree_stats { + size_t target_size; + size_t max_target_size; + size_t direct_jmp_count; + size_t direct_jmp2_count; + size_t cross_page; +}; + +static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer = data) +{ + const TranslationBlock *tb =3D value; + struct tb_tree_stats *tst =3D data; + + tst->target_size +=3D tb->size; + if (tb->size > tst->max_target_size) { + tst->max_target_size =3D tb->size; + } + if (tb->page_addr[1] !=3D -1) { + tst->cross_page++; + } + if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { + tst->direct_jmp_count++; + if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { + tst->direct_jmp2_count++; + } + } + return false; +} + void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) { - int i, target_code_size, max_target_code_size; - int direct_jmp_count, direct_jmp2_count, cross_page; - TranslationBlock *tb; + struct tb_tree_stats tst =3D {}; struct qht_stats hst; + size_t nb_tbs; =20 tb_lock(); =20 - target_code_size =3D 0; - max_target_code_size =3D 0; - cross_page =3D 0; - direct_jmp_count =3D 0; - direct_jmp2_count =3D 0; - for (i =3D 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) { - tb =3D tcg_ctx.tb_ctx.tbs[i]; - target_code_size +=3D tb->size; - if (tb->size > max_target_code_size) { - max_target_code_size =3D tb->size; - } - if (tb->page_addr[1] !=3D -1) { - cross_page++; - } - if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { - direct_jmp_count++; - if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { - direct_jmp2_count++; - } - } - } + nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); cpu_fprintf(f, "gen code size %td/%zd\n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); - cpu_fprintf(f, "TB count %d\n", tcg_ctx.tb_ctx.nb_tbs); - cpu_fprintf(f, "TB avg target size %d max=3D%d bytes\n", - tcg_ctx.tb_ctx.nb_tbs ? target_code_size / - tcg_ctx.tb_ctx.nb_tbs : 0, - max_target_code_size); + cpu_fprintf(f, "TB count %zu\n", nb_tbs); + cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", + nb_tbs ? tst.target_size / nb_tbs : 0, + tst.max_target_size); cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)= \n", - tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - tcg_ctx.tb_ctx.nb_tbs : 0, - target_code_size ? (double) (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - target_code_size : 0); - cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page, - tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0); - cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=3D%d %d%%)\n", - direct_jmp_count, - tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0, - direct_jmp2_count, - tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0); + nb_tbs ? (tcg_ctx.code_gen_ptr - + tcg_ctx.code_gen_buffer) / nb_tbs : 0, + tst.target_size ? (double) (tcg_ctx.code_gen_ptr - + tcg_ctx.code_gen_buffer) / + tst.target_size : 0); + cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, + nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); + cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=3D%zu %zu%%)\= n", + tst.direct_jmp_count, + nb_tbs ? (tst.direct_jmp_count * 100) / nb_tbs : 0, + tst.direct_jmp2_count, + nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); =20 qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst); print_qht_statistics(f, cpu_fprintf, hst); --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521083541905.1302134576986; Wed, 19 Jul 2017 20:24:43 -0700 (PDT) Received: from localhost ([::1]:35858 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY24v-0007TQ-OR for importer@patchew.org; Wed, 19 Jul 2017 23:24:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60262) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qP-00016l-5z for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qL-0005sI-5L for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:41 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:55933) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005rv-1g for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:37 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 9E9F320B61; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:36 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 654FD7E057; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Lx575OXlm/fnh8I 8yvFhoOvFJdD+y31o6+ltKwk9yiI=; b=RCT5IUEAw0lhS+OLRp7ul+1glwyDu0f 3o+U25gsanzWvPH3lW7buDFVdY/80uHsZcepqROpojFObzkZlsA0f9i9C/7VfUUD FT8xJkBjKhnJqHlMco4sEBe5ffVkItCA51yRPWbXgV0LarTnW2thQq4NXLbFuYSO aKrOsVy8rVIs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=Lx575OXlm/fnh8I8yvFhoOvFJdD+y31o6+ltKwk9yiI=; b=qQt/hfmz epZAfauCYTnRNjrOgV2YIWlQ9Nmyg+lNhit5jsxhn6HZ6p2fSVch3X8T3QtrJRk3 ixuvuubySbN4SU6+Q9Ak4XTVFAKmet8PxPA+z7uptTUySXvK/pwx1/Y5SMPUlqxO 9Qi84d1Ny2yI59nfmrOtoxzdyCyM8C3/fcYDKabn8nsv6UekStDOl1PVcP9XtYy2 xjLkBM9jzpwwHaW1Yjv++aHXQJ6MyIu9lqJONCCMHg+5C5qvXJA5RMOUGZfF4bVM wii5x+2LHk2sikMZMm9NtW5o+ARi+B9C4z79xsVyUCzyGpH+5yxE042gOxRq2Nni 1j/u1vMT59HCDg== X-ME-Sender: X-Sasl-enc: +6whNcFRnipuhewT1/48FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:14 -0400 Message-Id: <1500520169-23367-29-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 28/43] exec-all: rename tb_free to tb_remove X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 We don't really free anything in this function anymore; we just remove the TB from the binary search tree. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 2 +- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index eb3eb7b..7bc2050 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -428,7 +428,7 @@ static inline uint32_t curr_cflags(void) return parallel_cpus ? CF_PARALLEL : 0; } =20 -void tb_free(TranslationBlock *tb); +void tb_remove(TranslationBlock *tb); void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index cb1e6d3..1963bda 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -218,7 +218,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, =20 tb_lock(); tb_phys_invalidate(tb, -1); - tb_free(tb); + tb_remove(tb); tb_unlock(); } #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index cb71aef..448f13b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -375,7 +375,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) if (tb->cflags & CF_NOCACHE) { /* one-shot translation, invalidate it immediately */ tb_phys_invalidate(tb, -1); - tb_free(tb); + tb_remove(tb); } r =3D true; } @@ -874,7 +874,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) } =20 /* Called with tb_lock held. */ -void tb_free(TranslationBlock *tb) +void tb_remove(TranslationBlock *tb) { assert_tb_locked(); =20 @@ -1809,7 +1809,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) * cpu_exec_nocache() */ tb_phys_invalidate(tb->orig_tb, -1); } - tb_free(tb); + tb_remove(tb); } /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521087289998.9236799652398; Wed, 19 Jul 2017 20:24:47 -0700 (PDT) Received: from localhost ([::1]:35859 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY24z-0007X1-FY for importer@patchew.org; Wed, 19 Jul 2017 23:24:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016f-W0 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qL-0005sQ-8I for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:58453) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005s0-4A for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:37 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D552320B70; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:36 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 924712418A; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=h0j esI9EXfdHBGQKifX+geAWFe2KvS2L1dv8WILYAew=; b=scTwUIGmHdNuMwFi/hv 7EYQB5/lkbPrCdw3YuwbPGQw/AAlNKy6K/+OnPyeVVWZAcOc2bDa9msbn4gqBQru adcc19h260U+TsPdh3LC17Nw2KdnVCfE/ORvpN0soXZ9AxtfZab9AqUSsDMTxYYE SEtiKr/yY6tv4KRjdJoms0QI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=h0jesI9EXfdHBGQKifX+geAWFe2KvS2L1dv8WILYA ew=; b=Xc7W2dar3VSpFNqs2Oq2WXuQ1DqTvur0neZ6d5vBeBdGhW70RUTsI2BQK qzd74HuqUKGvesen9nlGla6KzpfeJ73QJlEULxCMsEa1RZf0qC3WMIhqUZzXdSA9 5+RddlrmvbzI1B52AD5McZWq5C9Q5urwEQPLmq2rWiytnd+3W20X0TU0WNRK+ZgA NI39+NtYE8aUD8qONDaAVwlw0VSGeugfhKnFc2m835bOlCDdYU4L18WW3vkwawh4 ZqBl7OUcJ5kyy6FwWZnvlJQ4zvOvaDuIWe5jNV+wE+Bshg9nul4cNYaT/EDWYm79 ziFzdmWe1eT+7rP1kYETwOcKhReBg== X-ME-Sender: X-Sasl-enc: +6w1MM1dgjVqneMazOU8FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:15 -0400 Message-Id: <1500520169-23367-30-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 29/43] translate-all: report correct avg host TB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the corresponding translated code") we are not fully utilizing code_gen_buffer for translated code, and therefore are incorrectly reporting the amount of translated code as well as the average host TB size. Address this by: - Making the conscious choice of misreporting the total translated code; doing otherwise would mislead users into thinking "-tb-size" is not honoured. - Expanding tb_tree_stats to accurately count the bytes of translated code = on the host, and using this for reporting the average tb host size, as well as the expansion ratio. In the future we might want to consider reporting the accurate numbers for the total translated code, together with a "bookkeeping/overhead" field to account for the TB structs. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 448f13b..d50e2b9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -923,6 +923,15 @@ static void page_flush_tb(void) } } =20 +static gboolean tb_host_size_iter(gpointer key, gpointer value, gpointer d= ata) +{ + const TranslationBlock *tb =3D value; + size_t *size =3D data; + + *size +=3D tb->tc.size; + return false; +} + /* flush all the translation blocks */ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) { @@ -937,11 +946,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) =20 if (DEBUG_TB_FLUSH_GATE) { size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + size_t host_size =3D 0; =20 - printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%td= \n", + g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_si= ze); + printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, - nb_tbs > 0 ? - (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs := 0); + nb_tbs > 0 ? host_size / nb_tbs : 0); } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { @@ -1883,6 +1893,7 @@ static void print_qht_statistics(FILE *f, fprintf_fun= ction cpu_fprintf, } =20 struct tb_tree_stats { + size_t host_size; size_t target_size; size_t max_target_size; size_t direct_jmp_count; @@ -1895,6 +1906,7 @@ static gboolean tb_tree_stats_iter(gpointer key, gpoi= nter value, gpointer data) const TranslationBlock *tb =3D value; struct tb_tree_stats *tst =3D data; =20 + tst->host_size +=3D tb->tc.size; tst->target_size +=3D tb->size; if (tb->size > tst->max_target_size) { tst->max_target_size =3D tb->size; @@ -1923,6 +1935,11 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); + /* + * Report total code size including the padding and TB structs; + * otherwise users might think "-tb-size" is not honoured. + * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. + */ cpu_fprintf(f, "gen code size %td/%zd\n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); @@ -1930,12 +1947,9 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, tst.max_target_size); - cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)= \n", - nb_tbs ? (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / nb_tbs : 0, - tst.target_size ? (double) (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - tst.target_size : 0); + cpu_fprintf(f, "TB avg host size %zu bytes (expansion ratio: %0.1f)= \n", + nb_tbs ? tst.host_size / nb_tbs : 0, + tst.target_size ? (double)tst.host_size / tst.target_size = : 0); cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=3D%zu %zu%%)\= n", --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052189401218.78084065041446; Wed, 19 Jul 2017 20:38:14 -0700 (PDT) Received: from localhost ([::1]:35923 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2Hw-0001pA-Ds for importer@patchew.org; Wed, 19 Jul 2017 23:38:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qV-0001Cd-Dr for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qL-0005sj-Go for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:41471) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005sC-8y for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:37 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1023720B6D; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:37 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C0B3A7E266; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=bf7 Z4MUhRjmjfX4o8iIuhspuVYXF0DESLS23Gn0zuOg=; b=O0upYlTePV0nSGQJ8mB 1IHfj5iM8i0sxM0/zJOW6lQovtauwDfSqFIAMINfvJOWJtuW5MxMOourLEm+6hHY KGpO11HPDkJ3qw9Le4AvfXkE2iM4ARAXknnKfrVuYtxzoCByFgianuwbSHSEr7p9 H+oAx0/yZb1Wqzx071SnDX+s= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=bf7Z4MUhRjmjfX4o8iIuhspuVYXF0DESLS23Gn0zu Og=; b=j03aV5VVNrBxNjzjVnxSLmklt8Pw9Vf24Ows87DXN3EFVJze2jf1N6/wj p/X6L1hklf1ptAvBPcJYmWSwcVy/xVajiR34/Nbl4/vOtcVJqi+dSzJv9TMc4d74 fS+NxelqgOW0DO6vXw7KY2PU4i9J8WecqWu8z+zzIyplK3DQQJNJ7L5B8mHbHvCI 9jOj/FjVrTsUQJpXkCsucNiQ7Yp3Kk4dlZhm2foK/ycZlS1c4JNeWH5Gn5vZ3rp9 Y8uBDiiaKbmzVccmj9pv/91vo12zW/Xt7Xl92Il5/q6M6nMuRD0JDezGwC4VYQ0D kFw4LhRjsngv2C6TuRliw8M6onOpA== X-ME-Sender: X-Sasl-enc: +6w/Os5Kgj1okukc0uk8FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:16 -0400 Message-Id: <1500520169-23367-31-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 30/43] tci: move tci_regs to tcg_qemu_tb_exec's stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Acked-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tci.c | 552 +++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 279 insertions(+), 273 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 4bdc645..f3216c1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -55,93 +55,95 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, t= cg_target_ulong, tcg_target_ulong); #endif =20 -static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; - -static tcg_target_ulong tci_read_reg(TCGReg index) +static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) { - tci_assert(index < ARRAY_SIZE(tci_reg)); - return tci_reg[index]; + tci_assert(index < TCG_TARGET_NB_REGS); + return regs[index]; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGReg index) +static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) { - return (int8_t)tci_read_reg(index); + return (int8_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGReg index) +static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { - return (int16_t)tci_read_reg(index); + return (int16_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(TCGReg index) +static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { - return (int32_t)tci_read_reg(index); + return (int32_t)tci_read_reg(regs, index); } #endif =20 -static uint8_t tci_read_reg8(TCGReg index) +static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) { - return (uint8_t)tci_read_reg(index); + return (uint8_t)tci_read_reg(regs, index); } =20 -static uint16_t tci_read_reg16(TCGReg index) +static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { - return (uint16_t)tci_read_reg(index); + return (uint16_t)tci_read_reg(regs, index); } =20 -static uint32_t tci_read_reg32(TCGReg index) +static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { - return (uint32_t)tci_read_reg(index); + return (uint32_t)tci_read_reg(regs, index); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(TCGReg index) +static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { - return tci_read_reg(index); + return tci_read_reg(regs, index); } #endif =20 -static void tci_write_reg(TCGReg index, tcg_target_ulong value) +static void +tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { - tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < TCG_TARGET_NB_REGS); tci_assert(index !=3D TCG_AREG0); tci_assert(index !=3D TCG_REG_CALL_STACK); - tci_reg[index] =3D value; + regs[index] =3D value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg32s(TCGReg index, int32_t value) +static void +tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 -static void tci_write_reg8(TCGReg index, uint8_t value) +static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 -static void tci_write_reg32(TCGReg index, uint32_t value) +static void +tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_write_reg64(uint32_t high_index, uint32_t low_index, - uint64_t value) +static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, + uint32_t low_index, uint64_t value) { - tci_write_reg(low_index, value); - tci_write_reg(high_index, value >> 32); + tci_write_reg(regs, low_index, value); + tci_write_reg(regs, high_index, value >> 32); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg64(TCGReg index, uint64_t value) +static void +tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 @@ -188,94 +190,97 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) #endif =20 /* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong tci_read_r(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - tcg_target_ulong value =3D tci_read_reg(**tb_ptr); + tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint8_t value =3D tci_read_reg8(**tb_ptr); + uint8_t value =3D tci_read_reg8(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int8_t value =3D tci_read_reg8s(**tb_ptr); + int8_t value =3D tci_read_reg8s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint16_t value =3D tci_read_reg16(**tb_ptr); + uint16_t value =3D tci_read_reg16(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int16_t value =3D tci_read_reg16s(**tb_ptr); + int16_t value =3D tci_read_reg16s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t value =3D tci_read_reg32(**tb_ptr); + uint32_t value =3D tci_read_reg32(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t low =3D tci_read_r32(tb_ptr); - return tci_uint64(tci_read_r32(tb_ptr), low); + uint32_t low =3D tci_read_r32(regs, tb_ptr); + return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int32_t value =3D tci_read_reg32s(**tb_ptr); + int32_t value =3D tci_read_reg32s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint64_t value =3D tci_read_reg64(**tb_ptr); + uint64_t value =3D tci_read_reg64(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register(s) with target address from bytecode. */ -static target_ulong tci_read_ulong(uint8_t **tb_ptr) +static target_ulong +tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(tb_ptr); + target_ulong taddr =3D tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; #endif return taddr; } =20 /* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r =3D **tb_ptr; @@ -283,13 +288,13 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i(tb_ptr); } else { - value =3D tci_read_reg(r); + value =3D tci_read_reg(regs, r); } return value; } =20 /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint32_t value; TCGReg r =3D **tb_ptr; @@ -297,21 +302,21 @@ static uint32_t tci_read_ri32(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i32(tb_ptr); } else { - value =3D tci_read_reg32(r); + value =3D tci_read_reg32(regs, r); } return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { - uint32_t low =3D tci_read_ri32(tb_ptr); - return tci_uint64(tci_read_ri32(tb_ptr), low); + uint32_t low =3D tci_read_ri32(regs, tb_ptr); + return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint64_t value; TCGReg r =3D **tb_ptr; @@ -319,7 +324,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i64(tb_ptr); } else { - value =3D tci_read_reg64(r); + value =3D tci_read_reg64(regs, r); } return value; } @@ -465,12 +470,13 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t ret =3D 0; =20 - tci_reg[TCG_AREG0] =3D (tcg_target_ulong)env; - tci_reg[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] =3D sp_value; tci_assert(tb_ptr); =20 for (;;) { @@ -503,27 +509,27 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_ri(&tb_ptr); + t0 =3D tci_read_ri(regs, &tb_ptr); #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5), - tci_read_reg(TCG_REG_R6), - tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8), - tci_read_reg(TCG_REG_R9), - tci_read_reg(TCG_REG_R10)); - tci_write_reg(TCG_REG_R0, tmp64); - tci_write_reg(TCG_REG_R1, tmp64 >> 32); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10)); + tci_write_reg(regs, TCG_REG_R0, tmp64); + tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5)); - tci_write_reg(TCG_REG_R0, tmp64); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5)); + tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; case INDEX_op_br: @@ -533,46 +539,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare32(t1, t2, condition)); + tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare64(tmp64, v64, condition)); + tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)= ); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg64(t0, tci_compare64(t1, t2, condition)); + tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; case INDEX_op_movi_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg32(t0, t1); + tci_write_reg32(regs, t0, t1); break; =20 /* Load/store operations (32 bit). */ =20 case INDEX_op_ld8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -583,25 +589,25 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i32: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) =3D t0; @@ -611,46 +617,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 + t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 - t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 * t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 / t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 % t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -660,71 +666,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 & t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 | t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 ^ t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 << (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 >> (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, rol32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ror32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_r32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp= 32)); break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_ri32(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -737,20 +743,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_add2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 +=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 +=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_sub2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 -=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 -=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -762,86 +768,86 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(&tb_ptr); - tmp64 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t1, t0, t2 * tmp64); + t2 =3D tci_read_r32(regs, &tb_ptr); + tmp64 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, ~t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, -t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; case INDEX_op_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg64(t0, t1); + tci_write_reg64(regs, t0, t1); break; =20 /* Load/store operations (64 bit). */ =20 case INDEX_op_ld8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -850,43 +856,43 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld32u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32s(t0, *(int32_t *)(t1 + t2)); + tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg64(t0, *(uint64_t *)(t1 + t2)); + tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i64: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st32_i64: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) =3D t0; @@ -896,21 +902,21 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 + t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 - t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 * t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -927,71 +933,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 & t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 | t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 ^ t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 << (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 >> (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, rol64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ror64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_r64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp= 64)); break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_ri64(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -1003,29 +1009,29 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1033,51 +1039,51 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: TODO(); t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, bswap64(t1)); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, ~t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, -t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ @@ -1098,7 +1104,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1128,14 +1134,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp32); + tci_write_reg(regs, t0, tmp32); break; case INDEX_op_qemu_ld_i64: t0 =3D *tb_ptr++; if (TCG_TARGET_REG_BITS =3D=3D 32) { t1 =3D *tb_ptr++; } - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1177,14 +1183,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp64); + tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(t1, tmp64 >> 32); + tci_write_reg(regs, t1, tmp64 >> 32); } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: @@ -1207,8 +1213,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) } break; case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521395872260.2985533237795; Wed, 19 Jul 2017 20:29:55 -0700 (PDT) Received: from localhost ([::1]:35882 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY29y-00040Q-0g for importer@patchew.org; Wed, 19 Jul 2017 23:29:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60338) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qR-000186-FC for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qL-0005t2-Jx for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:43 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:34021) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005sU-FV for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:37 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 4077B20B73; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:37 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id EBE61241E0; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=rPN6zwcmWaSZ80L fmrAWy/Bye+rsRnwRzNP0I/knPmU=; b=W+FNVLwqB77Q5Nrow5ureiXx/lDBF6A C0AI67lH/weNoBMplj85adGawUKo+e6X0T7KTV3BABcZ7yuzOmcwHq3c4P4qLp/F RPPCC6Lxog1Hid46uRRBwQRrq+RfBP1Li/iTCrqE2XRTK5O1/4Jbj7K88ayP9HNN tN3PScniNHdY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=rPN6zwcmWaSZ80LfmrAWy/Bye+rsRnwRzNP0I/knPmU=; b=hS0OZLep nA1C0ZnB+bIvM4l4lXewxJkfIs+kmExA04YqRwN6RT/iOqcbaLKVw0yhsG88nI4d XvsLFMNvS8m5IIqrRG7DfSfoYfCkDdo82dhzRqMNhKmaaCjCUR+xgv4OuVKb7TkS Y6NmZuQf4Z48iBJEuglH1axH1x+BtaX7aLxGE8f5A4WHQZkwXdrshJWgGYi923BR 7AGPxQMopMc0Umbqbt4gvxKorhooA3dTomGz8kCLzXRG9JVoaNCrLr69X5ezIuXN dM6dyF+XXjxdXhOsge41jBbnHYiNJvSug1rIxp7IvvkRAQG79wybgK4h15JAYo55 Kx5YYp/WnqjSCQ== X-ME-Sender: X-Sasl-enc: +6whNcxPnyZ+i+ca1ek8FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:17 -0400 Message-Id: <1500520169-23367-32-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 31/43] tcg: take tb_ctx out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/tb-context.h | 2 ++ tcg/tcg.h | 2 -- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 57 +++++++++++++++++++++++--------------------= ---- linux-user/main.c | 6 ++--- 5 files changed, 34 insertions(+), 35 deletions(-) diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index 1fa8dcc..1d41202 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -41,4 +41,6 @@ struct TBContext { int tb_phys_invalidate_count; }; =20 +extern TBContext tb_ctx; + #endif diff --git a/tcg/tcg.h b/tcg/tcg.h index 9b6dade..22f7ecd 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -707,8 +707,6 @@ struct TCGContext { /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; =20 - TBContext tb_ctx; - /* Track which vCPU triggers events */ CPUState *cpu; /* *_trans */ TCGv_env tcg_env; /* *_exec */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 1963bda..f42096a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -325,7 +325,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targe= t_ulong pc, phys_pc =3D get_page_addr_code(desc.env, pc); desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); - return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); + return qht_lookup(&tb_ctx.htable, tb_cmp, &desc, h); } =20 static inline TranslationBlock *tb_find(CPUState *cpu, diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d50e2b9..5509407 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -154,6 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ TCGContext tcg_ctx; +TBContext tb_ctx; bool parallel_cpus; =20 /* translation block context */ @@ -185,7 +186,7 @@ static void page_table_config_init(void) void tb_lock(void) { assert_tb_unlocked(); - qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_lock(&tb_ctx.tb_lock); have_tb_lock++; } =20 @@ -193,13 +194,13 @@ void tb_unlock(void) { assert_tb_locked(); have_tb_lock--; - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); } =20 void tb_lock_reset(void) { if (have_tb_lock) { - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); have_tb_lock =3D 0; } } @@ -826,15 +827,15 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } - tcg_ctx.tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); - qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); + tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); + qemu_mutex_init(&tb_ctx.tb_lock); } =20 static void tb_htable_init(void) { unsigned int mode =3D QHT_MODE_AUTO_RESIZE; =20 - qht_init(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode); + qht_init(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode); } =20 /* Must be called before using the QEMU cpus. 'tb_size' is the size @@ -878,7 +879,7 @@ void tb_remove(TranslationBlock *tb) { assert_tb_locked(); =20 - g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc); + g_tree_remove(tb_ctx.tb_tree, &tb->tc); } =20 static inline void invalidate_page_bitmap(PageDesc *p) @@ -940,15 +941,15 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) /* If it is already been done on request of another CPU, * just retry. */ - if (tcg_ctx.tb_ctx.tb_flush_count !=3D tb_flush_count.host_int) { + if (tb_ctx.tb_flush_count !=3D tb_flush_count.host_int) { goto done; } =20 if (DEBUG_TB_FLUSH_GATE) { - size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + size_t nb_tbs =3D g_tree_nnodes(tb_ctx.tb_tree); size_t host_size =3D 0; =20 - g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_si= ze); + g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); @@ -963,17 +964,16 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) } =20 /* Increment the refcount first so that destroy acts as a reset */ - g_tree_ref(tcg_ctx.tb_ctx.tb_tree); - g_tree_destroy(tcg_ctx.tb_ctx.tb_tree); + g_tree_ref(tb_ctx.tb_tree); + g_tree_destroy(tb_ctx.tb_tree); =20 - qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE); + qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 tcg_ctx.code_gen_ptr =3D tcg_ctx.code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ - atomic_mb_set(&tcg_ctx.tb_ctx.tb_flush_count, - tcg_ctx.tb_ctx.tb_flush_count + 1); + atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); =20 done: tb_unlock(); @@ -982,7 +982,7 @@ done: void tb_flush(CPUState *cpu) { if (tcg_enabled()) { - unsigned tb_flush_count =3D atomic_mb_read(&tcg_ctx.tb_ctx.tb_flus= h_count); + unsigned tb_flush_count =3D atomic_mb_read(&tb_ctx.tb_flush_count); async_safe_run_on_cpu(cpu, do_tb_flush, RUN_ON_CPU_HOST_INT(tb_flush_count)); } @@ -1015,7 +1015,7 @@ do_tb_invalidate_check(struct qht *ht, void *p, uint3= 2_t hash, void *userp) static void tb_invalidate_check(target_ulong address) { address &=3D TARGET_PAGE_MASK; - qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_invalidate_check, &address); + qht_iter(&tb_ctx.htable, do_tb_invalidate_check, &address); } =20 static void @@ -1035,7 +1035,7 @@ do_tb_page_check(struct qht *ht, void *p, uint32_t ha= sh, void *userp) /* verify that all the pages have correct rights for code */ static void tb_page_check(void) { - qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); + qht_iter(&tb_ctx.htable, do_tb_page_check, NULL); } =20 #endif /* CONFIG_USER_ONLY */ @@ -1135,7 +1135,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, tb->trace_vcpu_dstate); - qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); + qht_remove(&tb_ctx.htable, tb, h); =20 /* remove the TB from the page list */ if (tb->page_addr[0] !=3D page_addr) { @@ -1164,7 +1164,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) /* suppress any remaining jumps to this TB */ tb_jmp_unlink(tb); =20 - tcg_ctx.tb_ctx.tb_phys_invalidate_count++; + tb_ctx.tb_phys_invalidate_count++; } =20 #ifdef CONFIG_SOFTMMU @@ -1280,7 +1280,7 @@ static void tb_link_page(TranslationBlock *tb, tb_pag= e_addr_t phys_pc, /* add in the hash table */ h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MA= SK, tb->trace_vcpu_dstate); - qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); + qht_insert(&tb_ctx.htable, tb, h); =20 #ifdef CONFIG_USER_ONLY if (DEBUG_TB_CHECK_GATE) { @@ -1426,7 +1426,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * through the physical hash table and physical page list. */ tb_link_page(tb, phys_pc, phys_page2); - g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb); + g_tree_insert(tb_ctx.tb_tree, &tb->tc, tb); return tb; } =20 @@ -1706,7 +1706,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) { struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 - return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s); + return g_tree_lookup(tb_ctx.tb_tree, &s); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1931,8 +1931,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) =20 tb_lock(); =20 - nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); - g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); + nb_tbs =3D g_tree_nnodes(tb_ctx.tb_tree); + g_tree_foreach(tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); /* @@ -1958,15 +1958,14 @@ void dump_exec_info(FILE *f, fprintf_function cpu_f= printf) tst.direct_jmp2_count, nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); =20 - qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst); + qht_statistics_init(&tb_ctx.htable, &hst); print_qht_statistics(f, cpu_fprintf, hst); qht_statistics_destroy(&hst); =20 cpu_fprintf(f, "\nStatistics:\n"); cpu_fprintf(f, "TB flush count %u\n", - atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); - cpu_fprintf(f, "TB invalidate count %d\n", - tcg_ctx.tb_ctx.tb_phys_invalidate_count); + atomic_read(&tb_ctx.tb_flush_count)); + cpu_fprintf(f, "TB invalidate count %d\n", tb_ctx.tb_phys_invalidate_c= ount); cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 diff --git a/linux-user/main.c b/linux-user/main.c index 2b38d39..dbbe3d7 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -114,7 +114,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) void fork_start(void) { cpu_list_lock(); - qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_lock(&tb_ctx.tb_lock); mmap_fork_start(); } =20 @@ -130,11 +130,11 @@ void fork_end(int child) QTAILQ_REMOVE(&cpus, cpu, node); } } - qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_init(&tb_ctx.tb_lock); qemu_init_cpu_list(); gdbserver_fork(thread_cpu); } else { - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); cpu_list_unlock(); } } --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520529695349.740482495901; Wed, 19 Jul 2017 20:15:29 -0700 (PDT) Received: from localhost ([::1]:35814 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1us-0004zz-NA for importer@patchew.org; Wed, 19 Jul 2017 23:14:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qO-00016e-Sn for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qL-0005tJ-OY for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:40 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40079) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005sf-LA for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:37 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 6586320B76; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:37 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 2E4857E057; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=4YC3qzEAt5L5+vZ Y10tsIzrXfJd4IOSUI2zuJn63SKs=; b=EyiN7QCyLjJerZd/UiHB5XILWqpyEOP 0VzWyUxto3+1PN7CT824A7bKCPCI3ANihDXYOKefWLbIXojBKLW+XwaomQ1T/DmZ pTEj4d+Y7MYB/5SV7Nju53oxhBGSV3b2sP1r4MLwlvhBhpHhSMJ25G0C35My4zrK AtwGNpatJohg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=4YC3qzEAt5L5+vZY10tsIzrXfJd4IOSUI2zuJn63SKs=; b=Z9J62EJb CT6B0+gygBWC6zgk1P/K37ErXfEVDYae/DHpf72B0b4RoPAvVPvnqXjUBQfYlXti p/TkSmKFPxoRubVKz7i55/Z7chei7cHrAl4SdKJziITj8k4YAXpyuCuJvXfLoJQy JtoJ+NqEsZrgxgRmb+02Bm9Y+xNG8C2IZJmCO+E7jKEzfKYVXRCof7LunOn+L0c4 /bojUKZGGquOVKbCXItO8TVl0IXndMbQeh0e4NXPcTaNj/59M2inM5V0rDO/wEDN 0K405oGzi6Pp+9b57h+pRSSZR9Q2q0WggsMbHNPGXgLXOiXRLga6l6gVuTrKvMUJ LjzfvkHmPzgVCQ== X-ME-Sender: X-Sasl-enc: FMfWv9s0hRoY/4PxHpZ6CBSvof4SDhjLr9/IRGWU2AAL 1500520177 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:18 -0400 Message-Id: <1500520169-23367-33-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 32/43] tcg: take .helpers out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Groundwork for supporting multiple TCG contexts. The hash table becomes read-only after it is filled in, so we can save space by keeping just a global pointer to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 2 -- tcg/tcg.c | 10 +++++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 22f7ecd..53c679f 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -664,8 +664,6 @@ struct TCGContext { =20 tcg_insn_unit *code_ptr; =20 - GHashTable *helpers; - #ifdef CONFIG_PROFILER /* profiling info */ int64_t tb_count1; diff --git a/tcg/tcg.c b/tcg/tcg.c index 28c1b94..c0c2d6c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -319,6 +319,7 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; +static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -329,7 +330,6 @@ void tcg_context_init(TCGContext *s) TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; - GHashTable *helper_table; =20 memset(s, 0, sizeof(*s)); s->nb_globals =3D 0; @@ -357,7 +357,7 @@ void tcg_context_init(TCGContext *s) =20 /* Register helpers. */ /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - s->helpers =3D helper_table =3D g_hash_table_new(NULL, NULL); + helper_table =3D g_hash_table_new(NULL, NULL); =20 for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, @@ -761,7 +761,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg re= t, unsigned sizemask, flags; TCGHelperInfo *info; =20 - info =3D g_hash_table_lookup(s->helpers, (gpointer)func); + info =3D g_hash_table_lookup(helper_table, (gpointer)func); flags =3D info->flags; sizemask =3D info->sizemask; =20 @@ -990,8 +990,8 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char *b= uf, static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) { const char *ret =3D NULL; - if (s->helpers) { - TCGHelperInfo *info =3D g_hash_table_lookup(s->helpers, (gpointer)= val); + if (helper_table) { + TCGHelperInfo *info =3D g_hash_table_lookup(helper_table, (gpointe= r)val); if (info) { ret =3D info->name; } --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500522175553144.89827574758215; Wed, 19 Jul 2017 20:42:55 -0700 (PDT) Received: from localhost ([::1]:35943 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2MX-00057O-Da for importer@patchew.org; Wed, 19 Jul 2017 23:42:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60503) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qX-0001F7-Ep for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qM-0005uQ-CX for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:55779) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005tK-VO for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B021320B59; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:37 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 56D652418A; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=4Nx Uoy6A9RRcHQStPImDFHfK7xahwoICg0tEBzaJOak=; b=OzYFolPwNlwFz/CtMX7 h0mGEdSmkgbG2pVWL4F0CpD9IQyWLuqD47uUidaHCKxXLuCMha7bUFNfi1JYu5V0 pNpugRSkMZR2dJ53GUvXaPQ4bT1KYYApzNDpaFU/HI4Zy9vx+hOhosdPw9j+ppjv GYh2Zj/bOcfShFC3eZ4KnhVg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=4NxUoy6A9RRcHQStPImDFHfK7xahwoICg0tEBzaJO ak=; b=GIk4v8d6keZb9D7aaAEoFgOQ2fMIeoVO6nMtkqDjNH+HixmE+6Mr4aQJS Q2xTv3OooW8IAznbPrBGtg4jZQ4aEZlHw21X7uQTrF0E+vRzoobln/ylOMWg4LQr BGuRb0rTPQ8wJmBnag2znLyHEDkHiNzettbtqqLHW0tpL2eC1JBw0NTZA5aDCy0C RECrCrg2hL55p80B9lfZt0IdlqmBcnYc4okPYpDDPG6i1ZKeermEBIOsIOeHq1BA SfpjSghhDUF7TPXckhDMPywSHUAfysAR6/EeZLqQ4HrGevCZNuA1a7QLOqxipyJ+ 6znwF84Zr6cMzYsNW+R+FRN2B8rww== X-ME-Sender: X-Sasl-enc: FMfVsMIwghAL/o31GI56CBSvof4SDhjLr9/IRGWU2AAL 1500520177 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:19 -0400 Message-Id: <1500520169-23367-34-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 33/43] tcg: define tcg_init_ctx and make tcg_ctx a pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 10 ++--- include/exec/helper-gen.h | 12 +++--- tcg/tcg-op.h | 80 +++++++++++++++++------------------ tcg/tcg.h | 15 +++---- accel/tcg/translate-all.c | 97 ++++++++++++++++++++++-----------------= ---- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- target/alpha/translate.c | 2 +- target/arm/translate.c | 2 +- target/cris/translate.c | 2 +- target/cris/translate_v10.c | 2 +- target/hppa/translate.c | 2 +- target/i386/translate.c | 2 +- target/lm32/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/translate.c | 2 +- target/moxie/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/s390x/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- target/xtensa/translate.c | 2 +- tcg/tcg-op.c | 58 +++++++++++++------------- tcg/tcg-runtime.c | 2 +- tcg/tcg.c | 21 +++++----- 30 files changed, 171 insertions(+), 168 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 48b566c..c58b0b2 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count =3D tcg_temp_new_i32(); } =20 - tcg_gen_ld_i32(count, tcg_ctx.tcg_env, + tcg_gen_ld_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { @@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, tcg_ctx.tcg_env, + tcg_gen_st16_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } =20 @@ -56,13 +56,13 @@ static inline void gen_tb_end(TranslationBlock *tb, int= num_insns) tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); =20 /* Terminate the linked list. */ - tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next =3D 0; + tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next =3D 0; } =20 static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } @@ -70,7 +70,7 @@ static inline void gen_io_start(void) static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 8239ffc..3bcb901 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -9,7 +9,7 @@ #define DEF_HELPER_FLAGS_0(name, flags, ret) \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \ } =20 #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ @@ -17,7 +17,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1)) \ { \ TCGArg args[1] =3D { dh_arg(t1, 1) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \ } =20 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ @@ -25,7 +25,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ TCGArg args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \ } =20 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ @@ -33,7 +33,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ TCGArg args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \ } =20 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ @@ -43,7 +43,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \ } =20 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ @@ -53,7 +53,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \ } =20 #include "helper.h" diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 18d01b2..75c15cc 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -40,161 +40,161 @@ void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCG= Arg, TCGArg, =20 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) { - tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1)); + tcg_gen_op1(tcg_ctx, opc, GET_TCGV_I32(a1)); } =20 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) { - tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1)); + tcg_gen_op1(tcg_ctx, opc, GET_TCGV_I64(a1)); } =20 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) { - tcg_gen_op1(&tcg_ctx, opc, a1); + tcg_gen_op1(tcg_ctx, opc, a1); } =20 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); } =20 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); } =20 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I32(a1), a2); } =20 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I64(a1), a2); } =20 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, a1, a2); + tcg_gen_op2(tcg_ctx, opc, a1, a2); } =20 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3)); } =20 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3)); } =20 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGArg a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); } =20 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGArg a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); } =20 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offs= et); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offse= t); } =20 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offs= et); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offse= t); } =20 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4)); } =20 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4)); } =20 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4); } =20 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4); } =20 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); } =20 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); } =20 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); } =20 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); } =20 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); } =20 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); } =20 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4, a5); } =20 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGv_i64 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4, a5); } =20 @@ -202,7 +202,7 @@ static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_= i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGv_i32 a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), GET_TCGV_I32(a6)); } @@ -211,7 +211,7 @@ static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_= i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGv_i64 a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), GET_TCGV_I64(a6)); } @@ -220,7 +220,7 @@ static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv= _i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); } =20 @@ -228,7 +228,7 @@ static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv= _i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); } =20 @@ -236,7 +236,7 @@ static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCG= v_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); } =20 @@ -244,7 +244,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCG= v_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); } =20 @@ -253,12 +253,12 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, T= CGv_i64 a1, TCGv_i64 a2, =20 static inline void gen_set_label(TCGLabel *l) { - tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l)); + tcg_gen_op1(tcg_ctx, INDEX_op_set_label, label_arg(l)); } =20 static inline void tcg_gen_br(TCGLabel *l) { - tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); + tcg_gen_op1(tcg_ctx, INDEX_op_br, label_arg(l)); } =20 void tcg_gen_mb(TCGBar); @@ -732,12 +732,12 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret,= TCGv_i64 lo, TCGv_i64 hi) # if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc); + tcg_gen_op1(tcg_ctx, INDEX_op_insn_start, pc); } # else static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op2(tcg_ctx, INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); } # endif @@ -745,12 +745,12 @@ static inline void tcg_gen_insn_start(target_ulong pc) # if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1); + tcg_gen_op2(tcg_ctx, INDEX_op_insn_start, pc, a1); } # else static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op4(tcg_ctx, INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32), (uint32_t)a1, (uint32_t)(a1 >> 32)); } @@ -760,13 +760,13 @@ static inline void tcg_gen_insn_start(target_ulong pc= , target_ulong a1) static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2); + tcg_gen_op3(tcg_ctx, INDEX_op_insn_start, pc, a1, a2); } # else static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op6(tcg_ctx, INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32), (uint32_t)a1, (uint32_t)(a1 >> 32), (uint32_t)a2, (uint32_t)(a2 >> 32)); diff --git a/tcg/tcg.h b/tcg/tcg.h index 53c679f..c88746d 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -726,18 +726,19 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; =20 -extern TCGContext tcg_ctx; +extern TCGContext tcg_init_ctx; +extern TCGContext *tcg_ctx; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { - int op_argi =3D tcg_ctx.gen_op_buf[op_idx].args; - tcg_ctx.gen_opparam_buf[op_argi + arg] =3D v; + int op_argi =3D tcg_ctx->gen_op_buf[op_idx].args; + tcg_ctx->gen_opparam_buf[op_argi + arg] =3D v; } =20 /* The number of opcodes emitted so far. */ static inline int tcg_op_buf_count(void) { - return tcg_ctx.gen_next_op_idx; + return tcg_ctx->gen_next_op_idx; } =20 /* Test for whether to terminate the TB for using too many opcodes. */ @@ -756,13 +757,13 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s); /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; uint8_t *ptr, *ptr_end; size =3D (size + sizeof(long) - 1) & ~(sizeof(long) - 1); ptr =3D s->pool_cur; ptr_end =3D ptr + size; if (unlikely(ptr_end > s->pool_end)) { - return tcg_malloc_internal(&tcg_ctx, size); + return tcg_malloc_internal(tcg_ctx, size); } else { s->pool_cur =3D ptr_end; return ptr; @@ -1100,7 +1101,7 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); #else # define tcg_qemu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) + ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_pt= r) #endif =20 void tcg_register_jit(void *buf, size_t buf_size); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5509407..e6ee4e3 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -153,7 +153,8 @@ static int v_l2_levels; static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ -TCGContext tcg_ctx; +TCGContext tcg_init_ctx; +TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; =20 @@ -209,7 +210,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); =20 void cpu_gen_init(void) { - tcg_context_init(&tcg_ctx);=20 + tcg_context_init(&tcg_init_ctx); } =20 /* Encode VAL as a signed leb128 sequence at P. @@ -267,7 +268,7 @@ static target_long decode_sleb128(uint8_t **pp) =20 static int encode_search(TranslationBlock *tb, uint8_t *block) { - uint8_t *highwater =3D tcg_ctx.code_gen_highwater; + uint8_t *highwater =3D tcg_ctx->code_gen_highwater; uint8_t *p =3D block; int i, j, n; =20 @@ -280,12 +281,12 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) if (i =3D=3D 0) { prev =3D (j =3D=3D 0 ? tb->pc : 0); } else { - prev =3D tcg_ctx.gen_insn_data[i - 1][j]; + prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } - p =3D encode_sleb128(p, tcg_ctx.gen_insn_data[i][j] - prev); + p =3D encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); } - prev =3D (i =3D=3D 0 ? 0 : tcg_ctx.gen_insn_end_off[i - 1]); - p =3D encode_sleb128(p, tcg_ctx.gen_insn_end_off[i] - prev); + prev =3D (i =3D=3D 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); + p =3D encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); =20 /* Test for (pending) buffer overflow. The assumption is that any one row beginning below the high water mark cannot overrun @@ -345,8 +346,8 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER - tcg_ctx.restore_time +=3D profile_getclock() - ti; - tcg_ctx.restore_count++; + tcg_ctx->restore_time +=3D profile_getclock() - ti; + tcg_ctx->restore_count++; #endif return 0; } @@ -592,7 +593,7 @@ static inline void *split_cross_256mb(void *buf1, size_= t size1) buf1 =3D buf2; } =20 - tcg_ctx.code_gen_buffer_size =3D size1; + tcg_ctx->code_gen_buffer_size =3D size1; return buf1; } #endif @@ -655,16 +656,16 @@ static inline void *alloc_code_gen_buffer(void) size =3D full_size - qemu_real_host_page_size; =20 /* Honor a command-line option limiting the size of the buffer. */ - if (size > tcg_ctx.code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) + if (size > tcg_ctx->code_gen_buffer_size) { + size =3D (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) & qemu_real_host_page_mask) - (uintptr_t)buf; } - tcg_ctx.code_gen_buffer_size =3D size; + tcg_ctx->code_gen_buffer_size =3D size; =20 #ifdef __mips__ if (cross_256mb(buf, size)) { buf =3D split_cross_256mb(buf, size); - size =3D tcg_ctx.code_gen_buffer_size; + size =3D tcg_ctx->code_gen_buffer_size; } #endif =20 @@ -677,7 +678,7 @@ static inline void *alloc_code_gen_buffer(void) #elif defined(_WIN32) static inline void *alloc_code_gen_buffer(void) { - size_t size =3D tcg_ctx.code_gen_buffer_size; + size_t size =3D tcg_ctx->code_gen_buffer_size; void *buf1, *buf2; =20 /* Perform the allocation in two steps, so that the guard page @@ -696,7 +697,7 @@ static inline void *alloc_code_gen_buffer(void) { int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start =3D 0; - size_t size =3D tcg_ctx.code_gen_buffer_size; + size_t size =3D tcg_ctx->code_gen_buffer_size; void *buf; =20 /* Constrain the position of the buffer based on the host cpu. @@ -713,7 +714,7 @@ static inline void *alloc_code_gen_buffer(void) flags |=3D MAP_32BIT; /* Cannot expect to map more than 800MB in low memory. */ if (size > 800u * 1024 * 1024) { - tcg_ctx.code_gen_buffer_size =3D size =3D 800u * 1024 * 1024; + tcg_ctx->code_gen_buffer_size =3D size =3D 800u * 1024 * 1024; } # elif defined(__sparc__) start =3D 0x40000000ul; @@ -753,7 +754,7 @@ static inline void *alloc_code_gen_buffer(void) default: /* Split the original buffer. Free the smaller half. */ buf2 =3D split_cross_256mb(buf, size); - size2 =3D tcg_ctx.code_gen_buffer_size; + size2 =3D tcg_ctx->code_gen_buffer_size; if (buf =3D=3D buf2) { munmap(buf + size2 + qemu_real_host_page_size, size - size= 2); } else { @@ -821,9 +822,9 @@ static gint tb_tc_cmp(gconstpointer ap, gconstpointer b= p) =20 static inline void code_gen_alloc(size_t tb_size) { - tcg_ctx.code_gen_buffer_size =3D size_code_gen_buffer(tb_size); - tcg_ctx.code_gen_buffer =3D alloc_code_gen_buffer(); - if (tcg_ctx.code_gen_buffer =3D=3D NULL) { + tcg_ctx->code_gen_buffer_size =3D size_code_gen_buffer(tb_size); + tcg_ctx->code_gen_buffer =3D alloc_code_gen_buffer(); + if (tcg_ctx->code_gen_buffer =3D=3D NULL) { fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } @@ -851,7 +852,7 @@ void tcg_exec_init(unsigned long tb_size) #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); #endif } =20 @@ -867,7 +868,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) =20 assert_tb_locked(); =20 - tb =3D tcg_tb_alloc(&tcg_ctx); + tb =3D tcg_tb_alloc(tcg_ctx); if (unlikely(tb =3D=3D NULL)) { return NULL; } @@ -951,11 +952,11 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) =20 g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); } - if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) - > tcg_ctx.code_gen_buffer_size) { + if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) + > tcg_ctx->code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); } =20 @@ -970,7 +971,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 - tcg_ctx.code_gen_ptr =3D tcg_ctx.code_gen_buffer; + tcg_ctx->code_gen_ptr =3D tcg_ctx->code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1321,44 +1322,44 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cpu_loop_exit(cpu); } =20 - gen_code_buf =3D tcg_ctx.code_gen_ptr; + gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tcg_ctx.cf_parallel =3D !!(cflags & CF_PARALLEL); + tcg_ctx->cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER - tcg_ctx.tb_count1++; /* includes aborted translations because of + tcg_ctx->tb_count1++; /* includes aborted translations because of exceptions */ ti =3D profile_getclock(); #endif =20 - tcg_func_start(&tcg_ctx); + tcg_func_start(tcg_ctx); =20 - tcg_ctx.cpu =3D ENV_GET_CPU(env); + tcg_ctx->cpu =3D ENV_GET_CPU(env); gen_intermediate_code(env, tb); - tcg_ctx.cpu =3D NULL; + tcg_ctx->cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; tb->jmp_reset_offset[1] =3D TB_JMP_RESET_OFFSET_INVALID; - tcg_ctx.tb_jmp_reset_offset =3D tb->jmp_reset_offset; + tcg_ctx->tb_jmp_reset_offset =3D tb->jmp_reset_offset; #ifdef USE_DIRECT_JUMP - tcg_ctx.tb_jmp_insn_offset =3D tb->jmp_insn_offset; - tcg_ctx.tb_jmp_target_addr =3D NULL; + tcg_ctx->tb_jmp_insn_offset =3D tb->jmp_insn_offset; + tcg_ctx->tb_jmp_target_addr =3D NULL; #else - tcg_ctx.tb_jmp_insn_offset =3D NULL; - tcg_ctx.tb_jmp_target_addr =3D tb->jmp_target_addr; + tcg_ctx->tb_jmp_insn_offset =3D NULL; + tcg_ctx->tb_jmp_target_addr =3D tb->jmp_target_addr; #endif =20 #ifdef CONFIG_PROFILER - tcg_ctx.tb_count++; - tcg_ctx.interm_time +=3D profile_getclock() - ti; + tcg_ctx->tb_count++; + tcg_ctx->interm_time +=3D profile_getclock() - ti; ti =3D profile_getclock(); #endif =20 @@ -1367,7 +1368,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, the tcg optimization currently hidden inside tcg_gen_code. All that should be required is to flush the TBs, allocate a new TB, re-initialize it per above, and re-do the actual code generation. = */ - gen_code_size =3D tcg_gen_code(&tcg_ctx, tb); + gen_code_size =3D tcg_gen_code(tcg_ctx, tb); if (unlikely(gen_code_size < 0)) { goto buffer_overflow; } @@ -1378,10 +1379,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock() - ti; - tcg_ctx.code_in_len +=3D tb->size; - tcg_ctx.code_out_len +=3D gen_code_size; - tcg_ctx.search_out_len +=3D search_size; + tcg_ctx->code_time +=3D profile_getclock() - ti; + tcg_ctx->code_in_len +=3D tb->size; + tcg_ctx->code_out_len +=3D gen_code_size; + tcg_ctx->search_out_len +=3D search_size; #endif =20 #ifdef DEBUG_DISAS @@ -1396,7 +1397,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif =20 - tcg_ctx.code_gen_ptr =3D (void *) + tcg_ctx->code_gen_ptr =3D (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, CODE_GEN_ALIGN); =20 @@ -1941,8 +1942,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. */ cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, + tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index fa9c012..7a8b29e 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -978,7 +978,7 @@ int main(int argc, char **argv) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/linux-user/main.c b/linux-user/main.c index dbbe3d7..de7d948 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4459,7 +4459,7 @@ int main(int argc, char **argv, char **envp) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); =20 #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index f97a8e5..b506198 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -156,7 +156,7 @@ void alpha_translate_init(void) done_init =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 31; i++) { cpu_std_ir[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/arm/translate.c b/target/arm/translate.c index bd0ef58..657d1fe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -82,7 +82,7 @@ void arm_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 16; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/cris/translate.c b/target/cris/translate.c index 1703d91..afaeadf 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3365,7 +3365,7 @@ void cris_initialize_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c index 4a0b485..5d48920 100644 --- a/target/cris/translate_v10.c +++ b/target/cris/translate_v10.c @@ -1273,7 +1273,7 @@ void cris_initialize_crisv10_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 66aa11d..c1ba87c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -145,7 +145,7 @@ void hppa_translate_init(void) done_init =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 TCGV_UNUSED(cpu_gr[0]); for (i =3D 1; i < 32; i++) { diff --git a/target/i386/translate.c b/target/i386/translate.c index 0f38a48..0d574a7 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8335,7 +8335,7 @@ void tcg_x86_init(void) initialized =3D true; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_cc_op =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUX86State, cc_op), "cc_o= p"); cpu_cc_dst =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_ds= t), diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 3597c61..0e8ed34 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1203,7 +1203,7 @@ void lm32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 65044be..e1fd030 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -69,7 +69,7 @@ void m68k_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 #define DEFO32(name, offset) \ QREG_##name =3D tcg_global_mem_new_i32(cpu_env, \ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4cd184e..9e8e38c 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1861,7 +1861,7 @@ void mb_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 env_debug =3D tcg_global_mem_new(cpu_env, offsetof(CPUMBState, debug), diff --git a/target/mips/translate.c b/target/mips/translate.c index f839a2b..84eb5c2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20149,7 +20149,7 @@ void mips_tcg_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 TCGV_UNUSED(cpu_gpr[0]); for (i =3D 1; i < 32; i++) diff --git a/target/moxie/translate.c b/target/moxie/translate.c index f61aa2d..93983a6 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -106,7 +106,7 @@ void moxie_translate_init(void) return; } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, pc), "$pc"); for (i =3D 0; i < 16; i++) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 347790c..cbe67cb 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -75,7 +75,7 @@ void openrisc_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_sr =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e146aa3..b0ab44a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -90,7 +90,7 @@ void ppc_translate_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 p =3D cpu_reg_names; cpu_reg_names_size =3D sizeof(cpu_reg_names); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index ea8a90a..ca4d2b0 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -171,7 +171,7 @@ void s390x_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; psw_addr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 52fabb3..f1cb018 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -105,7 +105,7 @@ void sh4_translate_init(void) } =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 24; i++) { cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 768ce68..b22f765 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5933,7 +5933,7 @@ void gen_intermediate_code_init(CPUSPARCState *env) inited =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 cpu_regwptr =3D tcg_global_mem_new_ptr(cpu_env, offsetof(CPUSPARCState, regwptr), diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index 33be670..f32f088 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2447,7 +2447,7 @@ void tilegx_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), = "pc"); for (i =3D 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 3d8448c..4cce3cc 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8886,7 +8886,7 @@ void tricore_tcg_init(void) return; } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; /* reg init */ for (i =3D 0 ; i < 16 ; i++) { cpu_gpr_a[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 4cede72..d7c7d49 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -70,7 +70,7 @@ void uc32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 3ded61b..7f859cc 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -218,7 +218,7 @@ void xtensa_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, pc), "pc"); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ef420d4..4a7057e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -150,8 +150,8 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg= a1, TCGArg a2, =20 void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx.cf_parallel) { - tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); + if (tcg_ctx->cf_parallel) { + tcg_gen_op1(tcg_ctx, INDEX_op_mb, mb_type); } } =20 @@ -2486,7 +2486,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_mov_i32(ret, TCGV_LOW(arg)); } else if (TCG_TARGET_HAS_extrl_i64_i32) { - tcg_gen_op2(&tcg_ctx, INDEX_op_extrl_i64_i32, + tcg_gen_op2(tcg_ctx, INDEX_op_extrl_i64_i32, GET_TCGV_I32(ret), GET_TCGV_I64(arg)); } else { tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); @@ -2498,7 +2498,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); } else if (TCG_TARGET_HAS_extrh_i64_i32) { - tcg_gen_op2(&tcg_ctx, INDEX_op_extrh_i64_i32, + tcg_gen_op2(tcg_ctx, INDEX_op_extrh_i64_i32, GET_TCGV_I32(ret), GET_TCGV_I64(arg)); } else { TCGv_i64 t =3D tcg_temp_new_i64(); @@ -2514,7 +2514,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } else { - tcg_gen_op2(&tcg_ctx, INDEX_op_extu_i32_i64, + tcg_gen_op2(tcg_ctx, INDEX_op_extu_i32_i64, GET_TCGV_I64(ret), GET_TCGV_I32(arg)); } } @@ -2525,7 +2525,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } else { - tcg_gen_op2(&tcg_ctx, INDEX_op_ext_i32_i64, + tcg_gen_op2(tcg_ctx, INDEX_op_ext_i32_i64, GET_TCGV_I64(ret), GET_TCGV_I32(arg)); } } @@ -2581,8 +2581,8 @@ void tcg_gen_goto_tb(unsigned idx) tcg_debug_assert(idx <=3D 1); #ifdef CONFIG_DEBUG_TCG /* Verify that we havn't seen this numbered exit before. */ - tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) =3D=3D 0); - tcg_ctx.goto_tb_issue_mask |=3D 1 << idx; + tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) =3D=3D 0); + tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif tcg_gen_op1i(INDEX_op_goto_tb, idx); } @@ -2591,7 +2591,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { @@ -2637,7 +2637,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), = oi); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), o= i); } #endif } @@ -2650,7 +2650,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); } else { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), = oi); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), o= i); } #else if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -2665,7 +2665,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { memop =3D tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } @@ -2673,7 +2673,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { memop =3D tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } @@ -2691,7 +2691,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); } @@ -2704,7 +2704,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } @@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!tcg_ctx.cf_parallel) { + if (!tcg_ctx->cf_parallel) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2820,11 +2820,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv= addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif =20 if (memop & MO_SIGN) { @@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!tcg_ctx.cf_parallel) { + if (!tcg_ctx->cf_parallel) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -2865,14 +2865,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv= addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(retv, 0); @@ -2928,11 +2928,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv add= r, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx= )); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif =20 if (memop & MO_SIGN) { @@ -2973,14 +2973,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv add= r, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(ret, 0); @@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.cf_parallel) { \ + if (tcg_ctx->cf_parallel) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.cf_parallel) { \ + if (tcg_ctx->cf_parallel) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 9a87616..02d3acb 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -153,7 +153,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) =20 tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); if (tb =3D=3D NULL) { - return tcg_ctx.code_gen_epilogue; + return tcg_ctx->code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", diff --git a/tcg/tcg.c b/tcg/tcg.c index c0c2d6c..f907c47 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,7 +116,6 @@ static void tcg_out_tb_init(TCGContext *s); static bool tcg_out_tb_finalize(TCGContext *s); =20 =20 - static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -242,7 +241,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, t= cg_insn_unit *ptr) =20 TCGLabel *gen_new_label(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGLabel *l =3D tcg_malloc(sizeof(TCGLabel)); =20 *l =3D (TCGLabel){ @@ -381,6 +380,8 @@ void tcg_context_init(TCGContext *s) for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { indirect_reg_alloc_order[i] =3D tcg_target_reg_alloc_order[i]; } + + tcg_ctx =3D s; } =20 /* @@ -526,7 +527,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t = start, intptr_t size) =20 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int idx; =20 if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -538,7 +539,7 @@ TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char = *name) =20 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int idx; =20 if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -551,7 +552,7 @@ TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char = *name) int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *base_ts =3D &s->temps[GET_TCGV_PTR(base)]; TCGTemp *ts =3D tcg_global_alloc(s); int indirect_reg =3D 0, bigendian =3D 0; @@ -606,7 +607,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr = base, =20 static int tcg_temp_new_internal(TCGType type, int temp_local) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *ts; int idx, k; =20 @@ -668,7 +669,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local) =20 static void tcg_temp_free_internal(int idx) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *ts; int k; =20 @@ -733,13 +734,13 @@ TCGv_i64 tcg_const_local_i64(int64_t val) #if defined(CONFIG_DEBUG_TCG) void tcg_clear_temp_count(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; s->temps_in_use =3D 0; } =20 int tcg_check_temp_count(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; if (s->temps_in_use) { /* Clear the count so that we don't give another * warning immediately next time around. @@ -2707,7 +2708,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int64_t tb_count =3D s->tb_count; int64_t tb_div_count =3D tb_count ? tb_count : 1; int64_t tot =3D s->interm_time + s->code_time; --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521526164620.7356665419802; Wed, 19 Jul 2017 20:32:06 -0700 (PDT) Received: from localhost ([::1]:35897 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2C4-0005ot-Am for importer@patchew.org; Wed, 19 Jul 2017 23:32:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60324) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qQ-00017V-Rq for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qM-0005vS-LL for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:42 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:58839) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qM-0005tX-Ey for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C039020B5C; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:37 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 85A2C7E057; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=FUJLAMy+bUx1Eod MccvwYc91f48oZh49i9Jgzy5qjNQ=; b=exj5gwAl62U6T0k9XHkLXVdIOLXCu96 Ke3zcfxhijmVlpLz76ySrFmWqMhzZJCBwG+07V0b1+QayMhWE9MrRwVstwk88NeM SyVXWH6/5zR5yFl6S+wEkwx91PveD/aVoKXf9qolz6KsQlixGJLSfrHHvWGtPknF ClotAThgMMcA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=FUJLAMy+bUx1EodMccvwYc91f48oZh49i9Jgzy5qjNQ=; b=ABrcTkaM m2+sjtHarsBhW5OBaRqQcLYGlCEdB9/84PK+Ud4EGKKzckwMFymrg6J0kipFct80 b/4kcX8L3+261RGuVSWe0XgUhiq21N6OuzSDcQP58E4PtILK8bIytm+v4AJn+INi bqOJSvL5EOK6Kca/jgKEqR1ahGi3FBCaHtTInMdYBTiwoODzLUzPaFxxxdKCoQxO DpPn/g4poFd+9LUr9c7CtYTh9FwrSCWE7r8EYcOQuAMAkLzuUUyqys7tnCH3NHO3 daxxSHwNmy/WpuSedUgoAzfJQ+ZM4gN+gzGAiHsikTGStUSQsXPwQpnAWZWeIdF/ fnodsbjSV5XNyw== X-ME-Sender: X-Sasl-enc: FMfevtgwghwB4JPuD5h6CBSvof4SDhjLr9/IRGWU2AAL 1500520177 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:20 -0400 Message-Id: <1500520169-23367-35-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 34/43] gen-icount: fold exitreq_label into TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 7 +++---- tcg/tcg.h | 2 ++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index c58b0b2..fe80176 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -6,13 +6,12 @@ /* Helpers for instruction counting code generation. */ =20 static int icount_start_insn_idx; -static TCGLabel *exitreq_label; =20 static inline void gen_tb_start(TranslationBlock *tb) { TCGv_i32 count, imm; =20 - exitreq_label =3D gen_new_label(); + tcg_ctx->exitreq_label =3D gen_new_label(); if (tb_cflags(tb) & CF_USE_ICOUNT) { count =3D tcg_temp_local_new_i32(); } else { @@ -34,7 +33,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(imm); } =20 - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); =20 if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx->tcg_env, @@ -52,7 +51,7 @@ static inline void gen_tb_end(TranslationBlock *tb, int n= um_insns) tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); } =20 - gen_set_label(exitreq_label); + gen_set_label(tcg_ctx->exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); =20 /* Terminate the linked list. */ diff --git a/tcg/tcg.h b/tcg/tcg.h index c88746d..f83f9b0 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -712,6 +712,8 @@ struct TCGContext { /* The TCGBackendData structure is private to tcg-target.inc.c. */ struct TCGBackendData *be; =20 + TCGLabel *exitreq_label; + TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521991256291.2138133884731; Wed, 19 Jul 2017 20:39:51 -0700 (PDT) Received: from localhost ([::1]:35927 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2JY-0002vx-V6 for importer@patchew.org; Wed, 19 Jul 2017 23:39:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qY-0001G5-A3 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qM-0005vn-Pq for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:50 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:50359) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qM-0005ty-Dh for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 0ED2D20B62; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:38 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B0BD5241E0; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=n5g /MKWDlH9d+wkYacQLM0igFrKnNchnVLVrQX9OlPQ=; b=U0QzpcIV3PSqQ/iSAPE xSykj25UYJ11/9zG5L3SR5vA9SZP1TEKUnee5bdqWhB8JXMYj5ANSM+l8aXQFoEB 1nBS62BmuFwfavdZLs1eJXjLWj10eKvkFpo6ur5TdDBExy4LXmqqThLOIu51zI/Q fbZnOchC5CMDAyMn3NO9ROFo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=n5g/MKWDlH9d+wkYacQLM0igFrKnNchnVLVrQX9Ol PQ=; b=rr4L97LmtAt9sifkNAunk8ZCIiXUqCigxs/oHcXRUWGfIpkjVAC5IOcS2 vOBspx5TQLRZf/pn+25v+iaaLwZnbCnJdH6Q37Sc2ad+3otKp3IQ6PIH0ZnKz7yA /Db8ET+FqiiptCqCzY2GvK1eEB40GETnh6ViLYy7UqDVQRALOOXJKuss9uiSF5Sr G7hOR2pLngkbYA6Dl1WdxJExiFNsvUAAsJXHRyFUUPYPoCgilw2Nue+nStYo/GJC on7pSjOktAWriNNn+bQzm+iuExFa2k/HmAOISAGu2d6wmwOQSSUmsYTMvlm3tV7+ 8lGauhLDXD3d8js5WgK92HAvV/1GQ== X-ME-Sender: X-Sasl-enc: FMfMp9o0lAUE95n3Bph6CBSvof4SDhjLr9/IRGWU2AAL 1500520177 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:21 -0400 Message-Id: <1500520169-23367-36-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 35/43] tcg: dynamically allocate optimizer temps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. While at it, also allocate temps_used directly as a bitmap of the required size, instead of having a bitmap of TCG_MAX_TEMPS via TCGTempSet. Performance-wise we lose about 2% in a translation-heavy workload such as booting+shutting down debian-arm: Performance counter stats for 'taskset -c 0 arm-softmmu/qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Ddie-on-boot.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): Before: 19489.126318 task-clock # 0.960 CPUs utilized = ( +- 0.96% ) 23,697 context-switches # 0.001 M/sec = ( +- 0.51% ) 1 CPU-migrations # 0.000 M/sec 19,953 page-faults # 0.001 M/sec = ( +- 0.40% ) 56,214,402,410 cycles # 2.884 GHz = ( +- 0.95% ) [83.34%] 25,516,669,513 stalled-cycles-frontend # 45.39% frontend cycles idl= e ( +- 0.69% ) [83.33%] 17,266,165,747 stalled-cycles-backend # 30.71% backend cycles idl= e ( +- 0.59% ) [66.66%] 79,007,843,327 instructions # 1.41 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.19% ) [83.34%] 13,136,600,416 branches # 674.048 M/sec = ( +- 1.29% ) [83.34%] 274,715,270 branch-misses # 2.09% of all branches = ( +- 0.79% ) [83.33%] 20.300335944 seconds time elapsed = ( +- 0.55% ) After: 19917.737030 task-clock # 0.955 CPUs utilized = ( +- 0.74% ) 23,973 context-switches # 0.001 M/sec = ( +- 0.37% ) 1 CPU-migrations # 0.000 M/sec 19,824 page-faults # 0.001 M/sec = ( +- 0.38% ) 57,380,269,537 cycles # 2.881 GHz = ( +- 0.70% ) [83.34%] 26,462,452,508 stalled-cycles-frontend # 46.12% frontend cycles idl= e ( +- 0.65% ) [83.34%] 17,970,546,047 stalled-cycles-backend # 31.32% backend cycles idl= e ( +- 0.64% ) [66.67%] 79,527,238,334 instructions # 1.39 insns per cycle # 0.33 stalled cycles per = insn ( +- 0.79% ) [83.33%] 13,272,362,192 branches # 666.359 M/sec = ( +- 0.83% ) [83.34%] 278,357,773 branch-misses # 2.10% of all branches = ( +- 0.65% ) [83.33%] 20.850558455 seconds time elapsed = ( +- 0.55% ) That is, 2.70% slowdown. The perf difference shrinks a bit when using a high-performance allocator such as tcmalloc: Before: 19372.008814 task-clock # 0.957 CPUs utilized = ( +- 1.00% ) 23,621 context-switches # 0.001 M/sec = ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 13,289 page-faults # 0.001 M/sec = ( +- 1.46% ) 55,824,272,818 cycles # 2.882 GHz = ( +- 1.00% ) [83.33%] 25,284,946,453 stalled-cycles-frontend # 45.29% frontend cycles idl= e ( +- 1.12% ) [83.32%] 17,100,517,753 stalled-cycles-backend # 30.63% backend cycles idl= e ( +- 0.86% ) [66.69%] 78,193,046,990 instructions # 1.40 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.14% ) [83.35%] 12,986,014,194 branches # 670.349 M/sec = ( +- 1.22% ) [83.34%] 272,581,789 branch-misses # 2.10% of all branches = ( +- 0.62% ) [83.33%] 20.249726404 seconds time elapsed = ( +- 0.61% ) After: 19809.295886 task-clock # 0.962 CPUs utilized = ( +- 0.99% ) 23,894 context-switches # 0.001 M/sec = ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 12,927 page-faults # 0.001 M/sec = ( +- 0.78% ) 57,131,686,004 cycles # 2.884 GHz = ( +- 0.97% ) [83.34%] 25,965,120,001 stalled-cycles-frontend # 45.45% frontend cycles idl= e ( +- 0.71% ) [83.35%] 17,534,942,176 stalled-cycles-backend # 30.69% backend cycles idl= e ( +- 0.54% ) [66.68%] 80,000,003,715 instructions # 1.40 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.24% ) [83.34%] 13,327,272,806 branches # 672.779 M/sec = ( +- 1.31% ) [83.34%] 273,622,661 branch-misses # 2.05% of all branches = ( +- 0.95% ) [83.31%] 20.601366430 seconds time elapsed = ( +- 0.60% ) That is, 1.77% slowdown. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- tcg/optimize.c | 307 ++++++++++++++++++++++++++++++-----------------------= ---- 1 file changed, 162 insertions(+), 145 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index adfc56c..b727a4a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -40,21 +40,18 @@ struct tcg_temp_info { tcg_target_ulong mask; }; =20 -static struct tcg_temp_info temps[TCG_MAX_TEMPS]; -static TCGTempSet temps_used; - -static inline bool temp_is_const(TCGArg arg) +static inline bool temp_is_const(const struct tcg_temp_info *temps, TCGArg= arg) { return temps[arg].is_const; } =20 -static inline bool temp_is_copy(TCGArg arg) +static inline bool temp_is_copy(const struct tcg_temp_info *temps, TCGArg = arg) { return temps[arg].next_copy !=3D arg; } =20 /* Reset TEMP's state, possibly removing the temp for the list of copies. = */ -static void reset_temp(TCGArg temp) +static void reset_temp(struct tcg_temp_info *temps, TCGArg temp) { temps[temps[temp].next_copy].prev_copy =3D temps[temp].prev_copy; temps[temps[temp].prev_copy].next_copy =3D temps[temp].next_copy; @@ -64,21 +61,16 @@ static void reset_temp(TCGArg temp) temps[temp].mask =3D -1; } =20 -/* Reset all temporaries, given that there are NB_TEMPS of them. */ -static void reset_all_temps(int nb_temps) -{ - bitmap_zero(temps_used.l, nb_temps); -} - /* Initialize and activate a temporary. */ -static void init_temp_info(TCGArg temp) +static void init_temp_info(struct tcg_temp_info *temps, + unsigned long *temps_used, TCGArg temp) { - if (!test_bit(temp, temps_used.l)) { + if (!test_bit(temp, temps_used)) { temps[temp].next_copy =3D temp; temps[temp].prev_copy =3D temp; temps[temp].is_const =3D false; temps[temp].mask =3D -1; - set_bit(temp, temps_used.l); + set_bit(temp, temps_used); } } =20 @@ -116,7 +108,8 @@ static TCGOpcode op_to_movi(TCGOpcode op) } } =20 -static TCGArg find_better_copy(TCGContext *s, TCGArg temp) +static TCGArg find_better_copy(TCGContext *s, const struct tcg_temp_info *= temps, + TCGArg temp) { TCGArg i; =20 @@ -145,7 +138,8 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg te= mp) return temp; } =20 -static bool temps_are_copies(TCGArg arg1, TCGArg arg2) +static bool temps_are_copies(const struct tcg_temp_info *temps, TCGArg arg= 1, + TCGArg arg2) { TCGArg i; =20 @@ -153,7 +147,7 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return true; } =20 - if (!temp_is_copy(arg1) || !temp_is_copy(arg2)) { + if (!temp_is_copy(temps, arg1) || !temp_is_copy(temps, arg2)) { return false; } =20 @@ -166,15 +160,15 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return false; } =20 -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg val) +static void tcg_opt_gen_movi(TCGContext *s, struct tcg_temp_info *temps, + TCGOp *op, TCGArg *args, TCGArg dst, TCGArg v= al) { TCGOpcode new_op =3D op_to_movi(op->opc); tcg_target_ulong mask; =20 op->opc =3D new_op; =20 - reset_temp(dst); + reset_temp(temps, dst); temps[dst].is_const =3D true; temps[dst].val =3D val; mask =3D val; @@ -188,10 +182,10 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op= , TCGArg *args, args[1] =3D val; } =20 -static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg src) +static void tcg_opt_gen_mov(TCGContext *s, struct tcg_temp_info *temps, + TCGOp *op, TCGArg *args, TCGArg dst, TCGArg sr= c) { - if (temps_are_copies(dst, src)) { + if (temps_are_copies(temps, dst, src)) { tcg_op_remove(s, op); return; } @@ -201,7 +195,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, T= CGArg *args, =20 op->opc =3D new_op; =20 - reset_temp(dst); + reset_temp(temps, dst); mask =3D temps[src].mask; if (TCG_TARGET_REG_BITS > 32 && new_op =3D=3D INDEX_op_mov_i32) { /* High bits of the destination are now garbage. */ @@ -463,10 +457,11 @@ static bool do_constant_folding_cond_eq(TCGCond c) =20 /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, - TCGArg y, TCGCond c) +static TCGArg +do_constant_folding_cond(const struct tcg_temp_info *temps, TCGOpcode op, + TCGArg x, TCGArg y, TCGCond c) { - if (temp_is_const(x) && temp_is_const(y)) { + if (temp_is_const(temps, x) && temp_is_const(temps, y)) { switch (op_bits(op)) { case 32: return do_constant_folding_cond_32(temps[x].val, temps[y].val,= c); @@ -475,9 +470,9 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TC= GArg x, default: tcg_abort(); } - } else if (temps_are_copies(x, y)) { + } else if (temps_are_copies(temps, x, y)) { return do_constant_folding_cond_eq(c); - } else if (temp_is_const(y) && temps[y].val =3D=3D 0) { + } else if (temp_is_const(temps, y) && temps[y].val =3D=3D 0) { switch (c) { case TCG_COND_LTU: return 0; @@ -492,15 +487,17 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, = TCGArg x, =20 /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) +static TCGArg +do_constant_folding_cond2(const struct tcg_temp_info *temps, TCGArg *p1, + TCGArg *p2, TCGCond c) { TCGArg al =3D p1[0], ah =3D p1[1]; TCGArg bl =3D p2[0], bh =3D p2[1]; =20 - if (temp_is_const(bl) && temp_is_const(bh)) { + if (temp_is_const(temps, bl) && temp_is_const(temps, bh)) { uint64_t b =3D ((uint64_t)temps[bh].val << 32) | (uint32_t)temps[b= l].val; =20 - if (temp_is_const(al) && temp_is_const(ah)) { + if (temp_is_const(temps, al) && temp_is_const(temps, ah)) { uint64_t a; a =3D ((uint64_t)temps[ah].val << 32) | (uint32_t)temps[al].va= l; return do_constant_folding_cond_64(a, b, c); @@ -516,18 +513,19 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, T= CGArg *p2, TCGCond c) } } } - if (temps_are_copies(al, bl) && temps_are_copies(ah, bh)) { + if (temps_are_copies(temps, al, bl) && temps_are_copies(temps, ah, bh)= ) { return do_constant_folding_cond_eq(c); } return 2; } =20 -static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) +static bool swap_commutative(const struct tcg_temp_info *temps, TCGArg des= t, + TCGArg *p1, TCGArg *p2) { TCGArg a1 =3D *p1, a2 =3D *p2; int sum =3D 0; - sum +=3D temp_is_const(a1); - sum -=3D temp_is_const(a2); + sum +=3D temp_is_const(temps, a1); + sum -=3D temp_is_const(temps, a2); =20 /* Prefer the constant in second argument, and then the form op a, a, b, which is better handled on non-RISC hosts. */ @@ -539,13 +537,14 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1,= TCGArg *p2) return false; } =20 -static bool swap_commutative2(TCGArg *p1, TCGArg *p2) +static bool swap_commutative2(const struct tcg_temp_info *temps, TCGArg *p= 1, + TCGArg *p2) { int sum =3D 0; - sum +=3D temp_is_const(p1[0]); - sum +=3D temp_is_const(p1[1]); - sum -=3D temp_is_const(p2[0]); - sum -=3D temp_is_const(p2[1]); + sum +=3D temp_is_const(temps, p1[0]); + sum +=3D temp_is_const(temps, p1[1]); + sum -=3D temp_is_const(temps, p2[0]); + sum -=3D temp_is_const(temps, p2[1]); if (sum > 0) { TCGArg t; t =3D p1[0], p1[0] =3D p2[0], p2[0] =3D t; @@ -558,6 +557,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { + struct tcg_temp_info *temps; + unsigned long *temps_used; int oi, oi_next, nb_temps, nb_globals; TCGArg *prev_mb_args =3D NULL; =20 @@ -568,7 +569,8 @@ void tcg_optimize(TCGContext *s) =20 nb_temps =3D s->nb_temps; nb_globals =3D s->nb_globals; - reset_all_temps(nb_temps); + temps =3D g_new(struct tcg_temp_info, nb_temps); + temps_used =3D bitmap_new(nb_temps); =20 for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { tcg_target_ulong mask, partmask, affected; @@ -590,21 +592,21 @@ void tcg_optimize(TCGContext *s) for (i =3D 0; i < nb_oargs + nb_iargs; i++) { tmp =3D args[i]; if (tmp !=3D TCG_CALL_DUMMY_ARG) { - init_temp_info(tmp); + init_temp_info(temps, temps_used, tmp); } } } else { nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; for (i =3D 0; i < nb_oargs + nb_iargs; i++) { - init_temp_info(args[i]); + init_temp_info(temps, temps_used, args[i]); } } =20 /* Do copy propagation */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { - if (temp_is_copy(args[i])) { - args[i] =3D find_better_copy(s, args[i]); + if (temp_is_copy(temps, args[i])) { + args[i] =3D find_better_copy(s, temps, args[i]); } } =20 @@ -620,44 +622,44 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(nor): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - swap_commutative(args[0], &args[1], &args[2]); + swap_commutative(temps, args[0], &args[1], &args[2]); break; CASE_OP_32_64(brcond): - if (swap_commutative(-1, &args[0], &args[1])) { + if (swap_commutative(temps, -1, &args[0], &args[1])) { args[2] =3D tcg_swap_cond(args[2]); } break; CASE_OP_32_64(setcond): - if (swap_commutative(args[0], &args[1], &args[2])) { + if (swap_commutative(temps, args[0], &args[1], &args[2])) { args[3] =3D tcg_swap_cond(args[3]); } break; CASE_OP_32_64(movcond): - if (swap_commutative(-1, &args[1], &args[2])) { + if (swap_commutative(temps, -1, &args[1], &args[2])) { args[5] =3D tcg_swap_cond(args[5]); } /* For movcond, we canonicalize the "false" input reg to match the destination reg so that the tcg backend can implement a "move if true" operation. */ - if (swap_commutative(args[0], &args[4], &args[3])) { + if (swap_commutative(temps, args[0], &args[4], &args[3])) { args[5] =3D tcg_invert_cond(args[5]); } break; CASE_OP_32_64(add2): - swap_commutative(args[0], &args[2], &args[4]); - swap_commutative(args[1], &args[3], &args[5]); + swap_commutative(temps, args[0], &args[2], &args[4]); + swap_commutative(temps, args[1], &args[3], &args[5]); break; CASE_OP_32_64(mulu2): CASE_OP_32_64(muls2): - swap_commutative(args[0], &args[2], &args[3]); + swap_commutative(temps, args[0], &args[2], &args[3]); break; case INDEX_op_brcond2_i32: - if (swap_commutative2(&args[0], &args[2])) { + if (swap_commutative2(temps, &args[0], &args[2])) { args[4] =3D tcg_swap_cond(args[4]); } break; case INDEX_op_setcond2_i32: - if (swap_commutative2(&args[1], &args[3])) { + if (swap_commutative2(temps, &args[1], &args[3])) { args[5] =3D tcg_swap_cond(args[5]); } break; @@ -673,8 +675,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(sar): CASE_OP_32_64(rotl): CASE_OP_32_64(rotr): - if (temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temp_is_const(temps, args[1]) && temps[args[1]].val =3D=3D= 0) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -683,7 +685,7 @@ void tcg_optimize(TCGContext *s) TCGOpcode neg_op; bool have_neg; =20 - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { /* Proceed with possible constant folding. */ break; } @@ -697,9 +699,9 @@ void tcg_optimize(TCGContext *s) if (!have_neg) { break; } - if (temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0)= { + if (temp_is_const(temps, args[1]) && temps[args[1]].val = =3D=3D 0) { op->opc =3D neg_op; - reset_temp(args[0]); + reset_temp(temps, args[0]); args[1] =3D args[2]; continue; } @@ -707,30 +709,30 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(xor): CASE_OP_32_64(nand): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D -1)= { + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D -1) { i =3D 1; goto try_not; } break; CASE_OP_32_64(nor): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0) { + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D 0) { i =3D 1; goto try_not; } break; CASE_OP_32_64(andc): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val =3D=3D -1)= { + if (!temp_is_const(temps, args[2]) + && temp_is_const(temps, args[1]) && temps[args[1]].val =3D= =3D -1) { i =3D 2; goto try_not; } break; CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val =3D=3D 0) { + if (!temp_is_const(temps, args[2]) + && temp_is_const(temps, args[1]) && temps[args[1]].val =3D= =3D 0) { i =3D 2; goto try_not; } @@ -751,7 +753,7 @@ void tcg_optimize(TCGContext *s) break; } op->opc =3D not_op; - reset_temp(args[0]); + reset_temp(temps, args[0]); args[1] =3D args[i]; continue; } @@ -771,18 +773,18 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(or): CASE_OP_32_64(xor): CASE_OP_32_64(andc): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D 0) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; CASE_OP_32_64(and): CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val =3D=3D -1)= { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D -1) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; @@ -819,7 +821,7 @@ void tcg_optimize(TCGContext *s) =20 CASE_OP_32_64(and): mask =3D temps[args[2]].mask; - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { and_const: affected =3D temps[args[1]].mask & ~mask; } @@ -838,7 +840,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): /* Known-zeros does not imply known-ones. Therefore unless args[2] is constant, we can't infer anything from it. */ - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { mask =3D ~temps[args[2]].mask; goto and_const; } @@ -847,26 +849,26 @@ void tcg_optimize(TCGContext *s) break; =20 case INDEX_op_sar_i32: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 31; mask =3D (int32_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_sar_i64: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 63; mask =3D (int64_t)temps[args[1]].mask >> tmp; } break; =20 case INDEX_op_shr_i32: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 31; mask =3D (uint32_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_shr_i64: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & 63; mask =3D (uint64_t)temps[args[1]].mask >> tmp; } @@ -880,7 +882,7 @@ void tcg_optimize(TCGContext *s) break; =20 CASE_OP_32_64(shl): - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp =3D temps[args[2]].val & (TCG_TARGET_REG_BITS - 1); mask =3D temps[args[1]].mask << tmp; } @@ -976,12 +978,12 @@ void tcg_optimize(TCGContext *s) =20 if (partmask =3D=3D 0) { tcg_debug_assert(nb_oargs =3D=3D 1); - tcg_opt_gen_movi(s, op, args, args[0], 0); + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } if (affected =3D=3D 0) { tcg_debug_assert(nb_oargs =3D=3D 1); - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } =20 @@ -991,8 +993,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mul): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - if ((temp_is_const(args[2]) && temps[args[2]].val =3D=3D 0)) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if ((temp_is_const(temps, args[2]) && temps[args[2]].val =3D= =3D 0)) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -1004,8 +1006,8 @@ void tcg_optimize(TCGContext *s) switch (opc) { CASE_OP_32_64(or): CASE_OP_32_64(and): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (temps_are_copies(temps, args[1], args[2])) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; @@ -1018,8 +1020,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): CASE_OP_32_64(sub): CASE_OP_32_64(xor): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temps_are_copies(temps, args[1], args[2])) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -1032,10 +1034,10 @@ void tcg_optimize(TCGContext *s) allocator where needed and possible. Also detect copies. */ switch (opc) { CASE_OP_32_64(mov): - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); break; CASE_OP_32_64(movi): - tcg_opt_gen_movi(s, op, args, args[0], args[1]); + tcg_opt_gen_movi(s, temps, op, args, args[0], args[1]); break; =20 CASE_OP_32_64(not): @@ -1051,9 +1053,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp =3D do_constant_folding(opc, temps[args[1]].val, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; @@ -1080,66 +1082,70 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(divu): CASE_OP_32_64(rem): CASE_OP_32_64(remu): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { + if (temp_is_const(temps, args[1]) && + temp_is_const(temps, args[2])) { tmp =3D do_constant_folding(opc, temps[args[1]].val, temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(clz): CASE_OP_32_64(ctz): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { TCGArg v =3D temps[args[1]].val; if (v !=3D 0) { tmp =3D do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); } else { - tcg_opt_gen_mov(s, op, args, args[0], args[2]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[2]); } break; } goto do_default; =20 CASE_OP_32_64(deposit): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { + if (temp_is_const(temps, args[1]) && + temp_is_const(temps, args[2])) { tmp =3D deposit64(temps[args[1]].val, args[3], args[4], temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(extract): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp =3D extract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(sextract): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp =3D sextract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(setcond): - tmp =3D do_constant_folding_cond(opc, args[1], args[2], args[3= ]); + tmp =3D do_constant_folding_cond(temps, opc, args[1], args[2], + args[3]); if (tmp !=3D 2) { - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; =20 CASE_OP_32_64(brcond): - tmp =3D do_constant_folding_cond(opc, args[0], args[1], args[2= ]); + tmp =3D do_constant_folding_cond(temps, opc, args[0], args[1], + args[2]); if (tmp !=3D 2) { if (tmp) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_br; args[0] =3D args[3]; } else { @@ -1150,12 +1156,14 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 CASE_OP_32_64(movcond): - tmp =3D do_constant_folding_cond(opc, args[1], args[2], args[5= ]); + tmp =3D do_constant_folding_cond(temps, opc, args[1], args[2], + args[5]); if (tmp !=3D 2) { - tcg_opt_gen_mov(s, op, args, args[0], args[4-tmp]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[4 - tmp]= ); break; } - if (temp_is_const(args[3]) && temp_is_const(args[4])) { + if (temp_is_const(temps, args[3]) && + temp_is_const(temps, args[4])) { tcg_target_ulong tv =3D temps[args[3]].val; tcg_target_ulong fv =3D temps[args[4]].val; TCGCond cond =3D args[5]; @@ -1174,8 +1182,10 @@ void tcg_optimize(TCGContext *s) =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3]) - && temp_is_const(args[4]) && temp_is_const(args[5])) { + if (temp_is_const(temps, args[2]) && + temp_is_const(temps, args[3]) && + temp_is_const(temps, args[4]) && + temp_is_const(temps, args[5])) { uint32_t al =3D temps[args[2]].val; uint32_t ah =3D temps[args[3]].val; uint32_t bl =3D temps[args[4]].val; @@ -1194,8 +1204,8 @@ void tcg_optimize(TCGContext *s) =20 rl =3D args[0]; rh =3D args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(s, temps, op, args, rl, (int32_t)a); + tcg_opt_gen_movi(s, temps, op2, args2, rh, (int32_t)(a >> = 32)); =20 /* We've done all we need to do with the movi. Skip it. = */ oi_next =3D op2->next; @@ -1204,7 +1214,8 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_mulu2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3])) { + if (temp_is_const(temps, args[2]) && + temp_is_const(temps, args[3])) { uint32_t a =3D temps[args[2]].val; uint32_t b =3D temps[args[3]].val; uint64_t r =3D (uint64_t)a * b; @@ -1214,8 +1225,8 @@ void tcg_optimize(TCGContext *s) =20 rl =3D args[0]; rh =3D args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(s, temps, op, args, rl, (int32_t)r); + tcg_opt_gen_movi(s, temps, op2, args2, rh, (int32_t)(r >> = 32)); =20 /* We've done all we need to do with the movi. Skip it. = */ oi_next =3D op2->next; @@ -1224,11 +1235,11 @@ void tcg_optimize(TCGContext *s) goto do_default; =20 case INDEX_op_brcond2_i32: - tmp =3D do_constant_folding_cond2(&args[0], &args[2], args[4]); + tmp =3D do_constant_folding_cond2(temps, &args[0], &args[2], a= rgs[4]); if (tmp !=3D 2) { if (tmp) { do_brcond_true: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_br; args[0] =3D args[5]; } else { @@ -1236,12 +1247,14 @@ void tcg_optimize(TCGContext *s) tcg_op_remove(s, op); } } else if ((args[4] =3D=3D TCG_COND_LT || args[4] =3D=3D TCG_C= OND_GE) - && temp_is_const(args[2]) && temps[args[2]].val =3D= =3D 0 - && temp_is_const(args[3]) && temps[args[3]].val =3D= =3D 0) { + && temp_is_const(temps, args[2]) + && temps[args[2]].val =3D=3D 0 + && temp_is_const(temps, args[3]) + && temps[args[3]].val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_brcond_i32; args[0] =3D args[1]; args[1] =3D args[3]; @@ -1250,14 +1263,14 @@ void tcg_optimize(TCGContext *s) } else if (args[4] =3D=3D TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[0], args[2], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_brcond_false; } else if (tmp =3D=3D 1) { goto do_brcond_high; } - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[1], args[3], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_brcond_false; @@ -1265,7 +1278,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc =3D INDEX_op_brcond_i32; args[1] =3D args[2]; args[2] =3D args[4]; @@ -1273,14 +1286,14 @@ void tcg_optimize(TCGContext *s) } else if (args[4] =3D=3D TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[0], args[2], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_brcond_high; } else if (tmp =3D=3D 1) { goto do_brcond_true; } - tmp =3D do_constant_folding_cond(INDEX_op_brcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_brcond_i3= 2, args[1], args[3], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_brcond_low; @@ -1294,17 +1307,19 @@ void tcg_optimize(TCGContext *s) break; =20 case INDEX_op_setcond2_i32: - tmp =3D do_constant_folding_cond2(&args[1], &args[3], args[5]); + tmp =3D do_constant_folding_cond2(temps, &args[1], &args[3], a= rgs[5]); if (tmp !=3D 2) { do_setcond_const: - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); } else if ((args[5] =3D=3D TCG_COND_LT || args[5] =3D=3D TCG_C= OND_GE) - && temp_is_const(args[3]) && temps[args[3]].val =3D= =3D 0 - && temp_is_const(args[4]) && temps[args[4]].val =3D= =3D 0) { + && temp_is_const(temps, args[3]) + && temps[args[3]].val =3D=3D 0 + && temp_is_const(temps, args[4]) + && temps[args[4]].val =3D=3D 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_setcond_high: - reset_temp(args[0]); + reset_temp(temps, args[0]); temps[args[0]].mask =3D 1; op->opc =3D INDEX_op_setcond_i32; args[1] =3D args[2]; @@ -1313,14 +1328,14 @@ void tcg_optimize(TCGContext *s) } else if (args[5] =3D=3D TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[1], args[3], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_setcond_const; } else if (tmp =3D=3D 1) { goto do_setcond_high; } - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[2], args[4], TCG_COND_= EQ); if (tmp =3D=3D 0) { goto do_setcond_high; @@ -1328,7 +1343,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_setcond_low: - reset_temp(args[0]); + reset_temp(temps, args[0]); temps[args[0]].mask =3D 1; op->opc =3D INDEX_op_setcond_i32; args[2] =3D args[3]; @@ -1336,14 +1351,14 @@ void tcg_optimize(TCGContext *s) } else if (args[5] =3D=3D TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[1], args[3], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_setcond_high; } else if (tmp =3D=3D 1) { goto do_setcond_const; } - tmp =3D do_constant_folding_cond(INDEX_op_setcond_i32, + tmp =3D do_constant_folding_cond(temps, INDEX_op_setcond_i= 32, args[2], args[4], TCG_COND_= NE); if (tmp =3D=3D 0) { goto do_setcond_low; @@ -1360,8 +1375,8 @@ void tcg_optimize(TCGContext *s) if (!(args[nb_oargs + nb_iargs + 1] & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS)= )) { for (i =3D 0; i < nb_globals; i++) { - if (test_bit(i, temps_used.l)) { - reset_temp(i); + if (test_bit(i, temps_used)) { + reset_temp(temps, i); } } } @@ -1375,11 +1390,11 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); } else { do_reset_output: for (i =3D 0; i < nb_oargs; i++) { - reset_temp(args[i]); + reset_temp(temps, args[i]); /* Save the corresponding known-zero bits mask for the first output argument (only one supported so far). = */ if (i =3D=3D 0) { @@ -1428,4 +1443,6 @@ void tcg_optimize(TCGContext *s) prev_mb_args =3D args; } } + g_free(temps); + g_free(temps_used); } --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521154725726.9301312002037; Wed, 19 Jul 2017 20:25:54 -0700 (PDT) Received: from localhost ([::1]:35866 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY264-0000c8-Te for importer@patchew.org; Wed, 19 Jul 2017 23:25:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60349) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qR-00018V-PX for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qM-0005vy-UP for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:43 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:51671) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qM-0005u8-Mh for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 266C820B7A; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:38 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id DF2BC7E057; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=ggJ QIiv7qUT6i/iWyffACyGbbxcEugzNhSte9akN/uE=; b=Sc6Hcr0lxKgV8vBojV6 uIP6wlSwhtYuDM0EK02nBNAk4q/JGRVru+8kNVQBoZ/R4+tht7hva8Zf0xKewHXH IrHZAIUPZ0vMDoWpc2LRlBcfSeq9MMC1tuW3ewdczPHaK3xvKAZclOKhlfFM77z6 Hezefpl3IyeM3yT4RnSC6Xz8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=ggJQIiv7qUT6i/iWyffACyGbbxcEugzNhSte9akN/ uE=; b=W7MYLoHpOlqRVXczyUZwoJ/hesYBIy43BXSkqO2ZsZu7kZk6eCr5ZBqf4 OUPM1LRLabyWddWLe11Vy/x2Xru3zBLSKWsvuBNF6DMmZJxfi0+xgNV+RhE8NlTZ 2u2o341np3jlPGvr0Kz6GJm7+l3hZwDUwijuG22vr0bgNBNhN1dEPFvVVQEwQbC3 YgkFHdpM04EVD9cQLa5oQvSt/UtUGm0eUIasLAG9hBC4efeRsbplRE4S4JA3GrsU v6xKDnSUBtvOV41Dvf6mB1ctrLY7dvslljbCTfy5sGru9Ipwu/7m98B56+FzeKcP ZOaOUJBRL+jFP5ptA/HFLLeCFkifQ== X-ME-Sender: X-Sasl-enc: FMfdrMgonB4e44PvB456CBSvof4SDhjLr9/IRGWU2AAL 1500520177 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:22 -0400 Message-Id: <1500520169-23367-37-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 36/43] tcg: introduce **tcg_ctxs to keep track of all TCGContext's X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. Note that having n_tcg_ctxs is unnecessary. However, it is convenient to have it, since it will simplify iterating over the array: we'll have just a for loop instead of having to iterate over a NULL-terminated array (which would require n+1 elems) or having to check with ifdef's for usermode/softmmu. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- tcg/tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index f907c47..2217314 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,6 +115,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static void tcg_out_tb_init(TCGContext *s); static bool tcg_out_tb_finalize(TCGContext *s); =20 +static TCGContext **tcg_ctxs; +static unsigned int n_tcg_ctxs; =20 static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; @@ -382,6 +384,8 @@ void tcg_context_init(TCGContext *s) } =20 tcg_ctx =3D s; + tcg_ctxs =3D &tcg_ctx; + n_tcg_ctxs =3D 1; } =20 /* --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521671089913.2430033996163; Wed, 19 Jul 2017 20:34:31 -0700 (PDT) Received: from localhost ([::1]:35906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2EP-0007ia-7G for importer@patchew.org; Wed, 19 Jul 2017 23:34:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qT-0001Af-Ld for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qN-0005wA-3S for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:45 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:41411) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qM-0005ue-NF for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 5747820B77; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:38 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 169822418A; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=kCx LoMwLWZbYv4XNvIWzY0frNjMS6RkimQOCi9a9cT4=; b=PyLFpBoiNbnEs8q9UIv EXeQRbCDFxngTSdqWUWu09GhQGCK/QrKUbaduAUXQeIDsSbZspTAS0lZeRw8Dd2m 0ukPdqgWjK12uDZBpOP4b8T9/38nCpyVAPMi56Qxpm0IkVkq1wbaKVdo4rkjNI1B XH+jaj8Wf0DRmqhF7VitI4UA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=kCxLoMwLWZbYv4XNvIWzY0frNjMS6RkimQOCi9a9c T4=; b=g2WDa2QPJaUSuCNzMT7LmQvhHTJ1fQ77oF+LppPn+zpvBLodE02MQv870 u2y1tllrPSQ4BzB+XP8xcfQPFO264Ezxi8UQbC/tpi9RQXRqLadfRF5YikW1Mlj4 iKmRrUlwnVadSHc5NbFpK0OXz5uav4VY4v+p8L/4jRGlUBmdiFOluSasHRlCUWD+ i3sKVfVeh+sIaoPbL0l4HDXPnPmChWVso18maOZhR8FWIFTYN8tS8GKXMiIiYJop K3MEjLC8VwaG+glkE4efxldVF8zN6jNLT9KbNULDvYNwwUDfoK9mmsyqjqJe3w5j VwJg1wCvLZy6IHBKJAFYbWRP8vBjg== X-ME-Sender: X-Sasl-enc: bSG7ixaPuejl+igVLxjsOX5fqf86U+79CQiXx1QVSFei 1500520178 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:23 -0400 Message-Id: <1500520169-23367-38-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 37/43] tcg: distribute profiling counters across TCGContext's X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is groundwork for supporting multiple TCG contexts. To avoid scalability issues when profiling info is enabled, this patch makes the profiling info counters distributed via the following changes: 1) Consolidate profile info into its own struct, TCGProfile, which TCGContext also includes. Note that tcg_table_op_count is brought into TCGProfile after dropping the tcg_ prefix. 2) Iterate over the TCG contexts in the system to obtain the total counts. This change also requires updating the accessors to TCGProfile fields to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to them. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 38 +++++++++------- accel/tcg/translate-all.c | 23 +++++----- tcg/tcg.c | 110 ++++++++++++++++++++++++++++++++++++++----= ---- 3 files changed, 126 insertions(+), 45 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index f83f9b0..3611141 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -641,6 +641,26 @@ QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14)); /* Make sure that we don't overflow 64 bits without noticing. */ QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8); =20 +typedef struct TCGProfile { + int64_t tb_count1; + int64_t tb_count; + int64_t op_count; /* total insn count */ + int op_count_max; /* max insn per TB */ + int64_t temp_count; + int temp_count_max; + int64_t del_op_count; + int64_t code_in_len; + int64_t code_out_len; + int64_t search_out_len; + int64_t interm_time; + int64_t code_time; + int64_t la_time; + int64_t opt_time; + int64_t restore_count; + int64_t restore_time; + int64_t table_op_count[NB_OPS]; +} TCGProfile; + struct TCGContext { uint8_t *pool_cur, *pool_end; TCGPool *pool_first, *pool_current, *pool_first_large; @@ -665,23 +685,7 @@ struct TCGContext { tcg_insn_unit *code_ptr; =20 #ifdef CONFIG_PROFILER - /* profiling info */ - int64_t tb_count1; - int64_t tb_count; - int64_t op_count; /* total insn count */ - int op_count_max; /* max insn per TB */ - int64_t temp_count; - int temp_count_max; - int64_t del_op_count; - int64_t code_in_len; - int64_t code_out_len; - int64_t search_out_len; - int64_t interm_time; - int64_t code_time; - int64_t la_time; - int64_t opt_time; - int64_t restore_count; - int64_t restore_time; + TCGProfile prof; #endif =20 #ifdef CONFIG_DEBUG_TCG diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index e6ee4e3..36b17ac 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -312,6 +312,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti =3D profile_getclock(); #endif =20 @@ -346,8 +347,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER - tcg_ctx->restore_time +=3D profile_getclock() - ti; - tcg_ctx->restore_count++; + atomic_set(&prof->restore_time, + prof->restore_time + profile_getclock() - ti); + atomic_set(&prof->restore_count, prof->restore_count + 1); #endif return 0; } @@ -1302,6 +1304,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_insn_unit *gen_code_buf; int gen_code_size, search_size; #ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti; #endif assert_memory_lock(); @@ -1332,8 +1335,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER - tcg_ctx->tb_count1++; /* includes aborted translations because of - exceptions */ + /* includes aborted translations because of exceptions */ + atomic_set(&prof->tb_count1, prof->tb_count1 + 1); ti =3D profile_getclock(); #endif =20 @@ -1358,8 +1361,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #endif =20 #ifdef CONFIG_PROFILER - tcg_ctx->tb_count++; - tcg_ctx->interm_time +=3D profile_getclock() - ti; + atomic_set(&prof->tb_count, prof->tb_count + 1); + atomic_set(&prof->interm_time, prof->interm_time + profile_getclock() = - ti); ti =3D profile_getclock(); #endif =20 @@ -1379,10 +1382,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER - tcg_ctx->code_time +=3D profile_getclock() - ti; - tcg_ctx->code_in_len +=3D tb->size; - tcg_ctx->code_out_len +=3D gen_code_size; - tcg_ctx->search_out_len +=3D search_size; + atomic_set(&prof->code_time, prof->code_time + profile_getclock() - ti= ); + atomic_set(&prof->code_in_len, prof->code_in_len + tb->size); + atomic_set(&prof->code_out_len, prof->code_out_len + gen_code_size); + atomic_set(&prof->search_out_len, prof->search_out_len + search_size); #endif =20 #ifdef DEBUG_DISAS diff --git a/tcg/tcg.c b/tcg/tcg.c index 2217314..0ddd0dc 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1344,7 +1344,7 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) memset(op, 0, sizeof(*op)); =20 #ifdef CONFIG_PROFILER - s->del_op_count++; + atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); #endif } =20 @@ -2515,15 +2515,79 @@ static void tcg_reg_alloc_call(TCGContext *s, int n= b_oargs, int nb_iargs, =20 #ifdef CONFIG_PROFILER =20 -static int64_t tcg_table_op_count[NB_OPS]; +/* avoid copy/paste errors */ +#define PROF_ADD(to, from, field) \ + do { \ + (to)->field +=3D atomic_read(&((from)->field)); \ + } while (0) + +#define PROF_MAX(to, from, field) \ + do { \ + typeof((from)->field) val__ =3D atomic_read(&((from)->field)); \ + if (val__ > (to)->field) { \ + (to)->field =3D val__; \ + } \ + } while (0) + +/* Pass in a zero'ed @prof */ +static inline +void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) +{ + unsigned int i; + + for (i =3D 0; i < n_tcg_ctxs; i++) { + const TCGProfile *orig =3D &tcg_ctxs[i]->prof; + + if (counters) { + PROF_ADD(prof, orig, tb_count1); + PROF_ADD(prof, orig, tb_count); + PROF_ADD(prof, orig, op_count); + PROF_MAX(prof, orig, op_count_max); + PROF_ADD(prof, orig, temp_count); + PROF_MAX(prof, orig, temp_count_max); + PROF_ADD(prof, orig, del_op_count); + PROF_ADD(prof, orig, code_in_len); + PROF_ADD(prof, orig, code_out_len); + PROF_ADD(prof, orig, search_out_len); + PROF_ADD(prof, orig, interm_time); + PROF_ADD(prof, orig, code_time); + PROF_ADD(prof, orig, la_time); + PROF_ADD(prof, orig, opt_time); + PROF_ADD(prof, orig, restore_count); + PROF_ADD(prof, orig, restore_time); + } + if (table) { + int i; + + for (i =3D 0; i < NB_OPS; i++) { + PROF_ADD(prof, orig, table_op_count[i]); + } + } + } +} + +#undef PROF_ADD +#undef PROF_MAX + +static void tcg_profile_snapshot_counters(TCGProfile *prof) +{ + tcg_profile_snapshot(prof, true, false); +} + +static void tcg_profile_snapshot_table(TCGProfile *prof) +{ + tcg_profile_snapshot(prof, false, true); +} =20 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) { + TCGProfile prof =3D {}; int i; =20 + tcg_profile_snapshot_table(&prof); for (i =3D 0; i < NB_OPS; i++) { cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, - tcg_table_op_count[i]); + prof.table_op_count[i]); } } #else @@ -2536,6 +2600,9 @@ void tcg_dump_op_count(FILE *f, fprintf_function cpu_= fprintf) =20 int tcg_gen_code(TCGContext *s, TranslationBlock *tb) { +#ifdef CONFIG_PROFILER + TCGProfile *prof =3D &s->prof; +#endif int i, oi, oi_next, num_insns; =20 #ifdef CONFIG_PROFILER @@ -2543,15 +2610,15 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) int n; =20 n =3D s->gen_op_buf[0].prev + 1; - s->op_count +=3D n; - if (n > s->op_count_max) { - s->op_count_max =3D n; + atomic_set(&prof->op_count, prof->op_count + n); + if (n > prof->op_count_max) { + atomic_set(&prof->op_count_max, n); } =20 n =3D s->nb_temps; - s->temp_count +=3D n; - if (n > s->temp_count_max) { - s->temp_count_max =3D n; + atomic_set(&prof->temp_count, prof->temp_count + n); + if (n > prof->temp_count_max) { + atomic_set(&prof->temp_count_max, n); } } #endif @@ -2568,7 +2635,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 #ifdef CONFIG_PROFILER - s->opt_time -=3D profile_getclock(); + atomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); #endif =20 #ifdef USE_TCG_OPTIMIZATIONS @@ -2576,8 +2643,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 #ifdef CONFIG_PROFILER - s->opt_time +=3D profile_getclock(); - s->la_time -=3D profile_getclock(); + atomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); + atomic_set(&prof->la_time, prof->la_time - profile_getclock()); #endif =20 { @@ -2605,7 +2672,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } =20 #ifdef CONFIG_PROFILER - s->la_time +=3D profile_getclock(); + atomic_set(&prof->la_time, prof->la_time + profile_getclock()); #endif =20 #ifdef DEBUG_DISAS @@ -2636,7 +2703,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 oi_next =3D op->next; #ifdef CONFIG_PROFILER - tcg_table_op_count[opc]++; + atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] += 1); #endif =20 switch (opc) { @@ -2712,10 +2779,17 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s =3D tcg_ctx; - int64_t tb_count =3D s->tb_count; - int64_t tb_div_count =3D tb_count ? tb_count : 1; - int64_t tot =3D s->interm_time + s->code_time; + TCGProfile prof =3D {}; + const TCGProfile *s; + int64_t tb_count; + int64_t tb_div_count; + int64_t tot; + + tcg_profile_snapshot_counters(&prof); + s =3D &prof; + tb_count =3D s->tb_count; + tb_div_count =3D tb_count ? tb_count : 1; + tot =3D s->interm_time + s->code_time; =20 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n= ", tot, tot / 2.4e9); --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521530175970.533009818626; Wed, 19 Jul 2017 20:32:10 -0700 (PDT) Received: from localhost ([::1]:35898 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2C8-0005xv-CF for importer@patchew.org; Wed, 19 Jul 2017 23:32:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qS-00019d-Ud for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qN-0005wS-8E for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52273) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qN-0005vG-0V for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7690720B7C; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:38 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 408A57E057; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=/aN +A/ycS1RsDdxF2Qz0rkI6LyJVCzPwVDHUnIpPXvo=; b=N3Fa6rity+z4L2bbZVz C+Uk//7o3dcgt4UP511OAdXePmUwx0Cfrv9tGVAx4dlA1JtluUw/1EZSXVduCBEX cqvPm3YsjqVy2si4ple392i+VGs30ufrYjxsYAIyCXLjmH/n//dsdm+bhewXH521 PtIG7js110xkDziyj1Z05qzA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=/aN+A/ycS1RsDdxF2Qz0rkI6LyJVCzPwVDHUnIpPX vo=; b=kreDjP8zEAPV5dulAinMMM2q5jn36QPjVYGXnhTLQzdbMT8sxRwS+mLId miE+7l3jL+hmqlj5VZaoQd+5tkS//IuGSV/GQAbyydlhnzO+53kJetq+msudplh7 +srFyem8IWm19Z5N4HDHW5Vwz81eF179t+YfcFHCQzdGVKUhaWfDR/Zv/24Y+fox 99dF7q8hRhvjaPl3OdUavDiGBeD9cWuADnWeIGpkXLn8fEhyfCcWDTax+7Rd9CU4 vOh645vTrxCHRvuurohuSuj4VR/sH0OJ2FxvYIz5+SOzy13/0p+ZKae1S6fiZXBN dxQkVyXmuXS7yGSba4GqLO8fq5rxg== X-ME-Sender: X-Sasl-enc: bSG3jBiWruLn5TYKMgHsOX5fqf86U+79CQiXx1QVSFei 1500520178 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:24 -0400 Message-Id: <1500520169-23367-39-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 38/43] util: move qemu_real_host_page_size/mask to osdep.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These only depend on the host and therefore belong in the common osdep, not in a target-dependent object. While at it, query the host during an init constructor, which guarantees the page size will be well-defined throughout the execution of the program. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/cpu-all.h | 2 -- include/qemu/osdep.h | 6 ++++++ exec.c | 4 ---- util/pagesize.c | 18 ++++++++++++++++++ util/Makefile.objs | 1 + 5 files changed, 25 insertions(+), 6 deletions(-) create mode 100644 util/pagesize.c diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ffe43d5..778031c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -229,8 +229,6 @@ extern int target_page_bits; /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even * when intptr_t is 32-bit and we are aligning a long long. */ -extern uintptr_t qemu_real_host_page_size; -extern intptr_t qemu_real_host_page_mask; extern uintptr_t qemu_host_page_size; extern intptr_t qemu_host_page_mask; =20 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 3b74f6f..0cba871 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -481,6 +481,12 @@ char *qemu_get_pid_name(pid_t pid); */ pid_t qemu_fork(Error **errp); =20 +/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even + * when intptr_t is 32-bit and we are aligning a long long. + */ +extern uintptr_t qemu_real_host_page_size; +extern intptr_t qemu_real_host_page_mask; + extern int qemu_icache_linesize; extern int qemu_dcache_linesize; =20 diff --git a/exec.c b/exec.c index 94b0f3e..6e85535 100644 --- a/exec.c +++ b/exec.c @@ -121,8 +121,6 @@ int use_icount; =20 uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; -uintptr_t qemu_real_host_page_size; -intptr_t qemu_real_host_page_mask; =20 bool set_preferred_target_page_bits(int bits) { @@ -3621,8 +3619,6 @@ void page_size_init(void) { /* NOTE: we can always suppose that qemu_host_page_size >=3D TARGET_PAGE_SIZE */ - qemu_real_host_page_size =3D getpagesize(); - qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; if (qemu_host_page_size =3D=3D 0) { qemu_host_page_size =3D qemu_real_host_page_size; } diff --git a/util/pagesize.c b/util/pagesize.c new file mode 100644 index 0000000..998632c --- /dev/null +++ b/util/pagesize.c @@ -0,0 +1,18 @@ +/* + * pagesize.c - query the host about its page size + * + * Copyright (C) 2017, Emilio G. Cota + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +uintptr_t qemu_real_host_page_size; +intptr_t qemu_real_host_page_mask; + +static void __attribute__((constructor)) init_real_host_page_size(void) +{ + qemu_real_host_page_size =3D getpagesize(); + qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; +} diff --git a/util/Makefile.objs b/util/Makefile.objs index 50a55ec..2973b0a 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -40,6 +40,7 @@ util-obj-y +=3D buffer.o util-obj-y +=3D timed-average.o util-obj-y +=3D base64.o util-obj-y +=3D log.o +util-obj-y +=3D pagesize.o util-obj-y +=3D qdist.o util-obj-y +=3D qht.o util-obj-y +=3D range.o --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521389701761.6565931748484; Wed, 19 Jul 2017 20:29:49 -0700 (PDT) Received: from localhost ([::1]:35881 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY29r-0003sM-Tm for importer@patchew.org; Wed, 19 Jul 2017 23:29:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qS-00019H-H8 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qN-0005wn-CB for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:49319) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qN-0005vi-61 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id A2D9820B7D; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:38 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 62E7A241E0; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=gCw LHHgaBKuU85WtV5mvJtL0lEf5k7XFYEi2AR0BBtU=; b=UIi2acXR1aA57vqeMHk xyXB1JlrlctwbDHojNJ1jzZRvdXMLawoOVUCqAH9R1ig5zWn7zUJn7dzSKg7pUtU 1gACCMnLHf7iNUOnO8w6abokQFr9wsYwaTt71zxUUHE3p205b/dI5Afxsir8qcW6 QctitJwpLS7a/a3ok+otbev4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=gCwLHHgaBKuU85WtV5mvJtL0lEf5k7XFYEi2AR0BB tU=; b=WrONtMC+tfXBudUgtvQQM2Fr/93VL2R78Dblrw+bsKLIB3KVx22j1tBd3 dtVfoLXBaePfC+DeP8wG8UzEDz5b1MedCFGWaJ1VMhttvbGcNL/8IRzOLjMC4txu /RnqUmlIq7MuF6IzlEEX0PAf3MW2yC209X1PISRmBEqmyc/YYuHenn11HBfZ6k6v HcNH3xU1A9r1dl2asyAD42PPxTCAI13gvdYN/BvijbuQ9SnBddOlzphUdPRsRttH JUoiBEb8O5IqUQIXeUoiqIs5TbDndiA2Pn7pI6j0uD73oA7djGKcxvFkO921q14W ofzQhaNJLGZcEkQ3aMMkca3/G0hNw== X-ME-Sender: X-Sasl-enc: bSG/nRSSr+3w/S0DNgDsOX5fqf86U+79CQiXx1QVSFei 1500520178 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:25 -0400 Message-Id: <1500520169-23367-40-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 39/43] osdep: introduce qemu_mprotect_rwx/none X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/qemu/osdep.h | 2 ++ util/osdep.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 0cba871..2c7d7db 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -348,6 +348,8 @@ void sigaction_invoke(struct sigaction *action, #endif =20 int qemu_madvise(void *addr, size_t len, int advice); +int qemu_mprotect_rwx(void *addr, size_t size); +int qemu_mprotect_none(void *addr, size_t size); =20 int qemu_open(const char *name, int flags, ...); int qemu_close(int fd); diff --git a/util/osdep.c b/util/osdep.c index a2863c8..f72d679 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -81,6 +81,47 @@ int qemu_madvise(void *addr, size_t len, int advice) #endif } =20 +static int qemu_mprotect__osdep(void *addr, size_t size, int prot) +{ + g_assert(!((uintptr_t)addr & ~qemu_real_host_page_mask)); + g_assert(!(size & ~qemu_real_host_page_mask)); + +#ifdef _WIN32 + DWORD old_protect; + + if (!VirtualProtect(addr, size, prot, &old_protect)) { + error_report("%s: VirtualProtect failed with error code %d", + __func__, GetLastError()); + return -1; + } + return 0; +#else + if (mprotect(addr, size, prot)) { + error_report("%s: mprotect failed: %s", __func__, strerror(errno)); + return -1; + } + return 0; +#endif +} + +int qemu_mprotect_rwx(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_EXECUTE_READWRITE); +#else + return qemu_mprotect__osdep(addr, size, PROT_READ | PROT_WRITE | PROT_= EXEC); +#endif +} + +int qemu_mprotect_none(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_NOACCESS); +#else + return qemu_mprotect__osdep(addr, size, PROT_NONE); +#endif +} + #ifndef _WIN32 /* * Dups an fd and sets the flags --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052153699838.79587585487252; Wed, 19 Jul 2017 20:32:16 -0700 (PDT) Received: from localhost ([::1]:35899 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2CF-00063M-0u for importer@patchew.org; Wed, 19 Jul 2017 23:32:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qT-0001A6-96 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qN-0005wu-Eq for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:45 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:54867) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qN-0005w5-80 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C81C720B80; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:38 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 948517E057; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=eTQ ynNa3dcavbe+LbE/bkez1fIHytaAa6uFo5Y96wKE=; b=qA2whRbQrtM/Ob5J6Yl Flovgrx7ywwzvlS/0tx/GpUz06awVkDk8kMEnF84JWEeOJFfSB34ryNaS2kfIJF2 w52Ij2cq84VUpYRNT366R9M/BdnqnvfbE20rXSTVyzc3iR5uyOB+DBWpRRKGvFv1 GHL96eXLN0q4yjhOIsd09EyU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=eTQynNa3dcavbe+LbE/bkez1fIHytaAa6uFo5Y96w KE=; b=dUKcAejQLjrgnbHYLuRbXL4MNfHTM6wll11RXRCWb9FeGv25acpT2cpyP /s/WhnkDvRs7n+azjPEXmRlieA99AjA0Su9KU1FNSbDzcdDzzGO7opUOguyLjRGX +rCucdfuJrevDPD71dkiUvy1kYPTS/4nzJpn6zsb/Ll6vzm3Ib+p2tdwibGY4/yK AUHRkz9roI+tu5fIlJrZAw6BplPBPtR9oqWr2ZqFC96riXCu7kRf0KOVcqnyJo8L QIQZNVtv01fgnopzHqoXA6dz23xMA7wpoewmL0AdEC+iUU6MdtkYESKZnRu7i1aW b4jhgN/3+QVDY91wIG6FDnVo1BcRw== X-ME-Sender: X-Sasl-enc: bSG+gRKNouzw6yYONRPsOX5fqf86U+79CQiXx1QVSFei 1500520178 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:26 -0400 Message-Id: <1500520169-23367-41-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 40/43] translate-all: use qemu_protect_rwx/none helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The helpers require the address and size to be page-aligned, so do that before calling them. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 61 ++++++++++---------------------------------= ---- 1 file changed, 13 insertions(+), 48 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 36b17ac..e930bac 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -604,63 +604,24 @@ static inline void *split_cross_256mb(void *buf1, siz= e_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); =20 -# ifdef _WIN32 -static inline void do_protect(void *addr, long size, int prot) -{ - DWORD old_protect; - VirtualProtect(addr, size, prot, &old_protect); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PAGE_EXECUTE_READWRITE); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PAGE_NOACCESS); -} -# else -static inline void do_protect(void *addr, long size, int prot) -{ - uintptr_t start, end; - - start =3D (uintptr_t)addr; - start &=3D qemu_real_host_page_mask; - - end =3D (uintptr_t)addr + size; - end =3D ROUND_UP(end, qemu_real_host_page_size); - - mprotect((void *)start, end - start, prot); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PROT_NONE); -} -# endif /* WIN32 */ - static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; + void *end =3D static_code_gen_buffer + sizeof(static_code_gen_buffer); size_t full_size, size; =20 - /* The size of the buffer, rounded down to end on a page boundary. */ - full_size =3D (((uintptr_t)buf + sizeof(static_code_gen_buffer)) - & qemu_real_host_page_mask) - (uintptr_t)buf; + /* page-align the beginning and end of the buffer */ + buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); + end =3D QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); =20 /* Reserve a guard page. */ + full_size =3D end - buf; size =3D full_size - qemu_real_host_page_size; =20 /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx->code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) - & qemu_real_host_page_mask) - (uintptr_t)buf; + size =3D QEMU_ALIGN_DOWN(tcg_ctx->code_gen_buffer_size, + qemu_real_host_page_size); } tcg_ctx->code_gen_buffer_size =3D size; =20 @@ -671,8 +632,12 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - map_exec(buf, size); - map_none(buf + size, qemu_real_host_page_size); + if (qemu_mprotect_rwx(buf, size)) { + abort(); + } + if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { + abort(); + } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521898743151.29914218954036; Wed, 19 Jul 2017 20:38:18 -0700 (PDT) Received: from localhost ([::1]:35922 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2Hm-0001jF-KW for importer@patchew.org; Wed, 19 Jul 2017 23:37:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qS-000198-CX for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qN-0005x7-Ie for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:46157) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qN-0005wH-CD for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 03ED520B84; Wed, 19 Jul 2017 23:09:39 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:39 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B6CE0241E0; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=flUbX4nf7BvvNGC gstOveUHsp4JXvnqrKrnKihoBbM4=; b=LS7sJh2iXIYzlgmNqUqk2RsoPVQeOSb ybCXW5iBLJoG/dmwiliNLpeUU9cT2mmDCDPNBI0nsXYunxWpfW3hBfzl5vAyQPD9 VDE3RTnGwI1VcBN50eYQ2atP2W5bgjc9jjl8mwF24Vpxo8VCbubCSiCgWCLA6hrw qcyVnIwOWkJA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=flUbX4nf7BvvNGCgstOveUHsp4JXvnqrKrnKihoBbM4=; b=du0xX2gt 05uG7DLJoQBP84byyacF1IfrFfB6jhk1e0ldMSztPfTZL1VPnT5r780ptJLEOApQ CBehN+DyJn7GCIcJlWKOiaOs+tE5waC5vj4FHT784EFPRYmxP2xCRiHTkKCqH3DY 34svLNKKOMjna/JkBDk++03j90EaeCqFwNpf/XKwToVnS5MOUeHLqrYuc2oRawrj v5y6SrhzkWQ0Eh3gCSufqZHAC/ca8lhW4fTXmXBbxTGeybKZR7JIsX71f+ImesIk jOA9tbENzQtNt2eRxYkJEC6w7LcotdSZlZLzleNb0CiH6vUmUHVfaGCAm/GsAi5h azRBFlfKYElWcg== X-ME-Sender: X-Sasl-enc: bSGxgQedo/j+7ywPLB7sOX5fqf86U+79CQiXx1QVSFei 1500520178 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:27 -0400 Message-Id: <1500520169-23367-42-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 41/43] tcg: define TCG_HIGHWATER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Will come in handy very soon. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0ddd0dc..cb4ecbd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,6 +115,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static void tcg_out_tb_init(TCGContext *s); static bool tcg_out_tb_finalize(TCGContext *s); =20 +#define TCG_HIGHWATER 1024 + static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; =20 @@ -435,7 +437,7 @@ void tcg_prologue_init(TCGContext *s) /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger than we expect the code generation for any one opcode to require. = */ - s->code_gen_highwater =3D s->code_gen_buffer + (total_size - 1024); + s->code_gen_highwater =3D s->code_gen_buffer + (total_size - TCG_HIGHW= ATER); =20 tcg_register_jit(s->code_gen_buffer, total_size); =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500521786292886.6897858076421; Wed, 19 Jul 2017 20:36:26 -0700 (PDT) Received: from localhost ([::1]:35919 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2GG-0000gD-Fc for importer@patchew.org; Wed, 19 Jul 2017 23:36:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qW-0001ET-RD for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qO-0005xX-06 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:48 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:49951) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qN-0005wk-Le for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 4493320B86; Wed, 19 Jul 2017 23:09:39 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:39 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id E78AA7E057; Wed, 19 Jul 2017 23:09:38 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=QUD CTE3DaVxdGkFyklr+20Js+yCOMgBLSPaoTqAQQpQ=; b=0qA37fJ376RjdE1OLTi UopF4VB9j6Buh+4Vm7oMQ1Nlw+SGBf15GCXVVFyQkwJ5XM+731knW53BEAnDx36H 4UCS2TBhGFC3Z7j1fkY6SDfj7+ScTvUUy4QFnONKx2K2NA/kCPLFDslugm0wRznf D4PWtkSCqFDpu4zWLzRVxjBM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=QUDCTE3DaVxdGkFyklr+20Js+yCOMgBLSPaoTqAQQ pQ=; b=OHW9HgViHDMvSTn+gUV5+9RqBnWU3iE9bf8QPDwBlWYgJyldEjS0rfKtD +6s6E5pehFi1UhNRE8mN644AKwV8fxPy8PS7uVKT60zebvc3AZOpLLGfpv0SWQAy HGCcyknopR4FwPngUJLvSh1+hM5Iga4Kz8M0V/MU1RPC8UxY0YL+iMjI0c5elrQY xvE7MJoeEapISZHlNDeCDUYzTH5RZMibw1LrO0rAiXmWNtiJgEPFQ0hBtj/+sm9o gxzL70CQNlkzp30+HJ2oPvQ4y7w/EWwBky8g4eanaqlgx6LzGGtdkHBf+IB91an3 NcbeA8KYxlBtHLqZvQtUbxLfA3hSQ== X-ME-Sender: X-Sasl-enc: bSG/ih6Qqenu9SEeIwzsOX5fqf86U+79CQiXx1QVSFei 1500520178 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:28 -0400 Message-Id: <1500520169-23367-43-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 42/43] tcg: introduce regions to split code_gen_buffer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection, assigning regions that act just like pages do in virtual memory allocation. (BTW if you are wondering about the chosen naming, I did not want to use blocks or pages because those are already heavily used in QEMU). We use a global lock to serialize allocations as well as statistics reporting (we now export the size of the used code_gen_buffer with tcg_code_size()). Note that for the allocator we could just use a counter and atomic_inc; however, that would complicate the gathering of tcg_code_size()-like stats. So given that the region operations are not a fast path, a lock seems the most reasonable choice. The effectiveness of this approach is clear after seeing some numbers. I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark. Note that I'm evaluating this after enabling per-thread TCG (which is done by a subsequent commit). * -smp 1, 1 region (entire buffer): qemu: flush code_size=3D83885014 nb_tbs=3D154739 avg_tb_size=3D357 qemu: flush code_size=3D83884902 nb_tbs=3D153136 avg_tb_size=3D363 qemu: flush code_size=3D83885014 nb_tbs=3D152777 avg_tb_size=3D364 qemu: flush code_size=3D83884950 nb_tbs=3D150057 avg_tb_size=3D373 qemu: flush code_size=3D83884998 nb_tbs=3D150234 avg_tb_size=3D373 qemu: flush code_size=3D83885014 nb_tbs=3D154009 avg_tb_size=3D360 qemu: flush code_size=3D83885014 nb_tbs=3D151007 avg_tb_size=3D370 qemu: flush code_size=3D83885014 nb_tbs=3D151816 avg_tb_size=3D367 That is, 8 flushes. * -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]: qemu: flush code_size=3D76328008 nb_tbs=3D141040 avg_tb_size=3D356 qemu: flush code_size=3D75366534 nb_tbs=3D138000 avg_tb_size=3D361 qemu: flush code_size=3D76864546 nb_tbs=3D140653 avg_tb_size=3D361 qemu: flush code_size=3D76309084 nb_tbs=3D135945 avg_tb_size=3D375 qemu: flush code_size=3D74581856 nb_tbs=3D132909 avg_tb_size=3D375 qemu: flush code_size=3D73927256 nb_tbs=3D135616 avg_tb_size=3D360 qemu: flush code_size=3D78629426 nb_tbs=3D142896 avg_tb_size=3D365 qemu: flush code_size=3D76667052 nb_tbs=3D138508 avg_tb_size=3D368 Again, 8 flushes. Note how buffer utilization is not 100%, but it is close. Smaller region sizes would yield higher utilization, but we want region allocation to be rare (it acquires a lock), so we do not want to go too small. * -smp 8, static partitioning of 8 regions (10 MB per region): qemu: flush code_size=3D21936504 nb_tbs=3D40570 avg_tb_size=3D354 qemu: flush code_size=3D11472174 nb_tbs=3D20633 avg_tb_size=3D370 qemu: flush code_size=3D11603976 nb_tbs=3D21059 avg_tb_size=3D365 qemu: flush code_size=3D23254872 nb_tbs=3D41243 avg_tb_size=3D377 qemu: flush code_size=3D28289496 nb_tbs=3D52057 avg_tb_size=3D358 qemu: flush code_size=3D43605160 nb_tbs=3D78896 avg_tb_size=3D367 qemu: flush code_size=3D45166552 nb_tbs=3D82158 avg_tb_size=3D364 qemu: flush code_size=3D63289640 nb_tbs=3D116494 avg_tb_size=3D358 qemu: flush code_size=3D51389960 nb_tbs=3D93937 avg_tb_size=3D362 qemu: flush code_size=3D59665928 nb_tbs=3D107063 avg_tb_size=3D372 qemu: flush code_size=3D38380824 nb_tbs=3D68597 avg_tb_size=3D374 qemu: flush code_size=3D44884568 nb_tbs=3D79901 avg_tb_size=3D376 qemu: flush code_size=3D50782632 nb_tbs=3D90681 avg_tb_size=3D374 qemu: flush code_size=3D39848888 nb_tbs=3D71433 avg_tb_size=3D372 qemu: flush code_size=3D64708840 nb_tbs=3D119052 avg_tb_size=3D359 qemu: flush code_size=3D49830008 nb_tbs=3D90992 avg_tb_size=3D362 qemu: flush code_size=3D68372408 nb_tbs=3D123442 avg_tb_size=3D368 qemu: flush code_size=3D33555560 nb_tbs=3D59514 avg_tb_size=3D378 qemu: flush code_size=3D44748344 nb_tbs=3D80974 avg_tb_size=3D367 qemu: flush code_size=3D37104248 nb_tbs=3D67609 avg_tb_size=3D364 That is, 20 flushes. Note how a static partitioning approach uses the code buffer poorly, leading to many unnecessary flushes. Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 6 ++ accel/tcg/translate-all.c | 63 +++++----------- bsd-user/main.c | 1 + cpus.c | 12 +++ linux-user/main.c | 1 + tcg/tcg.c | 183 ++++++++++++++++++++++++++++++++++++++++++= +++- 6 files changed, 221 insertions(+), 45 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 3611141..3365da8 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -760,6 +760,12 @@ void *tcg_malloc_internal(TCGContext *s, int size); void tcg_pool_reset(TCGContext *s); TranslationBlock *tcg_tb_alloc(TCGContext *s); =20 +void tcg_region_init(void); +void tcg_region_reset_all(void); + +size_t tcg_code_size(void); +size_t tcg_code_capacity(void); + /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index e930bac..623b9e7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -608,15 +608,13 @@ static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; void *end =3D static_code_gen_buffer + sizeof(static_code_gen_buffer); - size_t full_size, size; + size_t size; =20 /* page-align the beginning and end of the buffer */ buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); end =3D QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); =20 - /* Reserve a guard page. */ - full_size =3D end - buf; - size =3D full_size - qemu_real_host_page_size; + size =3D end - buf; =20 /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx->code_gen_buffer_size) { @@ -635,9 +633,6 @@ static inline void *alloc_code_gen_buffer(void) if (qemu_mprotect_rwx(buf, size)) { abort(); } - if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { - abort(); - } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; @@ -646,22 +641,16 @@ static inline void *alloc_code_gen_buffer(void) static inline void *alloc_code_gen_buffer(void) { size_t size =3D tcg_ctx->code_gen_buffer_size; - void *buf1, *buf2; - - /* Perform the allocation in two steps, so that the guard page - is reserved but uncommitted. */ - buf1 =3D VirtualAlloc(NULL, size + qemu_real_host_page_size, - MEM_RESERVE, PAGE_NOACCESS); - if (buf1 !=3D NULL) { - buf2 =3D VirtualAlloc(buf1, size, MEM_COMMIT, PAGE_EXECUTE_READWRI= TE); - assert(buf1 =3D=3D buf2); - } + void *buf; =20 - return buf1; + buf =3D VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + PAGE_EXECUTE_READWRITE); + return buf; } #else static inline void *alloc_code_gen_buffer(void) { + int prot =3D PROT_WRITE | PROT_READ | PROT_EXEC; int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start =3D 0; size_t size =3D tcg_ctx->code_gen_buffer_size; @@ -695,8 +684,7 @@ static inline void *alloc_code_gen_buffer(void) # endif # endif =20 - buf =3D mmap((void *)start, size + qemu_real_host_page_size, - PROT_NONE, flags, -1, 0); + buf =3D mmap((void *)start, size, prot, flags, -1, 0); if (buf =3D=3D MAP_FAILED) { return NULL; } @@ -706,24 +694,23 @@ static inline void *alloc_code_gen_buffer(void) /* Try again, with the original still mapped, to avoid re-acquiring that 256mb crossing. This time don't specify an address. */ size_t size2; - void *buf2 =3D mmap(NULL, size + qemu_real_host_page_size, - PROT_NONE, flags, -1, 0); + void *buf2 =3D mmap(NULL, size, prot, flags, -1, 0); switch ((int)(buf2 !=3D MAP_FAILED)) { case 1: if (!cross_256mb(buf2, size)) { /* Success! Use the new buffer. */ - munmap(buf, size + qemu_real_host_page_size); + munmap(buf, size); break; } /* Failure. Work with what we had. */ - munmap(buf2, size + qemu_real_host_page_size); + munmap(buf2, size); /* fallthru */ default: /* Split the original buffer. Free the smaller half. */ buf2 =3D split_cross_256mb(buf, size); size2 =3D tcg_ctx->code_gen_buffer_size; if (buf =3D=3D buf2) { - munmap(buf + size2 + qemu_real_host_page_size, size - size= 2); + munmap(buf + size2, size - size2); } else { munmap(buf, size - size2); } @@ -734,10 +721,6 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - /* Make the final buffer accessible. The guard page at the end - will remain inaccessible with PROT_NONE. */ - mprotect(buf, size, PROT_WRITE | PROT_READ | PROT_EXEC); - /* Request large pages for the buffer. */ qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 @@ -918,13 +901,8 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data= tb_flush_count) size_t host_size =3D 0; =20 g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); - printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", - tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, - nb_tbs > 0 ? host_size / nb_tbs : 0); - } - if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) - > tcg_ctx->code_gen_buffer_size) { - cpu_abort(cpu, "Internal error: code buffer overflow\n"); + printf("qemu: flush code_size=3D%zu nb_tbs=3D%zu avg_tb_size=3D%zu= \n", + tcg_code_size(), nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : = 0); } =20 CPU_FOREACH(cpu) { @@ -938,7 +916,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 - tcg_ctx->code_gen_ptr =3D tcg_ctx->code_gen_buffer; + tcg_region_reset_all(); /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1279,9 +1257,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags |=3D CF_USE_ICOUNT; } =20 + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { - buffer_overflow: /* flush must be done */ tb_flush(cpu); mmap_unlock(); @@ -1365,9 +1343,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif =20 - tcg_ctx->code_gen_ptr =3D (void *) + atomic_set(&tcg_ctx->code_gen_ptr, (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, - CODE_GEN_ALIGN); + CODE_GEN_ALIGN)); =20 /* init jump list */ assert(((uintptr_t)tb & 3) =3D=3D 0); @@ -1909,9 +1887,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) * otherwise users might think "-tb-size" is not honoured. * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. */ - cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, - tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); + cpu_fprintf(f, "gen code size %zu/%zu\n", + tcg_code_size(), tcg_code_capacity()); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index 7a8b29e..aa52c97 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -979,6 +979,7 @@ int main(int argc, char **argv) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); + tcg_region_init(); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/cpus.c b/cpus.c index 9bed61e..6022d40 100644 --- a/cpus.c +++ b/cpus.c @@ -1664,6 +1664,18 @@ static void qemu_tcg_init_vcpu(CPUState *cpu) char thread_name[VCPU_THREAD_NAME_SIZE]; static QemuCond *single_tcg_halt_cond; static QemuThread *single_tcg_cpu_thread; + static int tcg_region_inited; + + /* + * Initialize TCG regions--once. Now is a good time, because: + * (1) TCG's init context, prologue and target globals have been set u= p. + * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before t= he + * -accel flag is processed, so the check doesn't work then). + */ + if (!tcg_region_inited) { + tcg_region_inited =3D 1; + tcg_region_init(); + } =20 if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) { cpu->thread =3D g_malloc0(sizeof(QemuThread)); diff --git a/linux-user/main.c b/linux-user/main.c index de7d948..aab4433 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4460,6 +4460,7 @@ int main(int argc, char **argv, char **envp) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); + tcg_region_init(); =20 #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/tcg/tcg.c b/tcg/tcg.c index cb4ecbd..22a949f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -120,6 +120,23 @@ static bool tcg_out_tb_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; =20 +/* + * We divide code_gen_buffer into equally-sized "regions" that TCG threads + * dynamically allocate from as demand dictates. Given appropriate region + * sizing, this minimizes flushes even when some TCG threads generate a lot + * more code than others. + */ +struct tcg_region_state { + QemuMutex lock; + void *buf; /* set at init time */ + size_t n; /* set at init time */ + size_t size; /* size of one region; set at init time */ + size_t current; /* protected by the lock */ + size_t n_full; /* protected by the lock */ +}; + +static struct tcg_region_state region; + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -257,6 +274,164 @@ TCGLabel *gen_new_label(void) =20 #include "tcg-target.inc.c" =20 +static void tcg_region_assign(TCGContext *s, size_t curr_region) +{ + void *buf; + + buf =3D region.buf + curr_region * (region.size + qemu_real_host_page_= size); + s->code_gen_buffer =3D buf; + s->code_gen_ptr =3D buf; + s->code_gen_buffer_size =3D region.size; + s->code_gen_highwater =3D buf + region.size - TCG_HIGHWATER; +} + +static bool tcg_region_alloc__locked(TCGContext *s) +{ + if (region.current =3D=3D region.n) { + return true; + } + tcg_region_assign(s, region.current); + region.current++; + return false; +} + +/* + * Request a new region once the one in use has filled up. + * Returns true on error. + */ +static bool tcg_region_alloc(TCGContext *s) +{ + bool err; + + qemu_mutex_lock(®ion.lock); + err =3D tcg_region_alloc__locked(s); + if (!err) { + region.n_full++; + } + qemu_mutex_unlock(®ion.lock); + return err; +} + +/* + * Perform a context's first region allocation. + * This function does _not_ increment region.n_full. + */ +static inline bool tcg_region_initial_alloc__locked(TCGContext *s) +{ + return tcg_region_alloc__locked(s); +} + +/* Call from a safe-work context */ +void tcg_region_reset_all(void) +{ + unsigned int i; + + qemu_mutex_lock(®ion.lock); + region.current =3D 0; + region.n_full =3D 0; + + for (i =3D 0; i < n_tcg_ctxs; i++) { + bool err =3D tcg_region_initial_alloc__locked(tcg_ctxs[i]); + + g_assert(!err); + } + qemu_mutex_unlock(®ion.lock); +} + +/* + * Initializes region partitioning. + * + * Called at init time from the parent thread (i.e. the one calling + * tcg_context_init), after the target's TCG globals have been set. + */ +void tcg_region_init(void) +{ + void *buf =3D tcg_init_ctx.code_gen_buffer; + size_t size =3D tcg_init_ctx.code_gen_buffer_size; + size_t region_size; + size_t n_regions; + size_t i; + + /* We do not yet support multiple TCG contexts, so use one region for = now */ + n_regions =3D 1; + + /* start on a page-aligned address */ + buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); + g_assert(buf < tcg_init_ctx.code_gen_buffer + size); + + /* discard that initial portion */ + size -=3D buf - tcg_init_ctx.code_gen_buffer; + + /* make region_size a multiple of page_size */ + region_size =3D size / n_regions; + region_size =3D QEMU_ALIGN_DOWN(region_size, qemu_real_host_page_size); + + /* A region must have at least 2 pages; one code, one guard */ + g_assert(region_size >=3D 2 * qemu_real_host_page_size); + + /* init the region struct */ + qemu_mutex_init(®ion.lock); + region.n =3D n_regions; + region.buf =3D buf; + /* do not count the guard page in region.size */ + region.size =3D region_size - qemu_real_host_page_size; + + /* set guard pages */ + for (i =3D 0; i < region.n; i++) { + void *guard; + int rc; + + guard =3D region.buf + region.size; + guard +=3D i * (region.size + qemu_real_host_page_size); + rc =3D qemu_mprotect_none(guard, qemu_real_host_page_size); + g_assert(!rc); + } + + /* We do not yet support multiple TCG contexts so allocate the region = now */ + { + bool err =3D tcg_region_initial_alloc__locked(tcg_ctx); + + g_assert(!err); + } +} + +/* + * Returns the size (in bytes) of all translated code (i.e. from all regio= ns) + * currently in the cache. + * See also: tcg_code_capacity() + * Do not confuse with tcg_current_code_size(); that one applies to a sing= le + * TCG context. + */ +size_t tcg_code_size(void) +{ + unsigned int i; + size_t total; + + qemu_mutex_lock(®ion.lock); + total =3D region.n_full * (region.size - TCG_HIGHWATER); + for (i =3D 0; i < n_tcg_ctxs; i++) { + const TCGContext *s =3D tcg_ctxs[i]; + size_t size; + + size =3D atomic_read(&s->code_gen_ptr) - s->code_gen_buffer; + g_assert(size <=3D s->code_gen_buffer_size); + total +=3D size; + } + qemu_mutex_unlock(®ion.lock); + return total; +} + +/* + * Returns the code capacity (in bytes) of the entire cache, i.e. includin= g all + * regions. + * See also: tcg_code_size() + */ +size_t tcg_code_capacity(void) +{ + /* no need for synchronization; these variables are set at init time */ + return region.n * (region.size - TCG_HIGHWATER); +} + /* pool based memory allocation */ void *tcg_malloc_internal(TCGContext *s, int size) { @@ -400,13 +575,17 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) TranslationBlock *tb; void *next; =20 + retry: tb =3D (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); next =3D (void *)ROUND_UP((uintptr_t)(tb + 1), align); =20 if (unlikely(next > s->code_gen_highwater)) { - return NULL; + if (tcg_region_alloc(s)) { + return NULL; + } + goto retry; } - s->code_gen_ptr =3D next; + atomic_set(&s->code_gen_ptr, next); return tb; } =20 --=20 2.7.4 From nobody Sun May 5 11:29:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052198027853.873718016190196; Wed, 19 Jul 2017 20:39:40 -0700 (PDT) Received: from localhost ([::1]:35926 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2JM-0002n9-Hl for importer@patchew.org; Wed, 19 Jul 2017 23:39:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qV-0001CG-7S for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qO-0005xc-1Q for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:59313) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qN-0005x0-Px for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 6B8DF20B7F; Wed, 19 Jul 2017 23:09:39 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:39 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 284542418A; Wed, 19 Jul 2017 23:09:39 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Z2x FfS8V1hyfo8KDpQDluzMbu6FGoFr3sGtTYV9MjVk=; b=2s5fh471AHBliQfR65l hkSI0FuPPCUqfqahxZ/x72y0Y714BYah7QAtxRd/p13MXYZBptmMJi3MyAuleDYT lprDLUkZ4nuq6WZzwkv+OR2tpYJCMApYLLkH19TEm493m9WOR4Bayio2Sl6J7uJa UIPQ/NTWeRj1xGeeSXo2hpqc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=Z2xFfS8V1hyfo8KDpQDluzMbu6FGoFr3sGtTYV9Mj Vk=; b=ZdXupvQJ7c6FG49QqCXL/KIov/JTEsFOM/beANL5cq0menCCzdJxpqSdh Rz3xwSMpZ/ElF1ErT+CNMkXab6qNcYphZ8XCvJQHx8F/+gVtp09Sl3ilgDgnZ2my qxDCEg3jJoSuJIXZbHnMoFdKSJTA8Yk4vBLhUrLxWK/WmiXVTBYV/AQxSEgGNEhz UT6sEYqhsQlmUBJIaHfo18lvKfo3oXEckS6RJUoj3LOfu/F6J37Ev4sCKt33gQaU 8WMPgK4KX0cYjub2fumYPRe2ateiZ+ZY3MOU6G8b78JfU0wbeuY5bGJdoRwQsRAV sOBPVacrujsARsRtWEt+DelysPqvA== X-ME-Sender: X-Sasl-enc: aYAuYPaEG3Z0ZjPJa7mW9boYdifc3kVhk9CAQCnX6HUc 1500520179 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:29 -0400 Message-Id: <1500520169-23367-44-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 43/43] tcg: enable multiple TCG contexts in softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This enables parallel TCG code generation. However, we do not take advantage of it yet since tb_lock is still held during tb_gen_code. In user-mode we use a single TCG context; see the documentation added to tcg_region_init for the rationale. Note that targets do not need any conversion: targets initialize a TCGContext (e.g. defining TCG globals), and after this initialization has finished, the context is cloned by the vCPU threads, each of them keeping a separate copy. TCG threads claim one entry in tcg_ctxs[] by atomically increasing n_tcg_ctxs. Do not be too annoyed by the subsequent atomic_read's of that variable; they are there just to play nice with analysis tools such as thread sanitizer. Note that we do not allocate an array of contexts (we allocate an array of pointers instead) because when tcg_context_init is called, we do not know yet how many contexts we'll use since the bool behind qemu_tcg_mttcg_enabled() isn't set yet. Previous patches folded some TCG globals into TCGContext. The non-const globals remaining are only set at init time, i.e. before the TCG threads are spawned. Here is a list of these set-at-init-time globals under tcg/: Only written by tcg_context_init: - indirect_reg_alloc_order - tcg_op_defs Only written by tcg_target_init (called from tcg_context_init): - tcg_target_available_regs - tcg_target_call_clobber_regs - arm: arm_arch, use_idiv_instructions - i386: have_cmov, have_bmi1, have_bmi2, have_lzcnt, have_movbe, have_popcnt - mips: use_movnz_instructions, use_mips32_instructions, use_mips32r2_instructions, got_sigill (tcg_target_detect_isa) - ppc: have_isa_2_06, have_isa_3_00, tb_ret_addr - s390: tb_ret_addr, s390_facilities - sparc: qemu_ld_trampoline, qemu_st_trampoline (build_trampolines), use_vis3_instructions Only written by tcg_prologue_init: - 'struct jit_code_entry one_entry' - aarch64: tb_ret_addr - arm: tb_ret_addr - i386: tb_ret_addr, guest_base_flags - ia64: tb_ret_addr - mips: tb_ret_addr, bswap32_addr, bswap32u_addr, bswap64_addr Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- tcg/tcg.h | 7 ++- accel/tcg/translate-all.c | 2 +- cpus.c | 2 + linux-user/syscall.c | 1 + tcg/tcg.c | 141 ++++++++++++++++++++++++++++++++++++++++++= ++-- 5 files changed, 143 insertions(+), 10 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 3365da8..68cd14e 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -733,7 +733,7 @@ struct TCGContext { }; =20 extern TCGContext tcg_init_ctx; -extern TCGContext *tcg_ctx; +extern __thread TCGContext *tcg_ctx; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { @@ -755,7 +755,7 @@ static inline bool tcg_op_buf_full(void) =20 /* pool based memory allocation */ =20 -/* tb_lock must be held for tcg_malloc_internal. */ +/* user-mode: tb_lock must be held for tcg_malloc_internal. */ void *tcg_malloc_internal(TCGContext *s, int size); void tcg_pool_reset(TCGContext *s); TranslationBlock *tcg_tb_alloc(TCGContext *s); @@ -766,7 +766,7 @@ void tcg_region_reset_all(void); size_t tcg_code_size(void); size_t tcg_code_capacity(void); =20 -/* Called with tb_lock held. */ +/* user-mode: Called with tb_lock held. */ static inline void *tcg_malloc(int size) { TCGContext *s =3D tcg_ctx; @@ -783,6 +783,7 @@ static inline void *tcg_malloc(int size) } =20 void tcg_context_init(TCGContext *s); +void tcg_register_thread(void); void tcg_prologue_init(TCGContext *s); void tcg_func_start(TCGContext *s); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 623b9e7..2e810b9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -154,7 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ TCGContext tcg_init_ctx; -TCGContext *tcg_ctx; +__thread TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; =20 diff --git a/cpus.c b/cpus.c index 6022d40..74ddd49 100644 --- a/cpus.c +++ b/cpus.c @@ -1307,6 +1307,7 @@ static void *qemu_tcg_rr_cpu_thread_fn(void *arg) CPUState *cpu =3D arg; =20 rcu_register_thread(); + tcg_register_thread(); =20 qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); @@ -1454,6 +1455,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) g_assert(!use_icount); =20 rcu_register_thread(); + tcg_register_thread(); =20 qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 003943b..bbf7913 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6214,6 +6214,7 @@ static void *clone_func(void *arg) TaskState *ts; =20 rcu_register_thread(); + tcg_register_thread(); env =3D info->env; cpu =3D ENV_GET_CPU(env); thread_cpu =3D cpu; diff --git a/tcg/tcg.c b/tcg/tcg.c index 22a949f..a5c01be 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -58,6 +58,7 @@ =20 #include "elf.h" #include "exec/log.h" +#include "sysemu/sysemu.h" =20 /* Forward declarations for functions declared in tcg-target.inc.c and used here. */ @@ -324,13 +325,14 @@ static inline bool tcg_region_initial_alloc__locked(T= CGContext *s) /* Call from a safe-work context */ void tcg_region_reset_all(void) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; =20 qemu_mutex_lock(®ion.lock); region.current =3D 0; region.n_full =3D 0; =20 - for (i =3D 0; i < n_tcg_ctxs; i++) { + for (i =3D 0; i < n_ctxs; i++) { bool err =3D tcg_region_initial_alloc__locked(tcg_ctxs[i]); =20 g_assert(!err); @@ -338,11 +340,71 @@ void tcg_region_reset_all(void) qemu_mutex_unlock(®ion.lock); } =20 +#ifdef CONFIG_SOFTMMU +/* + * It is likely that some vCPUs will translate more code than others, so we + * first try to set more regions than smp_cpus, with those regions being of + * reasonable size. If that's not possible we make do by evenly dividing + * the code_gen_buffer among the vCPUs. + */ +static size_t tcg_n_regions(void) +{ + size_t i; + + /* Use a single region if all we have is one vCPU thread */ + if (smp_cpus =3D=3D 1 || !qemu_tcg_mttcg_enabled()) { + return 1; + } + + /* Try to have more regions than smp_cpus, with each region being >=3D= 2 MB */ + for (i =3D 8; i > 0; i--) { + size_t regions_per_thread =3D i; + size_t region_size; + + region_size =3D tcg_init_ctx.code_gen_buffer_size; + region_size /=3D smp_cpus * regions_per_thread; + + if (region_size >=3D 2 * 1024u * 1024) { + return smp_cpus * regions_per_thread; + } + } + /* If we can't, then just allocate one region per vCPU thread */ + return smp_cpus; +} +#else /* user-mode */ +static size_t tcg_n_regions(void) +{ + return 1; +} +#endif + /* * Initializes region partitioning. * * Called at init time from the parent thread (i.e. the one calling * tcg_context_init), after the target's TCG globals have been set. + * + * Region partitioning works by splitting code_gen_buffer into separate re= gions, + * and then assigning regions to TCG threads so that the threads can trans= late + * code in parallel without synchronization. + * + * In softmmu the number of TCG threads is bounded by smp_cpus, so we use = at + * least smp_cpus regions in MTTCG. In !MTTCG we use a single region. + * Note that the TCG options from the command-line (i.e. -accel accel=3Dtc= g,[...]) + * must have been parsed before calling this function, since it calls + * qemu_tcg_mttcg_enabled(). + * + * In user-mode we use a single region. Having multiple regions in user-m= ode + * is not supported, because the number of vCPU threads (recall that each = thread + * spawned by the guest corresponds to a vCPU thread) is only bounded by t= he + * OS, and usually this number is huge (tens of thousands is not uncommon). + * Thus, given this large bound on the number of vCPU threads and the fact + * that code_gen_buffer is allocated at compile-time, we cannot guarantee + * that the availability of at least one region per vCPU thread. + * + * However, this user-mode limitation is unlikely to be a significant prob= lem + * in practice. Multi-threaded guests share most if not all of their trans= lated + * code, which makes parallel code generation less appealing than in softm= mu. */ void tcg_region_init(void) { @@ -352,8 +414,7 @@ void tcg_region_init(void) size_t n_regions; size_t i; =20 - /* We do not yet support multiple TCG contexts, so use one region for = now */ - n_regions =3D 1; + n_regions =3D tcg_n_regions(); =20 /* start on a page-aligned address */ buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); @@ -387,13 +448,69 @@ void tcg_region_init(void) g_assert(!rc); } =20 - /* We do not yet support multiple TCG contexts so allocate the region = now */ + /* In user-mode we support only one ctx, so do the initial allocation = now */ +#ifdef CONFIG_USER_ONLY { bool err =3D tcg_region_initial_alloc__locked(tcg_ctx); =20 g_assert(!err); } +#endif +} + +/* + * All TCG threads except the parent (i.e. the one that called tcg_context= _init + * and registered the target's TCG globals) must register with this functi= on + * before initiating translation. + * + * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentati= on + * of tcg_region_init() for the reasoning behind this. + * + * In softmmu each caller registers its context in tcg_ctxs[]. Note that in + * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial conte= xt + * is not used anymore for translation once this function is called. + * + * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iter= ates + * over the array (e.g. tcg_code_size() the same for both softmmu and user= -mode. + */ +#ifdef CONFIG_USER_ONLY +void tcg_register_thread(void) +{ + tcg_ctx =3D &tcg_init_ctx; +} +#else +void tcg_register_thread(void) +{ + TCGContext *s =3D g_malloc(sizeof(*s)); + unsigned int n; + bool err; + + memcpy(s, &tcg_init_ctx, sizeof(*s)); + + /* claim an entry in tcg_ctxs */ + n =3D atomic_fetch_inc(&n_tcg_ctxs); + g_assert(n < smp_cpus); + tcg_ctxs[n] =3D s; + + /* + * Zero out s->prof in all contexts but the first. + * This ensures that we correctly account for the profiling info + * generated during initialization, since tcg_init_ctx is not + * tracked by the array. + */ + if (n !=3D 0) { +#ifdef CONFIG_PROFILER + memset(&s->prof, 0, sizeof(s->prof)); +#endif + } + + tcg_ctx =3D s; + qemu_mutex_lock(®ion.lock); + err =3D tcg_region_initial_alloc__locked(tcg_ctx); + g_assert(!err); + qemu_mutex_unlock(®ion.lock); } +#endif /* !CONFIG_USER_ONLY */ =20 /* * Returns the size (in bytes) of all translated code (i.e. from all regio= ns) @@ -404,12 +521,13 @@ void tcg_region_init(void) */ size_t tcg_code_size(void) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; size_t total; =20 qemu_mutex_lock(®ion.lock); total =3D region.n_full * (region.size - TCG_HIGHWATER); - for (i =3D 0; i < n_tcg_ctxs; i++) { + for (i =3D 0; i < n_ctxs; i++) { const TCGContext *s =3D tcg_ctxs[i]; size_t size; =20 @@ -561,8 +679,18 @@ void tcg_context_init(TCGContext *s) } =20 tcg_ctx =3D s; + /* + * In user-mode we simply share the init context among threads, since = we + * use a single region. See the documentation tcg_region_init() for the + * reasoning behind this. + * In softmmu we will have at most smp_cpus TCG threads. + */ +#ifdef CONFIG_USER_ONLY tcg_ctxs =3D &tcg_ctx; n_tcg_ctxs =3D 1; +#else + tcg_ctxs =3D g_new(TCGContext *, smp_cpus); +#endif } =20 /* @@ -2714,9 +2842,10 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb= _oargs, int nb_iargs, static inline void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; =20 - for (i =3D 0; i < n_tcg_ctxs; i++) { + for (i =3D 0; i < n_ctxs; i++) { const TCGProfile *orig =3D &tcg_ctxs[i]->prof; =20 if (counters) { --=20 2.7.4