From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235602908880.6701297042091; Sun, 16 Jul 2017 13:06:42 -0700 (PDT) Received: from localhost ([::1]:46709 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpoO-0002SE-Pq for importer@patchew.org; Sun, 16 Jul 2017 16:06:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Ag-8L for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008GR-Dz for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:34963) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008FI-6g for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id DEE9E20A48; Sun, 16 Jul 2017 16:04:39 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:39 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id A90D97E84B; Sun, 16 Jul 2017 16:04:39 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=ptJEv8AGQNj3rlJ dT8z7Rc7EXN+LFg0HLjp4xX7LfrE=; b=2ItJPX5nksmRRPrvz0jPI/93WwstVdi R4xl3SLc+TNFZeFSIu8cFU8itqP1NKf0FF2q7mqzDRaNiogHkxXVVtIs4dTHt26Z e/cXHHs0UXRIdID41zm5KgBioOcagtTQ9LiJuBZH3oisSbPeFhnHUML82uqzamNT IUPvs3qwzTgk= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=ptJEv8AGQNj3rlJdT8z7Rc7EXN+LFg0HLjp4xX7LfrE=; b=J17vBENl nYiSvc+Wq1l7v9yJU14cKk9qotv5eQBiPUp9QbksmZ7foiJBwqZ5Z056TaUasjco T9cNJ5Sggz92u8+dwZHCpST5Ooaqp6qBLEIwk0aIXQQdpSL5JgsYJtKv1GmQSr58 mDBG9kvfuoiE8FLqxDOK1FnoZXnp86SzayBKn4YAGZ0z5K8HWf+dDlZ+xyvr2Ea2 EBeRyUlZ9vEAV+i5OCXfCDpxQaL0vUYOZhij8nqdhDi++eljM0fKKabE+lp9icgi lawFo5aZ0hekbbMXMf6PfvtncCR1OlzZneqcyXhOQayYZVZelxdNu6oNa+kXiC/z q43cOlcxnLyDiQ== X-ME-Sender: X-Sasl-enc: 4/izT2Ko5TIhFPdH6Aw79Zq/JmPZCj2vtcHosa2imwkm 1500235479 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:44 -0400 Message-Id: <1500235468-15341-2-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 01/45] vl: fix breakage of -tb-size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Commit e7b161d573 ("vl: add tcg_enabled() for tcg related code") adds a check to exit the program when !tcg_enabled() while parsing the -tb-size flag. It turns out that when the -tb-size flag is evaluated, tcg_enabled() can only return 0, since it is set (or not) much later by configure_accelerator= (). Fix it by unconditionally exiting if the flag is passed to a QEMU binary built with !CONFIG_TCG. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- vl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vl.c b/vl.c index d17c863..9ece570 100644 --- a/vl.c +++ b/vl.c @@ -3933,10 +3933,10 @@ int main(int argc, char **argv, char **envp) configure_rtc(opts); break; case QEMU_OPTION_tb_size: - if (!tcg_enabled()) { - error_report("TCG is disabled"); - exit(1); - } +#ifndef CONFIG_TCG + error_report("TCG is disabled"); + exit(1); +#endif if (qemu_strtoul(optarg, NULL, 0, &tcg_tb_size) < 0) { error_report("Invalid argument to -tb-size"); exit(1); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235753062290.4474906409845; Sun, 16 Jul 2017 13:09:13 -0700 (PDT) Received: from localhost ([::1]:46718 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpqp-0004by-N1 for importer@patchew.org; Sun, 16 Jul 2017 16:09:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmY-0001Ae-W1 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008G5-Df for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:35925) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008FL-7e for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 222F220A47; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:40 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id DBC142450F; Sun, 16 Jul 2017 16:04:39 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=vulZyVfFh1a/KkQ 9R33O/pPlt4RL1z1OblxCn47KoIA=; b=fQTATPRHrBC39nChtVv9iRymmKKb7WB GIF15uTI3gN15UXKE8/v/t1tUAeGiWXpf8RABjgtvILa31kTfZj4UdEg5pwudRho XHe/0jQYc3fAWm7+IQB7AJCgLX4sBH/S1ZhhLv8rTxDP/uBR5aCY8hvA1xYyBTB8 IahLrUQP3RVw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=vulZyVfFh1a/KkQ9R33O/pPlt4RL1z1OblxCn47KoIA=; b=g6E8n2A/ j3hhmgthtpWUe/rt84MNwAXna9aBzgcrBZCVuskbwzaNxtFV2+jtBr6HVzhySC/d izODrQ7rWS+uImtPQLATp6FfP7eU9l2ScdUfjZGBcK3u6hDDdZE3mlWk4uMRIYaN uvQOizzj4z2ftC5t8p5T1qJaQw9LpLAMa1k2hxyOHYhF/FR0+y3odtPcM2fViiV6 2XS1fuzJTpQnARoisT0xb+EVtfomBAsF7fgpW9s130yfCjycARg0WEnsBWaMv27w hb98MkELC4Hxfa3+igWRKPnF6WC7UxcqBv2z99dswSk89qU1XwrEhoQxiPcv5a8p BK9ztmRA4CriWw== X-ME-Sender: X-Sasl-enc: 4/imRmim/jE8AP9Q4xI79Zq/JmPZCj2vtcHosa2imwkm 1500235479 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:45 -0400 Message-Id: <1500235468-15341-3-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 02/45] translate-all: remove redundant !tcg_enabled check in dump_exec_info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This check is redundant because it is already performed by the only caller of dump_exec_info -- the caller was updated by b7da97eef ("monitor: Check whether TCG is enabled before running the "info jit" code"). Checking twice wouldn't necessarily be too bad, but here the check also returns with tb_lock held. So we can either do the check before tb_lock is acquired, or just get rid of it. Given that it is redundant, I am going for the latter option. Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index e09bd43..090ebad 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1858,11 +1858,6 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) =20 tb_lock(); =20 - if (!tcg_enabled()) { - cpu_fprintf(f, "TCG not enabled\n"); - return; - } - target_code_size =3D 0; max_target_code_size =3D 0; cross_page =3D 0; --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235750329171.02998649453082; Sun, 16 Jul 2017 13:09:10 -0700 (PDT) Received: from localhost ([::1]:46717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpqm-0004ZT-Rq for importer@patchew.org; Sun, 16 Jul 2017 16:09:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Af-05 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008Gc-Ef for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:36725) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008FJ-6c for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 58A4320A41; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:40 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 15F387E1FC; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=buHV2ud6KIgEkQM wGqy38a8ZRqf0F8XaW5hA3j+ERtU=; b=jZbOHpgvlc3Q5Z11PTh8AHX0U3BnO1g qaOrnC0u4wsjXp6fUB0VzMkOCAfPsER3UqhuwYcnISELiXCH0KjmZS+6zZvPAjy/ zIWyvSK2vFwxTvXlHg9uqbx0Rz6nGbqsnJSIdlgP7Jbm9BziOAen5IG1QMuG/npE ETTYojeFe+QQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=buHV2ud6KIgEkQMwGqy38a8ZRqf0F8XaW5hA3j+ERtU=; b=KmG9jH1f HvjGqD8aYVxAV1j+/5T2vTtkbEgndW+acIMjc7yjSYwsKSP62Vx/zODXcbLVyVbj xyCi4clQm6qmeDa6RIGcJxF8yQs2lbEDDHGkGDCUjXlOW7ID9cT7AOJu2Di4iRyJ sqkZLfVtlZ071S2jEtJq8gL6gtQTv/SNIuy93Ayg/mHO3vCiCiGsTiVFKQlwpx9Q 8N1zwWI0jNOGsArw/GeTEWvbEcDklY+4tTWccEjA0RqeGO+BOv6NOLlacD/8rq7f xfmQkFOLUPrAtqjMm3mpvb7o7AmAz3Bqv94/YpM9OlFOumU+JQxzro2pn4O8TpIi gPvbznFR1w3PRA== X-ME-Sender: X-Sasl-enc: 4HvT4lBj5QSjF7eGc6OK6V5Fk+9tvydWW7AvTCRUUTpV 1500235480 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:46 -0400 Message-Id: <1500235468-15341-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 03/45] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Note that this change also requires updating the accessors to tlb_flush_count to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f8..e43ff83 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f94178..c91db21 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 85635ae..9377110 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_f= unc fn, } } =20 -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count =3D 0; + + CPU_FOREACH(cpu) { + CPUArchState *env =3D cpu->env_ptr; + + count +=3D atomic_read(&env->tlb_flush_count); + } + return count; +} =20 /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } =20 assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 tb_lock(); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 090ebad..3ee69e5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1916,7 +1916,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 tb_unlock(); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235901193854.6987594605375; Sun, 16 Jul 2017 13:11:41 -0700 (PDT) Received: from localhost ([::1]:46731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWptE-000726-0L for importer@patchew.org; Sun, 16 Jul 2017 16:11:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46113) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmY-0001Ac-SR for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008GK-FK for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:51385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008FM-6v for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 814B220A49; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:40 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 47C872450F; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=N5tnzqG6f0zZxfu 55la5g3tuJZuEilKtjuICpak3PCY=; b=nuX1ZZTgzJIEXur/mkthGSeT3b0sgns fULTit+kauUzuDm9z5WpnG71onHRe+KgIPBe8+Nt24nOzcdxAZChLlxNcFWoC1oB 7at/OLAdSn0ONmZKlubXsqGCkA6mSmb9N2hWq9oErijlDJebsTx+nmOQGqAdFPTj sP7z9oblMuo4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=N5tnzqG6f0zZxfu55la5g3tuJZuEilKtjuICpak3PCY=; b=OHri1Rph 5vs4uHsKowGKrX9f1gzymsT1CkdzHPI0VbKbH7DlPNZu2136HbmVwbPKrLEaUy+C 2t3lPj5kpFFDPILp0AkECCXLYRk9lenarFzRDmzoturw0vBYEP99qqikBbp3eL4B qw/fFHelpAsw1h1EiWpduQlAcs6pWFUp5AoprRzkEMEq5jDFM3OmXgWr1i69syDs l4qCOQN2hTDpByGYjH8T+M/yonlk1UTh4dJ1bn8Aepd1scoglCrSUDlw/Pec1zV1 IsuKkkPH5o7brk/fDuZqnITpWkrA7ye36DoXBsQD/A8/HwWy04u0Cq0tg/bQDMXv 0Me7S18a2+E2BQ== X-ME-Sender: X-Sasl-enc: 4HvW7FR29RuxDq+HYLeK6V5Fk+9tvydWW7AvTCRUUTpV 1500235480 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:47 -0400 Message-Id: <1500235468-15341-5-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 04/45] tcg: fix corruption of code_time profiling counter upon tb_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Whenever there is an overflow in code_gen_buffer (e.g. we run out of space in it and have to flush it), the code_time profiling counter ends up with an invalid value (that is, code_time -=3D profile_getclock(), without later on getting +=3D profile_getclock() due to the goto). Fix it by using the ti variable, so that we only update code_time when there is no overflow. Note that in case there is an overflow we fail to account for the elapsed coding time, but this is quite rare so we can probably live with it. "info jit" before/after, roughly at the same time during debian-arm bootup: - before: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 998 JIT cycles -615191529184601 (-256329.804 s at 2.4 GHz) translated TBs 302310 (aborted=3D0 0.0%) avg ops/TB 48.4 max=3D438 deleted ops/TB 8.54 avg temps/TB 32.31 max=3D38 avg host code/TB 361.5 avg search data/TB 24.5 cycles/op -42014693.0 cycles/in byte -121444900.2 cycles/out byte -5629031.1 cycles/search byte -83114481.0 gen_interm time -0.0% gen_code time 100.0% optim./code time -0.0% liveness/code time -0.0% cpu_restore count 6236 avg cycles 110.4 - after: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 1010 JIT cycles 1996899624 (0.832 s at 2.4 GHz) translated TBs 297961 (aborted=3D0 0.0%) avg ops/TB 48.5 max=3D438 deleted ops/TB 8.56 avg temps/TB 32.31 max=3D38 avg host code/TB 361.8 avg search data/TB 24.5 cycles/op 138.2 cycles/in byte 398.4 cycles/out byte 18.5 cycles/search byte 273.1 gen_interm time 14.0% gen_code time 86.0% optim./code time 19.4% liveness/code time 10.3% cpu_restore count 6372 avg cycles 111.0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3ee69e5..63f8538 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1300,7 +1300,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; tcg_ctx.interm_time +=3D profile_getclock() - ti; - tcg_ctx.code_time -=3D profile_getclock(); + ti =3D profile_getclock(); #endif =20 /* ??? Overflow could be handled better here. In particular, we @@ -1318,7 +1318,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock(); + tcg_ctx.code_time +=3D profile_getclock() - ti; tcg_ctx.code_in_len +=3D tb->size; tcg_ctx.code_out_len +=3D gen_code_size; tcg_ctx.search_out_len +=3D search_size; --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236165172961.0219200258691; Sun, 16 Jul 2017 13:16:05 -0700 (PDT) Received: from localhost ([::1]:46753 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpxT-0002a6-QS for importer@patchew.org; Sun, 16 Jul 2017 16:16:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpma-0001An-UP for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008Hh-Tq for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:48 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:49617) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008GL-PY for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B315420A34; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:40 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 76AA87E1FC; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=4hp fFtHDfBoVDCzf8A8R6fLpYw2CfxjLS+6v4/ZK1JI=; b=N6yqHfxvh54tXQCSjT7 UqvmqhBAeU4TToT96impQmwP+ZHaJg0qBCKrrYGjwXS8+R4855NOcBzRg7GzmeoA mr0t/CO3Drz2f33Gi9lXxSVM0toRaa4brRqhkbBR1ejN24Zm9WyozFKb2FOTGfxW htJoPs+sVcZ0RYOcQ55jRERs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=4hpfFtHDfBoVDCzf8A8R6fLpYw2CfxjLS+6v4/ZK1 JI=; b=WRC1z/YdTZYl1ncfCGG/kPf83xjh9IV/xah6m/7aSsfQXyRFsN3xYnaKb c64drn27Y3eTgEFyguBWWI5mqOc8n2I2lD22tbyh+33IumKG8egp71DxL7lSso7w nSrlSey9XJnqBBMacvWVhPyWi9hL/YIg9as1YXQTPXeLVU2yfO01cO09Z17/q+Jz W89S994UkGq+q+aISdyO9T1BSx+x1YhKza6LNT3cdXRnANrJSKAnpObVN2b3nEp1 3MVOKBlP7oba14xmpXEhLrtYo2c7icWxkLzGN05FJSAy/uVqOG6X1gn1of3XGCHX xxWC524bqPnlg81FNA9UUOrhN7KwA== X-ME-Sender: X-Sasl-enc: 4HvN7Ux65QS4GKiPbaOK6V5Fk+9tvydWW7AvTCRUUTpV 1500235480 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:48 -0400 Message-Id: <1500235468-15341-6-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 05/45] exec-all: fix typos in TranslationBlock's documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 887d7b3..28e3a24 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -344,7 +344,7 @@ struct TranslationBlock { /* The following data are used to directly call another TB from * the code of this one. This can be done either by emitting direct or * indirect native jump instructions. These jumps are reset so that th= e TB - * just continue its execution. The TB can be linked to another one by + * just continues its execution. The TB can be linked to another one by * setting one of the jump targets (or patching the jump instruction).= Only * two of such jumps are supported. */ @@ -355,7 +355,7 @@ struct TranslationBlock { #else uintptr_t jmp_target_addr[2]; /* target address for indirect jump */ #endif - /* Each TB has an assosiated circular list of TBs jumping to this one. + /* Each TB has an associated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. * Since each TB can have two jumps, it can participate in two lists. --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235899238551.1649830412342; Sun, 16 Jul 2017 13:11:39 -0700 (PDT) Received: from localhost ([::1]:46730 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWptC-00070G-2f for importer@patchew.org; Sun, 16 Jul 2017 16:11:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Ai-Ce for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008Gp-Kj for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39293) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008Fw-Hz for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id E948520A4B; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:40 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id A590B2450F; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=NTmtzjRpKNYDuaU ZrGg/+ukEM6vlK1wMdSRtET/xq0o=; b=rumx8N0PjoJdzbYx0CM0N7r6JWZbVyp lNeWWkojldiRwwTTd+KOqyjp89xyAqp6JSqIx80u2ZjNuUvqWwNQ4WOOr6X0wf9G 69pXpTsCtZ8u2fmsvqAtrLS3DZ446OhL4GHxrCS8LTNxlJmJYkYeh2AEKzWDXioA xF5mef4UQRQE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=NTmtzjRpKNYDuaUZrGg/+ukEM6vlK1wMdSRtET/xq0o=; b=T2s4Vn/c FvJG9R6u0HS3oQJqacR+kB1kQtXYb4bXrta45p8O0GSMY/K5VfKRTb7nL58esfET SCknl5DUKj8sWty/T4wuBEaIoeIca+DYRW+HHv6EMKzQLR4N3WBTpjn/o/v1P1si 4rKeJajTFDUYYAv/y8Ltr+czcY8kJLqr/cLOoWoXcNUKpiyW0ED7y1jf6xZ5jX6E TdUELDiFVAQfNoCrND864DSpGxVtquc2O+utBOFGaOHuZ4rM8dvGIF3G4t2mGajY EADXk2tWslKgt6WNt0oV7spFwePD6klI5rbSQwOsGqUoha7ApeYxStx+jHZTSUTl +WsmJ5r1/Nc4Hw== X-ME-Sender: X-Sasl-enc: 4HvW9kJ79wG8FrWQZauK6V5Fk+9tvydWW7AvTCRUUTpV 1500235480 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:49 -0400 Message-Id: <1500235468-15341-7-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 06/45] translate-all: make have_tb_lock static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 It is only used by this object, and it's not exported to any other. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 63f8538..a124181 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -139,7 +139,7 @@ TCGContext tcg_ctx; bool parallel_cpus; =20 /* translation block context */ -__thread int have_tb_lock; +static __thread int have_tb_lock; =20 static void page_table_config_init(void) { --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235610276586.1176045625051; Sun, 16 Jul 2017 13:06:50 -0700 (PDT) Received: from localhost ([::1]:46711 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpoV-0002Xr-Uv for importer@patchew.org; Sun, 16 Jul 2017 16:06:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46132) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Ak-EX for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008HO-QU for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:56101) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008G1-K0 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1D3B720A42; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:41 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id D39DC7E1FC; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=ckj MGrw4uFoy19Vg1qN3iscMZwOCE4z5in1LUTFroqU=; b=M5NzS/NFhwTu68oHSOm fIsg/+Ezy2ZAoUXAktLoc8he0TmmP1ycCaZZ4TwoR3zrpEwM+Db0xnwiiMSWANQq oK8OCmPmc5cEnthdvYQY6bVW3vni5RXofVIDdaaizJEQFD0gA+sSnecEloX0O3EP B3irz/sKHA//PPtOup57aQBM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=ckjMGrw4uFoy19Vg1qN3iscMZwOCE4z5in1LUTFro qU=; b=aPGOK+OeOE9fEG5KMUgnzW6mMLp6CsV3pJHkrpoaGcxGVb+ELJhTfijzA pu0LBRw4a7D3+BghJjUEYZ185wz7iWitJR4/oHiXWMJWrXYsk9LRgm1s1+UAXnb7 jZ9Zl9Zfmb82rx8iWDJhUYMoa7fyh125mP86smkiuVH6YYXRQUxapFtw/i8lvNv+ XeDI6Dp0V4+R1f/MQ0lXdPnSh+7okKwuaw1cn/eq7qdlpnmVKm04u5ZQaxHUnA/7 Bbg9d7EvbAZXfg6xKpy+zfp7vuK/vtrNM8fYi7D4p/5v86cV83b0Uzb5d26Z/4EW rVYREpehTrHsO98jJ1NrWn1WEgfYA== X-ME-Sender: X-Sasl-enc: 4Hva+1tj6xCtGbeBeb+K6V5Fk+9tvydWW7AvTCRUUTpV 1500235480 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:50 -0400 Message-Id: <1500235468-15341-8-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 07/45] cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reusing the have_tb_lock name, which is also defined in translate-all.c, makes code reviewing unnecessarily harder. Avoid potential confusion by renaming the local have_tb_lock variable to something else. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d84b01d..c4c289b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -337,7 +337,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - bool have_tb_lock =3D false; + bool acquired_tb_lock =3D false; =20 /* we record a subset of the CPU state. It will always be the same before a given translated block @@ -356,7 +356,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, */ mmap_lock(); tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; =20 /* There's a chance that our desired tb has been translated wh= ile * taking the locks so we check again inside the lock. @@ -384,15 +384,15 @@ static inline TranslationBlock *tb_find(CPUState *cpu, #endif /* See if we can patch the calling TB. */ if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - if (!have_tb_lock) { + if (!acquired_tb_lock) { tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; } if (!tb->invalid) { tb_add_jump(last_tb, tb_exit, tb); } } - if (have_tb_lock) { + if (acquired_tb_lock) { tb_unlock(); } return tb; --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236040439586.1600400753794; Sun, 16 Jul 2017 13:14:00 -0700 (PDT) Received: from localhost ([::1]:46740 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpvT-0000rq-5V for importer@patchew.org; Sun, 16 Jul 2017 16:13:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46126) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Ah-90 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008H6-Nc for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:48037) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008G4-J0 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 4E64720809; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:41 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 0BE0B24606; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=HzhQbOk6ZtSYR/J fQiZvnrr5stExrz/79eIhjlu0Uwk=; b=mRipxpXDBjpT1sJoWLChirldohs90Ve 17W8A1BfcY0OvA9Nzno/adP53H14FlB9wYNbJChS2IcelDF2iCtmz7nZJxiHwsrK Rp3eTRUqeXDXpLsfX8EQPGEHGAPT/Ljowq5hOF0aniDsB1KL9yycYpYb7vjmZf5a lqNFv4It//dg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=HzhQbOk6ZtSYR/JfQiZvnrr5stExrz/79eIhjlu0Uwk=; b=pxIyh2b0 /PAtLQKlY9c2qxYO4UPWLdhU+G796SHnrXVCHbILfTU5nisDo4HRL5J16dF2JtN8 nZYKw9+hb755hWmlgF9RAmtlMXLTB2j+yg126jrHa7Ge90ZFAPWvQN40mSs87L4X 3yb+oT4duXXWL1+x2mwwhUiYvu7kr2n0J8nEa4rykuxh72QoW+dpu1ZkrSNL6XZx qdFCcVVKcfgYZ5Ug6eoXRVMrKjmzOEqYhl0M6z0nBsuAIi1v3/FDrQlNOEgea+/8 sUT2y3+LxphxFuc5D86nKfMV34xp0ltwQ8TE/3cXAIhQYJ+gBZ/+EJNtFlMsey76 Yl1AXfL9ojvFiA== X-ME-Sender: X-Sasl-enc: 2RRd39I6v12VZ4r06wEoKPY0/ecQZinqY2+Tv9YE1JXk 1500235481 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:51 -0400 Message-Id: <1500235468-15341-9-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 08/45] tcg/i386: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 01e3b4e..06df01a 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2514,7 +2514,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return NULL; } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_RBP, TCG_REG_RBX, --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236288897844.098565476209; Sun, 16 Jul 2017 13:18:08 -0700 (PDT) Received: from localhost ([::1]:46758 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpzT-000463-Jy for importer@patchew.org; Sun, 16 Jul 2017 16:18:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpma-0001Am-Rf for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008Hl-U2 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:48 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:47389) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008Gg-ON for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 75DA420A4C; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:41 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 3F2717E1FC; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=c0XyXNQgWv6N5nU vxoYlEDaZqby1EMzQFqFeac8obO0=; b=AAkgpuifTIrgN6g3prvjVC1csblla6I ur6hOZfjsj+AHAA9S/iTwptU6owOs6ZtwmmRN0I8jYCcjbQAhHS86Jhe9CNRk9bi eeWP0R4mnh7wR2WYoFm535yuBHtoyYv5T+PbdTkHsdoNH3CqZamqW+l7Ygk3CCxV WqtznuFg2FM4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=c0XyXNQgWv6N5nUvxoYlEDaZqby1EMzQFqFeac8obO0=; b=GTVTXS/M t3A9Wt7zW76kPcmivLwy2BOrF9Q+WZeYgo0EYV4U764MC1qAIE8r9BoExOAhJYmF 3aho+EKJd3D1fJsJzcCm/HBoQdQcmgpKBrhJQqoIPSI3uQhiES2aHDifGSBs5nhF JiZu6Ju4syK+NdoBIJWFmhRAG9ghlqhP3IO7KqR+eMtMlHPRmhuUX/l8R1dhEHWa S9XPL9MCUSf9HhTBfqnIovopvekXHEr7uj31ZgVpjOHgiqPjhWeLdrlFlLrVsP/T bJh5tal0ZdxCtonmgSGyLDMeM392icGH4FnOy0xgfGIlwexbgfVZ8iTi8tNpB0lU GV7UKJa04nK6dg== X-ME-Sender: X-Sasl-enc: 2RREz90prlGIf4r08gsoKPY0/ecQZinqY2+Tv9YE1JXk 1500235481 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:52 -0400 Message-Id: <1500235468-15341-10-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 09/45] tcg/mips: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 85756b8..56db228 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2323,7 +2323,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return NULL; } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S0, /* used for the global env (TCG_AREG0) */ TCG_REG_S1, TCG_REG_S2, --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236039254914.1213610527111; Sun, 16 Jul 2017 13:13:59 -0700 (PDT) Received: from localhost ([::1]:46739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpvR-0000mV-Pp for importer@patchew.org; Sun, 16 Jul 2017 16:13:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Al-Fi for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008H2-Mu for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:48619) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008G6-IB for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 9BADA20A4E; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:41 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 6E8B7246A5; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=CUb rzzm9aSiyRU+j82HvfE4OeX1m7RkRKhlK+iVROAo=; b=f97jp4zIRXEKnAGC/pe fjBZMAT0GbZ5QqmTB77xN87tDyLQX+aU7uODf+Ndu5aY3ST0k5pcve1HnuN54PzK 4uPRer+eUyCRSmVT2Er5j5i/sDL8e5vmKiNr8XEcb/kxXtxUv+pAzVVPjKi1qoAI a6IDze3E6Kuu1jeJX/BjvONM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=CUbrzzm9aSiyRU+j82HvfE4OeX1m7RkRKhlK+iVRO Ao=; b=V3ogcHHcpqqopOKj7CwQ0hSa6XLNxW3DP56gNuNzW2f7XMCPma4BPyjIV GfWJuJUTKA1GfSvbWCd7+OURKqb7jBp9TKjZXBotFGJkjihAKAUor1g3fSB2sBoG hqtp7NXgKB8e/W442VBL1+gJn/B3wdLNXr2Gh+y4qW9Pq8yUw1Tkt/dtWOWd0NT2 FhMPpT7B+hmdRJ2tNkocWikoyKw4ewqIaJOqKigvjsAXf7LoCLKBkLgUdzLsNOW1 nnLrpm5zeKmP+i3ioSRXFF1Lt698ySZXjPzLgKF1jm87Abyihr7+4D77xCD9CtNy +nczW3OdP8oAr6yh9vMtwjAL9tLpg== X-ME-Sender: X-Sasl-enc: 2RRA2M0/qliVdorj7RwoKPY0/ecQZinqY2+Tv9YE1JXk 1500235481 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:53 -0400 Message-Id: <1500235468-15341-11-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 10/45] translate-all: guarantee that tb_hash only holds valid TBs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This gets rid of the need to check the tb->invalid bit during lookups. After this change we do not need atomics to operate on tb->invalid: setting and checking its value is serialised with tb_lock. Signed-off-by: Emilio G. Cota --- accel/tcg/cpu-exec.c | 3 +-- accel/tcg/translate-all.c | 8 ++++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c4c289b..9b5ce13 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -292,8 +292,7 @@ static bool tb_cmp(const void *p, const void *d) tb->page_addr[0] =3D=3D desc->phys_page1 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && - tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && - !atomic_read(&tb->invalid)) { + tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { return true; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a124181..6d4c05f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1073,13 +1073,17 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_pa= ge_addr_t page_addr) =20 assert_tb_locked(); =20 - atomic_set(&tb->invalid, true); - /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); =20 + /* + * Mark the TB as invalid *after* it's been removed from tb_hash, which + * eliminates the need to check this bit on lookups. + */ + tb->invalid =3D true; + /* remove the TB from the page list */ if (tb->page_addr[0] !=3D page_addr) { p =3D page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236159188501.4928508843427; Sun, 16 Jul 2017 13:15:59 -0700 (PDT) Received: from localhost ([::1]:46752 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpxN-0002WS-Vh for importer@patchew.org; Sun, 16 Jul 2017 16:15:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Aj-Dj for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008HG-Qa for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39909) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008GA-Jz for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D7DE120A50; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:41 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 9CE3A7E1FC; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=G3W SHA+GbgxSeJ2Y/eqmWeXP2QoJva651P+5F3BIe3A=; b=NlgBrWMb5q4d11nVVfb HgaXxt0fohMJfL5WA5iIeupKYSDzoXI+iy7p/IkSb8wcCpomFLvdlgI0PhCTQFp3 xyDpLlF/35mfxxqU+8mhBq7hw67imeAF6RU19aKKVwgkp1iknNL+adB+v/UaDb3l CbytB64s9K8SFsgJ2oRpbYYA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=G3WSHA+GbgxSeJ2Y/eqmWeXP2QoJva651P+5F3BIe 3A=; b=aoj8P/jSbCTsBt5B/rWlg/hcDEyMDZWSCo15Big8qkzHmWibNeVo6csR9 faUnmaF6Z2yYPSHp/KhCKCts+ICuDnAJmeRRRlq7wGnN41woqUSsZq6pZn/kvkn5 onu3K+oZsjeRLdVOXiOevoRrTSCdp32nFL9RQYd/IkyBXd+lja4X3yAVWQ21zt4E BhwNg9+BbmfCVXW9249Pmfh6iGewOtzH8hkAlpAyR1BAtMprNEY2nR/WVKUqdYlH CxreZDgdtR1hX4Bs7sRwK7XVA6eOV1r8jt4VUkSuAzwr5Sxa3tu424AC5WJWq94c I2J2qnGJQ3an2fBLWbLn/kzaL5wNg== X-ME-Sender: X-Sasl-enc: 2RRP2NckoU2CdIL08BwoKPY0/ecQZinqY2+Tv9YE1JXk 1500235481 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:54 -0400 Message-Id: <1500235468-15341-12-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 11/45] exec-all: bring tb->invalid into tb->cflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This gets rid of a hole in struct TranslationBlock. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 3 +-- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 28e3a24..78a1714 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -326,12 +326,11 @@ struct TranslationBlock { #define CF_NOCACHE 0x10000 /* To be freed after execution */ #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ +#define CF_INVALID 0x80000 /* Protected by tb_lock */ =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - uint16_t invalid; - void *tc_ptr; /* pointer to the translated code */ uint8_t *tc_search; /* pointer to search data */ /* original tb when cflags has CF_NOCACHE */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9b5ce13..34841cd 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -387,7 +387,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, tb_lock(); acquired_tb_lock =3D true; } - if (!tb->invalid) { + if (!(tb->cflags & CF_INVALID)) { tb_add_jump(last_tb, tb_exit, tb); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6d4c05f..53fbb06 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1082,7 +1082,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) * Mark the TB as invalid *after* it's been removed from tb_hash, which * eliminates the need to check this bit on lookups. */ - tb->invalid =3D true; + tb->cflags |=3D CF_INVALID; =20 /* remove the TB from the page list */ if (tb->page_addr[0] !=3D page_addr) { @@ -1273,7 +1273,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tb->invalid =3D false; =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236780666503.4925785769823; Sun, 16 Jul 2017 13:26:20 -0700 (PDT) Received: from localhost ([::1]:46802 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq7P-0002nd-DN for importer@patchew.org; Sun, 16 Jul 2017 16:26:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmd-0001BG-Qs for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008HU-R6 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:56403) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008GC-Jc for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1601C20A52; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:42 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C66D42450F; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=pvx jtzUsakJca0yQwWlZRq/MQ2cab/j5s1n5YASNXqc=; b=BB0Fo60MNWdq/M8va7R /999JrxqLgG1Za02yYtjLFe6XNCOIVXcrlHB+aeZAX25hRmRvv7wX3vQe+raCrlH JqDA03+Z2YoJAzlc5aMWjgfBim0IPni7AheIMvuxzQn1nGpkCYz4vTC6flt8IP/q Mcbe901wAjECwDW9P0hgaxb4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=pvxjtzUsakJca0yQwWlZRq/MQ2cab/j5s1n5YASNX qc=; b=OzO5PT71guDfcOnd0E62zLr35C0E/zP0bnM+2WJgfraGdaKQFIgnPl9Se hrWYasYHOPRAnmYXQanL2jpOGHXb8X9QndkR8i3VzdiCcLE4bxzBOBXiD+kQbyTH bGTerSB4e9S2JJ8nuo9Y4N7E9p6cL1OQ7QVg3M3khT4XWpvWEEcZHPnPiKoj9kSt v36Hs0+Mbde0EOYxvkCe5RHm1JH/KvIigmFa5lJn2BqjzhOnWMz/Pe6nHNzAPeMx 7ANWlu51itS3qUHZt7WFPCbI3tqanwgWjUnrw8VrWIhlcg+4Y8f/OVqZe9jpwzKw IbadY3TvXMTXnW7Rn4jnUmcaf1vYw== X-ME-Sender: X-Sasl-enc: 2RRayNAxuFmHYon+6wIoKPY0/ecQZinqY2+Tv9YE1JXk 1500235481 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:55 -0400 Message-Id: <1500235468-15341-13-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 12/45] tcg: remove addr argument from lookup_tb_ptr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- tcg/tcg-op.h | 4 ++-- tcg/tcg-runtime.h | 2 +- target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 5 +---- target/hppa/translate.c | 6 +++--- target/i386/translate.c | 17 +++++------------ target/mips/translate.c | 4 ++-- target/s390x/translate.c | 2 +- tcg/tcg-op.c | 4 ++-- tcg/tcg-runtime.c | 20 ++++++++++---------- 11 files changed, 30 insertions(+), 40 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f..18d01b2 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -797,7 +797,7 @@ static inline void tcg_gen_exit_tb(uintptr_t val) void tcg_gen_goto_tb(unsigned idx); =20 /** - * tcg_gen_lookup_and_goto_ptr() - look up a TB and jump to it if valid + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if v= alid * @addr: Guest address of the target TB * * If the TB is not valid, jump to the epilogue. @@ -805,7 +805,7 @@ void tcg_gen_goto_tb(unsigned idx); * This operation is optional. If the TCG backend does not implement goto_= ptr, * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argume= nt. */ -void tcg_gen_lookup_and_goto_ptr(TCGv addr); +void tcg_gen_lookup_and_goto_ptr(void); =20 #if TARGET_LONG_BITS =3D=3D 32 #define tcg_temp_new() tcg_temp_new_i32() diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h index c41d38a..1df17d0 100644 --- a/tcg/tcg-runtime.h +++ b/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i6= 4) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) =20 -DEF_HELPER_FLAGS_2(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env, tl) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) =20 DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 232af9e..96c527b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3022,7 +3022,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) /* FALLTHRU */ case EXIT_PC_UPDATED: if (!use_exit_tb(&ctx)) { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; } /* FALLTHRU */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e55547d..49d35c2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -379,7 +379,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) } else if (s->singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); s->is_jmp =3D DISAS_TB_JUMP; } } @@ -11369,7 +11369,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, Transla= tionBlock *tb) gen_a64_set_pc_im(dc->pc); /* fall through */ case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; case DISAS_EXIT: tcg_gen_exit_tb(0); diff --git a/target/arm/translate.c b/target/arm/translate.c index 0862f9e..ebbe407 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4152,10 +4152,7 @@ static inline bool use_goto_tb(DisasContext *s, targ= et_ulong dest) =20 static void gen_goto_ptr(void) { - TCGv addr =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, cpu_R[15]); - tcg_gen_lookup_and_goto_ptr(addr); - tcg_temp_free(addr); + tcg_gen_lookup_and_goto_ptr(); } =20 static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e10abc5..91053e2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -517,7 +517,7 @@ static void gen_goto_tb(DisasContext *ctx, int which, if (ctx->singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -1527,7 +1527,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv = dest, if (link !=3D 0) { tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, NO_EXIT); } else { cond_prep(&ctx->null_cond); @@ -3885,7 +3885,7 @@ void gen_intermediate_code(CPUHPPAState *env, struct = TranslationBlock *tb) if (ctx.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/i386/translate.c b/target/i386/translate.c index ed3b896..291c577 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -2511,7 +2511,7 @@ static void gen_bnd_jmp(DisasContext *s) If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of S->TF. This is used by the syscall/sysret insns. */ static void -do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) +do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) { gen_update_cc_op(s); =20 @@ -2532,12 +2532,8 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) tcg_gen_exit_tb(0); } else if (s->tf) { gen_helper_single_step(cpu_env); - } else if (!TCGV_IS_UNUSED(jr)) { - TCGv vaddr =3D tcg_temp_new(); - - tcg_gen_add_tl(vaddr, jr, cpu_seg_base[R_CS]); - tcg_gen_lookup_and_goto_ptr(vaddr); - tcg_temp_free(vaddr); + } else if (jr) { + tcg_gen_lookup_and_goto_ptr(); } else { tcg_gen_exit_tb(0); } @@ -2547,10 +2543,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) static inline void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf) { - TCGv unused; - - TCGV_UNUSED(unused); - do_gen_eob_worker(s, inhibit, recheck_tf, unused); + do_gen_eob_worker(s, inhibit, recheck_tf, false); } =20 /* End of block. @@ -2569,7 +2562,7 @@ static void gen_eob(DisasContext *s) /* Jump to register */ static void gen_jr(DisasContext *s, TCGv dest) { - do_gen_eob_worker(s, false, false, dest); + do_gen_eob_worker(s, false, false, true); } =20 /* generate a jump to eip. No segment change must happen before as a diff --git a/target/mips/translate.c b/target/mips/translate.c index 559f8fe..a2f5385 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4233,7 +4233,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int= n, target_ulong dest) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); } } =20 @@ -10725,7 +10725,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); break; default: fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 592d6b0..b503c2c 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5859,7 +5859,7 @@ void gen_intermediate_code(CPUS390XState *env, struct= TranslationBlock *tb) } else if (use_exit_tb(&dc) || status =3D=3D EXIT_PC_STALE_NOCHAIN= ) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(psw_addr); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673e..205d07f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2587,11 +2587,11 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 -void tcg_gen_lookup_and_goto_ptr(TCGv addr) +void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env, addr); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 3e23649..e85a042 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -144,33 +144,33 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } =20 -void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) +void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, addr_hash; + uint32_t flags, hash; =20 - addr_hash =3D tb_jmp_cache_hash_func(addr); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[addr_hash]); cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + hash =3D tb_jmp_cache_hash_func(pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); =20 if (unlikely(!(tb - && tb->pc =3D=3D addr + && tb->pc =3D=3D pc && tb->cs_base =3D=3D cs_base && tb->flags =3D=3D flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, addr, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); if (!tb) { return tcg_ctx.code_gen_epilogue; } - atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); + atomic_set(&cpu->tb_jmp_cache[hash], tb); } =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, addr, + qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, addr, - lookup_symbol(addr)); + tb->tc_ptr, cpu->cpu_index, pc, + lookup_symbol(pc)); return tb->tc_ptr; } =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235767120813.5490488042027; Sun, 16 Jul 2017 13:09:27 -0700 (PDT) Received: from localhost ([::1]:46720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpr3-0004vH-O2 for importer@patchew.org; Sun, 16 Jul 2017 16:09:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmc-0001Az-En for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008HY-S3 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:50 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:53501) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008GE-Jj for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 3FB2E20A55; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:42 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 005FD7E17E; Sun, 16 Jul 2017 16:04:41 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=I4x p9tnm4rH1RwtRGpFWrXjxWsf41Nt4BovZevnXcyY=; b=ewjYAM5uJUu91KiOHeu MdBkKreWvfxTF1qkNfgj6bLr/95/DxNRfytWtfDxYzmQtU7MpPFec2xYEveolheA JzVyndQpW54rMfQ5gCXyEg5WXBuGrMIEVjNvqLPpJFLKUN4pvsZcaIMqBqZ5mWPB DsBwJ+kjKUbXTPqMh3SXxBbI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=I4xp9tnm4rH1RwtRGpFWrXjxWsf41Nt4BovZevnXc yY=; b=lOI5lP1HRHmHnIQLV+fjNiDkvk/kcLDo+5lRQBvr8LWN/+lHKD5v69h/o U6rdIdVC1w4AY2iqtqiScL7MhWId1UP50zYr+6f4RjSDcdcyi2K6EAIsPwSRjVSX pPlLqsO27UklV1Y05icFPyJwGjFdsr2qUADz4lq5TH7svBgeOO8KsgE4q3gPHt78 sb8a9LK2Bkg7bY9vD6s+6aW07X450XLeJuhI3WjwZ+v1NoX4qa2w+tDBUtL+C0ap feNtSswguvfUjjWWiVHUo3uteH87Q2RlrK9GR0ARN3ti+pm6Vp4y0FGxqVayZcMU 4evsZPRitsk/AigChaAuOi3n0bEiQ== X-ME-Sender: X-Sasl-enc: 0KyGFXcWhr5Ud32YbJZUfQ5vjzpkhLX2Bh9r/mwS9Nkr 1500235482 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:56 -0400 Message-Id: <1500235468-15341-14-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 13/45] tcg: consolidate TB lookups in tb_lookup__cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This avoids duplicating code. cpu_exec_step will also use the new common function once we integrate parallel_cpus into tb->cflags. Performance-wise, I measured a small improvement when booting debian-arm. Note that inlining pays off: Performance counter stats for 'taskset -c 0 qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Djessie.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): Before: 18714.917392 task-clock # 0.952 CPUs utilized = ( +- 0.95% ) 23,142 context-switches # 0.001 M/sec = ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 10,558 page-faults # 0.001 M/sec = ( +- 0.95% ) 53,957,727,252 cycles # 2.883 GHz = ( +- 0.91% ) [83.33%] 24,440,599,852 stalled-cycles-frontend # 45.30% frontend cycles idl= e ( +- 1.20% ) [83.33%] 16,495,714,424 stalled-cycles-backend # 30.57% backend cycles idl= e ( +- 0.95% ) [66.66%] 76,267,572,582 instructions # 1.41 insns per cycle # 0.32 stalled cycles per = insn ( +- 0.87% ) [83.34%] 12,692,186,323 branches # 678.186 M/sec = ( +- 0.92% ) [83.35%] 263,486,879 branch-misses # 2.08% of all branches = ( +- 0.73% ) [83.34%] 19.648474449 seconds time elapsed = ( +- 0.82% ) After, w/ inline (this patch): 18471.376627 task-clock # 0.955 CPUs utilized = ( +- 0.96% ) 23,048 context-switches # 0.001 M/sec = ( +- 0.48% ) 1 CPU-migrations # 0.000 M/sec 10,708 page-faults # 0.001 M/sec = ( +- 0.81% ) 53,208,990,796 cycles # 2.881 GHz = ( +- 0.98% ) [83.34%] 23,941,071,673 stalled-cycles-frontend # 44.99% frontend cycles idl= e ( +- 0.95% ) [83.34%] 16,161,773,848 stalled-cycles-backend # 30.37% backend cycles idl= e ( +- 0.76% ) [66.67%] 75,786,269,766 instructions # 1.42 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.24% ) [83.34%] 12,573,617,143 branches # 680.708 M/sec = ( +- 1.34% ) [83.33%] 260,235,550 branch-misses # 2.07% of all branches = ( +- 0.66% ) [83.33%] 19.340502161 seconds time elapsed = ( +- 0.56% ) After, w/o inline: 18791.253967 task-clock # 0.954 CPUs utilized = ( +- 0.78% ) 23,230 context-switches # 0.001 M/sec = ( +- 0.42% ) 1 CPU-migrations # 0.000 M/sec 10,563 page-faults # 0.001 M/sec = ( +- 1.27% ) 54,168,674,622 cycles # 2.883 GHz = ( +- 0.80% ) [83.34%] 24,244,712,629 stalled-cycles-frontend # 44.76% frontend cycles idl= e ( +- 1.37% ) [83.33%] 16,288,648,572 stalled-cycles-backend # 30.07% backend cycles idl= e ( +- 0.95% ) [66.66%] 77,659,755,503 instructions # 1.43 insns per cycle # 0.31 stalled cycles per = insn ( +- 0.97% ) [83.34%] 12,922,780,045 branches # 687.702 M/sec = ( +- 1.06% ) [83.34%] 261,962,386 branch-misses # 2.03% of all branches = ( +- 0.71% ) [83.35%] 19.700174670 seconds time elapsed = ( +- 0.56% ) Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/tb-lookup.h | 48 ++++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/cpu-exec.c | 47 ++++++++++++++++++--------------------------= --- tcg/tcg-runtime.c | 24 ++++++------------------ 3 files changed, 72 insertions(+), 47 deletions(-) create mode 100644 include/exec/tb-lookup.h diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h new file mode 100644 index 0000000..5e3f104 --- /dev/null +++ b/include/exec/tb-lookup.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2017, Emilio G. Cota + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef EXEC_TB_LOOKUP_H +#define EXEC_TB_LOOKUP_H + +#include "qemu/osdep.h" + +#ifdef NEED_CPU_H +#include "cpu.h" +#else +#include "exec/poison.h" +#endif + +#include "exec/exec-all.h" +#include "exec/tb-hash.h" + +/* Might cause an exception, so have a longjmp destination ready */ +static inline TranslationBlock * +tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, + uint32_t *flags) +{ + CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; + TranslationBlock *tb; + uint32_t hash; + + cpu_get_tb_cpu_state(env, pc, cs_base, flags); + hash =3D tb_jmp_cache_hash_func(*pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); + if (likely(tb && + tb->pc =3D=3D *pc && + tb->cs_base =3D=3D *cs_base && + tb->flags =3D=3D *flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate)) { + return tb; + } + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + if (tb =3D=3D NULL) { + return NULL; + } + atomic_set(&cpu->tb_jmp_cache[hash], tb); + return tb; +} + +#endif /* EXEC_TB_LOOKUP_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 34841cd..3a08ad0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "qemu/rcu.h" #include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "exec/log.h" #include "qemu/main-loop.h" #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) @@ -332,43 +333,31 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) { - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; =20 - /* we record a subset of the CPU state. It will - always be the same before a given translated block - is executed. */ - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]); - if (unlikely(!tb || tb->pc !=3D pc || tb->cs_base !=3D cs_base || - tb->flags !=3D flags || - tb->trace_vcpu_dstate !=3D *cpu->trace_dstate)) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - - /* mmap_lock is needed by tb_gen_code, and mmap_lock must be - * taken outside tb_lock. As system emulation is currently - * single threaded the locks are NOPs. - */ - mmap_lock(); - tb_lock(); - acquired_tb_lock =3D true; - - /* There's a chance that our desired tb has been translated wh= ile - * taking the locks so we check again inside the lock. - */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - /* if no translated code available, then translate it now = */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); - } + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + /* mmap_lock is needed by tb_gen_code, and mmap_lock must be + * taken outside tb_lock. As system emulation is currently + * single threaded the locks are NOPs. + */ + mmap_lock(); + tb_lock(); + acquired_tb_lock =3D true; =20 - mmap_unlock(); + /* There's a chance that our desired tb has been translated while + * taking the locks so we check again inside the lock. + */ + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + if (likely(tb =3D=3D NULL)) { + /* if no translated code available, then translate it now */ + tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); } =20 + mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup = */ atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); } diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index e85a042..7100339 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -27,7 +27,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" =20 @@ -149,24 +149,12 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, hash; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - hash =3D tb_jmp_cache_hash_func(pc); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); - - if (unlikely(!(tb - && tb->pc =3D=3D pc - && tb->cs_base =3D=3D cs_base - && tb->flags =3D=3D flags - && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - return tcg_ctx.code_gen_epilogue; - } - atomic_set(&cpu->tb_jmp_cache[hash], tb); - } + uint32_t flags; =20 + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + return tcg_ctx.code_gen_epilogue; + } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", tb->tc_ptr, cpu->cpu_index, pc, --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236288852363.0263513115701; Sun, 16 Jul 2017 13:18:08 -0700 (PDT) Received: from localhost ([::1]:46757 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpzT-000459-1X for importer@patchew.org; Sun, 16 Jul 2017 16:18:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmd-0001B9-J5 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmV-0008ID-4o for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:49409) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008Gk-U8 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:43 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 73EF420A4F; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:42 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 2B1BA2450F; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=MU4 cZfbV12elCaHKyo2WF5br2sGjCK4Bjxs56QAjOko=; b=WSUop7YwyE6qdjWR6CE nWEPdtl/3bWI6YUlxcGVYONGwdM8Zh9rDwIm1GshxxbJlA88XDxay9i/lgcgQM0n vAxqzcC9upZs2ddwuD5GJHhWzs4ssyQHgS5jH+RQekEUFByge/P97YpzLNp94myR fmigk5SU5w8bvoUgMd5ZNVg0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=MU4cZfbV12elCaHKyo2WF5br2sGjCK4Bjxs56QAjO ko=; b=KXQXqDvzKAxjTrlcHVz8Bs4ogwbWwP2D1RTxI6fPAKDARQpECzayfuxjc a5PS+N28gCa5UT/z31mLuJZckDeKeE2Kl+K1/rX+6fFns0tMpqvv79Njriw8fSak p5P5j+XfYU9Hx5ef16bjVOy8ivFrp/ZKr0+pMIZMJN0yRGV6JbaenTDeWU4BJfKp uNGNbRvaKr31QA/cSGHEqCfIxEcGdTGgxWZpd8cvl66pkJ7B6RCYlmWVXP4NgVoL CmVnva3nz9n2TYfMmdNzY8rl0pVBF0wLkl4Rt4fRSxVPL0Fn4nr2L1TUPYP9F6c1 spKdqKB/3z0HfIDhPLG3oUkQSMK6w== X-ME-Sender: X-Sasl-enc: 0KyEGGIOjKRca2aQbI1UfQ5vjzpkhLX2Bh9r/mwS9Nkr 1500235482 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:57 -0400 Message-Id: <1500235468-15341-15-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 14/45] tcg: define CF_PARALLEL and use it for TB hashing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This will enable us to decouple code translation from the value of parallel_cpus at any given time. It will also help us minimize TB flushes when generating code via EXCP_ATOMIC. Note that the declaration of parallel_cpus is brought to exec-all.h to be able to define there the inlines. The inlines use an unnecessary temp variable that is there just to make it easier to add more bits to the mask in the future. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 26 ++++++++++++++++++++++- include/exec/tb-hash-xx.h | 9 +++++--- include/exec/tb-hash.h | 4 ++-- include/exec/tb-lookup.h | 5 +++-- tcg/tcg.h | 1 - accel/tcg/cpu-exec.c | 53 +++++++++++++++++++++++++++----------------= ---- accel/tcg/translate-all.c | 23 ++++++++++++++++---- exec.c | 7 ++++++- hw/i386/kvmvapic.c | 7 ++++++- tcg/tcg-runtime.c | 2 +- tests/qht-bench.c | 2 +- 11 files changed, 100 insertions(+), 39 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 78a1714..b3f04c3 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -327,6 +327,7 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ #define CF_INVALID 0x80000 /* Protected by tb_lock */ +#define CF_PARALLEL 0x100000 /* Generate code for a parallel context */ =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; @@ -370,11 +371,34 @@ struct TranslationBlock { uintptr_t jmp_list_first; }; =20 +extern bool parallel_cpus; + +/* mask cflags for hashing/comparison */ +static inline uint32_t mask_cf(uint32_t cflags) +{ + uint32_t mask =3D 0; + + mask |=3D CF_PARALLEL; + return cflags & mask; +} + +/* current cflags, masked for hashing/comparison */ +static inline uint32_t curr_cf_mask(void) +{ + uint32_t val =3D 0; + + if (parallel_cpus) { + val |=3D CF_PARALLEL; + } + return val; +} + void tb_free(TranslationBlock *tb); void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags); + target_ulong cs_base, uint32_t flags, + uint32_t cf_mask); =20 #if defined(USE_DIRECT_JUMP) =20 diff --git a/include/exec/tb-hash-xx.h b/include/exec/tb-hash-xx.h index 6cd3022..747a9a6 100644 --- a/include/exec/tb-hash-xx.h +++ b/include/exec/tb-hash-xx.h @@ -48,8 +48,8 @@ * xxhash32, customized for input variables that are not guaranteed to be * contiguous in memory. */ -static inline -uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f) +static inline uint32_t +tb_hash_func7(uint64_t a0, uint64_t b0, uint32_t e, uint32_t f, uint32_t g) { uint32_t v1 =3D TB_HASH_XX_SEED + PRIME32_1 + PRIME32_2; uint32_t v2 =3D TB_HASH_XX_SEED + PRIME32_2; @@ -78,7 +78,7 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t= e, uint32_t f) v4 *=3D PRIME32_1; =20 h32 =3D rol32(v1, 1) + rol32(v2, 7) + rol32(v3, 12) + rol32(v4, 18); - h32 +=3D 24; + h32 +=3D 28; =20 h32 +=3D e * PRIME32_3; h32 =3D rol32(h32, 17) * PRIME32_4; @@ -86,6 +86,9 @@ uint32_t tb_hash_func6(uint64_t a0, uint64_t b0, uint32_t= e, uint32_t f) h32 +=3D f * PRIME32_3; h32 =3D rol32(h32, 17) * PRIME32_4; =20 + h32 +=3D g * PRIME32_3; + h32 =3D rol32(h32, 17) * PRIME32_4; + h32 ^=3D h32 >> 15; h32 *=3D PRIME32_2; h32 ^=3D h32 >> 13; diff --git a/include/exec/tb-hash.h b/include/exec/tb-hash.h index 17b5ee0..0526c4f 100644 --- a/include/exec/tb-hash.h +++ b/include/exec/tb-hash.h @@ -59,9 +59,9 @@ static inline unsigned int tb_jmp_cache_hash_func(target_= ulong pc) =20 static inline uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t fl= ags, - uint32_t trace_vcpu_dstate) + uint32_t cf_mask, uint32_t trace_vcpu_dstate) { - return tb_hash_func6(phys_pc, pc, flags, trace_vcpu_dstate); + return tb_hash_func7(phys_pc, pc, flags, cf_mask, trace_vcpu_dstate); } =20 #endif diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 5e3f104..9948b67 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -21,7 +21,7 @@ /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock * tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, - uint32_t *flags) + uint32_t *flags, uint32_t cf_mask) { CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; @@ -34,10 +34,11 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, t= arget_ulong *cs_base, tb->pc =3D=3D *pc && tb->cs_base =3D=3D *cs_base && tb->flags =3D=3D *flags && + mask_cf(tb->cflags) =3D=3D cf_mask && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate)) { return tb; } - tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask); if (tb =3D=3D NULL) { return NULL; } diff --git a/tcg/tcg.h b/tcg/tcg.h index da78721..96872f8 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -730,7 +730,6 @@ struct TCGContext { }; =20 extern TCGContext tcg_ctx; -extern bool parallel_cpus; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3a08ad0..efe5c85 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -198,16 +198,20 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, TranslationBlock *orig_tb, bool ignore_icount) { TranslationBlock *tb; + uint32_t cflags; =20 /* Should never happen. We only end up here when an existing TB is too long. */ if (max_cycles > CF_COUNT_MASK) max_cycles =3D CF_COUNT_MASK; =20 + cflags =3D max_cycles | CF_NOCACHE | (ignore_icount ? CF_IGNORE_ICOUNT= : 0); + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } tb_lock(); tb =3D tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, - max_cycles | CF_NOCACHE - | (ignore_icount ? CF_IGNORE_ICOUNT : 0)); + cflags); tb->orig_tb =3D orig_tb; tb_unlock(); =20 @@ -225,31 +229,26 @@ static void cpu_exec_nocache(CPUState *cpu, int max_c= ycles, static void cpu_exec_step(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; + uint32_t cflags =3D 1 | CF_IGNORE_ICOUNT; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { - mmap_lock(); - tb_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, - 1 | CF_NOCACHE | CF_IGNORE_ICOUNT); - tb->orig_tb =3D NULL; - tb_unlock(); - mmap_unlock(); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, mask_cf(cf= lags)); + if (tb =3D=3D NULL) { + mmap_lock(); + tb_lock(); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb_unlock(); + mmap_unlock(); + } =20 cc->cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb_nocache(tb, pc); + trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); - - tb_lock(); - tb_phys_invalidate(tb, -1); - tb_free(tb); - tb_unlock(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -281,6 +280,7 @@ struct tb_desc { CPUArchState *env; tb_page_addr_t phys_page1; uint32_t flags; + uint32_t cf_mask; uint32_t trace_vcpu_dstate; }; =20 @@ -293,6 +293,7 @@ static bool tb_cmp(const void *p, const void *d) tb->page_addr[0] =3D=3D desc->phys_page1 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && + mask_cf(tb->cflags) =3D=3D desc->cf_mask && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { @@ -312,7 +313,8 @@ static bool tb_cmp(const void *p, const void *d) } =20 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags) + target_ulong cs_base, uint32_t flags, + uint32_t cf_mask) { tb_page_addr_t phys_pc; struct tb_desc desc; @@ -321,11 +323,12 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, tar= get_ulong pc, desc.env =3D (CPUArchState *)cpu->env_ptr; desc.cs_base =3D cs_base; desc.flags =3D flags; + desc.cf_mask =3D cf_mask; desc.trace_vcpu_dstate =3D *cpu->trace_dstate; desc.pc =3D pc; phys_pc =3D get_page_addr_code(desc.env, pc); desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; - h =3D tb_hash_func(phys_pc, pc, flags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); } =20 @@ -337,8 +340,9 @@ static inline TranslationBlock *tb_find(CPUState *cpu, target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; + uint32_t cf_mask =3D curr_cf_mask(); =20 - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); if (tb =3D=3D NULL) { /* mmap_lock is needed by tb_gen_code, and mmap_lock must be * taken outside tb_lock. As system emulation is currently @@ -351,10 +355,15 @@ static inline TranslationBlock *tb_find(CPUState *cpu, /* There's a chance that our desired tb has been translated while * taking the locks so we check again inside the lock. */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); if (likely(tb =3D=3D NULL)) { + uint32_t cflags =3D 0; + + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } /* if no translated code available, then translate it now */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); } =20 mmap_unlock(); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 53fbb06..483248f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1075,7 +1075,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, mask_cf(tb->cflags), + tb->trace_vcpu_dstate); qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); =20 /* @@ -1226,7 +1227,8 @@ static void tb_link_page(TranslationBlock *tb, tb_pag= e_addr_t phys_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, mask_cf(tb->cflags), + tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 #ifdef DEBUG_TB_CHECK @@ -1504,10 +1506,15 @@ void tb_invalidate_phys_page_range(tb_page_addr_t s= tart, tb_page_addr_t end, #endif #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { + uint32_t cflags =3D 1; + + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } /* we generate a block containing just the instruction modifying the memory. It will ensure that it cannot modify itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, cflag= s); cpu_loop_exit_noexc(cpu); } #endif @@ -1622,10 +1629,15 @@ static bool tb_invalidate_phys_page(tb_page_addr_t = addr, uintptr_t pc) p->first_tb =3D NULL; #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { + uint32_t cflags =3D 1; + + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } /* we generate a block containing just the instruction modifying the memory. It will ensure that it cannot modify itself */ - tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cpu, current_pc, current_cs_base, current_flags, cflag= s); /* tb_lock will be reset after cpu_loop_exit_noexc longjmps * back into the cpu_exec loop. */ return true; @@ -1769,6 +1781,9 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) } =20 cflags =3D n | CF_LAST_IO; + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } pc =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; diff --git a/exec.c b/exec.c index a083ff8..adc160f 100644 --- a/exec.c +++ b/exec.c @@ -2414,8 +2414,13 @@ static void check_watchpoint(int offset, int len, Me= mTxAttrs attrs, int flags) cpu->exception_index =3D EXCP_DEBUG; cpu_loop_exit(cpu); } else { + uint32_t cflags =3D 1; + + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); - tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); + tb_gen_code(cpu, pc, cs_base, cpu_flags, cflags); cpu_loop_exit_noexc(cpu); } } diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 0d9ef77..22e151d 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -458,10 +458,15 @@ static void patch_instruction(VAPICROMState *s, X86CP= U *cpu, target_ulong ip) resume_all_vcpus(); =20 if (tcg_enabled()) { + uint32_t cflags =3D 1; + + if (parallel_cpus) { + cflags |=3D CF_PARALLEL; + } /* Both tb_lock and iothread_mutex will be reset when * longjmps back into the cpu_exec loop. */ tb_lock(); - tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); + tb_gen_code(cs, current_pc, current_cs_base, current_flags, cflags= ); cpu_loop_exit_noexc(cs); } } diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 7100339..bf6f248 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -151,7 +151,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) target_ulong cs_base, pc; uint32_t flags; =20 - tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cf_mask()= ); if (tb =3D=3D NULL) { return tcg_ctx.code_gen_epilogue; } diff --git a/tests/qht-bench.c b/tests/qht-bench.c index 11c1cec..4cabdfd 100644 --- a/tests/qht-bench.c +++ b/tests/qht-bench.c @@ -103,7 +103,7 @@ static bool is_equal(const void *obj, const void *userp) =20 static inline uint32_t h(unsigned long v) { - return tb_hash_func6(v, 0, 0, 0); + return tb_hash_func7(v, 0, 0, 0, 0); } =20 /* --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237201828196.8915588839294; Sun, 16 Jul 2017 13:33:21 -0700 (PDT) Received: from localhost ([::1]:46831 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqEC-00081Q-HG for importer@patchew.org; Sun, 16 Jul 2017 16:33:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmc-0001Ay-2w for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmV-0008I6-31 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:38477) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008H0-TQ for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 9379820A53; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:42 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 569B87E17E; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=6lr Ua5kHzH8wGHhnyq4wMOylHVZJ1UqKGKB+ORXq2CM=; b=y4+H3auboELM3rduIYL jVVfS3a6BIoKaT3R8hagAoE3RNZVeJS0KKtXuWtS9FtOGWGxMqrJ8u+lP4ZGtdRy /q/+u/Ei09IzfunECr4oi4m8hHqPfV+CZMZPWpqWj+DgD61aRmQGGiMaIiivL8Uh m90tjFKfRVDY5NtGAzRwyxJ0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=6lrUa5kHzH8wGHhnyq4wMOylHVZJ1UqKGKB+ORXq2 CM=; b=cqXiA1sUQQrpw7C2gWe0BJkWC7je3pPEPTk4JgS6fUkxxE2w4eiLWLBk9 golZO0+FrA2PeZWQiZXqjk++wE3TrENWjo9qwbEgtxdjZbVzgAxU4svHUSmZ2bAu V+D6kjCs0YxEHVeGoo+BAC3ISLsXlwJxRTmhEkKPEiwmuJZH7AZBGC/BzEgCHwHH YLJVg0wHoe4FXHGUGJMH683YVbFYCnJDfjgFPsafRYxr1QZeXbmI3XbsDa4DpXlF nFK2zim2JEaidFEEgv7e/DsCZEZfmNpiczikcP0nKUCnTtq3i3XhhCQZWtU5qj86 J2Wpe8+IIZWr87HOlxp6oDhn6LX6g== X-ME-Sender: X-Sasl-enc: 0KyFCHYSg71CY2Kbc4NUfQ5vjzpkhLX2Bh9r/mwS9Nkr 1500235482 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:58 -0400 Message-Id: <1500235468-15341-16-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 15/45] target/arm: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/arm/helper-a64.h | 4 ++++ target/arm/helper-a64.c | 38 ++++++++++++++++++++++++++++++++------ target/arm/op_helper.c | 7 ------- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ target/arm/translate.c | 9 +++++++-- 5 files changed, 68 insertions(+), 21 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba..85d8674 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -43,4 +43,8 @@ DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32= , f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82c..d0e435c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -430,8 +430,9 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, = uint32_t bytes) } =20 /* Returns 0 on success; 1 otherwise. */ -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -440,7 +441,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -484,8 +485,21 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env,= uint64_t addr, return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true); +} + +static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -494,7 +508,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -537,3 +551,15 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env,= uint64_t addr, =20 return !success; } + +uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true); +} diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..a28f254 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -450,13 +450,6 @@ void HELPER(yield)(CPUARMState *env) ARMCPU *cpu =3D arm_env_get_cpu(env); CPUState *cs =3D CPU(cpu); =20 - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - g_assert(!parallel_cpus); - /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the * top level loop so that a more deserving VCPU has a chance to run. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49d35c2..af28b26 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1333,13 +1333,18 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 3: /* WFI */ s->is_jmp =3D DISAS_WFI; return; + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* YIELD */ - if (!parallel_cpus) { + if (!(s->tb->cflags & CF_PARALLEL)) { s->is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ - if (!parallel_cpus) { + if (!(s->tb->cflags & CF_PARALLEL)) { s->is_jmp =3D DISAS_WFE; } return; @@ -1916,11 +1921,25 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } } } else { TCGv_i64 val =3D cpu_reg(s, rt); diff --git a/target/arm/translate.c b/target/arm/translate.c index ebbe407..34aa95d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4492,8 +4492,13 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* yield */ - if (!parallel_cpus) { + if (!(s->tb->cflags & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->is_jmp =3D DISAS_YIELD; } @@ -4503,7 +4508,7 @@ static void gen_nop_hint(DisasContext *s, int val) s->is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ - if (!parallel_cpus) { + if (!(s->tb->cflags & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->is_jmp =3D DISAS_WFE; } --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236996573548.5361507887523; Sun, 16 Jul 2017 13:29:56 -0700 (PDT) Received: from localhost ([::1]:46815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqAt-0005Y1-Cx for importer@patchew.org; Sun, 16 Jul 2017 16:29:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46212) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001At-Gs for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmV-0008IP-9V for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:48581) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmV-0008Hv-69 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:43 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D591C20A4D; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:42 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 9F1F72450F; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Msx oB5nSm/n7+hgKaC02rS8rjR+RvsACEG/6fu9Pm0M=; b=c+FtpqRp7WrCaIf7RU+ DjBw07SfgIkHfVXZ2UK+NEkkVGEimHvMDJY7jvsNuAQ96m5Ov89xyt3N/hN+tu3d Bcjb/S09N9FG6Yi7Dv7Mzmj84M64ruC68t8vEVxlAmdqan7ObNYFQPPY61x+ay2g 96Mx3nTNfpHPXZdhGtf2QYmg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=MsxoB5nSm/n7+hgKaC02rS8rjR+RvsACEG/6fu9Pm 0M=; b=pgiS3l7lBXAWyyTPS05aqNUqYHzNf4+8eaaagDFmN55/OlsfIJ6yOaYqV 4M3xTG4YLRwQXdJO0Yf+dY30r1zR2ykFGK8PPTrYuqL8gDeIv1VDX37PluOvPXZG Yvp5HZ1waovCHm774jcRo4el7mT6M9h+v59oO5KmXciT2DzMzqAHoYfNsIHKieh4 Re0irEklWCF8htY0qvUCKtTeSsagHy4prMv7saycJkKxi877vfbn6IC8Zc2l/Sxv E3duafk3SnAPM5MW+4zpA93J4tNPtMSs+rVCYI0/+BsDJ+PaHD8UiLadF4vRxtXg 0289eMp63MtAunnI/76bk6RUiD5Hg== X-ME-Sender: X-Sasl-enc: 0KyEHmMSh71DdWaFeJVUfQ5vjzpkhLX2Bh9r/mwS9Nkr 1500235482 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:59 -0400 Message-Id: <1500235468-15341-17-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 16/45] target/hppa: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++---- target/hppa/translate.c | 12 ++++++++++-- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 789f07f..0a6b900 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -3,7 +3,9 @@ DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) =20 DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 DEF_HELPER_FLAGS_1(probe_r, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(probe_w, TCG_CALL_NO_RWG_SE, tl, tl) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index c05c0d5..3104404 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -76,7 +76,8 @@ static void atomic_store_3(CPUHPPAState *env, target_ulon= g addr, uint32_t val, #endif } =20 -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, + bool parallel) { uintptr_t ra =3D GETPC(); =20 @@ -89,7 +90,7 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr,= target_ulong val) break; case 1: /* The 3 byte store must appear atomic. */ - if (parallel_cpus) { + if (parallel) { atomic_store_3(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); @@ -102,14 +103,26 @@ void HELPER(stby_b)(CPUHPPAState *env, target_ulong a= ddr, target_ulong val) } } =20 -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) +{ + do_stby_b(env, addr, val, false); +} + +void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, + target_ulong val) +{ + do_stby_b(env, addr, val, true); +} + +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong v= al, + bool parallel) { uintptr_t ra =3D GETPC(); =20 switch (addr & 3) { case 3: /* The 3 byte store must appear atomic. */ - if (parallel_cpus) { + if (parallel) { atomic_store_3(env, addr - 3, val, 0xffffff00u, ra); } else { cpu_stw_data_ra(env, addr - 3, val >> 16, ra); @@ -132,6 +145,17 @@ void HELPER(stby_e)(CPUHPPAState *env, target_ulong ad= dr, target_ulong val) } } =20 +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) +{ + do_stby_e(env, addr, val, false); +} + +void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, + target_ulong val) +{ + do_stby_e(env, addr, val, true); +} + target_ulong HELPER(probe_r)(target_ulong addr) { return page_check_range(addr, 1, PAGE_READ); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 91053e2..fde3dba 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2309,9 +2309,17 @@ static ExitStatus trans_stby(DisasContext *ctx, uint= 32_t insn, val =3D load_gpr(ctx, rt); =20 if (a) { - gen_helper_stby_e(cpu_env, addr, val); + if (ctx->tb->cflags & CF_PARALLEL) { + gen_helper_stby_e_parallel(cpu_env, addr, val); + } else { + gen_helper_stby_e(cpu_env, addr, val); + } } else { - gen_helper_stby_b(cpu_env, addr, val); + if (ctx->tb->cflags & CF_PARALLEL) { + gen_helper_stby_b_parallel(cpu_env, addr, val); + } else { + gen_helper_stby_b(cpu_env, addr, val); + } } =20 if (m) { --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236877113441.5418726280691; Sun, 16 Jul 2017 13:27:57 -0700 (PDT) Received: from localhost ([::1]:46808 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq8x-0003qA-JR for importer@patchew.org; Sun, 16 Jul 2017 16:27:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001Aq-I6 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmV-0008Je-EQ for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39555) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmV-0008II-BS for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:43 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 09B6020A57; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:43 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C2CD77E17E; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=EYQ ETpt/otuAPYPJHDkmY2GIy3BVrkCwo/tQSpKj0gA=; b=XAtS9aEoi4GDY7qA23c wSV/kiD+InTqPDPKxfzV9V8Pfx7GwKkTapayiA3cinUqQg3MaY16R5DkDRlEU4A+ az65mqdkEmkfR75+bDE2L+QCvlBjSs73eX8t3ZFm8RdV6WuDgJ9pcKqJaa+siI3s mXT+vEugqhBlb50nuGUYj6xg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=EYQETpt/otuAPYPJHDkmY2GIy3BVrkCwo/tQSpKj0 gA=; b=Dgmx8Z3+yYpiwPd8RcsizMByaqbdwN2puvd1YmTUsFZsSJmpTeQNxseDq ytgLgENnJb3qLrKw9QjsSjwioodHTVdoC2XPiCOMnLxGiHFgWUitPxKoQmzvQgyf G99950p412NJO79yKrf9gdYQqAsu5kUsoOb9hR9fbaex6rcYJvoM7pylbp95TYM2 2UUQxddceMX3OneT/TfxGJUzCIIsCbOLpUQjAjDztXN161+T2g0NY2FkYDFcCdKT diOnmnza8fwPlzValCxFTiSWSc9migLoaLfrldtY3iQAQ3A+OAH+M9IDHwdRQDUZ KvfNUDGMzg7XEj9BPA7vf7qdzPpwg== X-ME-Sender: X-Sasl-enc: 0KyJDm4WjKxHeHCVZ4dUfQ5vjzpkhLX2Bh9r/mwS9Nkr 1500235482 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:00 -0400 Message-Id: <1500235468-15341-18-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 17/45] target/i386: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 291c577..c5e4d77 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -5263,7 +5263,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) goto illegal_op; gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && parallel_cpus) { + if ((s->prefix & PREFIX_LOCK) && s->tb->cflags & CF_PARALLEL) { gen_helper_cmpxchg16b(cpu_env, cpu_A0); } else { gen_helper_cmpxchg16b_unlocked(cpu_env, cpu_A0); @@ -5274,7 +5274,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, if (!(s->cpuid_features & CPUID_CX8)) goto illegal_op; gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && parallel_cpus) { + if ((s->prefix & PREFIX_LOCK) && s->tb->cflags & CF_PARALLEL) { gen_helper_cmpxchg8b(cpu_env, cpu_A0); } else { gen_helper_cmpxchg8b_unlocked(cpu_env, cpu_A0); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236781402917.2532863716277; Sun, 16 Jul 2017 13:26:21 -0700 (PDT) Received: from localhost ([::1]:46803 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq7Q-0002o9-4y for importer@patchew.org; Sun, 16 Jul 2017 16:26:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001Aw-RY for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmV-0008K9-QN for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:57525) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmV-0008JT-M4 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:43 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 38A1E20A5A; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:43 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id EFA452450F; Sun, 16 Jul 2017 16:04:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=CuP 8GWJXSz38RDxtx1oJv7NO80WGP4qZV/7AcrnSYhU=; b=vK1n/GlerUQEdK6qYL+ Ti9hrRXz7/zm4wtlovpwdXJMx2Nr5Fmq36TEE23obfZCTa4vA/MJlyP7SYAAQYtO WTAzc1eGnM2Y9tIdc3oEfgZJcYhqKJ3Zb4SoTHPIJzQPvm9su+u4UX895veJDiUq Dgea6AwrQufeWWKplAErqkr0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=CuP8GWJXSz38RDxtx1oJv7NO80WGP4qZV/7AcrnSY hU=; b=deI59YO0QlPr6TSRyXioo6vSip5DoqscLXqZAo+BFmOM+5p6ganukA2Mj fCSChjd1xcEMF1Fbu45doueDHjHsFKQI8CFpwo0lIzA+JgkuiUS2iXf5BPHmnu8s 8jyCf4/MJ0gEKykGPzkzdAFKE+Wmkb3R/nNOzbZcbO+9R+EaDeX5cdd4hlO7ZTEn P7V33rnATC2KfMDNQ8fU8gUmaA25oVsAkl70G0IQUE35HHAhFlqiShH8AIixJdjV u2o/nwv1Fsm4Asg75WvacWQEZOdPIKkkf3uyuV/PgLauLD0lX0rq9QFqtYKMDf5C 1bKLOA5wiAluU27/TS/qAPKVodlwg== X-ME-Sender: X-Sasl-enc: 0KyEHWQChKNXZ3GZdJ9UfQ5vjzpkhLX2Bh9r/mwS9Nkr 1500235482 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:01 -0400 Message-Id: <1500235468-15341-19-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 18/45] target/m68k: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota --- target/m68k/helper.h | 2 ++ target/m68k/op_helper.c | 32 ++++++++++++++++++++++++++++---- target/m68k/translate.c | 12 ++++++++++-- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 475a1f2..137ef48 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -10,7 +10,9 @@ DEF_HELPER_4(divsll, void, env, int, int, s32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) DEF_HELPER_4(cas2w, void, env, i32, i32, i32) +DEF_HELPER_4(cas2w_parallel, void, env, i32, i32, i32) DEF_HELPER_4(cas2l, void, env, i32, i32, i32) +DEF_HELPER_4(cas2l_parallel, void, env, i32, i32, i32) =20 #define dh_alias_fp ptr #define dh_ctype_fp FPReg * diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 7b5126c..061d468 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -361,7 +361,8 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int re= gr, int32_t den) env->dregs[numr] =3D quot; } =20 -void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +static void do_cas2w(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32= _t a2, + bool parallel) { uint32_t Dc1 =3D extract32(regs, 9, 3); uint32_t Dc2 =3D extract32(regs, 6, 3); @@ -374,7 +375,7 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, ui= nt32_t a1, uint32_t a2) int16_t l1, l2; uintptr_t ra =3D GETPC(); =20 - if (parallel_cpus) { + if (parallel) { /* Tell the main loop we need to serialize this insn. */ cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } else { @@ -399,7 +400,19 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, u= int32_t a1, uint32_t a2) env->dregs[Dc2] =3D deposit32(env->dregs[Dc2], 0, 16, l2); } =20 -void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +{ + do_cas2w(env, regs, a1, a2, false); +} + +void HELPER(cas2w_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1, + uint32_t a2) +{ + do_cas2w(env, regs, a1, a2, true); +} + +static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32= _t a2, + bool parallel) { uint32_t Dc1 =3D extract32(regs, 9, 3); uint32_t Dc2 =3D extract32(regs, 6, 3); @@ -416,7 +429,7 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, ui= nt32_t a1, uint32_t a2) TCGMemOpIdx oi; #endif =20 - if (parallel_cpus) { + if (parallel) { /* We're executing in a parallel context -- must be atomic. */ #ifdef CONFIG_ATOMIC64 uint64_t c, u, l; @@ -470,6 +483,17 @@ void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, u= int32_t a1, uint32_t a2) env->dregs[Dc2] =3D l2; } =20 +void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t= a2) +{ + do_cas2l(env, regs, a1, a2, false); +} + +void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1, + uint32_t a2) +{ + do_cas2l(env, regs, a1, a2, true); +} + struct bf_data { uint32_t addr; uint32_t bofs; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3a519b7..5cfa25f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2308,7 +2308,11 @@ DISAS_INSN(cas2w) (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2w(cpu_env, regs, addr1, addr2); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_cas2w_parallel(cpu_env, regs, addr1, addr2); + } else { + gen_helper_cas2w(cpu_env, regs, addr1, addr2); + } tcg_temp_free(regs); =20 /* Note that cas2w also assigned to env->cc_op. */ @@ -2354,7 +2358,11 @@ DISAS_INSN(cas2l) (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2l(cpu_env, regs, addr1, addr2); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2); + } else { + gen_helper_cas2l(cpu_env, regs, addr1, addr2); + } tcg_temp_free(regs); =20 /* Note that cas2l also assigned to env->cc_op. */ --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236672975881.9653713427092; Sun, 16 Jul 2017 13:24:32 -0700 (PDT) Received: from localhost ([::1]:46791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq5f-0001Ow-GO for importer@patchew.org; Sun, 16 Jul 2017 16:24:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmd-0001B4-7Q for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmV-0008K2-QA for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:43041) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmV-0008Jm-MW for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:43 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 69AE820A54; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:43 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 2899E7E17E; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=j06 mtkwy5KPjzlo+J9lo2fj4gBNV2aSdvMZgq1wqWq8=; b=VOgjq4XdbkDVs1uowc4 xTj+TYD7e3H8gJLykYJaI5CIjSTmdKKN8x0w4//HmWsJTzip03n7l2BB6NzhF21N OD134RF2RxFMPyEKgpq0KgU8iHRyRCZCpoJqDAJQIEsgVoZLozhvBtdDV/dITK1A fiD0vF97vE9960ocSMpXlNjM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=j06mtkwy5KPjzlo+J9lo2fj4gBNV2aSdvMZgq1wqW q8=; b=T8lEbMLUoq79U2fT58fj3AnXq/TmzO5zBy4luh49T6nC/BFgiMiFZU3Qy e3StBT5AdIN8ejb/R0xt3C3lJLOQ846SqBGoh8U9Ftym9jCjRwIOJVqgiixP9pUp QAD3j7rwzYtezZzO196q9b6udbfrDlXWHG6Yk5hWGTtI/m8+TTu0Nfjtyo/A/ubH OAzu5kJJnPC0GBd70duwplmnx0su/1QMgb45WiaSyW/uf6fqaMtYRMilMeFJjRWH 2zS+n6mcNy4+/EbylOITZHUrHgP7Yal91XHXaj8UrBLMt2oITMn6t4DdzGeRKaEL OTDswVNHjVIabFZcL7dk/xRUV790A== X-ME-Sender: X-Sasl-enc: KvYjnphw1SXQkg6/zBkMgACehBKSVlRzGI4ldKMp+9Ee 1500235483 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:02 -0400 Message-Id: <1500235468-15341-20-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 19/45] target/s390x: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/s390x/helper.h | 3 +++ target/s390x/mem_helper.c | 50 +++++++++++++++++++++++++++++++++++++++----= ---- target/s390x/translate.c | 20 +++++++++++++++---- 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 964097b..db697d9 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -33,6 +33,7 @@ DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i64, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) +DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) @@ -104,7 +105,9 @@ DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) DEF_HELPER_2(stfle, i32, env, i64) DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lpq_parallel, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(stpq_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i64) DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index ede8471..2d9cdb1 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1312,8 +1312,8 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1= , uint32_t r2, return cc; } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) +static void do_cdsg(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3, bool parallel) { uintptr_t ra =3D GETPC(); Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); @@ -1321,7 +1321,7 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, Int128 oldv; bool fail; =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -1353,6 +1353,18 @@ void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + do_cdsg(env, addr, r1, r3, false); +} + +void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) +{ + do_cdsg(env, addr, r1, r3, true); +} + #if !defined(CONFIG_USER_ONLY) void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { @@ -1795,12 +1807,12 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) #endif =20 /* load pair from quadword */ -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) +static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -1821,13 +1833,23 @@ uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t a= ddr) return hi; } =20 +uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) +{ + return do_lpq(env, addr, false); +} + +uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) +{ + return do_lpq(env, addr, true); +} + /* store pair to quadword */ -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) +static void do_stpq(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high, bool parallel) { uintptr_t ra =3D GETPC(); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -1845,6 +1867,18 @@ void HELPER(stpq)(CPUS390XState *env, uint64_t addr, } } =20 +void HELPER(stpq)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + do_stpq(env, addr, low, high, false); +} + +void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + do_stpq(env, addr, low, high, true); +} + /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. diff --git a/target/s390x/translate.c b/target/s390x/translate.c index b503c2c..6535f6c 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2024,7 +2024,11 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps = *o) addr =3D get_address(s, 0, b2, d2); t_r1 =3D tcg_const_i32(r1); t_r3 =3D tcg_const_i32(r3); - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); + } else { + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + } tcg_temp_free_i64(addr); tcg_temp_free_i32(t_r1); tcg_temp_free_i32(t_r3); @@ -2881,7 +2885,7 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *o) TCGMemOp mop =3D s->insn->data; =20 /* In a parallel context, stop the world and single step. */ - if (parallel_cpus) { + if (s->tb->cflags & CF_PARALLEL) { potential_page_fault(s); gen_exception(EXCP_ATOMIC); return EXIT_NORETURN; @@ -2902,7 +2906,11 @@ static ExitStatus op_lpd(DisasContext *s, DisasOps *= o) =20 static ExitStatus op_lpq(DisasContext *s, DisasOps *o) { - gen_helper_lpq(o->out, cpu_env, o->in2); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_lpq_parallel(o->out, cpu_env, o->in2); + } else { + gen_helper_lpq(o->out, cpu_env, o->in2); + } return_low128(o->out2); return NO_EXIT; } @@ -4219,7 +4227,11 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps = *o) =20 static ExitStatus op_stpq(DisasContext *s, DisasOps *o) { - gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + if (s->tb->cflags & CF_PARALLEL) { + gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); + } else { + gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + } return NO_EXIT; } =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235907402291.77228549158394; Sun, 16 Jul 2017 13:11:47 -0700 (PDT) Received: from localhost ([::1]:46732 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWptJ-000770-AV for importer@patchew.org; Sun, 16 Jul 2017 16:11:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001As-GZ for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmW-0008LM-0Q for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:50759) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmV-0008Jv-Tb for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:43 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 91C4D20A5E; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:43 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 5800E2450F; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=ydY c0O/wFM1vjw5ewc1Gt2rmY0vsjWlTzVkKtNQ9MeQ=; b=2AMLuKrbJtdR81F7FwO xSwQkfnw0nJXmt4d7QJSdC2hjbLODWF41ptHESwReqckqp3qkztapsqOuHvtmbj/ rJmAZleTQbRioet+rsDgRwPlCfrt+76djUTDUuZmPetcwdv+7UNLVMqwpFdW3acO EISr1505ZDip4F629mbHhThw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=ydYc0O/wFM1vjw5ewc1Gt2rmY0vsjWlTzVkKtNQ9M eQ=; b=hGgprZvQWSxbTFWvAH8ligI408Olv9dEQ21T6XtajFcbjZwGoHU9PhdNS FmhLQlBEMlgSG67LRiw2noh+3h2Kc0m4kBs+6vrtWBwXIuhl1mH/855S4inOr2ts xpA0G21M9gj16klqDncSPm47givBufcxUnWLaaLFrFHerHWW/l0X5Vs+Ggp0ufS7 qlZL4UkJHINoYHPABCixh/uk6QW0AueznI93lxrBAVwMeMzUY5PQP8z2GvZdrltT UqAZ8WGN55moRfYRWN8gfB2fVCQCHeN3c9xBKlmlne5KOpYnVSZj4Gv4kTz4E4l0 K+qXnPD69il12Cj/Es/ixU5Ih42pg== X-ME-Sender: X-Sasl-enc: KvYjjop+wCPWkxC/yBgMgACehBKSVlRzGI4ldKMp+9Ee 1500235483 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:03 -0400 Message-Id: <1500235468-15341-21-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 20/45] target/sparc: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index aa6734d..0274e83 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2450,7 +2450,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst= , TCGv addr, int insn) default: /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ - if (parallel_cpus) { + if (dc->tb->cflags & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { TCGv_i32 r_asi =3D tcg_const_i32(da.asi); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236158241140.03965592230736; Sun, 16 Jul 2017 13:15:58 -0700 (PDT) Received: from localhost ([::1]:46751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpxM-0002VU-TM for importer@patchew.org; Sun, 16 Jul 2017 16:15:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmc-0001Ax-2J for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmW-0008MW-4q for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:42111) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmW-0008KE-1G for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:44 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id BC6A120A59; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:43 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 829F87E17E; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=JC7 yrNY97LiYJENBkzgE1rLFqvX9jD6u7QMTdIQBBic=; b=g9HLD1iqz9zNsRauCrE /1Od/RJANZtORWH02mRYwH2YtDrrplSw4njgibIKBOq13gPPko21WdwQykhiMOSy G2o3HwEKLWXl2kqoz48kw7DbBSK7SzlaRR32RXoCoM1lNGdJTduJyMvINmQCbD1T pIS4cFezoZiHw1WIK04GlxCg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=JC7yrNY97LiYJENBkzgE1rLFqvX9jD6u7QMTdIQBB ic=; b=QpqXBbT8Dlc7Zy+ErqK0w+k9gq75tsBEBM8PGiARpEikndl/eKUWBVoNl YLHKKBbSD1QtnujL82BTa1v4pnGcdGut2cLf6Z+1g5iZmP0dUq1w4sLiBJr0BCjA 6xHeE95YGI47JLEV8i7r2d+sFr53AheOXZ8LPGmR3Ul+e7Crr1ILMDeCerjky9P/ 887z6xShx3PfJ/RSVoqPJli6OR16UnWkkSTiX/8LbKpu23uq8/IpyWCweeLa8m56 oFIZncYN89Yj0kBNG+U70P1GsL32SUXRD9z6TX+pVZtu6pqINIZbbHYH6pOXnjic uPfYmT9/34tkfm5dEbnWoAp9e7ifA== X-ME-Sender: X-Sasl-enc: KvY5m51zwzPBngW62x8MgACehBKSVlRzGI4ldKMp+9Ee 1500235483 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:04 -0400 Message-Id: <1500235468-15341-22-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 21/45] tcg: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a bit to TCGContext, storing there whether CF_PARALLEL is set before translating every TB. Most architectures have <=3D 32 registers, which results in a 4-byte hole in TCGContext. Use this hole for the bit we need; use a uint8_t instead of a bool, since a bool might take more than one byte in some systems. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- tcg/tcg.h | 1 + accel/tcg/translate-all.c | 1 + tcg/tcg-op.c | 10 +++++----- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 96872f8..bd1fdfa 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,6 +656,7 @@ struct TCGContext { uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_J= UMP */ =20 TCGRegSet reserved_regs; + uint8_t cf_parallel; /* whether CF_PARALLEL is set in tb->cflags */ intptr_t current_frame_offset; intptr_t frame_start; intptr_t frame_end; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 483248f..80ac85a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1275,6 +1275,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; + tcg_ctx.cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 205d07f..ef420d4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -150,7 +150,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg= a1, TCGArg a2, =20 void tcg_gen_mb(TCGBar mb_type) { - if (parallel_cpus) { + if (tcg_ctx.cf_parallel) { tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); } } @@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!parallel_cpus) { + if (!tcg_ctx.cf_parallel) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!parallel_cpus) { + if (!tcg_ctx.cf_parallel) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.cf_parallel) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.cf_parallel) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236045108541.7329990064385; Sun, 16 Jul 2017 13:14:05 -0700 (PDT) Received: from localhost ([::1]:46741 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpvX-0000vL-U2 for importer@patchew.org; Sun, 16 Jul 2017 16:14:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001Ao-GR for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmW-0008Mr-Cy for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:44391) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmW-0008LR-8e for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:44 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id ECA5620A48; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:43 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id AF4F52450F; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=QZr KlRIy/W/Gq8I7OWS0HqPxJ+gC8h6oH3V57gSGcm4=; b=awza5YyV2ARkleCVE49 EN6p3HVnxLZRKTrtydlaETfpGMLOw/Y5H1X4GBD3lIk7JQ1hK24kRbMktGO4vgRw B0DqviAeEyqaYlJ7PSvjYjNR7eK5rMuidfejZwb8xZdpbWX5AseUKHpQFlX2jYW/ gk0ibe8PtyHNTnGsfmhMjf/8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=QZrKlRIy/W/Gq8I7OWS0HqPxJ+gC8h6oH3V57gSGc m4=; b=cWlI26HVzPGejSFp3uFy65cHaXABdky/rDrJGRJ4xSm8C/hmdEi9tpl8w e1voOXRsS3eroJ7S8e1XR9ITpYolzQEEW7P62F5j8M2bX6HLDic/75h/dAMnOc7t wmYpU7egaJ0xZuKiToHbAY3aXIl9rLWWRoYcLg3AJoiZCosKgrVX1rpxuZYXl824 TRrGQglSiMx8QZ4wqgqsnABYmv6fI6Ia4TGVvwH6R/wuoYi24uIU0tE0ieaL49s6 tMgyTkkHQ2jaPpma0/Wkk59M/nBsOABEEM34l7eekUcb6rLWNBW4WAaYk049uCC+ G9xYryPa01bauY0DxdTgJYQAlKEfg== X-ME-Sender: X-Sasl-enc: KvYrg4VwyyXIkxmvwAgMgACehBKSVlRzGI4ldKMp+9Ee 1500235483 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:05 -0400 Message-Id: <1500235468-15341-23-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 22/45] cpu-exec: lookup/generate TB outside exclusive region during step_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that all code generation has been converted to check CF_PARALLEL, we can generate !CF_PARALLEL code without having yet set !parallel_cpus -- and therefore without having to be in the exclusive region during cpu_exec_step_atomic. While at it, merge cpu_exec_step into cpu_exec_step_atomic. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index efe5c85..23e6d2c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -226,7 +226,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, } #endif =20 -static void cpu_exec_step(CPUState *cpu) +void cpu_exec_step_atomic(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); TranslationBlock *tb; @@ -239,16 +239,26 @@ static void cpu_exec_step(CPUState *cpu) if (tb =3D=3D NULL) { mmap_lock(); tb_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, mask_cf(cflag= s)); + if (likely(tb =3D=3D NULL)) { + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + } tb_unlock(); mmap_unlock(); } =20 + start_exclusive(); + + /* Since we got here, we know that parallel_cpus must be true. */ + parallel_cpus =3D false; cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); + parallel_cpus =3D true; + + end_exclusive(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -262,18 +272,6 @@ static void cpu_exec_step(CPUState *cpu) } } =20 -void cpu_exec_step_atomic(CPUState *cpu) -{ - start_exclusive(); - - /* Since we got here, we know that parallel_cpus must be true. */ - parallel_cpus =3D false; - cpu_exec_step(cpu); - parallel_cpus =3D true; - - end_exclusive(); -} - struct tb_desc { target_ulong pc; target_ulong cs_base; --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235758942450.354896918622; Sun, 16 Jul 2017 13:09:18 -0700 (PDT) Received: from localhost ([::1]:46719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpqv-0004gj-OC for importer@patchew.org; Sun, 16 Jul 2017 16:09:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001Ar-GR for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmW-0008N2-Hq for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:41485) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmW-0008Mj-E5 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:44 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 21E6E20A5B; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:44 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id DC3667E17E; Sun, 16 Jul 2017 16:04:43 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Bv/6kU5n3CXzUZd /SeOHHDMbodYDyQsgd1AZTJWrRoU=; b=U6ybxQ73/gH7fsNbEyichrUJde5hub1 /8IhbSa/pDpJUU9ZXR3pSoHrtGiW9gKpbnVr+JGfBkovkfiR/CgdaFvd6Yp+EQMk p4xHFv5eCHyq+GuBPi7gsgy6gwrymu+UoDWobJRLN2Ar1SrTNiVfqecmqWYaddet dIze7UtgT2P8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=Bv/6kU5n3CXzUZd/SeOHHDMbodYDyQsgd1AZTJWrRoU=; b=nZvlRap9 oFZviciePGoK20v8PPBLdjkpW0sxn/di71S6iOl/014KqPXlSAg6CClTfWcPHxCb zaS7c3KZAL6/8+nE3I87jfrX8SCl24+tfqvt0bUL349JvNHf9ccagkGmuEmbZ7Fz /WaON81OLXOdPBbQqF0CSA7d+Qryo1Z/sJDn52qWF7BQWb64Xtv5rU5EafSgq2HF bbDMnCjkC/R5k9+0Hqrw/D/t3HfgogSThsDmyx6lydcjpWiKKFwlwYuAP3XC0ftv QymLj0NyHe3+o2QLX9TQyEBdJM/EAGRn0OvCTplVqWugH4ZvhWipBn+fsj4IHzBe AhN8ETXXdVanRw== X-ME-Sender: X-Sasl-enc: KvYghph01iPRigSjxw8MgACehBKSVlRzGI4ldKMp+9Ee 1500235483 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:06 -0400 Message-Id: <1500235468-15341-24-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 23/45] translate-all: define and use DEBUG_TB_FLUSH_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This gets rid of some ifdef checks while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 80ac85a..c38448c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_FLUSH +#define DEBUG_TB_FLUSH_GATE 1 +#else +#define DEBUG_TB_FLUSH_GATE 0 +#endif + #if !defined(CONFIG_USER_ONLY) /* TB consistency checks only implemented for usermode emulation. */ #undef DEBUG_TB_CHECK @@ -899,13 +905,13 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) goto done; } =20 -#if defined(DEBUG_TB_FLUSH) - printf("qemu: flush code_size=3D%ld nb_tbs=3D%d avg_tb_size=3D%ld\n", - (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer= )) / - tcg_ctx.tb_ctx.nb_tbs : 0); -#endif + if (DEBUG_TB_FLUSH_GATE) { + printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, + tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / + tcg_ctx.tb_ctx.nb_tbs : 0); + } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236674419348.81457476167407; Sun, 16 Jul 2017 13:24:34 -0700 (PDT) Received: from localhost ([::1]:46792 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq5h-0001QP-8d for importer@patchew.org; Sun, 16 Jul 2017 16:24:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46255) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmc-0001B0-Mu for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmW-0008NE-NG for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:50 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:57813) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmW-0008My-JF for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:44 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 5327020A5F; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:44 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 144042450F; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=rezXetaBobQWS9Q X2k4GHgXvfTBeY9n7/+dmkFYiZ/A=; b=sZaiN76GFFjURWtRGvbYUKefmatdB4u u/JgZYtvWe5qqK5qb37GZNH3glD3EwyiFEKUS4katR7E8wauCO/qkeaE3KGK/Uv7 yzMikTq7zYHxytI1C1Po9oYPwzxThdf87a0p7oDubBuW+GBYU8jxRMsNnHbYDZ9b +xcJKtA4B0zM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=rezXetaBobQWS9QX2k4GHgXvfTBeY9n7/+dmkFYiZ/A=; b=kN7442Pg rsDbr8iJzo3T8vwN+5dQ6eWijM1nLgyR/8lsMCr3597XUovms0Icq08IfGxF6sb+ p8dEhTl7GiQcOklZcgcIcwDxgf5XhkIp2/BaToIJl/gomWXgRARwa168tzDuPdIX iMF+gqfHmbuT/hfoV7Vb+ATKvMsroDyprc3qT0+kE/MnxRNkpIe53mMzZXrCRXGI EJtiuEIu1uQoDEgF7P0CV0jVakRo2FVezIczll2zqKxndD28rA1iJyYyZOovInHf lFeWW68pYQeIMBep+43+nXVQBCVzK506jpWSr+fvuAxJ5bx8iNpY+752M4Ti0RRQ TiNsNDYK7Jhl3w== X-ME-Sender: X-Sasl-enc: 5ixChuQA5S8ADASqIhFffreyVp+lEFDHStWq0DdFx6xP 1500235484 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:07 -0400 Message-Id: <1500235468-15341-25-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 24/45] exec-all: introduce TB_PAGE_ADDR_FMT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 And fix the following warning when DEBUG_TB_INVALIDATE is enabled in translate-all.c: CC mipsn32-linux-user/accel/tcg/translate-all.o /data/src/qemu/accel/tcg/translate-all.c: In function =E2=80=98tb_alloc_pag= e=E2=80=99: /data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format =E2=80=98%l= x=E2=80=99 expects argument of type =E2=80=98long unsigned int=E2=80=99, bu= t argument 2 has type =E2=80=98tb_page_addr_t {aka unsigned int}=E2=80=99 [= -Werror=3Dformat=3D] printf("protecting code page: 0x" TARGET_FMT_lx "\n", ^ cc1: all warnings being treated as errors /data/src/qemu/rules.mak:66: recipe for target 'accel/tcg/translate-all.o' = failed make[1]: *** [accel/tcg/translate-all.o] Error 1 Makefile:328: recipe for target 'subdir-mipsn32-linux-user' failed make: *** [subdir-mipsn32-linux-user] Error 2 cota@flamenco:/data/src/qemu/build ((18f3fe1...) *$)$ Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 2 ++ accel/tcg/translate-all.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b3f04c3..13975af 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,10 @@ type. */ #if defined(CONFIG_USER_ONLY) typedef abi_ulong tb_page_addr_t; +#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx #else typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif =20 /* is_jmp field values */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c38448c..c8fa86a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1198,8 +1198,7 @@ static inline void tb_alloc_page(TranslationBlock *tb, mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); #ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TARGET_FMT_lx "\n", - page_addr); + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); #endif } #else --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236417150354.19574819201773; Sun, 16 Jul 2017 13:20:17 -0700 (PDT) Received: from localhost ([::1]:46766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq1X-00064q-U5 for importer@patchew.org; Sun, 16 Jul 2017 16:20:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001Av-Iy for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmW-0008NP-Uj for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:48403) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmW-0008N9-Qr for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:44 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7CCD720A61; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:44 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 41B297E17E; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=bmwWtNgJvN6fdby 8hGKnefJ38jXc7gCBo6M2QUBYfP0=; b=p7O7VfoJXT89WwYP4VgJ1k1PAwuHVKR nrLunQZRmpuz7EIUj8hDfhQC/zNZPOz4HiL0HAXsX80catwUWForXUL21vF60xlT EJf6CubVBVUIJO7FqZHrdlAjwW4Cvhxc+BF0WEK/r1lOnRDjdKkFgKlNmvdfWpQV tx6o4vmgO928= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=bmwWtNgJvN6fdby8hGKnefJ38jXc7gCBo6M2QUBYfP0=; b=PJoDC/9p WeYRxKLvYTEpxcVY70n/6/0Pr1g++yOPhO7GxuBoGZloe/UD9ogzcFgzI1ZJrLX9 8NsEoZ5d0DAH32XzZuJ9NjW4oQq1npTK9sQPRElKusafAphZ37cyCh70W8ZSeBKm Q5gPYh6M8FWX5S0V8Ltzi9M5mzOGLC7TCopbhTofviXg/tz9eVm5BQtbjX0UPO4v f6vmZHnxvqTUy29+ZcZS+KopschNoNxSvNQMYjShm0OW6YuexdD3E7ydqP28g/AS byvW/1o/BMFoyWvQ/Y6lkpeclP0ud5q/etDgpFHEruu9R1BEI0EAQ5sqR4Vz1ND/ i4BYTE8RHzb3zA== X-ME-Sender: X-Sasl-enc: 5ixSh/oX8CwXFQSxIg1ffreyVp+lEFDHStWq0DdFx6xP 1500235484 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:08 -0400 Message-Id: <1500235468-15341-26-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 25/45] translate-all: define and use DEBUG_TB_INVALIDATE_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This gets rid of an ifdef check while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c8fa86a..aaf3993 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_INVALIDATE +#define DEBUG_TB_INVALIDATE_GATE 1 +#else +#define DEBUG_TB_INVALIDATE_GATE 0 +#endif + #ifdef DEBUG_TB_FLUSH #define DEBUG_TB_FLUSH_GATE 1 #else @@ -1197,9 +1203,9 @@ static inline void tb_alloc_page(TranslationBlock *tb, } mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); -#ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); -#endif + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); + } } #else /* if some code is already present, then the pages are already --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236293506442.29969962759617; Sun, 16 Jul 2017 13:18:13 -0700 (PDT) Received: from localhost ([::1]:46759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpzY-00049i-8X for importer@patchew.org; Sun, 16 Jul 2017 16:18:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46264) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmc-0001B2-T1 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmX-0008NW-41 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:50 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:60087) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmW-0008NJ-WB for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:45 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id A87A520763; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:44 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 6D56F2450F; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=9PRaVCuh2f0JLEW XJK9hEIH4tbweealESkujF+rf39k=; b=r6W3lsOpbFoAy41jJQlHPrVXN1SD3d7 dQou3Mu3tpqGxeaGDUMLuRo3/j7Kcqz+/ZEX+DnD9Inp4/xB73q50BFfb6RYYEbt EI85Xbw41N+sNMj/GG0gDlydImMZcu77IHzKsnPEVAbTPrkoUb768Iw43iQh/PUa GY6Mwbfn0f4o= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=9PRaVCuh2f0JLEWXJK9hEIH4tbweealESkujF+rf39k=; b=YsYPQkbz gw/tcQ0gNSHZBXccS0LbOFYNC21X3cAXur48rMTuQg76YTVNOv9CQU3vNRvnLS9U O50b5+tl+B6Q5/QHKVOVWKMliILdhB95D819jBKDwwsK/fJNxonfXyqgJ9W9wtSs +ky98Q3FJpF0b5fda0MkP7+UL6/dGOCr4CP6XO6Dm9M974coTFXObNIbfnr9Z0Cq G6De68KcIn2iD6Kn0YWqf50toS14vluhEwDUwFpyCAXEjf4z5fTUB3ccgxmXyZlb LqZKj03FGuPDVWpswuSPZCVWyv4SvHDcr8Pd/lXbJO15oxSp7zX19rBM8N1P5MRz R8IZH9FvgcvMHQ== X-ME-Sender: X-Sasl-enc: 5ixKhf4T8CUSGxyoMgBffreyVp+lEFDHStWq0DdFx6xP 1500235484 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:09 -0400 Message-Id: <1500235468-15341-27-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 26/45] translate-all: define and use DEBUG_TB_CHECK_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This prevents bit rot by ensuring the debug code is compiled when building a user-mode target. Unfortunately the helpers are user-mode-only so we cannot fully get rid of the ifdef checks. Add a comment to explain this. Suggested-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index aaf3993..df1ccbf 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -82,6 +82,12 @@ #undef DEBUG_TB_CHECK #endif =20 +#ifdef DEBUG_TB_CHECK +#define DEBUG_TB_CHECK_GATE 1 +#else +#define DEBUG_TB_CHECK_GATE 0 +#endif + /* Access to the various translations structures need to be serialised via= locks * for consistency. This is automatic for SoftMMU based system * emulation due to its single threaded nature. In user-mode emulation @@ -950,7 +956,13 @@ void tb_flush(CPUState *cpu) } } =20 -#ifdef DEBUG_TB_CHECK +/* + * Formerly ifdef DEBUG_TB_CHECK. These debug functions are user-mode-only, + * so in order to prevent bit rot we compile them unconditionally in user-= mode, + * and let the optimizer get rid of them by wrapping their user-only calle= rs + * with if (DEBUG_TB_CHECK_GATE). + */ +#ifdef CONFIG_USER_ONLY =20 static void do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp) @@ -994,7 +1006,7 @@ static void tb_page_check(void) qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); } =20 -#endif +#endif /* CONFIG_USER_ONLY */ =20 static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock= *tb) { @@ -1242,8 +1254,10 @@ static void tb_link_page(TranslationBlock *tb, tb_pa= ge_addr_t phys_pc, tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 -#ifdef DEBUG_TB_CHECK - tb_page_check(); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_page_check(); + } #endif } =20 @@ -2223,8 +2237,10 @@ int page_unprotect(target_ulong address, uintptr_t p= c) /* and since the content will be modified, we must invalidate the corresponding translated code. */ current_tb_invalidated |=3D tb_invalidate_phys_page(addr, pc); -#ifdef DEBUG_TB_CHECK - tb_invalidate_check(addr); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_invalidate_check(addr); + } #endif } mprotect((void *)g2h(host_start), qemu_host_page_size, --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237095593853.7493366483405; Sun, 16 Jul 2017 13:31:35 -0700 (PDT) Received: from localhost ([::1]:46827 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqCU-0006xB-Cc for importer@patchew.org; Sun, 16 Jul 2017 16:31:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46258) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmc-0001B1-Q2 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmX-0008O1-Qc for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:50 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:33937) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmX-0008Na-MR for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:45 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id DF02E20A62; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:44 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 9B3387E17E; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=MJb WQKvklNsfBJrB5oXkmZDXUk31Kw3e74+RxXLef9g=; b=WAKXZgexeXO6KulhAwi CwulxzXLoUhJTN69yPWnJzq6v2f0YxnXsOYR79NiFtD7Ff16d0Rn8jZr5MUjYF8N V716L1N+SR1U0vXJET8LgiEt5xHoBptf7HL/UrO/wWRL6mX+iweU0Ze0Wvh3aVAp yiR79UEDPPENh7hdYI49A/G4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=MJbWQKvklNsfBJrB5oXkmZDXUk31Kw3e74+RxXLef 9g=; b=WgIsPmZBw72+tY6DSOTNewUrYb0XZ8GLC73hBaJJoMWGj0qsQOiZGRJGe jSvZ5ASUxitr2FOVOrVOpyIVglSoBxQdwAJES2TgkBZwVPCjKxdERcUNn94OcaA9 NlFVW1Ma/DZx+EBc8ensWSb2n4ob6d4PvIlJHuHTMXRkHv0J7d7MefTrXYTsTjM4 TfX5M7mnOILp7HBiDglDl/qT5EXrtpeO7TiwH/pvjEyYzc5VxG9oGdrXYKaWAyon bWnTJWIajaONLBXypqedCqvBlGUQOPrIz7H9Q3FMZJqkcJmkeuiSWdDOduXNW0ae KzpKmwUSptYFDYsNllPCbAz877Hmw== X-ME-Sender: X-Sasl-enc: 5ixIhuMc9jIGGQmyOR9ffreyVp+lEFDHStWq0DdFx6xP 1500235484 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:10 -0400 Message-Id: <1500235468-15341-28-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 27/45] exec-all: extract tb->tc_* into a separate struct tc_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In preparation for adding tc.size to be able to keep track of TB's using the binary search tree implementation from glib. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 20 ++++++++++++++------ accel/tcg/cpu-exec.c | 6 +++--- accel/tcg/translate-all.c | 20 ++++++++++---------- tcg/tcg-runtime.c | 4 ++-- tcg/tcg.c | 4 ++-- 5 files changed, 31 insertions(+), 23 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 13975af..7356c3e 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -315,6 +315,14 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced= (CPUState *cpu, #define USE_DIRECT_JUMP #endif =20 +/* + * Translation Cache-related fields of a TB. + */ +struct tb_tc { + void *ptr; /* pointer to the translated code */ + uint8_t *search; /* pointer to search data */ +}; + struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -334,8 +342,8 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - void *tc_ptr; /* pointer to the translated code */ - uint8_t *tc_search; /* pointer to search data */ + struct tb_tc tc; + /* original tb when cflags has CF_NOCACHE */ struct TranslationBlock *orig_tb; /* first and second physical page containing code. The lower bit @@ -442,7 +450,7 @@ static inline void tb_set_jmp_target(TranslationBlock *= tb, int n, uintptr_t addr) { uint16_t offset =3D tb->jmp_insn_offset[n]; - tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); + tb_set_jmp_target1((uintptr_t)(tb->tc.ptr + offset), addr); } =20 #else @@ -469,11 +477,11 @@ static inline void tb_add_jump(TranslationBlock *tb, = int n, qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); + tb->tc.ptr, tb->pc, n, + tb_next->tc.ptr, tb_next->pc); =20 /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); =20 /* add in TB jmp circular list */ tb->jmp_list_next[n] =3D tb_next->jmp_list_first; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 23e6d2c..ba36f83 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -143,11 +143,11 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *= cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr =3D itb->tc_ptr; + uint8_t *tb_ptr =3D itb->tc.ptr; =20 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %p [%d: " TARGET_FMT_lx "] %s\n", - itb->tc_ptr, cpu->cpu_index, itb->pc, + itb->tc.ptr, cpu->cpu_index, itb->pc, lookup_symbol(itb->pc)); =20 #if defined(DEBUG_DISAS) @@ -179,7 +179,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc_ptr, last_tb->pc, + last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); if (cc->synchronize_from_tb) { cc->synchronize_from_tb(cpu, last_tb); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index df1ccbf..cfef6da 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -260,7 +260,7 @@ static target_long decode_sleb128(uint8_t **pp) which comes from the host pc of the end of the code implementing the in= sn. =20 Each line of the table is encoded as sleb128 deltas from the previous - line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }. + line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. That is, the first column is seeded with the guest pc, the last column with the host pc, and the middle columns with zeros. */ =20 @@ -270,7 +270,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) uint8_t *p =3D block; int i, j, n; =20 - tb->tc_search =3D block; + tb->tc.search =3D block; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { target_ulong prev; @@ -305,9 +305,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uintptr_t searched_pc) { target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; - uintptr_t host_pc =3D (uintptr_t)tb->tc_ptr; + uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; - uint8_t *p =3D tb->tc_search; + uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER int64_t ti =3D profile_getclock(); @@ -858,7 +858,7 @@ void tb_free(TranslationBlock *tb) tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); =20 - tcg_ctx.code_gen_ptr =3D tb->tc_ptr - struct_size; + tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; tcg_ctx.tb_ctx.nb_tbs--; } } @@ -1059,7 +1059,7 @@ static inline void tb_remove_from_jmp_list(Translatio= nBlock *tb, int n) another TB */ static inline void tb_reset_jump(TranslationBlock *tb, int n) { - uintptr_t addr =3D (uintptr_t)(tb->tc_ptr + tb->jmp_reset_offset[n]); + uintptr_t addr =3D (uintptr_t)(tb->tc.ptr + tb->jmp_reset_offset[n]); tb_set_jmp_target(tb, n, addr); } =20 @@ -1294,7 +1294,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 gen_code_buf =3D tcg_ctx.code_gen_ptr; - tb->tc_ptr =3D gen_code_buf; + tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; @@ -1314,7 +1314,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_intermediate_code(env, tb); tcg_ctx.cpu =3D NULL; =20 - trace_translate_block(tb, tb->pc, tb->tc_ptr); + trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1360,7 +1360,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(tb->pc)) { qemu_log_lock(); qemu_log("OUT: [size=3D%d]\n", gen_code_size); - log_disas(tb->tc_ptr, gen_code_size); + log_disas(tb->tc.ptr, gen_code_size); qemu_log("\n"); qemu_log_flush(); qemu_log_unlock(); @@ -1696,7 +1696,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) while (m_min <=3D m_max) { m =3D (m_min + m_max) >> 1; tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc_ptr; + v =3D (uintptr_t)tb->tc.ptr; if (v =3D=3D tc_ptr) { return tb; } else if (tc_ptr < v) { diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index bf6f248..08fe077 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -157,9 +157,9 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, pc, + tb->tc.ptr, cpu->cpu_index, pc, lookup_symbol(pc)); - return tb->tc_ptr; + return tb->tc.ptr; } =20 void HELPER(exit_atomic)(CPUArchState *env) diff --git a/tcg/tcg.c b/tcg/tcg.c index 3559829..28c1b94 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2616,8 +2616,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 tcg_reg_alloc_start(s); =20 - s->code_buf =3D tb->tc_ptr; - s->code_ptr =3D tb->tc_ptr; + s->code_buf =3D tb->tc.ptr; + s->code_ptr =3D tb->tc.ptr; =20 tcg_out_tb_init(s); =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237528318372.8380769851127; Sun, 16 Jul 2017 13:38:48 -0700 (PDT) Received: from localhost ([::1]:46859 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqJS-0003jD-VC for importer@patchew.org; Sun, 16 Jul 2017 16:38:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46338) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpme-0001Ba-GE for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008OO-7S for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:52 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:35183) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008Nu-2v for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1861120A63; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:45 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C827F2450F; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=BOb nbrSCyucsP0Y5DwAXYtCj+HN8cCI0GqYbPrp47rs=; b=zUeme82goAu14XFa/E3 1PiEeMegl/NCKP3NODieh1vImM2wtpEK9yrM+1KVrvilhUyymETRX/6yUyGF9bJz vOldqDtFSxiDrw05s/gHByeRyuWcqdWWSVV+QOztWJtFmagdpkXrYeQFnbXik1Qu nsl8PPCTCIlOaJXyPFxnaSJM= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=BObnbrSCyucsP0Y5DwAXYtCj+HN8cCI0GqYbPrp47 rs=; b=L1NnIjGP4nRCmTLvPmScE4W1wpykQ5w4Jm7ruuXipFBluwd4C7/MPQz6y ESRxyPFpju00oGCRby2VXf3VhRv66vb5FRd+e10su9uLhRIgGBmW7hs43a+ebvFB DSSpOn8ywxAJm2lwKNQiHnxkkcz+89EIbqWKH0YY9UK5yKLE7i6UgxrEXc1gcaxd /PjNaOsSRAPmvDprgAcfCFP8Dg1RJEddKAd1nLpfexwC5wxpn/O/dAGWXu6urU7W uHwADl4qzvPgfO8IMwyTHh0ct8NVSc8dOYzSxI8tVix3yihjSByeGx6fqoZsGVyq QX+z3Bn4FNpxFpSe0kTNnwFYYYt5Q== X-ME-Sender: X-Sasl-enc: 5ixUgOwS9iMEBRe2MhRffreyVp+lEFDHStWq0DdFx6xP 1500235484 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:11 -0400 Message-Id: <1500235468-15341-29-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 28/45] translate-all: use a binary search tree to track TBs in TBContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a prerequisite for supporting multiple TCG contexts, since we will have threads generating code in separate regions of code_gen_buffer. For this we need a new field (.size) in struct tb_tc to keep track of the size of the translated code. This field adds a 4-byte hole to the struct (and therefore to TranslationBlock), but we can live with that. The comparison function we use is optimized for the common case: insertions. Profiling shows that upon booting debian-arm, 98% of comparisons are between existing tb's (i.e. a->size and b->size are both !0), which happens during insertions (and removals, but those are rare). The remaining cases are lookups. From reading the glib sources we see that the first key is always the lookup key. However, the code does not assume this to always be the case because this behaviour is not guaranteed in the glib docs. However, we embed this knowledge in the code as a branch hint for the compiler. Note that tb_free does not free space in the code_gen_buffer anymore, since we cannot easily know whether the tb is the last one inserted in code_gen_buffer. The next patch in this series renames tb_free to tb_remove to reflect this. Performance-wise, lookups in tb_find_pc are the same as before: O(log n). However, insertions are O(log n) instead of O(1), which results in a small slowdown when booting debian-arm: Performance counter stats for 'build/arm-softmmu/qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Dimg/arm/jessie-arm32.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel img/arm/aarch32-current-linux-kernel-only.img \ -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): - Before: 8048.598422 task-clock (msec) # 0.931 CPUs utilized = ( +- 0.28% ) 16,974 context-switches # 0.002 M/sec = ( +- 0.12% ) 0 cpu-migrations # 0.000 K/sec 10,125 page-faults # 0.001 M/sec = ( +- 1.23% ) 35,144,901,879 cycles # 4.367 GHz = ( +- 0.14% ) stalled-cycles-frontend stalled-cycles-backend 65,758,252,643 instructions # 1.87 insns per cycl= e ( +- 0.33% ) 10,871,298,668 branches # 1350.707 M/sec = ( +- 0.41% ) 192,322,212 branch-misses # 1.77% of all branche= s ( +- 0.32% ) 8.640869419 seconds time elapsed = ( +- 0.57% ) - After: 8146.242027 task-clock (msec) # 0.923 CPUs utilized = ( +- 1.23% ) 17,016 context-switches # 0.002 M/sec = ( +- 0.40% ) 0 cpu-migrations # 0.000 K/sec 18,769 page-faults # 0.002 M/sec = ( +- 0.45% ) 35,660,956,120 cycles # 4.378 GHz = ( +- 1.22% ) stalled-cycles-frontend stalled-cycles-backend 65,095,366,607 instructions # 1.83 insns per cycl= e ( +- 1.73% ) 10,803,480,261 branches # 1326.192 M/sec = ( +- 1.95% ) 195,601,289 branch-misses # 1.81% of all branche= s ( +- 0.39% ) 8.828660235 seconds time elapsed = ( +- 0.38% ) Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 5 ++ include/exec/tb-context.h | 4 +- accel/tcg/translate-all.c | 217 ++++++++++++++++++++++++------------------= ---- 3 files changed, 118 insertions(+), 108 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 7356c3e..c7bf683 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -317,10 +317,15 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synce= d(CPUState *cpu, =20 /* * Translation Cache-related fields of a TB. + * This struct exists just for convenience; we keep track of TB's in a bin= ary + * search tree, and the only fields needed to compare TB's in the tree are + * @ptr and @size. @search is brought here for consistency, since it is al= so + * a TC-related field. */ struct tb_tc { void *ptr; /* pointer to the translated code */ uint8_t *search; /* pointer to search data */ + unsigned int size; }; =20 struct TranslationBlock { diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index 25c2afe..1fa8dcc 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -31,10 +31,8 @@ typedef struct TBContext TBContext; =20 struct TBContext { =20 - TranslationBlock **tbs; + GTree *tb_tree; struct qht htable; - size_t tbs_size; - int nb_tbs; /* any access to the tbs or the page table must use this lock */ QemuMutex tb_lock; =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index cfef6da..7a01af0 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -776,6 +776,48 @@ static inline void *alloc_code_gen_buffer(void) } #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ =20 +/* compare a pointer @ptr and a tb_tc @s */ +static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s) +{ + if (ptr >=3D s->ptr + s->size) { + return 1; + } else if (ptr < s->ptr) { + return -1; + } + return 0; +} + +static gint tb_tc_cmp(gconstpointer ap, gconstpointer bp) +{ + const struct tb_tc *a =3D ap; + const struct tb_tc *b =3D bp; + + /* + * When both sizes are set, we know this isn't a lookup and therefore + * the two buffers are non-overlapping. + * This is the most likely case: every TB must be inserted; lookups + * are a lot less frequent. + */ + if (likely(a->size && b->size)) { + /* a->ptr =3D=3D b->ptr would mean the buffers overlap */ + g_assert(a->ptr !=3D b->ptr); + + if (a->ptr > b->ptr) { + return 1; + } + return -1; + } + /* + * All lookups have either .size field set to 0. + * From the glib sources we see that @ap is always the lookup key. How= ever + * the docs provide no guarantee, so we just mark this case as likely. + */ + if (likely(a->size =3D=3D 0)) { + return ptr_cmp_tb_tc(a->ptr, b); + } + return ptr_cmp_tb_tc(b->ptr, a); +} + static inline void code_gen_alloc(size_t tb_size) { tcg_ctx.code_gen_buffer_size =3D size_code_gen_buffer(tb_size); @@ -784,15 +826,7 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } - - /* size this conservatively -- realloc later if needed */ - tcg_ctx.tb_ctx.tbs_size =3D - tcg_ctx.code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE / 8; - if (unlikely(!tcg_ctx.tb_ctx.tbs_size)) { - tcg_ctx.tb_ctx.tbs_size =3D 64 * 1024; - } - tcg_ctx.tb_ctx.tbs =3D g_new(TranslationBlock *, tcg_ctx.tb_ctx.tbs_si= ze); - + tcg_ctx.tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); } =20 @@ -829,7 +863,6 @@ void tcg_exec_init(unsigned long tb_size) static TranslationBlock *tb_alloc(target_ulong pc) { TranslationBlock *tb; - TBContext *ctx; =20 assert_tb_locked(); =20 @@ -837,12 +870,6 @@ static TranslationBlock *tb_alloc(target_ulong pc) if (unlikely(tb =3D=3D NULL)) { return NULL; } - ctx =3D &tcg_ctx.tb_ctx; - if (unlikely(ctx->nb_tbs =3D=3D ctx->tbs_size)) { - ctx->tbs_size *=3D 2; - ctx->tbs =3D g_renew(TranslationBlock *, ctx->tbs, ctx->tbs_size); - } - ctx->tbs[ctx->nb_tbs++] =3D tb; return tb; } =20 @@ -851,16 +878,7 @@ void tb_free(TranslationBlock *tb) { assert_tb_locked(); =20 - /* In practice this is mostly used for single use temporary TB - Ignore the hard cases and just back up if this TB happens to - be the last one generated. */ - if (tcg_ctx.tb_ctx.nb_tbs > 0 && - tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { - size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); - - tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; - tcg_ctx.tb_ctx.nb_tbs--; - } + g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc); } =20 static inline void invalidate_page_bitmap(PageDesc *p) @@ -918,11 +936,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) } =20 if (DEBUG_TB_FLUSH_GATE) { - printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / - tcg_ctx.tb_ctx.nb_tbs : 0); + size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + + printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%td= \n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs := 0); } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { @@ -933,7 +952,10 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data= tb_flush_count) cpu_tb_jmp_cache_clear(cpu); } =20 - tcg_ctx.tb_ctx.nb_tbs =3D 0; + /* Increment the refcount first so that destroy acts as a reset */ + g_tree_ref(tcg_ctx.tb_ctx.tb_tree); + g_tree_destroy(tcg_ctx.tb_ctx.tb_tree); + qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 @@ -1347,6 +1369,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, if (unlikely(search_size < 0)) { goto buffer_overflow; } + tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER tcg_ctx.code_time +=3D profile_getclock() - ti; @@ -1397,6 +1420,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * through the physical hash table and physical page list. */ tb_link_page(tb, phys_pc, phys_page2); + g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb); return tb; } =20 @@ -1675,37 +1699,16 @@ static bool tb_invalidate_phys_page(tb_page_addr_t = addr, uintptr_t pc) } #endif =20 -/* find the TB 'tb' such that tb[0].tc_ptr <=3D tc_ptr < - tb[1].tc_ptr. Return NULL if not found */ +/* + * Find the TB 'tb' such that + * tb->tc.ptr <=3D tc_ptr < tb->tc.ptr + tb->tc.size + * Return NULL if not found. + */ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) { - int m_min, m_max, m; - uintptr_t v; - TranslationBlock *tb; + struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 - if (tcg_ctx.tb_ctx.nb_tbs <=3D 0) { - return NULL; - } - if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || - tc_ptr >=3D (uintptr_t)tcg_ctx.code_gen_ptr) { - return NULL; - } - /* binary search (cf Knuth) */ - m_min =3D 0; - m_max =3D tcg_ctx.tb_ctx.nb_tbs - 1; - while (m_min <=3D m_max) { - m =3D (m_min + m_max) >> 1; - tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc.ptr; - if (v =3D=3D tc_ptr) { - return tb; - } else if (tc_ptr < v) { - m_max =3D m - 1; - } else { - m_min =3D m + 1; - } - } - return tcg_ctx.tb_ctx.tbs[m_max]; + return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1893,63 +1896,67 @@ static void print_qht_statistics(FILE *f, fprintf_f= unction cpu_fprintf, g_free(hgram); } =20 +struct tb_tree_stats { + size_t target_size; + size_t max_target_size; + size_t direct_jmp_count; + size_t direct_jmp2_count; + size_t cross_page; +}; + +static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer = data) +{ + const TranslationBlock *tb =3D value; + struct tb_tree_stats *tst =3D data; + + tst->target_size +=3D tb->size; + if (tb->size > tst->max_target_size) { + tst->max_target_size =3D tb->size; + } + if (tb->page_addr[1] !=3D -1) { + tst->cross_page++; + } + if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { + tst->direct_jmp_count++; + if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { + tst->direct_jmp2_count++; + } + } + return false; +} + void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) { - int i, target_code_size, max_target_code_size; - int direct_jmp_count, direct_jmp2_count, cross_page; - TranslationBlock *tb; + struct tb_tree_stats tst =3D {}; struct qht_stats hst; + size_t nb_tbs; =20 tb_lock(); =20 - target_code_size =3D 0; - max_target_code_size =3D 0; - cross_page =3D 0; - direct_jmp_count =3D 0; - direct_jmp2_count =3D 0; - for (i =3D 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) { - tb =3D tcg_ctx.tb_ctx.tbs[i]; - target_code_size +=3D tb->size; - if (tb->size > max_target_code_size) { - max_target_code_size =3D tb->size; - } - if (tb->page_addr[1] !=3D -1) { - cross_page++; - } - if (tb->jmp_reset_offset[0] !=3D TB_JMP_RESET_OFFSET_INVALID) { - direct_jmp_count++; - if (tb->jmp_reset_offset[1] !=3D TB_JMP_RESET_OFFSET_INVALID) { - direct_jmp2_count++; - } - } - } + nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); cpu_fprintf(f, "gen code size %td/%zd\n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); - cpu_fprintf(f, "TB count %d\n", tcg_ctx.tb_ctx.nb_tbs); - cpu_fprintf(f, "TB avg target size %d max=3D%d bytes\n", - tcg_ctx.tb_ctx.nb_tbs ? target_code_size / - tcg_ctx.tb_ctx.nb_tbs : 0, - max_target_code_size); + cpu_fprintf(f, "TB count %zu\n", nb_tbs); + cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", + nb_tbs ? tst.target_size / nb_tbs : 0, + tst.max_target_size); cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)= \n", - tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - tcg_ctx.tb_ctx.nb_tbs : 0, - target_code_size ? (double) (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - target_code_size : 0); - cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page, - tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0); - cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=3D%d %d%%)\n", - direct_jmp_count, - tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0, - direct_jmp2_count, - tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) / - tcg_ctx.tb_ctx.nb_tbs : 0); + nb_tbs ? (tcg_ctx.code_gen_ptr - + tcg_ctx.code_gen_buffer) / nb_tbs : 0, + tst.target_size ? (double) (tcg_ctx.code_gen_ptr - + tcg_ctx.code_gen_buffer) / + tst.target_size : 0); + cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, + nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); + cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=3D%zu %zu%%)\= n", + tst.direct_jmp_count, + nb_tbs ? (tst.direct_jmp_count * 100) / nb_tbs : 0, + tst.direct_jmp2_count, + nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); =20 qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst); print_qht_statistics(f, cpu_fprintf, hst); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236413142260.64516986597584; Sun, 16 Jul 2017 13:20:13 -0700 (PDT) Received: from localhost ([::1]:46765 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq1T-000622-Sd for importer@patchew.org; Sun, 16 Jul 2017 16:20:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmb-0001Ap-GO for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008OC-3N for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52669) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmX-0008Nt-Vp for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 3FEF820A5C; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:45 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id F2B637E1FC; Sun, 16 Jul 2017 16:04:44 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=jlyKV2vnjLs640+ zxh9q87ehSJQskOkqSwL2Vxkj7NY=; b=e187JNqcbrGJEMiBjuwkbqH26+Z/p+5 SKwK72tZtBL/K2ZJQvdtiBO3s+1A9YQs/Jbr7AhmSTO6H27hv+Vxm1PeoWM8Es8G S8j23ni9F1gPWOCvxfnSwJmjOYgBcq7yPBvMzZr6lEgbJcDHXUiMrrpDxaWMmZs5 qjVhbFCuC6k8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=jlyKV2vnjLs640+zxh9q87ehSJQskOkqSwL2Vxkj7NY=; b=fepHhHki ee++RgdHdNXuCH871JIfgOwWzuhStJ+j1hzOiavZ1gLm9aMMpgEtSPhHoVT3X+5F LYH3kC05zp5lUc5PH5Lzte4yfd4JqdLy77M6+bq0SHkWRib3xxZE2XpHFoXIzBay hmGt7iUMmCzhNMQBeV5Oc3RYg/58+Peui8QdskxKXYIkegdC1sEiOFSw7CxIiNfB iyqxd4CxOXTUVKnyvR32t/kugtcLNYsZWQkTlA+dTFyfPHWu2Nc4snvb26LGNyeC jooT7VR5UxQfKeHzISqgA+qupbMH3SI+y4E2pvQJple6WCSKPagx2oZ3fxRzyhNk VEzXdUU+lX7YlA== X-ME-Sender: X-Sasl-enc: 5ixQkOoV+yIOFRytNgBffreyVp+lEFDHStWq0DdFx6xP 1500235484 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:12 -0400 Message-Id: <1500235468-15341-30-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 29/45] exec-all: rename tb_free to tb_remove X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 We don't really free anything in this function anymore; we just remove the TB from the binary search tree. Suggested-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 2 +- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index c7bf683..37487d7 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -408,7 +408,7 @@ static inline uint32_t curr_cf_mask(void) return val; } =20 -void tb_free(TranslationBlock *tb); +void tb_remove(TranslationBlock *tb); void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ba36f83..604fee2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -221,7 +221,7 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cyc= les, =20 tb_lock(); tb_phys_invalidate(tb, -1); - tb_free(tb); + tb_remove(tb); tb_unlock(); } #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7a01af0..7c6e401 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -375,7 +375,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) if (tb->cflags & CF_NOCACHE) { /* one-shot translation, invalidate it immediately */ tb_phys_invalidate(tb, -1); - tb_free(tb); + tb_remove(tb); } r =3D true; } @@ -874,7 +874,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) } =20 /* Called with tb_lock held. */ -void tb_free(TranslationBlock *tb) +void tb_remove(TranslationBlock *tb) { assert_tb_locked(); =20 @@ -1823,7 +1823,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) * cpu_exec_nocache() */ tb_phys_invalidate(tb->orig_tb, -1); } - tb_free(tb); + tb_remove(tb); } /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236537483907.4963723159193; Sun, 16 Jul 2017 13:22:17 -0700 (PDT) Received: from localhost ([::1]:46778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq3U-0007ey-20 for importer@patchew.org; Sun, 16 Jul 2017 16:22:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46283) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmd-0001B3-5E for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008OY-Bu for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:42911) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008Nx-6s for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7A57F20A64; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:45 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 3236024606; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=kru EQwQlTmy7tEjCAh1b68ocBCRRRWEg5DbI6hpbAjE=; b=Ji7p4w3qFMqYRZHybKD GSKDxa03c8P/Rf8FBGc4fTm7qDu/culaoweWiINjr55Mas6x5sXKSYWLN0IiqD7m 25CnpzrHH2A7dLT/i96gxKHBs39bFFMh0L4lCjJ/YpDUYIml5xYlGITDGe9/tfe+ gkNg6QaOanKhWjGxgBePmRDA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=kruEQwQlTmy7tEjCAh1b68ocBCRRRWEg5DbI6hpbA jE=; b=bVyvzXXp/+iqVkqIVROPYNP/9VLyfe9gi2v7ojfdlVOuNmGS1RjRT8tv7 w0SxLcSOxb6yBdFFSVOc1WCiJf8IyFG/pEua+/4V05+plsvmy3RTBP/PULCC9NUV R2i/hWz1dlwDjOClqIjT+Sje9YU8Y8XtqMN6qCrvNuNtyGdGU3KEEr0lY7Ev+jU9 LRb4qINThNob+lrgMwEVI2ssPTy3mxfkXQ9g1sQgAv8HyV0PuLM3D0Sk4LnNcAD2 YKRHqATntzJjPaCrj5X7qDo4+LfY6No9rYs+u4ChSGq0S0OgWRyCBYoNBQ7t+6lr fr7ZRkR2CWHkCteWlxH3kRTkPJCFQ== X-ME-Sender: X-Sasl-enc: NWno0ojr5ATZiRo8JrJouRTZtChV2oJYCrwJupfa25OH 1500235485 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:13 -0400 Message-Id: <1500235468-15341-31-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 30/45] translate-all: report correct avg host TB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since commit 6e3b2bfd6 ("tcg: allocate TB structs before the corresponding translated code") we are not fully utilizing code_gen_buffer for translated code, and therefore are incorrectly reporting the amount of translated code as well as the average host TB size. Address this by: - Making the conscious choice of misreporting the total translated code; doing otherwise would mislead users into thinking "-tb-size" is not honoured. - Expanding tb_tree_stats to accurately count the bytes of translated code = on the host, and using this for reporting the average tb host size, as well as the expansion ratio. In the future we might want to consider reporting the accurate numbers for the total translated code, together with a "bookkeeping/overhead" field to account for the TB structs. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7c6e401..b655931 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -923,6 +923,15 @@ static void page_flush_tb(void) } } =20 +static gboolean tb_host_size_iter(gpointer key, gpointer value, gpointer d= ata) +{ + const TranslationBlock *tb =3D value; + size_t *size =3D data; + + *size +=3D tb->tc.size; + return false; +} + /* flush all the translation blocks */ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) { @@ -937,11 +946,12 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) =20 if (DEBUG_TB_FLUSH_GATE) { size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + size_t host_size =3D 0; =20 - printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%td= \n", + g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_si= ze); + printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, - nb_tbs > 0 ? - (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / nb_tbs := 0); + nb_tbs > 0 ? host_size / nb_tbs : 0); } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { @@ -1897,6 +1907,7 @@ static void print_qht_statistics(FILE *f, fprintf_fun= ction cpu_fprintf, } =20 struct tb_tree_stats { + size_t host_size; size_t target_size; size_t max_target_size; size_t direct_jmp_count; @@ -1909,6 +1920,7 @@ static gboolean tb_tree_stats_iter(gpointer key, gpoi= nter value, gpointer data) const TranslationBlock *tb =3D value; struct tb_tree_stats *tst =3D data; =20 + tst->host_size +=3D tb->tc.size; tst->target_size +=3D tb->size; if (tb->size > tst->max_target_size) { tst->max_target_size =3D tb->size; @@ -1937,6 +1949,11 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); + /* + * Report total code size including the padding and TB structs; + * otherwise users might think "-tb-size" is not honoured. + * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. + */ cpu_fprintf(f, "gen code size %td/%zd\n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); @@ -1944,12 +1961,9 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fp= rintf) cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, tst.max_target_size); - cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)= \n", - nb_tbs ? (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / nb_tbs : 0, - tst.target_size ? (double) (tcg_ctx.code_gen_ptr - - tcg_ctx.code_gen_buffer) / - tst.target_size : 0); + cpu_fprintf(f, "TB avg host size %zu bytes (expansion ratio: %0.1f)= \n", + nb_tbs ? tst.host_size / nb_tbs : 0, + tst.target_size ? (double)tst.host_size / tst.target_size = : 0); cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=3D%zu %zu%%)\= n", --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235926929150.44431426722758; Sun, 16 Jul 2017 13:12:06 -0700 (PDT) Received: from localhost ([::1]:46733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWptd-0007KQ-GT for importer@patchew.org; Sun, 16 Jul 2017 16:12:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmi-0001Fy-Fw for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008Oj-FA for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:56 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:36327) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008O7-9L for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id BB0B120A66; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:45 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 658627E17E; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=CDi e2W1Hfgwyj8zFAPELddmsd9H3iTz5LcVk5le1wnQ=; b=dwIh9b0G8NSb7RyuPBy hgp/2hiLRPLW6bmOVBtgNJJRU3hFwtgP8aLDcCbTsvjNlUO8hp0kkfp2j3x3BSnK 5M8izpy3WYHUzqt87u9TvEaat7qKegj4qqX9iVFNjSoG56fVaoxp1yEHtOzOPC6N 83c/UG3geF+5uAeJ+vTPHkM8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=CDie2W1Hfgwyj8zFAPELddmsd9H3iTz5LcVk5le1w nQ=; b=fI8mGZ9b4R6bKMXWrRYX1eAoR0uXmXSDOqQW1xCoGJwJ6zR42Ha2B12Y/ dPTzQptRg2uMYcpTT6/f17xh954vviP6Ev4/eQQXKRU/gw1+RFpZAvG2JIvW4NOo 5ThGhMpQ10A3l4Y+uSYsv+LccmT6WOLeHKXk4j0bTCLIlF3M/9PQcyq6RnVrVjs3 +DFJjPaVnk0aFHrbvWb50fj4mwIXMQxuwK52zm5VXafuw9t5QSjvt92CY7U+Pw83 fjtXO7/BapFtsjqMPem1yAZ0H90v1U+Sq+qKmje1TGLBeGOo2S5dVwzMAvBUBlJD KIbdbnIFW0YupYrrZKBMl5ho960jg== X-ME-Sender: X-Sasl-enc: NWn01on5+APSgQI+Or9ouRTZtChV2oJYCrwJupfa25OH 1500235485 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:14 -0400 Message-Id: <1500235468-15341-32-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 31/45] tci: move tci_regs to tcg_qemu_tb_exec's stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota Acked-by: Richard Henderson --- tcg/tci.c | 552 +++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 279 insertions(+), 273 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 4bdc645..f3216c1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -55,93 +55,95 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, t= cg_target_ulong, tcg_target_ulong); #endif =20 -static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; - -static tcg_target_ulong tci_read_reg(TCGReg index) +static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) { - tci_assert(index < ARRAY_SIZE(tci_reg)); - return tci_reg[index]; + tci_assert(index < TCG_TARGET_NB_REGS); + return regs[index]; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGReg index) +static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) { - return (int8_t)tci_read_reg(index); + return (int8_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGReg index) +static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { - return (int16_t)tci_read_reg(index); + return (int16_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(TCGReg index) +static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { - return (int32_t)tci_read_reg(index); + return (int32_t)tci_read_reg(regs, index); } #endif =20 -static uint8_t tci_read_reg8(TCGReg index) +static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) { - return (uint8_t)tci_read_reg(index); + return (uint8_t)tci_read_reg(regs, index); } =20 -static uint16_t tci_read_reg16(TCGReg index) +static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { - return (uint16_t)tci_read_reg(index); + return (uint16_t)tci_read_reg(regs, index); } =20 -static uint32_t tci_read_reg32(TCGReg index) +static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { - return (uint32_t)tci_read_reg(index); + return (uint32_t)tci_read_reg(regs, index); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(TCGReg index) +static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { - return tci_read_reg(index); + return tci_read_reg(regs, index); } #endif =20 -static void tci_write_reg(TCGReg index, tcg_target_ulong value) +static void +tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { - tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < TCG_TARGET_NB_REGS); tci_assert(index !=3D TCG_AREG0); tci_assert(index !=3D TCG_REG_CALL_STACK); - tci_reg[index] =3D value; + regs[index] =3D value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg32s(TCGReg index, int32_t value) +static void +tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 -static void tci_write_reg8(TCGReg index, uint8_t value) +static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 -static void tci_write_reg32(TCGReg index, uint32_t value) +static void +tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_write_reg64(uint32_t high_index, uint32_t low_index, - uint64_t value) +static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, + uint32_t low_index, uint64_t value) { - tci_write_reg(low_index, value); - tci_write_reg(high_index, value >> 32); + tci_write_reg(regs, low_index, value); + tci_write_reg(regs, high_index, value >> 32); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg64(TCGReg index, uint64_t value) +static void +tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 @@ -188,94 +190,97 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) #endif =20 /* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong tci_read_r(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - tcg_target_ulong value =3D tci_read_reg(**tb_ptr); + tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint8_t value =3D tci_read_reg8(**tb_ptr); + uint8_t value =3D tci_read_reg8(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int8_t value =3D tci_read_reg8s(**tb_ptr); + int8_t value =3D tci_read_reg8s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint16_t value =3D tci_read_reg16(**tb_ptr); + uint16_t value =3D tci_read_reg16(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int16_t value =3D tci_read_reg16s(**tb_ptr); + int16_t value =3D tci_read_reg16s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t value =3D tci_read_reg32(**tb_ptr); + uint32_t value =3D tci_read_reg32(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t low =3D tci_read_r32(tb_ptr); - return tci_uint64(tci_read_r32(tb_ptr), low); + uint32_t low =3D tci_read_r32(regs, tb_ptr); + return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int32_t value =3D tci_read_reg32s(**tb_ptr); + int32_t value =3D tci_read_reg32s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint64_t value =3D tci_read_reg64(**tb_ptr); + uint64_t value =3D tci_read_reg64(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register(s) with target address from bytecode. */ -static target_ulong tci_read_ulong(uint8_t **tb_ptr) +static target_ulong +tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(tb_ptr); + target_ulong taddr =3D tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; #endif return taddr; } =20 /* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r =3D **tb_ptr; @@ -283,13 +288,13 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i(tb_ptr); } else { - value =3D tci_read_reg(r); + value =3D tci_read_reg(regs, r); } return value; } =20 /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint32_t value; TCGReg r =3D **tb_ptr; @@ -297,21 +302,21 @@ static uint32_t tci_read_ri32(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i32(tb_ptr); } else { - value =3D tci_read_reg32(r); + value =3D tci_read_reg32(regs, r); } return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { - uint32_t low =3D tci_read_ri32(tb_ptr); - return tci_uint64(tci_read_ri32(tb_ptr), low); + uint32_t low =3D tci_read_ri32(regs, tb_ptr); + return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint64_t value; TCGReg r =3D **tb_ptr; @@ -319,7 +324,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i64(tb_ptr); } else { - value =3D tci_read_reg64(r); + value =3D tci_read_reg64(regs, r); } return value; } @@ -465,12 +470,13 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t ret =3D 0; =20 - tci_reg[TCG_AREG0] =3D (tcg_target_ulong)env; - tci_reg[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] =3D sp_value; tci_assert(tb_ptr); =20 for (;;) { @@ -503,27 +509,27 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_ri(&tb_ptr); + t0 =3D tci_read_ri(regs, &tb_ptr); #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5), - tci_read_reg(TCG_REG_R6), - tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8), - tci_read_reg(TCG_REG_R9), - tci_read_reg(TCG_REG_R10)); - tci_write_reg(TCG_REG_R0, tmp64); - tci_write_reg(TCG_REG_R1, tmp64 >> 32); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10)); + tci_write_reg(regs, TCG_REG_R0, tmp64); + tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5)); - tci_write_reg(TCG_REG_R0, tmp64); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5)); + tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; case INDEX_op_br: @@ -533,46 +539,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare32(t1, t2, condition)); + tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare64(tmp64, v64, condition)); + tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)= ); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg64(t0, tci_compare64(t1, t2, condition)); + tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; case INDEX_op_movi_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg32(t0, t1); + tci_write_reg32(regs, t0, t1); break; =20 /* Load/store operations (32 bit). */ =20 case INDEX_op_ld8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -583,25 +589,25 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i32: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) =3D t0; @@ -611,46 +617,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 + t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 - t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 * t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 / t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 % t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -660,71 +666,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 & t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 | t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 ^ t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 << (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 >> (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, rol32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ror32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_r32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp= 32)); break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_ri32(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -737,20 +743,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_add2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 +=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 +=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_sub2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 -=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 -=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -762,86 +768,86 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(&tb_ptr); - tmp64 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t1, t0, t2 * tmp64); + t2 =3D tci_read_r32(regs, &tb_ptr); + tmp64 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, ~t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, -t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; case INDEX_op_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg64(t0, t1); + tci_write_reg64(regs, t0, t1); break; =20 /* Load/store operations (64 bit). */ =20 case INDEX_op_ld8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -850,43 +856,43 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld32u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32s(t0, *(int32_t *)(t1 + t2)); + tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg64(t0, *(uint64_t *)(t1 + t2)); + tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i64: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st32_i64: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) =3D t0; @@ -896,21 +902,21 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 + t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 - t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 * t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -927,71 +933,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 & t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 | t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 ^ t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 << (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 >> (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, rol64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ror64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_r64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp= 64)); break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_ri64(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -1003,29 +1009,29 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1033,51 +1039,51 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: TODO(); t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, bswap64(t1)); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, ~t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, -t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ @@ -1098,7 +1104,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1128,14 +1134,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp32); + tci_write_reg(regs, t0, tmp32); break; case INDEX_op_qemu_ld_i64: t0 =3D *tb_ptr++; if (TCG_TARGET_REG_BITS =3D=3D 32) { t1 =3D *tb_ptr++; } - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1177,14 +1183,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp64); + tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(t1, tmp64 >> 32); + tci_write_reg(regs, t1, tmp64 >> 32); } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: @@ -1207,8 +1213,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) } break; case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236543423135.05153083625123; Sun, 16 Jul 2017 13:22:23 -0700 (PDT) Received: from localhost ([::1]:46780 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq3a-0007im-4h for importer@patchew.org; Sun, 16 Jul 2017 16:22:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmf-0001CP-4H for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008Oo-GE for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:57697) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008OL-BG for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 0151820A68; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:46 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id A3F1E24772; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=0JugUyf9zAyCvk5 BYe1qZrXG/BkGnTUpWi/gn2zzCUk=; b=I26ri67mAOp+qlgBi77SpFtIkF7nWDY nrfY+1FEQLfxnZothRuIFD6hCJdiEVjjtM17uND20VO/Wy+sabD3w+qekDoWeOrF /GnWNgEKXSlrrIvR/fc1EysDmrZMEkEJPRTw2jmlGW4ZB1fJjT7UD/XpaC1JBCmL FMUYELlXInsg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=0JugUyf9zAyCvk5BYe1qZrXG/BkGnTUpWi/gn2zzCUk=; b=FALvWgEd KKUT1H7TZFqMhEhaqrROnSBPRpM6LeOvgbc76VrLPjopeqJGjY4V68Qsu693WR2C 2mnSQ8mSCLGnPRiW/9/jc2WgHC6JiiZt1MbRsjUKfJ4EJiMLesTpmU3VMgOoGQGn jeu8TpYTT/Sc76P0Qvbp/t9lscFDrhno7ybFUPAiOV+QDun4ajTu/qAzceaWZDiK 3fQKfi5InKJtySH/8199hgsGXLyL1f8mpAQtglRKKh6ad8BopGfJVrImuwKYHHfA 3uNIqdKIqS0xbQNSE7A2QbuAoQnkudumUY4/NU888N1Ejl7pk4UGTqmfVmYs/OhZ N1KVy1deBi4Ueg== X-ME-Sender: X-Sasl-enc: NWn21oL/5h/WihUqIrpouRTZtChV2oJYCrwJupfa25OH 1500235485 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:15 -0400 Message-Id: <1500235468-15341-33-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 32/45] tcg: take tb_ctx out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/tb-context.h | 2 ++ tcg/tcg.h | 2 -- accel/tcg/cpu-exec.c | 2 +- accel/tcg/translate-all.c | 57 +++++++++++++++++++++++--------------------= ---- linux-user/main.c | 6 ++--- 5 files changed, 34 insertions(+), 35 deletions(-) diff --git a/include/exec/tb-context.h b/include/exec/tb-context.h index 1fa8dcc..1d41202 100644 --- a/include/exec/tb-context.h +++ b/include/exec/tb-context.h @@ -41,4 +41,6 @@ struct TBContext { int tb_phys_invalidate_count; }; =20 +extern TBContext tb_ctx; + #endif diff --git a/tcg/tcg.h b/tcg/tcg.h index bd1fdfa..1090285 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -707,8 +707,6 @@ struct TCGContext { /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; =20 - TBContext tb_ctx; - /* Track which vCPU triggers events */ CPUState *cpu; /* *_trans */ TCGv_env tcg_env; /* *_exec */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 604fee2..0799b16 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -327,7 +327,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targe= t_ulong pc, phys_pc =3D get_page_addr_code(desc.env, pc); desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; h =3D tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); - return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); + return qht_lookup(&tb_ctx.htable, tb_cmp, &desc, h); } =20 static inline TranslationBlock *tb_find(CPUState *cpu, diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b655931..919ef6b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -154,6 +154,7 @@ static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ TCGContext tcg_ctx; +TBContext tb_ctx; bool parallel_cpus; =20 /* translation block context */ @@ -185,7 +186,7 @@ static void page_table_config_init(void) void tb_lock(void) { assert_tb_unlocked(); - qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_lock(&tb_ctx.tb_lock); have_tb_lock++; } =20 @@ -193,13 +194,13 @@ void tb_unlock(void) { assert_tb_locked(); have_tb_lock--; - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); } =20 void tb_lock_reset(void) { if (have_tb_lock) { - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); have_tb_lock =3D 0; } } @@ -826,15 +827,15 @@ static inline void code_gen_alloc(size_t tb_size) fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } - tcg_ctx.tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); - qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); + tb_ctx.tb_tree =3D g_tree_new(tb_tc_cmp); + qemu_mutex_init(&tb_ctx.tb_lock); } =20 static void tb_htable_init(void) { unsigned int mode =3D QHT_MODE_AUTO_RESIZE; =20 - qht_init(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode); + qht_init(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE, mode); } =20 /* Must be called before using the QEMU cpus. 'tb_size' is the size @@ -878,7 +879,7 @@ void tb_remove(TranslationBlock *tb) { assert_tb_locked(); =20 - g_tree_remove(tcg_ctx.tb_ctx.tb_tree, &tb->tc); + g_tree_remove(tb_ctx.tb_tree, &tb->tc); } =20 static inline void invalidate_page_bitmap(PageDesc *p) @@ -940,15 +941,15 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) /* If it is already been done on request of another CPU, * just retry. */ - if (tcg_ctx.tb_ctx.tb_flush_count !=3D tb_flush_count.host_int) { + if (tb_ctx.tb_flush_count !=3D tb_flush_count.host_int) { goto done; } =20 if (DEBUG_TB_FLUSH_GATE) { - size_t nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); + size_t nb_tbs =3D g_tree_nnodes(tb_ctx.tb_tree); size_t host_size =3D 0; =20 - g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_host_size_iter, &host_si= ze); + g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); @@ -963,17 +964,16 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) } =20 /* Increment the refcount first so that destroy acts as a reset */ - g_tree_ref(tcg_ctx.tb_ctx.tb_tree); - g_tree_destroy(tcg_ctx.tb_ctx.tb_tree); + g_tree_ref(tb_ctx.tb_tree); + g_tree_destroy(tb_ctx.tb_tree); =20 - qht_reset_size(&tcg_ctx.tb_ctx.htable, CODE_GEN_HTABLE_SIZE); + qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 tcg_ctx.code_gen_ptr =3D tcg_ctx.code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ - atomic_mb_set(&tcg_ctx.tb_ctx.tb_flush_count, - tcg_ctx.tb_ctx.tb_flush_count + 1); + atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); =20 done: tb_unlock(); @@ -982,7 +982,7 @@ done: void tb_flush(CPUState *cpu) { if (tcg_enabled()) { - unsigned tb_flush_count =3D atomic_mb_read(&tcg_ctx.tb_ctx.tb_flus= h_count); + unsigned tb_flush_count =3D atomic_mb_read(&tb_ctx.tb_flush_count); async_safe_run_on_cpu(cpu, do_tb_flush, RUN_ON_CPU_HOST_INT(tb_flush_count)); } @@ -1015,7 +1015,7 @@ do_tb_invalidate_check(struct qht *ht, void *p, uint3= 2_t hash, void *userp) static void tb_invalidate_check(target_ulong address) { address &=3D TARGET_PAGE_MASK; - qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_invalidate_check, &address); + qht_iter(&tb_ctx.htable, do_tb_invalidate_check, &address); } =20 static void @@ -1035,7 +1035,7 @@ do_tb_page_check(struct qht *ht, void *p, uint32_t ha= sh, void *userp) /* verify that all the pages have correct rights for code */ static void tb_page_check(void) { - qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); + qht_iter(&tb_ctx.htable, do_tb_page_check, NULL); } =20 #endif /* CONFIG_USER_ONLY */ @@ -1133,7 +1133,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, mask_cf(tb->cflags), tb->trace_vcpu_dstate); - qht_remove(&tcg_ctx.tb_ctx.htable, tb, h); + qht_remove(&tb_ctx.htable, tb, h); =20 /* * Mark the TB as invalid *after* it's been removed from tb_hash, which @@ -1168,7 +1168,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) /* suppress any remaining jumps to this TB */ tb_jmp_unlink(tb); =20 - tcg_ctx.tb_ctx.tb_phys_invalidate_count++; + tb_ctx.tb_phys_invalidate_count++; } =20 #ifdef CONFIG_SOFTMMU @@ -1284,7 +1284,7 @@ static void tb_link_page(TranslationBlock *tb, tb_pag= e_addr_t phys_pc, /* add in the hash table */ h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, mask_cf(tb->cflags), tb->trace_vcpu_dstate); - qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); + qht_insert(&tb_ctx.htable, tb, h); =20 #ifdef CONFIG_USER_ONLY if (DEBUG_TB_CHECK_GATE) { @@ -1430,7 +1430,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * through the physical hash table and physical page list. */ tb_link_page(tb, phys_pc, phys_page2); - g_tree_insert(tcg_ctx.tb_ctx.tb_tree, &tb->tc, tb); + g_tree_insert(tb_ctx.tb_tree, &tb->tc, tb); return tb; } =20 @@ -1718,7 +1718,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) { struct tb_tc s =3D { .ptr =3D (void *)tc_ptr }; =20 - return g_tree_lookup(tcg_ctx.tb_ctx.tb_tree, &s); + return g_tree_lookup(tb_ctx.tb_tree, &s); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1945,8 +1945,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) =20 tb_lock(); =20 - nb_tbs =3D g_tree_nnodes(tcg_ctx.tb_ctx.tb_tree); - g_tree_foreach(tcg_ctx.tb_ctx.tb_tree, tb_tree_stats_iter, &tst); + nb_tbs =3D g_tree_nnodes(tb_ctx.tb_tree); + g_tree_foreach(tb_ctx.tb_tree, tb_tree_stats_iter, &tst); /* XXX: avoid using doubles ? */ cpu_fprintf(f, "Translation buffer state:\n"); /* @@ -1972,15 +1972,14 @@ void dump_exec_info(FILE *f, fprintf_function cpu_f= printf) tst.direct_jmp2_count, nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); =20 - qht_statistics_init(&tcg_ctx.tb_ctx.htable, &hst); + qht_statistics_init(&tb_ctx.htable, &hst); print_qht_statistics(f, cpu_fprintf, hst); qht_statistics_destroy(&hst); =20 cpu_fprintf(f, "\nStatistics:\n"); cpu_fprintf(f, "TB flush count %u\n", - atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); - cpu_fprintf(f, "TB invalidate count %d\n", - tcg_ctx.tb_ctx.tb_phys_invalidate_count); + atomic_read(&tb_ctx.tb_flush_count)); + cpu_fprintf(f, "TB invalidate count %d\n", tb_ctx.tb_phys_invalidate_c= ount); cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 diff --git a/linux-user/main.c b/linux-user/main.c index ad03c9e..630c73d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -114,7 +114,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) void fork_start(void) { cpu_list_lock(); - qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_lock(&tb_ctx.tb_lock); mmap_fork_start(); } =20 @@ -130,11 +130,11 @@ void fork_end(int child) QTAILQ_REMOVE(&cpus, cpu, node); } } - qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_init(&tb_ctx.tb_lock); qemu_init_cpu_list(); gdbserver_fork(thread_cpu); } else { - qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); + qemu_mutex_unlock(&tb_ctx.tb_lock); cpu_list_unlock(); } } --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150023641236048.724010581018206; Sun, 16 Jul 2017 13:20:12 -0700 (PDT) Received: from localhost ([::1]:46764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq1T-00060q-75 for importer@patchew.org; Sun, 16 Jul 2017 16:20:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmd-0001BF-Oc for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008P5-JZ for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:52219) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008OS-Ge for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2522420A69; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:46 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id DB51F7E1FC; Sun, 16 Jul 2017 16:04:45 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=p2hdfjRusNgkFDg 6XWQc7YxAfcIt/WxqKojHIfFP9vE=; b=bUDCSDlwgwRowQVkeTxZQDqny2FQQoZ PvxJi86BEtGXMuUvK2gehVr/2IpHKMz2Ur5HXEpItQXZNX9jnZz3UtpcKj8fg0Ku l13bny0OK391u8cJrdYy2a51RPlGE+FZkOH0/fO6QbYzrG45RHG3esM67lNFY9IS lvta0mjZvSrs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=p2hdfjRusNgkFDg6XWQc7YxAfcIt/WxqKojHIfFP9vE=; b=oG6dJeDq xOtJTSE6WNxngUDrzyUKcgMOvdZB5/CQdVtlj0JiGop+ssxk+d1bu0YZc0LpnVYr vV+xUk0n117b/AKbjYTobrDUHSWgv6RQzRm4dLD4k/uUqfgnS2WMo5UJVz3XHXfF tqYjXkKifkHYKoGSvSTrnY8yH6zQDKY47qGYix2NUQ4dJVExianc6cdqkuMvzQDA Tiai8Tz9n9uTa4VFmiGp1P6dwY4sLBrQr+s9aCO11W2gtLsnnI0njUgWxp690c0B qSsM1HpHH7XuLP97v1haOyxUlMsjxKJOobQlDCbLNUAoby/D6V1JY/e1jLdBs3KV 6lldopXc+ohwfA== X-ME-Sender: X-Sasl-enc: NWnq1JDm5xzEhhoiL7BouRTZtChV2oJYCrwJupfa25OH 1500235485 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:16 -0400 Message-Id: <1500235468-15341-34-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 33/45] tcg: take .helpers out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Groundwork for supporting multiple TCG contexts. The hash table becomes read-only after it is filled in, so we can save space by keeping just a global pointer to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 2 -- tcg/tcg.c | 10 +++++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 1090285..7cbe802 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -664,8 +664,6 @@ struct TCGContext { =20 tcg_insn_unit *code_ptr; =20 - GHashTable *helpers; - #ifdef CONFIG_PROFILER /* profiling info */ int64_t tb_count1; diff --git a/tcg/tcg.c b/tcg/tcg.c index 28c1b94..c0c2d6c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -319,6 +319,7 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; +static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -329,7 +330,6 @@ void tcg_context_init(TCGContext *s) TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; - GHashTable *helper_table; =20 memset(s, 0, sizeof(*s)); s->nb_globals =3D 0; @@ -357,7 +357,7 @@ void tcg_context_init(TCGContext *s) =20 /* Register helpers. */ /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - s->helpers =3D helper_table =3D g_hash_table_new(NULL, NULL); + helper_table =3D g_hash_table_new(NULL, NULL); =20 for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, @@ -761,7 +761,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg re= t, unsigned sizemask, flags; TCGHelperInfo *info; =20 - info =3D g_hash_table_lookup(s->helpers, (gpointer)func); + info =3D g_hash_table_lookup(helper_table, (gpointer)func); flags =3D info->flags; sizemask =3D info->sizemask; =20 @@ -990,8 +990,8 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char *b= uf, static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) { const char *ret =3D NULL; - if (s->helpers) { - TCGHelperInfo *info =3D g_hash_table_lookup(s->helpers, (gpointer)= val); + if (helper_table) { + TCGHelperInfo *info =3D g_hash_table_lookup(helper_table, (gpointe= r)val); if (info) { ret =3D info->name; } --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150023773522529.927405737832032; Sun, 16 Jul 2017 13:42:15 -0700 (PDT) Received: from localhost ([::1]:46875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqMn-0005qB-Qo for importer@patchew.org; Sun, 16 Jul 2017 16:42:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmk-0001Hw-5i for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008PR-TD for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:58 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:48345) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008Ov-NP for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 5CE1820A6E; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:46 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 139E12450F; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Qxf uWKM4kWDHfPAuWPCFyKjKsngeuepPnVTWqhiLKd0=; b=XOhBtiSWV4w9gRIkXGm n7m9LtpdcbKuBu4PYSMp61tqjraJTRSukezr3iFP3KrQa2w2AB2ATRx/pTvVXEjS SAEhtjMPnXx8DfEh5O5QknNjacUcEUyctFTunHIzB5t6EW/COM8fjuvu3yMa5M+8 BTrbUC/dH6nhQeTSCBB/heTs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=QxfuWKM4kWDHfPAuWPCFyKjKsngeuepPnVTWqhiLK d0=; b=eYZJaVQ4pW4M6eOOlp6X2aGjxIPku2wWJQ6hctqyS2yxuookekFLCJRHV Qd9vyfpyx0NluXwFqcTPVscMSlAnlTwOVExF4XyiddPAB/Fsw4tdTNmPchDIMu9e NI4qPecUnxTzNLxksB8570pu86knthjXA519Rym9pPxb5dsaAzO1GeuJUU/ftD9H +equhbailo7jPOBx051wi3MzhSiHtdHH5rhMIIwMoJeOtGCGwLGoROVlkgTvH38n x6K4HmEyDu9Ao1de3rLYdZxYjhBEM/eaEAenLke4VXacvAC3BiRnJfCtMre35Bts FHLu11PjP91PKLBTIVQs9ngQTaufg== X-ME-Sender: X-Sasl-enc: svzudH1rkn8J7ruNeoH/TDVTY8PUDosMy0lPcBiHQ6PD 1500235486 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:17 -0400 Message-Id: <1500235468-15341-35-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 34/45] tcg: define tcg_init_ctx and make tcg_ctx a pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. To avoid diff churn we could do something like > TCGContext *tcg_ctx_ptr; > #define tcg_ctx (*tcg_ctx_ptr) as Richard suggested during review, but sooner or later we'd end up doing the conversion anyway, so do it now. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/gen-icount.h | 10 ++--- include/exec/helper-gen.h | 12 +++--- tcg/tcg-op.h | 80 +++++++++++++++++------------------ tcg/tcg.h | 15 +++---- accel/tcg/translate-all.c | 97 ++++++++++++++++++++++-----------------= ---- bsd-user/main.c | 2 +- linux-user/main.c | 2 +- target/alpha/translate.c | 2 +- target/arm/translate.c | 2 +- target/cris/translate.c | 2 +- target/cris/translate_v10.c | 2 +- target/hppa/translate.c | 2 +- target/i386/translate.c | 2 +- target/lm32/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/translate.c | 2 +- target/moxie/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/s390x/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tilegx/translate.c | 2 +- target/tricore/translate.c | 2 +- target/unicore32/translate.c | 2 +- target/xtensa/translate.c | 2 +- tcg/tcg-op.c | 58 +++++++++++++------------- tcg/tcg-runtime.c | 2 +- tcg/tcg.c | 21 +++++----- 30 files changed, 171 insertions(+), 168 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 9b3cb14..4a55da8 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -19,7 +19,7 @@ static inline void gen_tb_start(TranslationBlock *tb) count =3D tcg_temp_new_i32(); } =20 - tcg_gen_ld_i32(count, tcg_ctx.tcg_env, + tcg_gen_ld_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u32)); =20 if (tb->cflags & CF_USE_ICOUNT) { @@ -37,7 +37,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); =20 if (tb->cflags & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, tcg_ctx.tcg_env, + tcg_gen_st16_i32(count, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.= low)); } =20 @@ -56,13 +56,13 @@ static inline void gen_tb_end(TranslationBlock *tb, int= num_insns) tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); =20 /* Terminate the linked list. */ - tcg_ctx.gen_op_buf[tcg_ctx.gen_op_buf[0].prev].next =3D 0; + tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next =3D 0; } =20 static inline void gen_io_start(void) { TCGv_i32 tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } @@ -70,7 +70,7 @@ static inline void gen_io_start(void) static inline void gen_io_end(void) { TCGv_i32 tmp =3D tcg_const_i32(0); - tcg_gen_st_i32(tmp, tcg_ctx.tcg_env, + tcg_gen_st_i32(tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io)); tcg_temp_free_i32(tmp); } diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 8239ffc..3bcb901 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -9,7 +9,7 @@ #define DEF_HELPER_FLAGS_0(name, flags, ret) \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 0, NULL); \ } =20 #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ @@ -17,7 +17,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1)) \ { \ TCGArg args[1] =3D { dh_arg(t1, 1) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 1, args); \ } =20 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ @@ -25,7 +25,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ TCGArg args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 2, args); \ } =20 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ @@ -33,7 +33,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ TCGArg args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 3, args); \ } =20 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ @@ -43,7 +43,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 4, args); \ } =20 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ @@ -53,7 +53,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ { \ TCGArg args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(&tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \ + tcg_gen_callN(tcg_ctx, HELPER(name), dh_retvar(ret), 5, args); \ } =20 #include "helper.h" diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 18d01b2..75c15cc 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -40,161 +40,161 @@ void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCG= Arg, TCGArg, =20 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) { - tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1)); + tcg_gen_op1(tcg_ctx, opc, GET_TCGV_I32(a1)); } =20 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) { - tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1)); + tcg_gen_op1(tcg_ctx, opc, GET_TCGV_I64(a1)); } =20 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) { - tcg_gen_op1(&tcg_ctx, opc, a1); + tcg_gen_op1(tcg_ctx, opc, a1); } =20 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2)); } =20 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2)); } =20 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I32(a1), a2); } =20 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2); + tcg_gen_op2(tcg_ctx, opc, GET_TCGV_I64(a1), a2); } =20 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) { - tcg_gen_op2(&tcg_ctx, opc, a1, a2); + tcg_gen_op2(tcg_ctx, opc, a1, a2); } =20 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3)); } =20 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3)); } =20 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGArg a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3); } =20 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGArg a3) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3); } =20 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offs= et); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offse= t); } =20 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, TCGv_ptr base, TCGArg offset) { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offs= et); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offse= t); } =20 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4)); } =20 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4)); } =20 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4); } =20 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4); } =20 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4); } =20 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGArg a3, TCGArg a4) { - tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); + tcg_gen_op4(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4); } =20 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5)); } =20 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5)); } =20 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5); } =20 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5); } =20 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, TCGv_i32 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), a4, a5); } =20 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, TCGv_i64 a3, TCGArg a4, TCGArg a5) { - tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op5(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), a4, a5); } =20 @@ -202,7 +202,7 @@ static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_= i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGv_i32 a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), GET_TCGV_I32(a6)); } @@ -211,7 +211,7 @@ static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_= i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGv_i64 a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), GET_TCGV_I64(a6)); } @@ -220,7 +220,7 @@ static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv= _i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6); } =20 @@ -228,7 +228,7 @@ static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv= _i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6); } =20 @@ -236,7 +236,7 @@ static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCG= v_i32 a1, TCGv_i32 a2, TCGv_i32 a3, TCGv_i32 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6); } =20 @@ -244,7 +244,7 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCG= v_i64 a1, TCGv_i64 a2, TCGv_i64 a3, TCGv_i64 a4, TCGArg a5, TCGArg a6) { - tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), + tcg_gen_op6(tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6); } =20 @@ -253,12 +253,12 @@ static inline void tcg_gen_op6ii_i64(TCGOpcode opc, T= CGv_i64 a1, TCGv_i64 a2, =20 static inline void gen_set_label(TCGLabel *l) { - tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l)); + tcg_gen_op1(tcg_ctx, INDEX_op_set_label, label_arg(l)); } =20 static inline void tcg_gen_br(TCGLabel *l) { - tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l)); + tcg_gen_op1(tcg_ctx, INDEX_op_br, label_arg(l)); } =20 void tcg_gen_mb(TCGBar); @@ -732,12 +732,12 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret,= TCGv_i64 lo, TCGv_i64 hi) # if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc); + tcg_gen_op1(tcg_ctx, INDEX_op_insn_start, pc); } # else static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op2(tcg_ctx, INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); } # endif @@ -745,12 +745,12 @@ static inline void tcg_gen_insn_start(target_ulong pc) # if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1); + tcg_gen_op2(tcg_ctx, INDEX_op_insn_start, pc, a1); } # else static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op4(tcg_ctx, INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32), (uint32_t)a1, (uint32_t)(a1 >> 32)); } @@ -760,13 +760,13 @@ static inline void tcg_gen_insn_start(target_ulong pc= , target_ulong a1) static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2); + tcg_gen_op3(tcg_ctx, INDEX_op_insn_start, pc, a1, a2); } # else static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start, + tcg_gen_op6(tcg_ctx, INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32), (uint32_t)a1, (uint32_t)(a1 >> 32), (uint32_t)a2, (uint32_t)(a2 >> 32)); diff --git a/tcg/tcg.h b/tcg/tcg.h index 7cbe802..6913d4b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -726,18 +726,19 @@ struct TCGContext { target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; }; =20 -extern TCGContext tcg_ctx; +extern TCGContext tcg_init_ctx; +extern TCGContext *tcg_ctx; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { - int op_argi =3D tcg_ctx.gen_op_buf[op_idx].args; - tcg_ctx.gen_opparam_buf[op_argi + arg] =3D v; + int op_argi =3D tcg_ctx->gen_op_buf[op_idx].args; + tcg_ctx->gen_opparam_buf[op_argi + arg] =3D v; } =20 /* The number of opcodes emitted so far. */ static inline int tcg_op_buf_count(void) { - return tcg_ctx.gen_next_op_idx; + return tcg_ctx->gen_next_op_idx; } =20 /* Test for whether to terminate the TB for using too many opcodes. */ @@ -756,13 +757,13 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s); /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; uint8_t *ptr, *ptr_end; size =3D (size + sizeof(long) - 1) & ~(sizeof(long) - 1); ptr =3D s->pool_cur; ptr_end =3D ptr + size; if (unlikely(ptr_end > s->pool_end)) { - return tcg_malloc_internal(&tcg_ctx, size); + return tcg_malloc_internal(tcg_ctx, size); } else { s->pool_cur =3D ptr_end; return ptr; @@ -1100,7 +1101,7 @@ static inline unsigned get_mmuidx(TCGMemOpIdx oi) uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); #else # define tcg_qemu_tb_exec(env, tb_ptr) \ - ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) + ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_pt= r) #endif =20 void tcg_register_jit(void *buf, size_t buf_size); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 919ef6b..961e357 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -153,7 +153,8 @@ static int v_l2_levels; static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ -TCGContext tcg_ctx; +TCGContext tcg_init_ctx; +TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; =20 @@ -209,7 +210,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); =20 void cpu_gen_init(void) { - tcg_context_init(&tcg_ctx);=20 + tcg_context_init(&tcg_init_ctx); } =20 /* Encode VAL as a signed leb128 sequence at P. @@ -267,7 +268,7 @@ static target_long decode_sleb128(uint8_t **pp) =20 static int encode_search(TranslationBlock *tb, uint8_t *block) { - uint8_t *highwater =3D tcg_ctx.code_gen_highwater; + uint8_t *highwater =3D tcg_ctx->code_gen_highwater; uint8_t *p =3D block; int i, j, n; =20 @@ -280,12 +281,12 @@ static int encode_search(TranslationBlock *tb, uint8_= t *block) if (i =3D=3D 0) { prev =3D (j =3D=3D 0 ? tb->pc : 0); } else { - prev =3D tcg_ctx.gen_insn_data[i - 1][j]; + prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } - p =3D encode_sleb128(p, tcg_ctx.gen_insn_data[i][j] - prev); + p =3D encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); } - prev =3D (i =3D=3D 0 ? 0 : tcg_ctx.gen_insn_end_off[i - 1]); - p =3D encode_sleb128(p, tcg_ctx.gen_insn_end_off[i] - prev); + prev =3D (i =3D=3D 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); + p =3D encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); =20 /* Test for (pending) buffer overflow. The assumption is that any one row beginning below the high water mark cannot overrun @@ -345,8 +346,8 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER - tcg_ctx.restore_time +=3D profile_getclock() - ti; - tcg_ctx.restore_count++; + tcg_ctx->restore_time +=3D profile_getclock() - ti; + tcg_ctx->restore_count++; #endif return 0; } @@ -592,7 +593,7 @@ static inline void *split_cross_256mb(void *buf1, size_= t size1) buf1 =3D buf2; } =20 - tcg_ctx.code_gen_buffer_size =3D size1; + tcg_ctx->code_gen_buffer_size =3D size1; return buf1; } #endif @@ -655,16 +656,16 @@ static inline void *alloc_code_gen_buffer(void) size =3D full_size - qemu_real_host_page_size; =20 /* Honor a command-line option limiting the size of the buffer. */ - if (size > tcg_ctx.code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) + if (size > tcg_ctx->code_gen_buffer_size) { + size =3D (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) & qemu_real_host_page_mask) - (uintptr_t)buf; } - tcg_ctx.code_gen_buffer_size =3D size; + tcg_ctx->code_gen_buffer_size =3D size; =20 #ifdef __mips__ if (cross_256mb(buf, size)) { buf =3D split_cross_256mb(buf, size); - size =3D tcg_ctx.code_gen_buffer_size; + size =3D tcg_ctx->code_gen_buffer_size; } #endif =20 @@ -677,7 +678,7 @@ static inline void *alloc_code_gen_buffer(void) #elif defined(_WIN32) static inline void *alloc_code_gen_buffer(void) { - size_t size =3D tcg_ctx.code_gen_buffer_size; + size_t size =3D tcg_ctx->code_gen_buffer_size; void *buf1, *buf2; =20 /* Perform the allocation in two steps, so that the guard page @@ -696,7 +697,7 @@ static inline void *alloc_code_gen_buffer(void) { int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start =3D 0; - size_t size =3D tcg_ctx.code_gen_buffer_size; + size_t size =3D tcg_ctx->code_gen_buffer_size; void *buf; =20 /* Constrain the position of the buffer based on the host cpu. @@ -713,7 +714,7 @@ static inline void *alloc_code_gen_buffer(void) flags |=3D MAP_32BIT; /* Cannot expect to map more than 800MB in low memory. */ if (size > 800u * 1024 * 1024) { - tcg_ctx.code_gen_buffer_size =3D size =3D 800u * 1024 * 1024; + tcg_ctx->code_gen_buffer_size =3D size =3D 800u * 1024 * 1024; } # elif defined(__sparc__) start =3D 0x40000000ul; @@ -753,7 +754,7 @@ static inline void *alloc_code_gen_buffer(void) default: /* Split the original buffer. Free the smaller half. */ buf2 =3D split_cross_256mb(buf, size); - size2 =3D tcg_ctx.code_gen_buffer_size; + size2 =3D tcg_ctx->code_gen_buffer_size; if (buf =3D=3D buf2) { munmap(buf + size2 + qemu_real_host_page_size, size - size= 2); } else { @@ -821,9 +822,9 @@ static gint tb_tc_cmp(gconstpointer ap, gconstpointer b= p) =20 static inline void code_gen_alloc(size_t tb_size) { - tcg_ctx.code_gen_buffer_size =3D size_code_gen_buffer(tb_size); - tcg_ctx.code_gen_buffer =3D alloc_code_gen_buffer(); - if (tcg_ctx.code_gen_buffer =3D=3D NULL) { + tcg_ctx->code_gen_buffer_size =3D size_code_gen_buffer(tb_size); + tcg_ctx->code_gen_buffer =3D alloc_code_gen_buffer(); + if (tcg_ctx->code_gen_buffer =3D=3D NULL) { fprintf(stderr, "Could not allocate dynamic translator buffer\n"); exit(1); } @@ -851,7 +852,7 @@ void tcg_exec_init(unsigned long tb_size) #if defined(CONFIG_SOFTMMU) /* There's no guest base to take into account, so go ahead and initialize the prologue now. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); #endif } =20 @@ -867,7 +868,7 @@ static TranslationBlock *tb_alloc(target_ulong pc) =20 assert_tb_locked(); =20 - tb =3D tcg_tb_alloc(&tcg_ctx); + tb =3D tcg_tb_alloc(tcg_ctx); if (unlikely(tb =3D=3D NULL)) { return NULL; } @@ -951,11 +952,11 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) =20 g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, nb_tbs, + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); } - if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) - > tcg_ctx.code_gen_buffer_size) { + if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) + > tcg_ctx->code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); } =20 @@ -970,7 +971,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 - tcg_ctx.code_gen_ptr =3D tcg_ctx.code_gen_buffer; + tcg_ctx->code_gen_ptr =3D tcg_ctx->code_gen_buffer; /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1325,44 +1326,44 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cpu_loop_exit(cpu); } =20 - gen_code_buf =3D tcg_ctx.code_gen_ptr; + gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tcg_ctx.cf_parallel =3D !!(cflags & CF_PARALLEL); + tcg_ctx->cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER - tcg_ctx.tb_count1++; /* includes aborted translations because of + tcg_ctx->tb_count1++; /* includes aborted translations because of exceptions */ ti =3D profile_getclock(); #endif =20 - tcg_func_start(&tcg_ctx); + tcg_func_start(tcg_ctx); =20 - tcg_ctx.cpu =3D ENV_GET_CPU(env); + tcg_ctx->cpu =3D ENV_GET_CPU(env); gen_intermediate_code(env, tb); - tcg_ctx.cpu =3D NULL; + tcg_ctx->cpu =3D NULL; =20 trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; tb->jmp_reset_offset[1] =3D TB_JMP_RESET_OFFSET_INVALID; - tcg_ctx.tb_jmp_reset_offset =3D tb->jmp_reset_offset; + tcg_ctx->tb_jmp_reset_offset =3D tb->jmp_reset_offset; #ifdef USE_DIRECT_JUMP - tcg_ctx.tb_jmp_insn_offset =3D tb->jmp_insn_offset; - tcg_ctx.tb_jmp_target_addr =3D NULL; + tcg_ctx->tb_jmp_insn_offset =3D tb->jmp_insn_offset; + tcg_ctx->tb_jmp_target_addr =3D NULL; #else - tcg_ctx.tb_jmp_insn_offset =3D NULL; - tcg_ctx.tb_jmp_target_addr =3D tb->jmp_target_addr; + tcg_ctx->tb_jmp_insn_offset =3D NULL; + tcg_ctx->tb_jmp_target_addr =3D tb->jmp_target_addr; #endif =20 #ifdef CONFIG_PROFILER - tcg_ctx.tb_count++; - tcg_ctx.interm_time +=3D profile_getclock() - ti; + tcg_ctx->tb_count++; + tcg_ctx->interm_time +=3D profile_getclock() - ti; ti =3D profile_getclock(); #endif =20 @@ -1371,7 +1372,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, the tcg optimization currently hidden inside tcg_gen_code. All that should be required is to flush the TBs, allocate a new TB, re-initialize it per above, and re-do the actual code generation. = */ - gen_code_size =3D tcg_gen_code(&tcg_ctx, tb); + gen_code_size =3D tcg_gen_code(tcg_ctx, tb); if (unlikely(gen_code_size < 0)) { goto buffer_overflow; } @@ -1382,10 +1383,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock() - ti; - tcg_ctx.code_in_len +=3D tb->size; - tcg_ctx.code_out_len +=3D gen_code_size; - tcg_ctx.search_out_len +=3D search_size; + tcg_ctx->code_time +=3D profile_getclock() - ti; + tcg_ctx->code_in_len +=3D tb->size; + tcg_ctx->code_out_len +=3D gen_code_size; + tcg_ctx->search_out_len +=3D search_size; #endif =20 #ifdef DEBUG_DISAS @@ -1400,7 +1401,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif =20 - tcg_ctx.code_gen_ptr =3D (void *) + tcg_ctx->code_gen_ptr =3D (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, CODE_GEN_ALIGN); =20 @@ -1955,8 +1956,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. */ cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, - tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); + tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, + tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index fa9c012..7a8b29e 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -978,7 +978,7 @@ int main(int argc, char **argv) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/linux-user/main.c b/linux-user/main.c index 630c73d..ad4c6f5 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4456,7 +4456,7 @@ int main(int argc, char **argv, char **envp) /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ - tcg_prologue_init(&tcg_ctx); + tcg_prologue_init(tcg_ctx); =20 #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 96c527b..ee309bb 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -154,7 +154,7 @@ void alpha_translate_init(void) done_init =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 31; i++) { cpu_std_ir[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/arm/translate.c b/target/arm/translate.c index 34aa95d..4fbbd71 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -82,7 +82,7 @@ void arm_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 16; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/cris/translate.c b/target/cris/translate.c index 0ee05ca..a503b96 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3365,7 +3365,7 @@ void cris_initialize_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/cris/translate_v10.c b/target/cris/translate_v10.c index 4a0b485..5d48920 100644 --- a/target/cris/translate_v10.c +++ b/target/cris/translate_v10.c @@ -1273,7 +1273,7 @@ void cris_initialize_crisv10_tcg(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cc_x =3D tcg_global_mem_new(cpu_env, offsetof(CPUCRISState, cc_x), "cc_x"); cc_src =3D tcg_global_mem_new(cpu_env, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fde3dba..6f476db 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -145,7 +145,7 @@ void hppa_translate_init(void) done_init =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 TCGV_UNUSED(cpu_gr[0]); for (i =3D 1; i < 32; i++) { diff --git a/target/i386/translate.c b/target/i386/translate.c index c5e4d77..4da5a8f 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8335,7 +8335,7 @@ void tcg_x86_init(void) initialized =3D true; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_cc_op =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUX86State, cc_op), "cc_o= p"); cpu_cc_dst =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_ds= t), diff --git a/target/lm32/translate.c b/target/lm32/translate.c index 692882f..b38e1e5 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -1203,7 +1203,7 @@ void lm32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5cfa25f..6dd72bc 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -69,7 +69,7 @@ void m68k_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 #define DEFO32(name, offset) \ QREG_##name =3D tcg_global_mem_new_i32(cpu_env, \ diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index cb65d1e..cb2ef50 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1861,7 +1861,7 @@ void mb_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 env_debug =3D tcg_global_mem_new(cpu_env, offsetof(CPUMBState, debug), diff --git a/target/mips/translate.c b/target/mips/translate.c index a2f5385..2929e61 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20139,7 +20139,7 @@ void mips_tcg_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 TCGV_UNUSED(cpu_gpr[0]); for (i =3D 1; i < 32; i++) diff --git a/target/moxie/translate.c b/target/moxie/translate.c index 0660b44..5a5f62f 100644 --- a/target/moxie/translate.c +++ b/target/moxie/translate.c @@ -106,7 +106,7 @@ void moxie_translate_init(void) return; } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUMoxieState, pc), "$pc"); for (i =3D 0; i < 16; i++) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index e49518e..27714f6 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -75,7 +75,7 @@ void openrisc_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_sr =3D tcg_global_mem_new(cpu_env, offsetof(CPUOpenRISCState, sr), "sr"); cpu_dflag =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c0cd64d..b842bd5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -90,7 +90,7 @@ void ppc_translate_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 p =3D cpu_reg_names; cpu_reg_names_size =3D sizeof(cpu_reg_names); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 6535f6c..b23356b 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -171,7 +171,7 @@ void s390x_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; psw_addr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 8bc132b..f745eb2 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -102,7 +102,7 @@ void sh4_translate_init(void) return; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 24; i++) cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0274e83..0b4ab3d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5933,7 +5933,7 @@ void gen_intermediate_code_init(CPUSPARCState *env) inited =3D 1; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 cpu_regwptr =3D tcg_global_mem_new_ptr(cpu_env, offsetof(CPUSPARCState, regwptr), diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index ff2ef7b..913cbe4 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -2447,7 +2447,7 @@ void tilegx_tcg_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), = "pc"); for (i =3D 0; i < TILEGX_R_COUNT; i++) { cpu_regs[i] =3D tcg_global_mem_new_i64(cpu_env, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ddd2dd0..bb56f03 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8886,7 +8886,7 @@ void tricore_tcg_init(void) return; } cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; /* reg init */ for (i =3D 0 ; i < 16 ; i++) { cpu_gpr_a[i] =3D tcg_global_mem_new(cpu_env, diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 666a201..5f36fb3 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -70,7 +70,7 @@ void uc32_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; =20 for (i =3D 0; i < 32; i++) { cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 2630024..c984fb4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -218,7 +218,7 @@ void xtensa_translate_init(void) int i; =20 cpu_env =3D tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env =3D cpu_env; + tcg_ctx->tcg_env =3D cpu_env; cpu_pc =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, pc), "pc"); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index ef420d4..4a7057e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -150,8 +150,8 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg= a1, TCGArg a2, =20 void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx.cf_parallel) { - tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); + if (tcg_ctx->cf_parallel) { + tcg_gen_op1(tcg_ctx, INDEX_op_mb, mb_type); } } =20 @@ -2486,7 +2486,7 @@ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg) if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_mov_i32(ret, TCGV_LOW(arg)); } else if (TCG_TARGET_HAS_extrl_i64_i32) { - tcg_gen_op2(&tcg_ctx, INDEX_op_extrl_i64_i32, + tcg_gen_op2(tcg_ctx, INDEX_op_extrl_i64_i32, GET_TCGV_I32(ret), GET_TCGV_I64(arg)); } else { tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg))); @@ -2498,7 +2498,7 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg) if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_mov_i32(ret, TCGV_HIGH(arg)); } else if (TCG_TARGET_HAS_extrh_i64_i32) { - tcg_gen_op2(&tcg_ctx, INDEX_op_extrh_i64_i32, + tcg_gen_op2(tcg_ctx, INDEX_op_extrh_i64_i32, GET_TCGV_I32(ret), GET_TCGV_I64(arg)); } else { TCGv_i64 t =3D tcg_temp_new_i64(); @@ -2514,7 +2514,7 @@ void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_movi_i32(TCGV_HIGH(ret), 0); } else { - tcg_gen_op2(&tcg_ctx, INDEX_op_extu_i32_i64, + tcg_gen_op2(tcg_ctx, INDEX_op_extu_i32_i64, GET_TCGV_I64(ret), GET_TCGV_I32(arg)); } } @@ -2525,7 +2525,7 @@ void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg) tcg_gen_mov_i32(TCGV_LOW(ret), arg); tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31); } else { - tcg_gen_op2(&tcg_ctx, INDEX_op_ext_i32_i64, + tcg_gen_op2(tcg_ctx, INDEX_op_ext_i32_i64, GET_TCGV_I64(ret), GET_TCGV_I32(arg)); } } @@ -2581,8 +2581,8 @@ void tcg_gen_goto_tb(unsigned idx) tcg_debug_assert(idx <=3D 1); #ifdef CONFIG_DEBUG_TCG /* Verify that we havn't seen this numbered exit before. */ - tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) =3D=3D 0); - tcg_ctx.goto_tb_issue_mask |=3D 1 << idx; + tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) =3D=3D 0); + tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif tcg_gen_op1i(INDEX_op_goto_tb, idx); } @@ -2591,7 +2591,7 @@ void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx->tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { @@ -2637,7 +2637,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); } else { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), = oi); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), o= i); } #endif } @@ -2650,7 +2650,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); } else { - tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), = oi); + tcg_gen_op3(tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), o= i); } #else if (TCG_TARGET_REG_BITS =3D=3D 32) { @@ -2665,7 +2665,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,= TCGv addr, void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { memop =3D tcg_canonicalize_memop(memop, 0, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } @@ -2673,7 +2673,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { memop =3D tcg_canonicalize_memop(memop, 0, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } @@ -2691,7 +2691,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 0)); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); } @@ -2704,7 +2704,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } =20 memop =3D tcg_canonicalize_memop(memop, 1, 1); - trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, + trace_guest_mem_before_tcg(tcg_ctx->cpu, tcg_ctx->tcg_env, addr, trace_mem_get_info(memop, 1)); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); } @@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!tcg_ctx.cf_parallel) { + if (!tcg_ctx->cf_parallel) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2820,11 +2820,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv= addr, TCGv_i32 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif =20 if (memop & MO_SIGN) { @@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!tcg_ctx.cf_parallel) { + if (!tcg_ctx->cf_parallel) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -2865,14 +2865,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv= addr, TCGv_i64 cmpv, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop, idx)); - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv, oi); tcg_temp_free_i32(oi); } #else - gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv); + gen(retv, tcg_ctx->tcg_env, addr, cmpv, newv); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(retv, 0); @@ -2928,11 +2928,11 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv add= r, TCGv_i32 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx= )); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif =20 if (memop & MO_SIGN) { @@ -2973,14 +2973,14 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv add= r, TCGv_i64 val, #ifdef CONFIG_SOFTMMU { TCGv_i32 oi =3D tcg_const_i32(make_memop_idx(memop & ~MO_SIGN,= idx)); - gen(ret, tcg_ctx.tcg_env, addr, val, oi); + gen(ret, tcg_ctx->tcg_env, addr, val, oi); tcg_temp_free_i32(oi); } #else - gen(ret, tcg_ctx.tcg_env, addr, val); + gen(ret, tcg_ctx->tcg_env, addr, val); #endif #else - gen_helper_exit_atomic(tcg_ctx.tcg_env); + gen_helper_exit_atomic(tcg_ctx->tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(ret, 0); @@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.cf_parallel) { \ + if (tcg_ctx->cf_parallel) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (tcg_ctx.cf_parallel) { \ + if (tcg_ctx->cf_parallel) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ diff --git a/tcg/tcg-runtime.c b/tcg/tcg-runtime.c index 08fe077..2f80b19 100644 --- a/tcg/tcg-runtime.c +++ b/tcg/tcg-runtime.c @@ -153,7 +153,7 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) =20 tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cf_mask()= ); if (tb =3D=3D NULL) { - return tcg_ctx.code_gen_epilogue; + return tcg_ctx->code_gen_epilogue; } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", diff --git a/tcg/tcg.c b/tcg/tcg.c index c0c2d6c..f907c47 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,7 +116,6 @@ static void tcg_out_tb_init(TCGContext *s); static bool tcg_out_tb_finalize(TCGContext *s); =20 =20 - static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -242,7 +241,7 @@ static void tcg_out_label(TCGContext *s, TCGLabel *l, t= cg_insn_unit *ptr) =20 TCGLabel *gen_new_label(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGLabel *l =3D tcg_malloc(sizeof(TCGLabel)); =20 *l =3D (TCGLabel){ @@ -381,6 +380,8 @@ void tcg_context_init(TCGContext *s) for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { indirect_reg_alloc_order[i] =3D tcg_target_reg_alloc_order[i]; } + + tcg_ctx =3D s; } =20 /* @@ -526,7 +527,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t = start, intptr_t size) =20 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int idx; =20 if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -538,7 +539,7 @@ TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char = *name) =20 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int idx; =20 if (tcg_regset_test_reg(s->reserved_regs, reg)) { @@ -551,7 +552,7 @@ TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char = *name) int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, intptr_t offset, const char *name) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *base_ts =3D &s->temps[GET_TCGV_PTR(base)]; TCGTemp *ts =3D tcg_global_alloc(s); int indirect_reg =3D 0, bigendian =3D 0; @@ -606,7 +607,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr = base, =20 static int tcg_temp_new_internal(TCGType type, int temp_local) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *ts; int idx, k; =20 @@ -668,7 +669,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local) =20 static void tcg_temp_free_internal(int idx) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; TCGTemp *ts; int k; =20 @@ -733,13 +734,13 @@ TCGv_i64 tcg_const_local_i64(int64_t val) #if defined(CONFIG_DEBUG_TCG) void tcg_clear_temp_count(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; s->temps_in_use =3D 0; } =20 int tcg_check_temp_count(void) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; if (s->temps_in_use) { /* Clear the count so that we don't give another * warning immediately next time around. @@ -2707,7 +2708,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s =3D &tcg_ctx; + TCGContext *s =3D tcg_ctx; int64_t tb_count =3D s->tb_count; int64_t tb_div_count =3D tb_count ? tb_count : 1; int64_t tot =3D s->interm_time + s->code_time; --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150023654018494.01457794686507; Sun, 16 Jul 2017 13:22:20 -0700 (PDT) Received: from localhost ([::1]:46779 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq3W-0007gz-Tx for importer@patchew.org; Sun, 16 Jul 2017 16:22:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46309) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmd-0001BE-OF for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmY-0008Pc-Ue for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:35779) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmY-0008P3-RM for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 7D30020A6F; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:46 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 3F1AC7E17E; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=UPpIXcenopkn0dc OXIOkNBIdukOLwJAWKZEqWAbvjNc=; b=zFNMrQ2XawAPFENAPq09s96jj7PivvL Rjjgd91JqkJWYgt3HAool4lU6D5Qy9JBMBkuDp9lwnxmkSFGAWAJsSX63HRBAZm8 wcsaAFXBALCvqaV83m8j3QzQO8OSQRmqjUawP816I+avi2jd1Q4wUooPqb4zCFsQ OpHUzHDQAKCs= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=UPpIXcenopkn0dcOXIOkNBIdukOLwJAWKZEqWAbvjNc=; b=FdAFXL9h ptJIaeCkAO1BsNBl0PKsVQkxk618/N30LDk6As5JqeusQ7Cn24zdf/wGQOx8mp5o Rwv4lZa2kBKYVKnKix0lUTEEefOelIFmP6Ygd4wPiZ5awSc1fomNXuDedYQuVP8I OwJH2LLj4yVukumOnZsVaVpF994Dbx7q0v1AqXc7BzTAo3GYvTL6VKxA8ycpb4Ge 5HUENAGO2RZT35JrUfy+IggM6yQidkVqbmDWukPdi/6i0aoVmt6iy5xHchyp+ecx O808JTaNzJiJI8bvaO8g4C3xhcfYQwGGj60flOcgTtyLR/IEmQjXP/2xOfXD0yY/ FDMBYjK80LhjSQ== X-ME-Sender: X-Sasl-enc: svz0a3BjhmgE9LKCcZL/TDVTY8PUDosMy0lPcBiHQ6PD 1500235486 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:18 -0400 Message-Id: <1500235468-15341-36-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 35/45] gen-icount: fold exitreq_label into TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Groundwork for supporting multiple TCG contexts. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/gen-icount.h | 7 +++---- tcg/tcg.h | 2 ++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 4a55da8..7723aa0 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -6,13 +6,12 @@ /* Helpers for instruction counting code generation. */ =20 static int icount_start_insn_idx; -static TCGLabel *exitreq_label; =20 static inline void gen_tb_start(TranslationBlock *tb) { TCGv_i32 count, imm; =20 - exitreq_label =3D gen_new_label(); + tcg_ctx->exitreq_label =3D gen_new_label(); if (tb->cflags & CF_USE_ICOUNT) { count =3D tcg_temp_local_new_i32(); } else { @@ -34,7 +33,7 @@ static inline void gen_tb_start(TranslationBlock *tb) tcg_temp_free_i32(imm); } =20 - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, exitreq_label); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); =20 if (tb->cflags & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_ctx->tcg_env, @@ -52,7 +51,7 @@ static inline void gen_tb_end(TranslationBlock *tb, int n= um_insns) tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); } =20 - gen_set_label(exitreq_label); + gen_set_label(tcg_ctx->exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); =20 /* Terminate the linked list. */ diff --git a/tcg/tcg.h b/tcg/tcg.h index 6913d4b..569f823 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -712,6 +712,8 @@ struct TCGContext { /* The TCGBackendData structure is private to tcg-target.inc.c. */ struct TCGBackendData *be; =20 + TCGLabel *exitreq_label; + TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237301918323.2829758146062; Sun, 16 Jul 2017 13:35:01 -0700 (PDT) Received: from localhost ([::1]:46835 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqFo-00010i-Nl for importer@patchew.org; Sun, 16 Jul 2017 16:35:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46342) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpme-0001Bb-HR for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmZ-0008QD-9f for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:52 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39975) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmZ-0008PO-2o for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C4E8D20A72; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:46 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 6CA6F24606; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=1/h H4vnMuwfH96H3aNbuZU6rdzAgqBWwcqGUDchDgkw=; b=k1p2xUMLbfQj9sAQ38i VLcoU7L1yS70HGXZOqTG/Xbh6Rnp1umEyQoWRtts4ZX0Jv7ioHaWtsE1V4TT8t6L iwtfTjPlDiKnAn5yP4EQr2+Obr5NxvpOcJceDkXEMuOqB+rZx78tYc4opamrDl/2 lcY2+orpSfuXB7e7lgYt2bPw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=1/hH4vnMuwfH96H3aNbuZU6rdzAgqBWwcqGUDchDg kw=; b=jS1Dg4QClQOP2Vwm9LJ6sYGV74GIHYWIhjayYsTPwNXx+t+YFrol0tryL XQAKB1rLcG1B16tD4J4AznKuiwwosvPdUlYkXzzjWpVSRAoM7+sKUPwi7i0w6nzP HtxG84VHJW1qVUOGc/vG+RhFNThBS9hx4WeinRi5cu5fWtdVFeE3r6nU53rwLZYl +lMjfHq4AGNmUKgJFho50lJxKyTrFgb/alJkGY4pXUvBrVfxECaSBFdX6xPREnAi uMzKKdnoGGuzrsuxsLYSoVNbAsfeEGwJgt9aD2BuPATSt0S4vXEP02OdEYfJRTZG id4B0RVezlRjOlabhi04R3RIdkZPw== X-ME-Sender: X-Sasl-enc: svz8YHtxiGoQ76KWa57/TDVTY8PUDosMy0lPcBiHQ6PD 1500235486 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:19 -0400 Message-Id: <1500235468-15341-37-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 36/45] tcg: dynamically allocate optimizer globals + fold into TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 12 ++++++++++++ tcg/optimize.c | 40 +++++++++++++++++++++++----------------- 2 files changed, 35 insertions(+), 17 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 569f823..175d4de 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -641,6 +641,14 @@ QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14)); /* Make sure that we don't overflow 64 bits without noticing. */ QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8); =20 +struct tcg_temp_info { + bool is_const; + uint16_t prev_copy; + uint16_t next_copy; + tcg_target_ulong val; + tcg_target_ulong mask; +}; + struct TCGContext { uint8_t *pool_cur, *pool_end; TCGPool *pool_first, *pool_current, *pool_first_large; @@ -717,6 +725,10 @@ struct TCGContext { TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ =20 + /* optimizer */ + struct tcg_temp_info *opt_temps; + TCGTempSet opt_temps_used; + /* Tells which temporary holds a given register. It does not take into account fixed registers */ TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; diff --git a/tcg/optimize.c b/tcg/optimize.c index adfc56c..61ca870 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -32,30 +32,21 @@ glue(glue(case INDEX_op_, x), _i32): \ glue(glue(case INDEX_op_, x), _i64) =20 -struct tcg_temp_info { - bool is_const; - uint16_t prev_copy; - uint16_t next_copy; - tcg_target_ulong val; - tcg_target_ulong mask; -}; - -static struct tcg_temp_info temps[TCG_MAX_TEMPS]; -static TCGTempSet temps_used; - static inline bool temp_is_const(TCGArg arg) { - return temps[arg].is_const; + return tcg_ctx->opt_temps[arg].is_const; } =20 static inline bool temp_is_copy(TCGArg arg) { - return temps[arg].next_copy !=3D arg; + return tcg_ctx->opt_temps[arg].next_copy !=3D arg; } =20 /* Reset TEMP's state, possibly removing the temp for the list of copies. = */ static void reset_temp(TCGArg temp) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; + temps[temps[temp].next_copy].prev_copy =3D temps[temp].prev_copy; temps[temps[temp].prev_copy].next_copy =3D temps[temp].next_copy; temps[temp].next_copy =3D temp; @@ -67,18 +58,20 @@ static void reset_temp(TCGArg temp) /* Reset all temporaries, given that there are NB_TEMPS of them. */ static void reset_all_temps(int nb_temps) { - bitmap_zero(temps_used.l, nb_temps); + bitmap_zero(tcg_ctx->opt_temps_used.l, nb_temps); } =20 /* Initialize and activate a temporary. */ static void init_temp_info(TCGArg temp) { - if (!test_bit(temp, temps_used.l)) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; + + if (!test_bit(temp, tcg_ctx->opt_temps_used.l)) { temps[temp].next_copy =3D temp; temps[temp].prev_copy =3D temp; temps[temp].is_const =3D false; temps[temp].mask =3D -1; - set_bit(temp, temps_used.l); + set_bit(temp, tcg_ctx->opt_temps_used.l); } } =20 @@ -118,6 +111,7 @@ static TCGOpcode op_to_movi(TCGOpcode op) =20 static TCGArg find_better_copy(TCGContext *s, TCGArg temp) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; TCGArg i; =20 /* If this is already a global, we can't do better. */ @@ -147,6 +141,7 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg te= mp) =20 static bool temps_are_copies(TCGArg arg1, TCGArg arg2) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; TCGArg i; =20 if (arg1 =3D=3D arg2) { @@ -169,6 +164,7 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args, TCGArg dst, TCGArg val) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; TCGOpcode new_op =3D op_to_movi(op->opc); tcg_target_ulong mask; =20 @@ -196,6 +192,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, T= CGArg *args, return; } =20 + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; TCGOpcode new_op =3D op_to_mov(op->opc); tcg_target_ulong mask; =20 @@ -466,6 +463,8 @@ static bool do_constant_folding_cond_eq(TCGCond c) static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, TCGArg y, TCGCond c) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; + if (temp_is_const(x) && temp_is_const(y)) { switch (op_bits(op)) { case 32: @@ -494,6 +493,7 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TC= GArg x, of the condition (0 or 1) if it can */ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) { + struct tcg_temp_info *temps =3D tcg_ctx->opt_temps; TCGArg al =3D p1[0], ah =3D p1[1]; TCGArg bl =3D p2[0], bh =3D p2[1]; =20 @@ -558,9 +558,15 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { + struct tcg_temp_info *temps; int oi, oi_next, nb_temps, nb_globals; TCGArg *prev_mb_args =3D NULL; =20 + if (tcg_ctx->opt_temps =3D=3D NULL) { + tcg_ctx->opt_temps =3D g_new(struct tcg_temp_info, TCG_MAX_TEMPS); + } + temps =3D tcg_ctx->opt_temps; + /* Array VALS has an element for each temp. If this temp holds a constant then its value is kept in VALS' eleme= nt. If this temp is a copy of other ones then the other copies are @@ -1360,7 +1366,7 @@ void tcg_optimize(TCGContext *s) if (!(args[nb_oargs + nb_iargs + 1] & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS)= )) { for (i =3D 0; i < nb_globals; i++) { - if (test_bit(i, temps_used.l)) { + if (test_bit(i, tcg_ctx->opt_temps_used.l)) { reset_temp(i); } } --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235616656688.9906498381529; Sun, 16 Jul 2017 13:06:56 -0700 (PDT) Received: from localhost ([::1]:46712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpod-0002eT-58 for importer@patchew.org; Sun, 16 Jul 2017 16:06:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmf-0001CQ-5O for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmZ-0008Qz-Nd for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:48583) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmZ-0008Q2-Fp for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id F06A220A70; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:46 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B22487E17E; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=EA6 YlV6U3s3I0GTtEZ5g/rnbNWDidMPckGkiWlDcOdo=; b=0f50i7paiHhfTiCLAUF ZHFaqqUGwtqFqaQMlT5HykAHs51OX7Jdmb6KIE+MxkrTCJ7w5XxpS1KUllt+pumg 0dq9dJ/vfYAxIC7TN6PpgpfPsMphRQHybqc31+6RRlIQXdgbdxmXkO+USmAdvNzY l1WFAW5hadgxKuZoL2q+s18E= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=EA6YlV6U3s3I0GTtEZ5g/rnbNWDidMPckGkiWlDcO do=; b=NSCOIDHXtRR7aBAa7poy0V+FpSmMFMAm/JgepzfOVlzATKTFulkzu58aO y9W6XkQEs8sfqWI8AfjILq6ROSCb5vSV57ZbadnWRL+RhtrmvwijTyvdYGTY56DN t167/nxPJF5mrdnfH5x6r8uvbZ6D93DZkBWFikUY7L+hd+/rYUmrHK/kTFRTleY/ DtUXn+UqPzI2SKQLKyKGoFUdtDHUpN15DNn2vt/S3qBoj5kWdFZbL0dbsghcWgxJ SeQPwGJgU4EHMrjYQ6yWhXWzZI1mzV3KZhd1HiB74Cr4naZo/4NBzUOVTH3Wj74R DPo2oyIGh/b0seQA8bMVrbOuzc7bQ== X-ME-Sender: X-Sasl-enc: svztcXVhl2gX8K+OeYP/TDVTY8PUDosMy0lPcBiHQ6PD 1500235486 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:20 -0400 Message-Id: <1500235468-15341-38-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 37/45] tcg: introduce **tcg_ctxs to keep track of all TCGContext's X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. Note that having n_tcg_ctxs is unnecessary. However, it is convenient to have it, since it will simplify iterating over the array: we'll have just a for loop instead of having to iterate over a NULL-terminated array (which would require n+1 elems) or having to check with ifdef's for usermode/softmmu. Signed-off-by: Emilio G. Cota --- tcg/tcg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index f907c47..8094278 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,6 +115,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static void tcg_out_tb_init(TCGContext *s); static bool tcg_out_tb_finalize(TCGContext *s); =20 +static TCGContext **tcg_ctxs; +static unsigned int n_tcg_ctxs; =20 static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; @@ -323,6 +325,13 @@ static GHashTable *helper_table; static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); =20 +static void tcg_ctxs_init(TCGContext *s) +{ + tcg_ctxs =3D g_new(TCGContext *, 1); + tcg_ctxs[0] =3D s; + n_tcg_ctxs =3D 1; +} + void tcg_context_init(TCGContext *s) { int op, total_args, n, i; @@ -381,6 +390,7 @@ void tcg_context_init(TCGContext *s) indirect_reg_alloc_order[i] =3D tcg_target_reg_alloc_order[i]; } =20 + tcg_ctxs_init(s); tcg_ctx =3D s; } =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150023729973570.34547912360324; Sun, 16 Jul 2017 13:34:59 -0700 (PDT) Received: from localhost ([::1]:46834 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqFm-0000yz-7T for importer@patchew.org; Sun, 16 Jul 2017 16:34:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46428) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmg-0001EJ-VO for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmZ-0008R8-Ru for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:54 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:46747) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmZ-0008QJ-Jb for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 3618920A3C; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:47 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id EE40124606; Sun, 16 Jul 2017 16:04:46 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=hAJ KmjYdq3rIkx8R3r/4C3ftFuNBYF7Whdd9/7PfxDQ=; b=tR70ZeGJsdsd+pZipFD bKZitNcBA/jHX9Y3YiiWy1Zn9r26O5trED6wmluCOVN2fzeZIgMu0qJnYH7oxMZY a0bZfQoysO/oUWFHdnRpmtlxBqq8f04Y9t87M7ZByHPwywvvVuYN6Lk1GalfG5J9 ZbiDh8P/IL6I2fmVkvnjFs5U= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=hAJKmjYdq3rIkx8R3r/4C3ftFuNBYF7Whdd9/7Pfx DQ=; b=sgRZCQxCJ3vmymTlovkSLNpfceoLjDXjaEB9mYComHotJvb0qyMjLUktq UCIWQu7bkw7qMYZhqV0YLC1XIYZPyMbKXQgfbvayrrRl/6YRspJUJVZ1temKOtkO d9NGfY97LlUbBkPkcGpp+ie9dmEqR9eqff+0kIsquY2wnXmPt1E4XKaDjUah6Kjv 4zKvKCKnHDMHWyuFEbDTA0n/E9PD3+uAxKWdLZc1WpTt/U9zO6sdybUeSseF8rhG 2H+95uM8qsj1+RsAA0qzGvNCDgBcGPZVXOSf5W7boIfTGVYiLXj6g3cYVrkyonIN dQFUvPZXjBuZsyVlWsbu8WthGZ/Fg== X-ME-Sender: X-Sasl-enc: svz0emxzh3AE9bCDaoP/TDVTY8PUDosMy0lPcBiHQ6PD 1500235486 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:21 -0400 Message-Id: <1500235468-15341-39-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 38/45] tcg: distribute profiling counters across TCGContext's X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is groundwork for supporting multiple TCG contexts. To avoid scalability issues when profiling info is enabled, this patch makes the profiling info counters distributed via the following changes: 1) Consolidate profile info into its own struct, TCGProfile, which TCGContext also includes. Note that tcg_table_op_count is brought into TCGProfile after dropping the tcg_ prefix. 2) Iterate over the TCG contexts in the system to obtain the total counts. This change also requires updating the accessors to TCGProfile fields to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to them. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- tcg/tcg.h | 38 +++++++++------- accel/tcg/translate-all.c | 23 +++++----- tcg/tcg.c | 110 ++++++++++++++++++++++++++++++++++++++----= ---- 3 files changed, 126 insertions(+), 45 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 175d4de..9d17584 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -649,6 +649,26 @@ struct tcg_temp_info { tcg_target_ulong mask; }; =20 +typedef struct TCGProfile { + int64_t tb_count1; + int64_t tb_count; + int64_t op_count; /* total insn count */ + int op_count_max; /* max insn per TB */ + int64_t temp_count; + int temp_count_max; + int64_t del_op_count; + int64_t code_in_len; + int64_t code_out_len; + int64_t search_out_len; + int64_t interm_time; + int64_t code_time; + int64_t la_time; + int64_t opt_time; + int64_t restore_count; + int64_t restore_time; + int64_t table_op_count[NB_OPS]; +} TCGProfile; + struct TCGContext { uint8_t *pool_cur, *pool_end; TCGPool *pool_first, *pool_current, *pool_first_large; @@ -673,23 +693,7 @@ struct TCGContext { tcg_insn_unit *code_ptr; =20 #ifdef CONFIG_PROFILER - /* profiling info */ - int64_t tb_count1; - int64_t tb_count; - int64_t op_count; /* total insn count */ - int op_count_max; /* max insn per TB */ - int64_t temp_count; - int temp_count_max; - int64_t del_op_count; - int64_t code_in_len; - int64_t code_out_len; - int64_t search_out_len; - int64_t interm_time; - int64_t code_time; - int64_t la_time; - int64_t opt_time; - int64_t restore_count; - int64_t restore_time; + TCGProfile prof; #endif =20 #ifdef CONFIG_DEBUG_TCG diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 961e357..fd3e4a0 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -312,6 +312,7 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti =3D profile_getclock(); #endif =20 @@ -346,8 +347,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, restore_state_to_opc(env, tb, data); =20 #ifdef CONFIG_PROFILER - tcg_ctx->restore_time +=3D profile_getclock() - ti; - tcg_ctx->restore_count++; + atomic_set(&prof->restore_time, + prof->restore_time + profile_getclock() - ti); + atomic_set(&prof->restore_count, prof->restore_count + 1); #endif return 0; } @@ -1306,6 +1308,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_insn_unit *gen_code_buf; int gen_code_size, search_size; #ifdef CONFIG_PROFILER + TCGProfile *prof =3D &tcg_ctx->prof; int64_t ti; #endif assert_memory_lock(); @@ -1336,8 +1339,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER - tcg_ctx->tb_count1++; /* includes aborted translations because of - exceptions */ + /* includes aborted translations because of exceptions */ + atomic_set(&prof->tb_count1, prof->tb_count1 + 1); ti =3D profile_getclock(); #endif =20 @@ -1362,8 +1365,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #endif =20 #ifdef CONFIG_PROFILER - tcg_ctx->tb_count++; - tcg_ctx->interm_time +=3D profile_getclock() - ti; + atomic_set(&prof->tb_count, prof->tb_count + 1); + atomic_set(&prof->interm_time, prof->interm_time + profile_getclock() = - ti); ti =3D profile_getclock(); #endif =20 @@ -1383,10 +1386,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->tc.size =3D gen_code_size; =20 #ifdef CONFIG_PROFILER - tcg_ctx->code_time +=3D profile_getclock() - ti; - tcg_ctx->code_in_len +=3D tb->size; - tcg_ctx->code_out_len +=3D gen_code_size; - tcg_ctx->search_out_len +=3D search_size; + atomic_set(&prof->code_time, prof->code_time + profile_getclock() - ti= ); + atomic_set(&prof->code_in_len, prof->code_in_len + tb->size); + atomic_set(&prof->code_out_len, prof->code_out_len + gen_code_size); + atomic_set(&prof->search_out_len, prof->search_out_len + search_size); #endif =20 #ifdef DEBUG_DISAS diff --git a/tcg/tcg.c b/tcg/tcg.c index 8094278..5afb80a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1350,7 +1350,7 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) memset(op, 0, sizeof(*op)); =20 #ifdef CONFIG_PROFILER - s->del_op_count++; + atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); #endif } =20 @@ -2521,15 +2521,79 @@ static void tcg_reg_alloc_call(TCGContext *s, int n= b_oargs, int nb_iargs, =20 #ifdef CONFIG_PROFILER =20 -static int64_t tcg_table_op_count[NB_OPS]; +/* avoid copy/paste errors */ +#define PROF_ADD(to, from, field) \ + do { \ + (to)->field +=3D atomic_read(&((from)->field)); \ + } while (0) + +#define PROF_ADD_MAX(to, from, field) \ + do { \ + typeof((from)->field) val__ =3D atomic_read(&((from)->field)); \ + if (val__ > (to)->field) { \ + (to)->field =3D val__; \ + } \ + } while (0) + +/* Pass in a zero'ed @prof */ +static inline +void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) +{ + unsigned int i; + + for (i =3D 0; i < n_tcg_ctxs; i++) { + const TCGProfile *orig =3D &tcg_ctxs[i]->prof; + + if (counters) { + PROF_ADD(prof, orig, tb_count1); + PROF_ADD(prof, orig, tb_count); + PROF_ADD(prof, orig, op_count); + PROF_ADD_MAX(prof, orig, op_count_max); + PROF_ADD(prof, orig, temp_count); + PROF_ADD_MAX(prof, orig, temp_count_max); + PROF_ADD(prof, orig, del_op_count); + PROF_ADD(prof, orig, code_in_len); + PROF_ADD(prof, orig, code_out_len); + PROF_ADD(prof, orig, search_out_len); + PROF_ADD(prof, orig, interm_time); + PROF_ADD(prof, orig, code_time); + PROF_ADD(prof, orig, la_time); + PROF_ADD(prof, orig, opt_time); + PROF_ADD(prof, orig, restore_count); + PROF_ADD(prof, orig, restore_time); + } + if (table) { + int i; + + for (i =3D 0; i < NB_OPS; i++) { + PROF_ADD(prof, orig, table_op_count[i]); + } + } + } +} + +#undef PROF_ADD +#undef PROF_ADD_MAX + +static void tcg_profile_snapshot_counters(TCGProfile *prof) +{ + tcg_profile_snapshot(prof, true, false); +} + +static void tcg_profile_snapshot_table(TCGProfile *prof) +{ + tcg_profile_snapshot(prof, false, true); +} =20 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) { + TCGProfile prof =3D {}; int i; =20 + tcg_profile_snapshot_table(&prof); for (i =3D 0; i < NB_OPS; i++) { cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name, - tcg_table_op_count[i]); + prof.table_op_count[i]); } } #else @@ -2542,6 +2606,9 @@ void tcg_dump_op_count(FILE *f, fprintf_function cpu_= fprintf) =20 int tcg_gen_code(TCGContext *s, TranslationBlock *tb) { +#ifdef CONFIG_PROFILER + TCGProfile *prof =3D &s->prof; +#endif int i, oi, oi_next, num_insns; =20 #ifdef CONFIG_PROFILER @@ -2549,15 +2616,15 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) int n; =20 n =3D s->gen_op_buf[0].prev + 1; - s->op_count +=3D n; - if (n > s->op_count_max) { - s->op_count_max =3D n; + atomic_set(&prof->op_count, prof->op_count + n); + if (n > prof->op_count_max) { + atomic_set(&prof->op_count_max, n); } =20 n =3D s->nb_temps; - s->temp_count +=3D n; - if (n > s->temp_count_max) { - s->temp_count_max =3D n; + atomic_set(&prof->temp_count, prof->temp_count + n); + if (n > prof->temp_count_max) { + atomic_set(&prof->temp_count_max, n); } } #endif @@ -2574,7 +2641,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 #ifdef CONFIG_PROFILER - s->opt_time -=3D profile_getclock(); + atomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); #endif =20 #ifdef USE_TCG_OPTIMIZATIONS @@ -2582,8 +2649,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #endif =20 #ifdef CONFIG_PROFILER - s->opt_time +=3D profile_getclock(); - s->la_time -=3D profile_getclock(); + atomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); + atomic_set(&prof->la_time, prof->la_time - profile_getclock()); #endif =20 { @@ -2611,7 +2678,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) } =20 #ifdef CONFIG_PROFILER - s->la_time +=3D profile_getclock(); + atomic_set(&prof->la_time, prof->la_time + profile_getclock()); #endif =20 #ifdef DEBUG_DISAS @@ -2642,7 +2709,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 oi_next =3D op->next; #ifdef CONFIG_PROFILER - tcg_table_op_count[opc]++; + atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] += 1); #endif =20 switch (opc) { @@ -2718,10 +2785,17 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) #ifdef CONFIG_PROFILER void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf) { - TCGContext *s =3D tcg_ctx; - int64_t tb_count =3D s->tb_count; - int64_t tb_div_count =3D tb_count ? tb_count : 1; - int64_t tot =3D s->interm_time + s->code_time; + TCGProfile prof =3D {}; + const TCGProfile *s; + int64_t tb_count; + int64_t tb_div_count; + int64_t tot; + + tcg_profile_snapshot_counters(&prof); + s =3D &prof; + tb_count =3D s->tb_count; + tb_div_count =3D tb_count ? tb_count : 1; + tot =3D s->interm_time + s->code_time; =20 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n= ", tot, tot / 2.4e9); --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236876346458.5109152325034; Sun, 16 Jul 2017 13:27:56 -0700 (PDT) Received: from localhost ([::1]:46807 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWq8w-0003pQ-ML for importer@patchew.org; Sun, 16 Jul 2017 16:27:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46407) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmg-0001D5-05 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpma-0008RO-4j for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:34053) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmZ-0008Qp-T6 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:47 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 6628920A73; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:47 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 28FB77E17E; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=Czm AFzrrZM1EsCXvbU/T5GV6jf/WCV/oe8pknTL2v+c=; b=TzpljyeJ2dbU9A9lwNq ghof5wB7JM8894wb+/Wfnaf7wW1pVtaynIXvGnCpYoasgQV5WCSWkVhaIE0EAVoI I5EPiTvo6Fvu/inordpZ+2bzgKk/t7axLJQewlwOBdjKPFynU4P0WyZ3Gy91qlvb Hve5nqAXCg921rygiJLnAfbk= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=CzmAFzrrZM1EsCXvbU/T5GV6jf/WCV/oe8pknTL2v +c=; b=NKV705uVUR4mhZsnsv0UHI4QwQsOVnbqN6P90XRrrUI/BRIS7clMXLQ1V N+xVKYx63NbNlHJriqs3o8TlXkbzm03S75dLf4v2xgtBNvI2f6u+btHFDVIOzl3E mAPZtEnEcNmiGknFYYNx0IxSsFsDsSHZ0TSaMfMysY0bYc+YF3gL0Y1ZAN+yQOxT ju5jzNyO8T0qyO1Oj6JCFw4xOvJ/xYpMGdPQItTUaYxyoi2EOlBLcbqWhtqybSh3 97L0zCp7giV/gqwl1J/9dc/lOjqF05zkbjjeWnYJthB86Ac8ERvOHb0IlDNZOuel xOzEuThb5NyUrmmW9sb+OoTNl0eFw== X-ME-Sender: X-Sasl-enc: n0VQud9vGdMgL+lAWpXa6ZqMpqfm8HIPwerrj4wXIz0T 1500235487 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:22 -0400 Message-Id: <1500235468-15341-40-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 39/45] osdep: move qemu_real_host_page_size/mask to osdep X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These only depend on the host and therefore belong in the common osdep, not in a target-dependent object. Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 2 -- include/qemu/osdep.h | 8 ++++++++ exec.c | 5 +---- util/osdep.c | 9 +++++++++ 4 files changed, 18 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ffe43d5..778031c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -229,8 +229,6 @@ extern int target_page_bits; /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even * when intptr_t is 32-bit and we are aligning a long long. */ -extern uintptr_t qemu_real_host_page_size; -extern intptr_t qemu_real_host_page_mask; extern uintptr_t qemu_host_page_size; extern intptr_t qemu_host_page_mask; =20 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 8559634..3cb36e6 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -483,6 +483,14 @@ char *qemu_get_pid_name(pid_t pid); */ pid_t qemu_fork(Error **errp); =20 +void real_host_page_size_init(void); + +/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even + * when intptr_t is 32-bit and we are aligning a long long. + */ +extern uintptr_t qemu_real_host_page_size; +extern intptr_t qemu_real_host_page_mask; + extern int qemu_icache_linesize; extern int qemu_dcache_linesize; =20 diff --git a/exec.c b/exec.c index adc160f..135dcbc 100644 --- a/exec.c +++ b/exec.c @@ -120,8 +120,6 @@ int use_icount; =20 uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; -uintptr_t qemu_real_host_page_size; -intptr_t qemu_real_host_page_mask; =20 bool set_preferred_target_page_bits(int bits) { @@ -3608,8 +3606,7 @@ void page_size_init(void) { /* NOTE: we can always suppose that qemu_host_page_size >=3D TARGET_PAGE_SIZE */ - qemu_real_host_page_size =3D getpagesize(); - qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; + real_host_page_size_init(); if (qemu_host_page_size =3D=3D 0) { qemu_host_page_size =3D qemu_real_host_page_size; } diff --git a/util/osdep.c b/util/osdep.c index a2863c8..90f4f11 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -46,6 +46,9 @@ extern int madvise(caddr_t, size_t, int); #define QEMU_GETLK F_GETLK #endif =20 +uintptr_t qemu_real_host_page_size; +intptr_t qemu_real_host_page_mask; + static bool fips_enabled =3D false; =20 static const char *hw_version =3D QEMU_HW_VERSION; @@ -65,6 +68,12 @@ int socket_set_nodelay(int fd) return qemu_setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, &v, sizeof(v)); } =20 +void real_host_page_size_init(void) +{ + qemu_real_host_page_size =3D getpagesize(); + qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; +} + int qemu_madvise(void *addr, size_t len, int advice) { if (advice =3D=3D QEMU_MADV_INVALID) { --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237437024974.778840169253; Sun, 16 Jul 2017 13:37:17 -0700 (PDT) Received: from localhost ([::1]:46854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqHz-0002WK-Sg for importer@patchew.org; Sun, 16 Jul 2017 16:37:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmf-0001CW-Ay for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpma-0008Rc-As for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:56025) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpma-0008R5-54 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:48 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 96CCA20A74; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:47 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 55F7B24606; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=gZZ psojyMJWFh0UBZWAMl/m0u1Hcet75TgaaCJh8Wm0=; b=MiyCF+ZTacVEEgYUc8Q xbMHX84QXMrK8OOfQbuA7bPD2KX0YztsWMRpqhwsuAMLk0b1CmDUMlu/RDyIipJq GRqabUjxgBeG1Mo21R3oHr3RhbVDZPkU40U8m8ynUEMnoCX1knXjqQhSe63TtCxL fbyF5dlHiEgCUseTAXC0uTHU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=gZZpsojyMJWFh0UBZWAMl/m0u1Hcet75TgaaCJh8W m0=; b=ZLZb6mMSv4MeJGxOyPiMrAQhHHahuVZE595BeHKrLuTRSz8qCOy7wh0g8 G0YFsetc+MeQxfHTGA8/KAK9XSvoZEzlZvj5qv2SCirUiux004mmEK7JwAbP+yup cd7kWpvtakU39aSBBJGj1UEPMmvwuC2SvC+CodLxb10T91PVZ5PNQBK4YSCgLsCh nV15lO/+rxwMXSU3gV8xgYdaQ+i0KgNm50yXClJT4Gu+0Erhxw2RRm4lHgQAXyaq hgP4lwPnX284MoCNGbDGLIPE3YlFO6/1ixZ6aD7OOeWHyoVjzEPcNse9sD0leBRq JGfFEtT7Z+VB+tEY8tXjJMbQt+O7g== X-ME-Sender: X-Sasl-enc: n0VItdVtG8A/P/9FUJ3a6ZqMpqfm8HIPwerrj4wXIz0T 1500235487 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:23 -0400 Message-Id: <1500235468-15341-41-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 40/45] osdep: introduce qemu_mprotect_rwx/none X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- include/qemu/osdep.h | 2 ++ util/osdep.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 3cb36e6..dcecfbc 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -348,6 +348,8 @@ void sigaction_invoke(struct sigaction *action, #endif =20 int qemu_madvise(void *addr, size_t len, int advice); +int qemu_mprotect_rwx(void *addr, size_t size); +int qemu_mprotect_none(void *addr, size_t size); =20 int qemu_open(const char *name, int flags, ...); int qemu_close(int fd); diff --git a/util/osdep.c b/util/osdep.c index 90f4f11..85df97e 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -90,6 +90,46 @@ int qemu_madvise(void *addr, size_t len, int advice) #endif } =20 +static int qemu_mprotect__osdep(void *addr, size_t size, int prot) +{ + void *start =3D QEMU_ALIGN_PTR_DOWN(addr, qemu_real_host_page_size); + void *end =3D QEMU_ALIGN_PTR_UP(addr + size, qemu_real_host_page_size); +#ifdef _WIN32 + DWORD old_protect; + + if (!VirtualProtect(start, end - start, prot, &old_protect)) { + error_report("%s: VirtualProtect failed with error code %d", + __func__, GetLastError()); + return -1; + } + return 0; +#else + if (mprotect(start, end - start, prot)) { + error_report("%s: mprotect failed: %s", __func__, strerror(errno)); + return -1; + } + return 0; +#endif +} + +int qemu_mprotect_rwx(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_EXECUTE_READWRITE); +#else + return qemu_mprotect__osdep(addr, size, PROT_READ | PROT_WRITE | PROT_= EXEC); +#endif +} + +int qemu_mprotect_none(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_NOACCESS); +#else + return qemu_mprotect__osdep(addr, size, PROT_NONE); +#endif +} + #ifndef _WIN32 /* * Dups an fd and sets the flags --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500236994799977.1906920391554; Sun, 16 Jul 2017 13:29:54 -0700 (PDT) Received: from localhost ([::1]:46814 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqAr-0005Vi-Jk for importer@patchew.org; Sun, 16 Jul 2017 16:29:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmj-0001GV-1T for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpma-0008Ru-JM for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:55717) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpma-0008RE-Bf for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:48 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id CC00520A71; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:47 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 877C87E17E; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=T4e J7gZqddN9SDrG7JMO9e2XsHamYDl79suft7gkhUs=; b=wrSH5prY8eNDYkYoL8M 7erK53HQbEaLWHvQvd+mvwsZh1VK4gA+D4q5R2ILgG4G0TD1povswS+K4h0DNWph zZtBcQCGAZLACpRFWZXnTygfuUD8lTmbA2K9PLsI4SjoHmixxsGSXjlntBao97eJ bLqyd40+hE644AFH8bjUV/wI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=T4eJ7gZqddN9SDrG7JMO9e2XsHamYDl79suft7gkh Us=; b=lq1LQPejSGhJryLJhtG0T8ZkaLTUYienGpK35zGpRVdEZqZ6w6tztu6YV 7CN+X7IXAQW8AnRN2z+pnzr7gArjd86xbyXSfIcMYXgXvTK6oJpzy740cniCjFZM i5w1c6PINZiXApOcbaNJxl0sjz60NuWOKyJbNhOckatKi9j62Md8TTeRvxhZBAJr lY3gZg/eg9YupWR7sSaqyGaToePYR5mdmn0rLlQtT2zuz60ZKl8n/7gil1LnFgV3 4kZlDNaXjgF7UWRGjX1o+rysaUvL3QhVG4AEz/amplEahbz4NzlYSfADNdlW1DUc /0VXkWwXQ4oHEMIP/kzdTYJk5DvAA== X-ME-Sender: X-Sasl-enc: n0VYs9lhBMgnPOBKQpza6ZqMpqfm8HIPwerrj4wXIz0T 1500235487 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:24 -0400 Message-Id: <1500235468-15341-42-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 41/45] translate-all: use qemu_protect_rwx/none helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 49 ++++++-------------------------------------= ---- 1 file changed, 6 insertions(+), 43 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fd3e4a0..913b1c5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -604,47 +604,6 @@ static inline void *split_cross_256mb(void *buf1, size= _t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); =20 -# ifdef _WIN32 -static inline void do_protect(void *addr, long size, int prot) -{ - DWORD old_protect; - VirtualProtect(addr, size, prot, &old_protect); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PAGE_EXECUTE_READWRITE); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PAGE_NOACCESS); -} -# else -static inline void do_protect(void *addr, long size, int prot) -{ - uintptr_t start, end; - - start =3D (uintptr_t)addr; - start &=3D qemu_real_host_page_mask; - - end =3D (uintptr_t)addr + size; - end =3D ROUND_UP(end, qemu_real_host_page_size); - - mprotect((void *)start, end - start, prot); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PROT_NONE); -} -# endif /* WIN32 */ - static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; @@ -671,8 +630,12 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - map_exec(buf, size); - map_none(buf + size, qemu_real_host_page_size); + if (qemu_mprotect_rwx(buf, size)) { + abort(); + } + if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { + abort(); + } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237092822103.96255255490428; Sun, 16 Jul 2017 13:31:32 -0700 (PDT) Received: from localhost ([::1]:46826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqCR-0006vf-Ej for importer@patchew.org; Sun, 16 Jul 2017 16:31:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46386) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmf-0001Ch-Il for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpma-0008SD-SG for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:53 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:60479) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpma-0008RX-KX for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:48 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 0BEF420A75; Sun, 16 Jul 2017 16:04:48 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:48 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id B97942450F; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=EqwquXg/lhqzKVZ WcH+l8aUH6gB1CPPjM042L9K29xs=; b=TZa3weOtq8OBZf3MQ7hNQ+7Tt8hVr5k EY6EyPW/Rr+z9Tu8z1kUhhEpLLRVjlr3icwsDZSEzAILJG5Z82dXppsres3MY8WW hjlOssN+xscultRHK77hHUiOHJicKpX2fT83nYUfxEfme//Q8dGTK5q4Rb6FEY7u pswUc1kcXPVk= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=EqwquXg/lhqzKVZWcH+l8aUH6gB1CPPjM042L9K29xs=; b=iUyyWFkd VjOphtSwm0g2mdFU46PT19xXXzYCGuLXrK1DtYjuBpPCHn/MVd5TahrVvxuhuKmL 5Y09ZR0DOXgVVwEjJebhT4MgVIrWnoiLQMAj6ShfffEqRCAFXMQDjEi/A/ezI8Lg ZGNJ8hyJopXd5LS78KLzhO7b5MoQWWBvR/OnQyn7DqnD+kDX0xbO5jYbcwLCxPFx yZ583NoH0XQJ1NZ07Vo14EZRDoOXS0t5jIfyZLA0OyGGW/EcAD5M3K8rMZo3yUB1 /MoWP8AMnF1SYGauCnoLNbMYSi1487KtNUeUairK+BoIAHD0gDjxEUM6VgY7m+9U nrkVmkwoENpN9Q== X-ME-Sender: X-Sasl-enc: n0VGr9tzHckkLuxFSpHa6ZqMpqfm8HIPwerrj4wXIz0T 1500235487 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:25 -0400 Message-Id: <1500235468-15341-43-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 42/45] tcg: define TCG_HIGHWATER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Will come in handy very soon. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 5afb80a..e8aae1f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,6 +115,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static void tcg_out_tb_init(TCGContext *s); static bool tcg_out_tb_finalize(TCGContext *s); =20 +#define TCG_HIGHWATER 1024 + static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; =20 @@ -441,7 +443,7 @@ void tcg_prologue_init(TCGContext *s) /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger than we expect the code generation for any one opcode to require. = */ - s->code_gen_highwater =3D s->code_gen_buffer + (total_size - 1024); + s->code_gen_highwater =3D s->code_gen_buffer + (total_size - TCG_HIGHW= ATER); =20 tcg_register_jit(s->code_gen_buffer, total_size); =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237668819232.3501752567522; Sun, 16 Jul 2017 13:41:08 -0700 (PDT) Received: from localhost ([::1]:46873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqLj-0005Hx-AW for importer@patchew.org; Sun, 16 Jul 2017 16:41:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmj-0001GT-0q for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpma-0008SM-TO for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:56 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:46541) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpma-0008Rg-KJ for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:48 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 3EE6520A7C; Sun, 16 Jul 2017 16:04:48 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:48 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id EB8D07E17E; Sun, 16 Jul 2017 16:04:47 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=t7T odIt8JA/Z4PoBtlmFw38N78j9U9x6ZXzW14hEMV4=; b=psO5MBav146uokICSTZ 7vJnrJVa4ueqw1lue57cDgDGUwcJIzL8yaXdsjX1tdJnGFS4j2mkqGY/KlU3vXhO qEYyXT8V6nOm0XgNb9IBpcMj/kEglALjnqArBt13tn2w1aah+ZYsAMS8KZBwQ7WR VByvgHyuZ2/s1jZrzotaypg8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=t7TodIt8JA/Z4PoBtlmFw38N78j9U9x6ZXzW14hEM V4=; b=mCznS/BIoNonnsdZRf5y+7GSaEq41ApvO+1BsBLqoj1COk2ftJMUFaxSD /vXKE80nxEqndk51hgEpCXzhA7IeTBsWTNLkhgNui416Bncej1NUIt0GQ5DXpZgp saVAhD6Lnfo2Doz2hvrfbkpfxxqVetn8QcXsDqY9pVB9P/qR4d4uWlJt1boHqr4y 4Pp7vSK0efLNU7V9YAdJuf4tPSbT1GaefMsBpuEM1YPj3QZ+cZybONZ+tzgWYq/m NazlWmYU9xyCsWEb1/VgrqU0J+auaytUPWkglGRO8F2LBDgdHA9CcS+EtU9Kvn0X 73sxiVZtFYhA7elkwnwlCBCGwwtAA== X-ME-Sender: X-Sasl-enc: n0VRts1vGt0jPPpWXI3a6ZqMpqfm8HIPwerrj4wXIz0T 1500235487 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:26 -0400 Message-Id: <1500235468-15341-44-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 43/45] tcg: introduce regions to split code_gen_buffer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is groundwork for supporting multiple TCG contexts. The naive solution here is to split code_gen_buffer statically among the TCG threads; this however results in poor utilization if translation needs are different across TCG threads. What we do here is to add an extra layer of indirection, assigning regions that act just like pages do in virtual memory allocation. (BTW if you are wondering about the chosen naming, I did not want to use blocks or pages because those are already heavily used in QEMU). We use a global lock to serialize allocations as well as statistics reporting (we now export the size of the used code_gen_buffer with tcg_code_size()). Note that for the allocator we could just use a counter and atomic_inc; however, that would complicate the gathering of tcg_code_size()-like stats. So given that the region operations are not a fast path, a lock seems the most reasonable choice. The effectiveness of this approach is clear after seeing some numbers. I used the bootup+shutdown of debian-arm with '-tb-size 80' as a benchmark. Note that I'm evaluating this after enabling per-thread TCG (which is done by a subsequent commit). * -smp 1, 1 region (entire buffer): qemu: flush code_size=3D83885014 nb_tbs=3D154739 avg_tb_size=3D357 qemu: flush code_size=3D83884902 nb_tbs=3D153136 avg_tb_size=3D363 qemu: flush code_size=3D83885014 nb_tbs=3D152777 avg_tb_size=3D364 qemu: flush code_size=3D83884950 nb_tbs=3D150057 avg_tb_size=3D373 qemu: flush code_size=3D83884998 nb_tbs=3D150234 avg_tb_size=3D373 qemu: flush code_size=3D83885014 nb_tbs=3D154009 avg_tb_size=3D360 qemu: flush code_size=3D83885014 nb_tbs=3D151007 avg_tb_size=3D370 qemu: flush code_size=3D83885014 nb_tbs=3D151816 avg_tb_size=3D367 That is, 8 flushes. * -smp 8, 32 regions (80/32 MB per region) [i.e. this patch]: qemu: flush code_size=3D76328008 nb_tbs=3D141040 avg_tb_size=3D356 qemu: flush code_size=3D75366534 nb_tbs=3D138000 avg_tb_size=3D361 qemu: flush code_size=3D76864546 nb_tbs=3D140653 avg_tb_size=3D361 qemu: flush code_size=3D76309084 nb_tbs=3D135945 avg_tb_size=3D375 qemu: flush code_size=3D74581856 nb_tbs=3D132909 avg_tb_size=3D375 qemu: flush code_size=3D73927256 nb_tbs=3D135616 avg_tb_size=3D360 qemu: flush code_size=3D78629426 nb_tbs=3D142896 avg_tb_size=3D365 qemu: flush code_size=3D76667052 nb_tbs=3D138508 avg_tb_size=3D368 Again, 8 flushes. Note how buffer utilization is not 100%, but it is close. Smaller region sizes would yield higher utilization, but we want region allocation to be rare (it acquires a lock), so we do not want to go too small. * -smp 8, static partitioning of 8 regions (10 MB per region): qemu: flush code_size=3D21936504 nb_tbs=3D40570 avg_tb_size=3D354 qemu: flush code_size=3D11472174 nb_tbs=3D20633 avg_tb_size=3D370 qemu: flush code_size=3D11603976 nb_tbs=3D21059 avg_tb_size=3D365 qemu: flush code_size=3D23254872 nb_tbs=3D41243 avg_tb_size=3D377 qemu: flush code_size=3D28289496 nb_tbs=3D52057 avg_tb_size=3D358 qemu: flush code_size=3D43605160 nb_tbs=3D78896 avg_tb_size=3D367 qemu: flush code_size=3D45166552 nb_tbs=3D82158 avg_tb_size=3D364 qemu: flush code_size=3D63289640 nb_tbs=3D116494 avg_tb_size=3D358 qemu: flush code_size=3D51389960 nb_tbs=3D93937 avg_tb_size=3D362 qemu: flush code_size=3D59665928 nb_tbs=3D107063 avg_tb_size=3D372 qemu: flush code_size=3D38380824 nb_tbs=3D68597 avg_tb_size=3D374 qemu: flush code_size=3D44884568 nb_tbs=3D79901 avg_tb_size=3D376 qemu: flush code_size=3D50782632 nb_tbs=3D90681 avg_tb_size=3D374 qemu: flush code_size=3D39848888 nb_tbs=3D71433 avg_tb_size=3D372 qemu: flush code_size=3D64708840 nb_tbs=3D119052 avg_tb_size=3D359 qemu: flush code_size=3D49830008 nb_tbs=3D90992 avg_tb_size=3D362 qemu: flush code_size=3D68372408 nb_tbs=3D123442 avg_tb_size=3D368 qemu: flush code_size=3D33555560 nb_tbs=3D59514 avg_tb_size=3D378 qemu: flush code_size=3D44748344 nb_tbs=3D80974 avg_tb_size=3D367 qemu: flush code_size=3D37104248 nb_tbs=3D67609 avg_tb_size=3D364 That is, 20 flushes. Note how a static partitioning approach uses the code buffer poorly, leading to many unnecessary flushes. Signed-off-by: Emilio G. Cota --- include/exec/exec-all.h | 3 + tcg/tcg.h | 6 ++ accel/tcg/translate-all.c | 56 +++++++++---- bsd-user/main.c | 1 + cpus.c | 12 +++ linux-user/main.c | 1 + tcg/tcg.c | 197 ++++++++++++++++++++++++++++++++++++++++++= +++- 7 files changed, 260 insertions(+), 16 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 37487d7..69a2a21 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -49,6 +49,9 @@ void gen_intermediate_code(CPUArchState *env, struct Tran= slationBlock *tb); void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, target_ulong *data); =20 +#ifdef CONFIG_SOFTMMU +void softmmu_tcg_region_init(void); +#endif void cpu_gen_init(void); bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index 9d17584..6f6720b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -772,6 +772,12 @@ void *tcg_malloc_internal(TCGContext *s, int size); void tcg_pool_reset(TCGContext *s); TranslationBlock *tcg_tb_alloc(TCGContext *s); =20 +void tcg_region_init(size_t n_regions); +void tcg_region_reset_all(void); + +size_t tcg_code_size(void); +size_t tcg_code_capacity(void); + /* Called with tb_lock held. */ static inline void *tcg_malloc(int size) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 913b1c5..c30d400 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -59,6 +59,7 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "sysemu/cpus.h" +#include "sysemu/sysemu.h" =20 /* #define DEBUG_TB_INVALIDATE */ /* #define DEBUG_TB_FLUSH */ @@ -797,6 +798,39 @@ static inline void code_gen_alloc(size_t tb_size) qemu_mutex_init(&tb_ctx.tb_lock); } =20 +#ifdef CONFIG_SOFTMMU +/* + * It is likely that some vCPUs will translate more code than others, so we + * first try to set more regions than smp_cpus, with those regions being + * larger than the minimum code_gen_buffer size. If that's not possible we + * make do by evenly dividing the code_gen_buffer among the vCPUs. + */ +void softmmu_tcg_region_init(void) +{ + size_t i; + + /* Use a single region if all we have is one vCPU thread */ + if (smp_cpus =3D=3D 1 || !qemu_tcg_mttcg_enabled()) { + tcg_region_init(0); + return; + } + + for (i =3D 8; i > 0; i--) { + size_t regions_per_thread =3D i; + size_t region_size; + + region_size =3D tcg_init_ctx.code_gen_buffer_size; + region_size /=3D smp_cpus * regions_per_thread; + + if (region_size >=3D 2 * MIN_CODE_GEN_BUFFER_SIZE) { + tcg_region_init(smp_cpus * regions_per_thread); + return; + } + } + tcg_region_init(smp_cpus); +} +#endif + static void tb_htable_init(void) { unsigned int mode =3D QHT_MODE_AUTO_RESIZE; @@ -916,13 +950,8 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data= tb_flush_count) size_t host_size =3D 0; =20 g_tree_foreach(tb_ctx.tb_tree, tb_host_size_iter, &host_size); - printf("qemu: flush code_size=3D%td nb_tbs=3D%zu avg_tb_size=3D%zu= \n", - tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, nb_tbs, - nb_tbs > 0 ? host_size / nb_tbs : 0); - } - if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) - > tcg_ctx->code_gen_buffer_size) { - cpu_abort(cpu, "Internal error: code buffer overflow\n"); + printf("qemu: flush code_size=3D%zu nb_tbs=3D%zu avg_tb_size=3D%zu= \n", + tcg_code_size(), nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : = 0); } =20 CPU_FOREACH(cpu) { @@ -936,7 +965,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data = tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); page_flush_tb(); =20 - tcg_ctx->code_gen_ptr =3D tcg_ctx->code_gen_buffer; + tcg_region_reset_all(); /* XXX: flush processor icache at this point if cache flush is expensive */ atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); @@ -1281,9 +1310,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags |=3D CF_USE_ICOUNT; } =20 + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { - buffer_overflow: /* flush must be done */ tb_flush(cpu); mmap_unlock(); @@ -1367,9 +1396,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #endif =20 - tcg_ctx->code_gen_ptr =3D (void *) + atomic_set(&tcg_ctx->code_gen_ptr, (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, - CODE_GEN_ALIGN); + CODE_GEN_ALIGN)); =20 /* init jump list */ assert(((uintptr_t)tb & 3) =3D=3D 0); @@ -1921,9 +1950,8 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) * otherwise users might think "-tb-size" is not honoured. * For avg host size we use the precise numbers from tb_tree_stats tho= ugh. */ - cpu_fprintf(f, "gen code size %td/%zd\n", - tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer, - tcg_ctx->code_gen_highwater - tcg_ctx->code_gen_buffer); + cpu_fprintf(f, "gen code size %zu/%zu\n", + tcg_code_size(), tcg_code_capacity()); cpu_fprintf(f, "TB count %zu\n", nb_tbs); cpu_fprintf(f, "TB avg target size %zu max=3D%zu bytes\n", nb_tbs ? tst.target_size / nb_tbs : 0, diff --git a/bsd-user/main.c b/bsd-user/main.c index 7a8b29e..bc06c1c 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -979,6 +979,7 @@ int main(int argc, char **argv) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); + tcg_region_init(0); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/cpus.c b/cpus.c index 14bb8d5..5455819 100644 --- a/cpus.c +++ b/cpus.c @@ -1664,6 +1664,18 @@ static void qemu_tcg_init_vcpu(CPUState *cpu) char thread_name[VCPU_THREAD_NAME_SIZE]; static QemuCond *single_tcg_halt_cond; static QemuThread *single_tcg_cpu_thread; + static int tcg_region_inited; + + /* + * Initialize TCG regions--once, of course. Now is a good time, becaus= e: + * (1) TCG's init context, prologue and target globals have been set u= p. + * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before t= he + * -accel flag is processed, so the check doesn't work then). + */ + if (!tcg_region_inited) { + softmmu_tcg_region_init(); + tcg_region_inited =3D 1; + } =20 if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) { cpu->thread =3D g_malloc0(sizeof(QemuThread)); diff --git a/linux-user/main.c b/linux-user/main.c index ad4c6f5..0500628 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4457,6 +4457,7 @@ int main(int argc, char **argv, char **envp) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); + tcg_region_init(0); =20 #if defined(TARGET_I386) env->cr[0] =3D CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; diff --git a/tcg/tcg.c b/tcg/tcg.c index e8aae1f..daec7d1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -33,6 +33,7 @@ #include "qemu/cutils.h" #include "qemu/host-utils.h" #include "qemu/timer.h" +#include "qemu/osdep.h" =20 /* Note: the long term plan is to reduce the dependencies on the QEMU CPU definitions. Currently they are used for qemu_ld/st @@ -120,6 +121,23 @@ static bool tcg_out_tb_finalize(TCGContext *s); static TCGContext **tcg_ctxs; static unsigned int n_tcg_ctxs; =20 +/* + * We divide code_gen_buffer into equally-sized "regions" that TCG threads + * dynamically allocate from as demand dictates. Given appropriate region + * sizing, this minimizes flushes even when some TCG threads generate a lot + * more code than others. + */ +struct tcg_region_state { + QemuMutex lock; + void *buf; /* set at init time */ + size_t n; /* set at init time */ + size_t size; /* size of one region; set at init time */ + size_t current; /* protected by the lock */ + size_t n_full; /* protected by the lock */ +}; + +static struct tcg_region_state region; + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -257,6 +275,177 @@ TCGLabel *gen_new_label(void) =20 #include "tcg-target.inc.c" =20 +static void tcg_region_assign(TCGContext *s, size_t curr_region) +{ + size_t guard_size =3D qemu_real_host_page_size; + void *buf =3D region.buf + curr_region * (region.size + guard_size); + + s->code_gen_buffer =3D buf; + s->code_gen_ptr =3D buf; + s->code_gen_buffer_size =3D region.size; + s->code_gen_highwater =3D buf + region.size - TCG_HIGHWATER; +} + +static bool tcg_region_alloc__locked(TCGContext *s) +{ + if (region.current =3D=3D region.n) { + return true; + } + tcg_region_assign(s, region.current); + region.current++; + return false; +} + +/* + * Request a new region once the one in use has filled up. + * Returns true on error. + */ +static bool tcg_region_alloc(TCGContext *s) +{ + bool err; + + qemu_mutex_lock(®ion.lock); + err =3D tcg_region_alloc__locked(s); + if (!err) { + region.n_full++; + } + qemu_mutex_unlock(®ion.lock); + return err; +} + +/* + * Perform a context's first region allocation. + * This function does _not_ increment region.n_full. + */ +static inline bool tcg_region_initial_alloc__locked(TCGContext *s) +{ + return tcg_region_alloc__locked(s); +} + +/* Call from a safe-work context */ +void tcg_region_reset_all(void) +{ + unsigned int i; + + qemu_mutex_lock(®ion.lock); + region.current =3D 0; + region.n_full =3D 0; + + for (i =3D 0; i < n_tcg_ctxs; i++) { + if (unlikely(tcg_region_initial_alloc__locked(tcg_ctxs[i]))) { + tcg_abort(); + } + } + qemu_mutex_unlock(®ion.lock); +} + +static void tcg_region_set_guard_pages(void) +{ + size_t guard_size =3D qemu_real_host_page_size; + size_t i; + + for (i =3D 0; i < region.n; i++) { + void *guard =3D region.buf + region.size + i * (region.size + guar= d_size); + + if (qemu_mprotect_none(guard, qemu_real_host_page_size)) { + tcg_abort(); + } + } +} + +/* + * Initializes region partitioning, setting the number of regions via + * @n_regions. + * Set @n_regions to 0 or 1 to use a single region that uses all of + * code_gen_buffer. + * + * Called at init time from the parent thread (i.e. the one calling + * tcg_context_init), after the target's TCG globals have been set. + * + * Region partitioning works by splitting code_gen_buffer into separate re= gions, + * and then assigning regions to TCG threads so that the threads can trans= late + * code in parallel without synchronization. + */ +void tcg_region_init(size_t n_regions) +{ + void *buf =3D tcg_init_ctx.code_gen_buffer; + size_t size =3D tcg_init_ctx.code_gen_buffer_size; + + if (!n_regions) { + n_regions =3D 1; + } + + /* start on a page-aligned address */ + buf =3D QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); + if (unlikely(buf > tcg_init_ctx.code_gen_buffer + size)) { + tcg_abort(); + } + /* discard that initial portion */ + size -=3D buf - tcg_init_ctx.code_gen_buffer; + + /* make region.size a multiple of page_size */ + region.size =3D size / n_regions; + region.size &=3D qemu_real_host_page_mask; + + /* A region must have at least 2 pages; one code, one guard */ + if (unlikely(region.size < 2 * qemu_real_host_page_size)) { + tcg_abort(); + } + + /* do not count the guard page in region.size */ + region.size -=3D qemu_real_host_page_size; + region.n =3D n_regions; + region.buf =3D buf; + tcg_region_set_guard_pages(); + qemu_mutex_init(®ion.lock); + /* + * We do not yet support multiple TCG contexts, so do the initial + * allocation now. + */ + if (unlikely(tcg_region_initial_alloc__locked(tcg_ctx))) { + tcg_abort(); + } +} + +/* + * Returns the size (in bytes) of all translated code (i.e. from all regio= ns) + * currently in the cache. + * See also: tcg_code_capacity() + * Do not confuse with tcg_current_code_size(); that one applies to a sing= le + * TCG context. + */ +size_t tcg_code_size(void) +{ + unsigned int i; + size_t total; + + qemu_mutex_lock(®ion.lock); + total =3D region.n_full * (region.size - TCG_HIGHWATER); + for (i =3D 0; i < n_tcg_ctxs; i++) { + const TCGContext *s =3D tcg_ctxs[i]; + size_t size; + + size =3D atomic_read(&s->code_gen_ptr) - s->code_gen_buffer; + if (unlikely(size > s->code_gen_buffer_size)) { + tcg_abort(); + } + total +=3D size; + } + qemu_mutex_unlock(®ion.lock); + return total; +} + +/* + * Returns the code capacity (in bytes) of the entire cache, i.e. includin= g all + * regions. + * See also: tcg_code_size() + */ +size_t tcg_code_capacity(void) +{ + /* no need for synchronization; these variables are set at init time */ + return region.n * (region.size - TCG_HIGHWATER); +} + /* pool based memory allocation */ void *tcg_malloc_internal(TCGContext *s, int size) { @@ -406,13 +595,17 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) TranslationBlock *tb; void *next; =20 + retry: tb =3D (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); next =3D (void *)ROUND_UP((uintptr_t)(tb + 1), align); =20 if (unlikely(next > s->code_gen_highwater)) { - return NULL; + if (tcg_region_alloc(s)) { + return NULL; + } + goto retry; } - s->code_gen_ptr =3D next; + atomic_set(&s->code_gen_ptr, next); return tb; } =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237197660718.9268611746814; Sun, 16 Jul 2017 13:33:17 -0700 (PDT) Received: from localhost ([::1]:46830 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqE8-0007zj-6f for importer@patchew.org; Sun, 16 Jul 2017 16:33:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46415) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmg-0001Dl-Dt for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmb-0008Sl-71 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:54 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:36519) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpma-0008Rt-U5 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 60AAA20A76; Sun, 16 Jul 2017 16:04:48 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:48 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 25D9F2450F; Sun, 16 Jul 2017 16:04:48 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=rlH 6yV1pfD9yFuJY5DqIeHk0Oo5U/p8kn0nVEEah+i8=; b=DAbjf3DQ2BlbDit442H tOTnUT9XqvHWNBUO5XeyZx7y68sXjUdk9IBHknMbm3dVn9CZi4R6cXPC7gGQRiTr omPJ7fHBYIPxqMIPVNjkApdyXZxRVsi6C8ibdV9MqlvaVgPihI/35yKerrvog8NW TABYVvjJBw5JN5IFZxHR2+MU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=rlH6yV1pfD9yFuJY5DqIeHk0Oo5U/p8kn0nVEEah+ i8=; b=QX9gLVVTkrL6NylPnaP6YR1LuEv6EtsQYUuItlp44RbVqA/GHcx3fPr7H yOOODMhZpMfOIDPPnGoQcyYvtthqWkLvyD+jIT6nTfO+Sa64orwIzuK0DsDb5One Nw9RNt41erjQ5wJdlHCPfwAkHqvMJ46D/EopIYgXr1VYd/kAt3A95oESoKimRiw2 xHgUW5P3wtoYe9vZBjZN/2X23g89vhxNqLpo3ogGhtkVDuQgO3Pjr3tQbqn8mXcG V8NcfkBxs0c4GaCzKX7pS8IH+mDkqfG5vwGmaPICtX1q8mAo0jmpf7UbjY+S6xDW MOW5KzClBgrtygUaavSZiPXMXDOUg== X-ME-Sender: X-Sasl-enc: kW5gSliKGAQmt6W24IBQRzsv1KRnsBng808FTQRmE1Q6 1500235488 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:27 -0400 Message-Id: <1500235468-15341-45-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 44/45] translate-all: do not allocate a guard page for code_gen_buffer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" TCG regions already have a guard page. Signed-off-by: Emilio G. Cota --- accel/tcg/translate-all.c | 47 ++++++++++++-------------------------------= ---- 1 file changed, 12 insertions(+), 35 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c30d400..98aa63e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -608,19 +608,11 @@ static uint8_t static_code_gen_buffer[DEFAULT_CODE_GE= N_BUFFER_SIZE] static inline void *alloc_code_gen_buffer(void) { void *buf =3D static_code_gen_buffer; - size_t full_size, size; - - /* The size of the buffer, rounded down to end on a page boundary. */ - full_size =3D (((uintptr_t)buf + sizeof(static_code_gen_buffer)) - & qemu_real_host_page_mask) - (uintptr_t)buf; - - /* Reserve a guard page. */ - size =3D full_size - qemu_real_host_page_size; + size_t size =3D sizeof(static_code_gen_buffer); =20 /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx->code_gen_buffer_size) { - size =3D (((uintptr_t)buf + tcg_ctx->code_gen_buffer_size) - & qemu_real_host_page_mask) - (uintptr_t)buf; + size =3D tcg_ctx->code_gen_buffer_size; } tcg_ctx->code_gen_buffer_size =3D size; =20 @@ -634,9 +626,6 @@ static inline void *alloc_code_gen_buffer(void) if (qemu_mprotect_rwx(buf, size)) { abort(); } - if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { - abort(); - } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 return buf; @@ -645,22 +634,16 @@ static inline void *alloc_code_gen_buffer(void) static inline void *alloc_code_gen_buffer(void) { size_t size =3D tcg_ctx->code_gen_buffer_size; - void *buf1, *buf2; - - /* Perform the allocation in two steps, so that the guard page - is reserved but uncommitted. */ - buf1 =3D VirtualAlloc(NULL, size + qemu_real_host_page_size, - MEM_RESERVE, PAGE_NOACCESS); - if (buf1 !=3D NULL) { - buf2 =3D VirtualAlloc(buf1, size, MEM_COMMIT, PAGE_EXECUTE_READWRI= TE); - assert(buf1 =3D=3D buf2); - } + void *buf; =20 - return buf1; + buf =3D VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, + PAGE_EXECUTE_READWRITE); + return buf; } #else static inline void *alloc_code_gen_buffer(void) { + int prot =3D PROT_WRITE | PROT_READ | PROT_EXEC; int flags =3D MAP_PRIVATE | MAP_ANONYMOUS; uintptr_t start =3D 0; size_t size =3D tcg_ctx->code_gen_buffer_size; @@ -694,8 +677,7 @@ static inline void *alloc_code_gen_buffer(void) # endif # endif =20 - buf =3D mmap((void *)start, size + qemu_real_host_page_size, - PROT_NONE, flags, -1, 0); + buf =3D mmap((void *)start, size, prot, flags, -1, 0); if (buf =3D=3D MAP_FAILED) { return NULL; } @@ -705,24 +687,23 @@ static inline void *alloc_code_gen_buffer(void) /* Try again, with the original still mapped, to avoid re-acquiring that 256mb crossing. This time don't specify an address. */ size_t size2; - void *buf2 =3D mmap(NULL, size + qemu_real_host_page_size, - PROT_NONE, flags, -1, 0); + void *buf2 =3D mmap(NULL, size, prot, flags, -1, 0); switch ((int)(buf2 !=3D MAP_FAILED)) { case 1: if (!cross_256mb(buf2, size)) { /* Success! Use the new buffer. */ - munmap(buf, size + qemu_real_host_page_size); + munmap(buf, size); break; } /* Failure. Work with what we had. */ - munmap(buf2, size + qemu_real_host_page_size); + munmap(buf2, size); /* fallthru */ default: /* Split the original buffer. Free the smaller half. */ buf2 =3D split_cross_256mb(buf, size); size2 =3D tcg_ctx->code_gen_buffer_size; if (buf =3D=3D buf2) { - munmap(buf + size2 + qemu_real_host_page_size, size - size= 2); + munmap(buf + size2, size - size2); } else { munmap(buf, size - size2); } @@ -733,10 +714,6 @@ static inline void *alloc_code_gen_buffer(void) } #endif =20 - /* Make the final buffer accessible. The guard page at the end - will remain inaccessible with PROT_NONE. */ - mprotect(buf, size, PROT_WRITE | PROT_READ | PROT_EXEC); - /* Request large pages for the buffer. */ qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); =20 --=20 2.7.4 From nobody Tue Apr 30 01:00:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500237593934509.3630259512712; Sun, 16 Jul 2017 13:39:53 -0700 (PDT) Received: from localhost ([::1]:46863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWqKW-0004SA-ON for importer@patchew.org; Sun, 16 Jul 2017 16:39:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmj-0001HX-TW for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:05:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmb-0008TW-LB for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:57 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:47883) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmb-0008S5-4b for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:49 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 8F12020A7E; Sun, 16 Jul 2017 16:04:48 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:48 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 4CCF77E17E; Sun, 16 Jul 2017 16:04:48 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=hTv 8r7uFbTgN9alHPDjf5MOo8n5Ihao+PBXSzWnK9YA=; b=vxV/U+c/Gmebvrczlnd BzCITyKxWj1W5SxTur2d2OdwjY3epLGIGpgHouSYm4E1L7UFJaYuZl7C/v69WV/z Vw37fUV7KEFIJP/Jo8wx7YR/pTisz3ROHhdO+MIrQMX4srJlCB0CstX9yG2oxuAa WwgOYm/lPOnbC4zFoB9CICIk= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=hTv8r7uFbTgN9alHPDjf5MOo8n5Ihao+PBXSzWnK9 YA=; b=JFcfMDem5GVz8O31hRKqhVq4S5/7YVHqCHnWOqPK1w/cHpya5cB+Luqa3 2diZRzTqR2tST4AeU4UkQoxmcQSAbuxiOhxieUjU5smcRrgiWCPN1WvjcLCkCbqV Wa8FPB7RrhAf5Er8gzMnghWbFa71V3D1pEaD9JzXzhhNvs16+KJuz4fQY4TVf72y ByaUJu43FlR6Uy+1HMKKaVrFR50Ej8HnHpO/DY0Jve8b48JyrVcfTCZ11gUd3Svp HhM0dXVKa/jnGl3h/8nKYbl+HDJXHpbeWxcCK10PyoCxM8GzX0Xp6370cOIFl2RV Nj4osthjCeOvZ6C9d1Zdq2uQ8AUug== X-ME-Sender: X-Sasl-enc: kW5hSF2BFBAzv6K/5JtQRzsv1KRnsBng808FTQRmE1Q6 1500235488 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:04:28 -0400 Message-Id: <1500235468-15341-46-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 45/45] tcg: enable multiple TCG contexts in softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This enables parallel TCG code generation. However, we do not take advantage of it yet since tb_lock is still held during tb_gen_code. In user-mode we use a single TCG context; see the documentation added to tcg_region_init for the rationale. Note that targets do not need any conversion: targets initialize a TCGContext (e.g. defining TCG globals), and after this initialization has finished, the context is cloned by the vCPU threads, each of them keeping a separate copy. TCG threads claim one entry in tcg_ctxs[] atomically using cmpxchg. They also increment n_tcg_ctxs atomically. Do not be too annoyed by the subsequent atomic_read's of that variable; they are there just to play nice with analysis tools such as thread sanitizer. Previous patches folded some TCG globals into TCGContext. The non-const globals remaining are only set at init time, i.e. before the TCG threads are spawned. Here is a list of these set-at-init-time globals under tcg/: Only written by tcg_context_init: - indirect_reg_alloc_order - tcg_op_defs Only written by tcg_target_init (called from tcg_context_init): - tcg_target_available_regs - tcg_target_call_clobber_regs - arm: arm_arch, use_idiv_instructions - i386: have_cmov, have_bmi1, have_bmi2, have_lzcnt, have_movbe, have_popcnt - mips: use_movnz_instructions, use_mips32_instructions, use_mips32r2_instructions, got_sigill (tcg_target_detect_isa) - ppc: have_isa_2_06, have_isa_3_00, tb_ret_addr - s390: tb_ret_addr, s390_facilities - sparc: qemu_ld_trampoline, qemu_st_trampoline (build_trampolines), use_vis3_instructions Only written by tcg_prologue_init: - 'struct jit_code_entry one_entry' - aarch64: tb_ret_addr - arm: tb_ret_addr - i386: tb_ret_addr, guest_base_flags - ia64: tb_ret_addr - mips: tb_ret_addr, bswap32_addr, bswap32u_addr, bswap64_addr Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 7 ++-- accel/tcg/translate-all.c | 2 +- cpus.c | 2 + linux-user/syscall.c | 1 + tcg/tcg.c | 103 ++++++++++++++++++++++++++++++++++++++++++= ---- 5 files changed, 104 insertions(+), 11 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 6f6720b..2f7661b 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -745,7 +745,7 @@ struct TCGContext { }; =20 extern TCGContext tcg_init_ctx; -extern TCGContext *tcg_ctx; +extern __thread TCGContext *tcg_ctx; =20 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) { @@ -767,7 +767,7 @@ static inline bool tcg_op_buf_full(void) =20 /* pool based memory allocation */ =20 -/* tb_lock must be held for tcg_malloc_internal. */ +/* user-mode: tb_lock must be held for tcg_malloc_internal. */ void *tcg_malloc_internal(TCGContext *s, int size); void tcg_pool_reset(TCGContext *s); TranslationBlock *tcg_tb_alloc(TCGContext *s); @@ -778,7 +778,7 @@ void tcg_region_reset_all(void); size_t tcg_code_size(void); size_t tcg_code_capacity(void); =20 -/* Called with tb_lock held. */ +/* user-mode: Called with tb_lock held. */ static inline void *tcg_malloc(int size) { TCGContext *s =3D tcg_ctx; @@ -795,6 +795,7 @@ static inline void *tcg_malloc(int size) } =20 void tcg_context_init(TCGContext *s); +void tcg_register_thread(void); void tcg_prologue_init(TCGContext *s); void tcg_func_start(TCGContext *s); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 98aa63e..78457a4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -155,7 +155,7 @@ static void *l1_map[V_L1_MAX_SIZE]; =20 /* code generation context */ TCGContext tcg_init_ctx; -TCGContext *tcg_ctx; +__thread TCGContext *tcg_ctx; TBContext tb_ctx; bool parallel_cpus; =20 diff --git a/cpus.c b/cpus.c index 5455819..170071c 100644 --- a/cpus.c +++ b/cpus.c @@ -1307,6 +1307,7 @@ static void *qemu_tcg_rr_cpu_thread_fn(void *arg) CPUState *cpu =3D arg; =20 rcu_register_thread(); + tcg_register_thread(); =20 qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); @@ -1454,6 +1455,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) g_assert(!use_icount); =20 rcu_register_thread(); + tcg_register_thread(); =20 qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 925ae11..1beb11c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6214,6 +6214,7 @@ static void *clone_func(void *arg) TaskState *ts; =20 rcu_register_thread(); + tcg_register_thread(); env =3D info->env; cpu =3D ENV_GET_CPU(env); thread_cpu =3D cpu; diff --git a/tcg/tcg.c b/tcg/tcg.c index daec7d1..f56ab44 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -59,6 +59,7 @@ =20 #include "elf.h" #include "exec/log.h" +#include "sysemu/sysemu.h" =20 /* Forward declarations for functions declared in tcg-target.inc.c and used here. */ @@ -325,13 +326,14 @@ static inline bool tcg_region_initial_alloc__locked(T= CGContext *s) /* Call from a safe-work context */ void tcg_region_reset_all(void) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; =20 qemu_mutex_lock(®ion.lock); region.current =3D 0; region.n_full =3D 0; =20 - for (i =3D 0; i < n_tcg_ctxs; i++) { + for (i =3D 0; i < n_ctxs; i++) { if (unlikely(tcg_region_initial_alloc__locked(tcg_ctxs[i]))) { tcg_abort(); } @@ -365,6 +367,23 @@ static void tcg_region_set_guard_pages(void) * Region partitioning works by splitting code_gen_buffer into separate re= gions, * and then assigning regions to TCG threads so that the threads can trans= late * code in parallel without synchronization. + * + * In softmmu the number of TCG threads is bounded by smp_cpus, so + * tcg_region_init callers must ensure that @n_regions is set so that ther= e will + * be at least as many regions as TCG threads. + * + * User-mode callers must set @n_regions to 0/1, thereby using a single re= gion. + * Having multiple regions in user-mode is not supported, since the number= of + * vCPU threads (recall that each thread spawned by the guest corresponds = to + * a vCPU thread) is only bounded by the OS, and usually this number is hu= ge + * (tens of thousands is not uncommon). Thus, given this large bound on t= he + * number of vCPU threads and the fact that code_gen_buffer is allocated at + * compile-time, we cannot guarantee that the availability of at least one + * region per vCPU thread. + * + * However, this user-mode limitation is unlikely to be a significant prob= lem + * in practice. Multi-threaded guests share most if not all of their trans= lated + * code, which makes parallel code generation less appealing than in softm= mu. */ void tcg_region_init(size_t n_regions) { @@ -398,13 +417,71 @@ void tcg_region_init(size_t n_regions) region.buf =3D buf; tcg_region_set_guard_pages(); qemu_mutex_init(®ion.lock); - /* - * We do not yet support multiple TCG contexts, so do the initial - * allocation now. - */ +#ifdef CONFIG_USER_ONLY + /* In user-mode we support only one ctx, so do the initial allocation = now */ if (unlikely(tcg_region_initial_alloc__locked(tcg_ctx))) { tcg_abort(); } +#endif +} + +/* + * All TCG threads except the parent (i.e. the one that called tcg_context= _init + * and registered the target's TCG globals) must register with this functi= on + * before initiating translation. + * + * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentati= on + * of tcg_region_init() for the reasoning behind this. + * + * In softmmu each caller registers its context in tcg_ctxs[]. Note that in + * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial conte= xt + * is not used anymore for translation once this function is called. + * + * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iter= ates + * over the array (e.g. tcg_code_size() the same for both softmmu and user= -mode. + */ +void tcg_register_thread(void) +{ +#ifdef CONFIG_USER_ONLY + tcg_ctx =3D &tcg_init_ctx; +#else + TCGContext *s =3D g_malloc(sizeof(*s)); + int i; + + memcpy(s, &tcg_init_ctx, sizeof(*s)); + /* tcg_optimize will allocate a new opt_temps array for this ctx */ + s->opt_temps =3D NULL; + + /* claim the first free pointer in tcg_ctxs and increment n_tcg_ctxs */ + for (i =3D 0; i < smp_cpus; i++) { + if (atomic_cmpxchg(&tcg_ctxs[i], NULL, s) =3D=3D NULL) { + unsigned int n; + + n =3D atomic_fetch_inc(&n_tcg_ctxs); + /* + * Zero out s->prof in all contexts but the first. + * This ensures that we correctly account for the profiling in= fo + * generated during initialization, since tcg_init_ctx is not + * tracked by the array. + */ + if (n !=3D 0) { +#ifdef CONFIG_PROFILER + memset(&s->prof, 0, sizeof(s->prof)); +#endif + } + break; + } + } + /* Only vCPU threads can call this function */ + g_assert(i < smp_cpus); + + tcg_ctx =3D s; + qemu_mutex_lock(®ion.lock); + if (unlikely(tcg_region_initial_alloc__locked(tcg_ctx))) { + tcg_abort(); + } + qemu_mutex_unlock(®ion.lock); +#endif } =20 /* @@ -416,12 +493,13 @@ void tcg_region_init(size_t n_regions) */ size_t tcg_code_size(void) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; size_t total; =20 qemu_mutex_lock(®ion.lock); total =3D region.n_full * (region.size - TCG_HIGHWATER); - for (i =3D 0; i < n_tcg_ctxs; i++) { + for (i =3D 0; i < n_ctxs; i++) { const TCGContext *s =3D tcg_ctxs[i]; size_t size; =20 @@ -516,11 +594,21 @@ static GHashTable *helper_table; static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); =20 +/* + * In user-mode we simply share the init context among threads, since we + * use a single region. See the documentation tcg_region_init() for the + * reasoning behind this. + * In softmmu we will have at most smp_cpus TCG threads. + */ static void tcg_ctxs_init(TCGContext *s) { +#ifdef CONFIG_USER_ONLY tcg_ctxs =3D g_new(TCGContext *, 1); tcg_ctxs[0] =3D s; n_tcg_ctxs =3D 1; +#else + tcg_ctxs =3D g_new0(TCGContext *, smp_cpus); +#endif } =20 void tcg_context_init(TCGContext *s) @@ -2734,9 +2822,10 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb= _oargs, int nb_iargs, static inline void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) { + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); unsigned int i; =20 - for (i =3D 0; i < n_tcg_ctxs; i++) { + for (i =3D 0; i < n_ctxs; i++) { const TCGProfile *orig =3D &tcg_ctxs[i]->prof; =20 if (counters) { --=20 2.7.4