From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496046910847862.5454818159907; Mon, 29 May 2017 01:35:10 -0700 (PDT) Received: from localhost ([::1]:47463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG8r-0006o3-D1 for importer@patchew.org; Mon, 29 May 2017 04:35:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG71-0005gu-GO for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG6z-0004sM-68 for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:15 -0400 Received: from mga02.intel.com ([134.134.136.20]:62237) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG6y-0004s0-RH for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:13 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:11 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607747" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:31 +0800 Message-Id: <1496079043-26694-2-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 1/6] vfio: Add Intel platform definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces device descriptions for Intel platforms. Most of the Intel device definitions come from i915. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/Makefile.objs | 2 +- hw/vfio/intel-platform.c | 366 +++++++++++++++++++++++++++++++++++++++++++= ++++ hw/vfio/intel-platform.h | 38 +++++ hw/vfio/pci-quirks.c | 28 ++-- 4 files changed, 421 insertions(+), 13 deletions(-) create mode 100644 hw/vfio/intel-platform.c create mode 100644 hw/vfio/intel-platform.h diff --git a/hw/vfio/Makefile.objs b/hw/vfio/Makefile.objs index 05e7fbb..b183f5c 100644 --- a/hw/vfio/Makefile.objs +++ b/hw/vfio/Makefile.objs @@ -1,6 +1,6 @@ ifeq ($(CONFIG_LINUX), y) obj-$(CONFIG_SOFTMMU) +=3D common.o -obj-$(CONFIG_PCI) +=3D pci.o pci-quirks.o +obj-$(CONFIG_PCI) +=3D pci.o pci-quirks.o intel-platform.o obj-$(CONFIG_SOFTMMU) +=3D platform.o obj-$(CONFIG_VFIO_XGMAC) +=3D calxeda-xgmac.o obj-$(CONFIG_VFIO_AMD_XGBE) +=3D amd-xgbe.o diff --git a/hw/vfio/intel-platform.c b/hw/vfio/intel-platform.c new file mode 100644 index 0000000..41f1fa0 --- /dev/null +++ b/hw/vfio/intel-platform.c @@ -0,0 +1,366 @@ +/* + * Device descriptions for Intel platforms. + * + * Copyright Intel Coporation 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "intel-platform.h" + +#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ +#define SNB_GMCH_GGMS_MASK 0x3 +#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ +#define SNB_GMCH_GMS_MASK 0x1f +#define BDW_GMCH_GGMS_SHIFT 6 +#define BDW_GMCH_GGMS_MASK 0x3 +#define BDW_GMCH_GMS_SHIFT 8 +#define BDW_GMCH_GMS_MASK 0xff + +static unsigned int gen6_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GMS_SHIFT; + gmch &=3D SNB_GMCH_GMS_MASK; + return gmch << 25; /* 32 MB units */ +} + +static unsigned int bdw_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D BDW_GMCH_GMS_SHIFT; + gmch &=3D BDW_GMCH_GMS_MASK; + return gmch << 25; /* 32 MB units */ +} + +static unsigned int chv_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GMS_SHIFT; + gmch &=3D SNB_GMCH_GMS_MASK; + + /* + * 0x0 to 0x10: 32MB increments starting at 0MB + * 0x11 to 0x16: 4MB increments starting at 8MB + * 0x17 to 0x1d: 4MB increments start at 36MB + */ + if (gmch < 0x11) + return gmch << 25; + else if (gmch < 0x17) + return (gmch - 0x11 + 2) << 22; + else + return (gmch - 0x17 + 9) << 22; +} + +static unsigned int gen9_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D BDW_GMCH_GMS_SHIFT; + gmch &=3D BDW_GMCH_GMS_MASK; + + if (gmch < 0xf0) + return gmch << 25; /* 32 MB units */ + else + /* 4MB increments starting at 0xf0 for 4MB */ + return (gmch - 0xf0 + 1) << 22; +} + +static unsigned int gen6_get_gtt_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GGMS_SHIFT; + gmch &=3D SNB_GMCH_GGMS_MASK; + return gmch << 20; +} + +static unsigned int gen8_get_gtt_size(uint16_t gmch) +{ + gmch >>=3D BDW_GMCH_GGMS_SHIFT; + gmch &=3D BDW_GMCH_GGMS_MASK; + if (gmch) + gmch =3D 1 << gmch; + + return gmch << 20; +} + +static unsigned int chv_get_gtt_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GGMS_SHIFT; + gmch &=3D SNB_GMCH_GGMS_MASK; + + if (gmch) + return 1 << (20 + gmch); + + return 0; +} + +static const struct intel_device_info intel_sandybridge_info =3D { + .gen =3D 6, + .platform =3D INTEL_SANDYBRIDGE, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_ivybridge_info =3D { + .gen =3D 7, + .platform =3D INTEL_IVYBRIDGE, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_valleyview_info =3D { + .gen =3D 7, + .platform =3D INTEL_VALLEYVIEW, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_haswell_info =3D { + .gen =3D 7, /* Actually HASWELL is GEN 7.5 */ + .platform =3D INTEL_HASWELL, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_broadwell_info =3D { + .gen =3D 8, + .platform =3D INTEL_BROADWELL, + .gtt_entry_size =3D 8, + .get_stolen_size =3D bdw_get_stolen_size, + .get_gtt_size =3D gen8_get_gtt_size, +}; + +static const struct intel_device_info intel_cherryview_info =3D { + .gen =3D 8, + .platform =3D INTEL_CHERRYVIEW, + .gtt_entry_size =3D 8, + .get_stolen_size =3D chv_get_stolen_size, + .get_gtt_size =3D chv_get_gtt_size, +}; + +static const struct intel_device_info intel_skylake_info =3D { + .gen =3D 9, + .platform =3D INTEL_SKYLAKE, + .gtt_entry_size =3D 8, + .get_stolen_size =3D gen9_get_stolen_size, + .get_gtt_size =3D gen8_get_gtt_size, +}; + +static const struct intel_device_info intel_broxton_info =3D { + .gen =3D 9, + .platform =3D INTEL_BROXTON, + .gtt_entry_size =3D 8, + .get_stolen_size =3D gen9_get_stolen_size, + .get_gtt_size =3D gen8_get_gtt_size, +}; + +struct intel_pci_device_id { + uint16_t device_id; + const struct intel_device_info *info; +}; + +#define INTEL_VGA_DEVICE(id, info) \ + { id, info } + +#define INTEL_SNB_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0102, info), \ + INTEL_VGA_DEVICE(0x0112, info), \ + INTEL_VGA_DEVICE(0x0122, info), \ + INTEL_VGA_DEVICE(0x010A, info) + +#define INTEL_SNB_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0106, info), \ + INTEL_VGA_DEVICE(0x0116, info), \ + INTEL_VGA_DEVICE(0x0126, info) + +#define INTEL_IVB_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ + +#define INTEL_IVB_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ + +#define INTEL_HSW_IDS(info) \ + INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ + INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ + INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ + INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ + INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ + +#define INTEL_VLV_IDS(info) \ + INTEL_VGA_DEVICE(0x0f30, info), \ + INTEL_VGA_DEVICE(0x0f31, info), \ + INTEL_VGA_DEVICE(0x0f32, info), \ + INTEL_VGA_DEVICE(0x0f33, info), \ + INTEL_VGA_DEVICE(0x0157, info), \ + INTEL_VGA_DEVICE(0x0155, info) + +#define INTEL_BDW_GT12_IDS(info) \ + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ + INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ + INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ + INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ + INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ + INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ + +#define INTEL_BDW_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ + INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ + +#define INTEL_BDW_RSVD_IDS(info) \ + INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \ + INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ + +#define INTEL_BDW_IDS(info) \ + INTEL_BDW_GT12_IDS(info), \ + INTEL_BDW_GT3_IDS(info), \ + INTEL_BDW_RSVD_IDS(info) + +#define INTEL_CHV_IDS(info) \ + INTEL_VGA_DEVICE(0x22b0, info), \ + INTEL_VGA_DEVICE(0x22b1, info), \ + INTEL_VGA_DEVICE(0x22b2, info), \ + INTEL_VGA_DEVICE(0x22b3, info) + +#define INTEL_SKL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ + +#define INTEL_SKL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ + +#define INTEL_SKL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x192B, info) /* Halo GT3 */ \ + +#define INTEL_SKL_GT4_IDS(info) \ + INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ + INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ + INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ + +#define INTEL_SKL_IDS(info) \ + INTEL_SKL_GT1_IDS(info), \ + INTEL_SKL_GT2_IDS(info), \ + INTEL_SKL_GT3_IDS(info), \ + INTEL_SKL_GT4_IDS(info) + +#define INTEL_BXT_IDS(info) \ + INTEL_VGA_DEVICE(0x0A84, info), \ + INTEL_VGA_DEVICE(0x1A84, info), \ + INTEL_VGA_DEVICE(0x1A85, info), \ + INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ + INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ + +static const struct intel_pci_device_id pciidlist[] =3D { + INTEL_SNB_D_IDS(&intel_sandybridge_info), + INTEL_SNB_M_IDS(&intel_sandybridge_info), + INTEL_IVB_M_IDS(&intel_ivybridge_info), + INTEL_IVB_D_IDS(&intel_ivybridge_info), + INTEL_HSW_IDS(&intel_haswell_info), + INTEL_VLV_IDS(&intel_valleyview_info), + INTEL_BDW_GT12_IDS(&intel_broadwell_info), + INTEL_BDW_GT3_IDS(&intel_broadwell_info), + INTEL_BDW_RSVD_IDS(&intel_broadwell_info), + INTEL_CHV_IDS(&intel_cherryview_info), + INTEL_SKL_GT1_IDS(&intel_skylake_info), + INTEL_SKL_GT2_IDS(&intel_skylake_info), + INTEL_SKL_GT3_IDS(&intel_skylake_info), + INTEL_SKL_GT4_IDS(&intel_skylake_info), + INTEL_BXT_IDS(&intel_broxton_info), +}; + +const struct intel_device_info *intel_get_device_info(uint16_t device_id) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(pciidlist); i++) + if (pciidlist[i].device_id =3D=3D device_id) + return pciidlist[i].info; + + return NULL; +} diff --git a/hw/vfio/intel-platform.h b/hw/vfio/intel-platform.h new file mode 100644 index 0000000..7a2655e --- /dev/null +++ b/hw/vfio/intel-platform.h @@ -0,0 +1,38 @@ +/* + * Device descriptions for Intel platforms. + * + * Copyright Intel Coporation 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#ifndef HW_VFIO_INTEL_PLATFORM_H +#define HW_VFIO_INTEL_PLATFORM_H + +#include "qemu/osdep.h" + +enum intel_platform { + INTEL_PLATFORM_UNINITIALIZED =3D 0, + INTEL_SANDYBRIDGE, + INTEL_IVYBRIDGE, + INTEL_VALLEYVIEW, + INTEL_HASWELL, + INTEL_BROADWELL, + INTEL_CHERRYVIEW, + INTEL_SKYLAKE, + INTEL_BROXTON, + INTEL_MAX_PLATFORMS +}; + +struct intel_device_info { + uint8_t gen; + enum intel_platform platform; + uint32_t gtt_entry_size; + unsigned int (*get_stolen_size)(uint16_t gmch); + unsigned int (*get_gtt_size)(uint16_t gmch); +}; + +const struct intel_device_info *intel_get_device_info(uint16_t device_id); + +#endif /* HW_VFIO_INTEL_PLATFORM_H */ diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 349085e..71360ef 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -17,6 +17,7 @@ #include "hw/nvram/fw_cfg.h" #include "pci.h" #include "trace.h" +#include "intel-platform.h" =20 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match = hw */ static bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t dev= ice) @@ -1360,6 +1361,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) *host =3D NULL, *lpc =3D NULL; VFIOQuirk *quirk; VFIOIGDQuirk *igd; + const struct intel_device_info *info; PCIDevice *lpc_bridge; int i, ret, ggms_mb, gms_mb =3D 0, gen; uint64_t *bdsm_size; @@ -1380,6 +1382,20 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) } =20 /* + * IGD is not a standard, they like to change their specs often. We + * only attempt to support back to SandBridge and we hope that newer + * devices maintain compatibility with generation 8. + */ + info =3D intel_get_device_info(vdev->device_id); + if (!info) { + error_report("IGD device %s is unsupported in legacy mode, " + "try SandyBridge or newer", vdev->vbasedev.name); + return; + } + + gen =3D info->gen; + + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not * one we can hack on, legacy mode is no-go. Sorry Q35. @@ -1394,18 +1410,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) } =20 /* - * IGD is not a standard, they like to change their specs often. We - * only attempt to support back to SandBridge and we hope that newer - * devices maintain compatibility with generation 8. - */ - gen =3D igd_gen(vdev); - if (gen !=3D 6 && gen !=3D 8) { - error_report("IGD device %s is unsupported in legacy mode, " - "try SandyBridge or newer", vdev->vbasedev.name); - return; - } - - /* * Most of what we're doing here is to enable the ROM to run, so if * there's no ROM, there's no point in setting up this quirk. * NB. We only seem to get BIOS ROMs, so a UEFI VM would need CSM supp= ort. --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047039400766.6771608497403; Mon, 29 May 2017 01:37:19 -0700 (PDT) Received: from localhost ([::1]:47476 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGAv-0008RZ-Rq for importer@patchew.org; Mon, 29 May 2017 04:37:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7F-0005pK-9H for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG7D-00051Y-0f for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:29 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG7C-0004sQ-CS for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:26 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:25 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607886" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:38 +0800 Message-Id: <1496079043-26694-9-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 1/6] vfio: Add Intel platform definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces device descriptions for Intel platforms. Most of the Intel device definitions come from i915. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/Makefile.objs | 2 +- hw/vfio/intel-platform.c | 366 +++++++++++++++++++++++++++++++++++++++++++= ++++ hw/vfio/intel-platform.h | 38 +++++ hw/vfio/pci-quirks.c | 28 ++-- 4 files changed, 421 insertions(+), 13 deletions(-) create mode 100644 hw/vfio/intel-platform.c create mode 100644 hw/vfio/intel-platform.h diff --git a/hw/vfio/Makefile.objs b/hw/vfio/Makefile.objs index 05e7fbb..b183f5c 100644 --- a/hw/vfio/Makefile.objs +++ b/hw/vfio/Makefile.objs @@ -1,6 +1,6 @@ ifeq ($(CONFIG_LINUX), y) obj-$(CONFIG_SOFTMMU) +=3D common.o -obj-$(CONFIG_PCI) +=3D pci.o pci-quirks.o +obj-$(CONFIG_PCI) +=3D pci.o pci-quirks.o intel-platform.o obj-$(CONFIG_SOFTMMU) +=3D platform.o obj-$(CONFIG_VFIO_XGMAC) +=3D calxeda-xgmac.o obj-$(CONFIG_VFIO_AMD_XGBE) +=3D amd-xgbe.o diff --git a/hw/vfio/intel-platform.c b/hw/vfio/intel-platform.c new file mode 100644 index 0000000..41f1fa0 --- /dev/null +++ b/hw/vfio/intel-platform.c @@ -0,0 +1,366 @@ +/* + * Device descriptions for Intel platforms. + * + * Copyright Intel Coporation 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include "intel-platform.h" + +#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ +#define SNB_GMCH_GGMS_MASK 0x3 +#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ +#define SNB_GMCH_GMS_MASK 0x1f +#define BDW_GMCH_GGMS_SHIFT 6 +#define BDW_GMCH_GGMS_MASK 0x3 +#define BDW_GMCH_GMS_SHIFT 8 +#define BDW_GMCH_GMS_MASK 0xff + +static unsigned int gen6_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GMS_SHIFT; + gmch &=3D SNB_GMCH_GMS_MASK; + return gmch << 25; /* 32 MB units */ +} + +static unsigned int bdw_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D BDW_GMCH_GMS_SHIFT; + gmch &=3D BDW_GMCH_GMS_MASK; + return gmch << 25; /* 32 MB units */ +} + +static unsigned int chv_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GMS_SHIFT; + gmch &=3D SNB_GMCH_GMS_MASK; + + /* + * 0x0 to 0x10: 32MB increments starting at 0MB + * 0x11 to 0x16: 4MB increments starting at 8MB + * 0x17 to 0x1d: 4MB increments start at 36MB + */ + if (gmch < 0x11) + return gmch << 25; + else if (gmch < 0x17) + return (gmch - 0x11 + 2) << 22; + else + return (gmch - 0x17 + 9) << 22; +} + +static unsigned int gen9_get_stolen_size(uint16_t gmch) +{ + gmch >>=3D BDW_GMCH_GMS_SHIFT; + gmch &=3D BDW_GMCH_GMS_MASK; + + if (gmch < 0xf0) + return gmch << 25; /* 32 MB units */ + else + /* 4MB increments starting at 0xf0 for 4MB */ + return (gmch - 0xf0 + 1) << 22; +} + +static unsigned int gen6_get_gtt_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GGMS_SHIFT; + gmch &=3D SNB_GMCH_GGMS_MASK; + return gmch << 20; +} + +static unsigned int gen8_get_gtt_size(uint16_t gmch) +{ + gmch >>=3D BDW_GMCH_GGMS_SHIFT; + gmch &=3D BDW_GMCH_GGMS_MASK; + if (gmch) + gmch =3D 1 << gmch; + + return gmch << 20; +} + +static unsigned int chv_get_gtt_size(uint16_t gmch) +{ + gmch >>=3D SNB_GMCH_GGMS_SHIFT; + gmch &=3D SNB_GMCH_GGMS_MASK; + + if (gmch) + return 1 << (20 + gmch); + + return 0; +} + +static const struct intel_device_info intel_sandybridge_info =3D { + .gen =3D 6, + .platform =3D INTEL_SANDYBRIDGE, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_ivybridge_info =3D { + .gen =3D 7, + .platform =3D INTEL_IVYBRIDGE, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_valleyview_info =3D { + .gen =3D 7, + .platform =3D INTEL_VALLEYVIEW, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_haswell_info =3D { + .gen =3D 7, /* Actually HASWELL is GEN 7.5 */ + .platform =3D INTEL_HASWELL, + .gtt_entry_size =3D 4, + .get_stolen_size =3D gen6_get_stolen_size, + .get_gtt_size =3D gen6_get_gtt_size, +}; + +static const struct intel_device_info intel_broadwell_info =3D { + .gen =3D 8, + .platform =3D INTEL_BROADWELL, + .gtt_entry_size =3D 8, + .get_stolen_size =3D bdw_get_stolen_size, + .get_gtt_size =3D gen8_get_gtt_size, +}; + +static const struct intel_device_info intel_cherryview_info =3D { + .gen =3D 8, + .platform =3D INTEL_CHERRYVIEW, + .gtt_entry_size =3D 8, + .get_stolen_size =3D chv_get_stolen_size, + .get_gtt_size =3D chv_get_gtt_size, +}; + +static const struct intel_device_info intel_skylake_info =3D { + .gen =3D 9, + .platform =3D INTEL_SKYLAKE, + .gtt_entry_size =3D 8, + .get_stolen_size =3D gen9_get_stolen_size, + .get_gtt_size =3D gen8_get_gtt_size, +}; + +static const struct intel_device_info intel_broxton_info =3D { + .gen =3D 9, + .platform =3D INTEL_BROXTON, + .gtt_entry_size =3D 8, + .get_stolen_size =3D gen9_get_stolen_size, + .get_gtt_size =3D gen8_get_gtt_size, +}; + +struct intel_pci_device_id { + uint16_t device_id; + const struct intel_device_info *info; +}; + +#define INTEL_VGA_DEVICE(id, info) \ + { id, info } + +#define INTEL_SNB_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0102, info), \ + INTEL_VGA_DEVICE(0x0112, info), \ + INTEL_VGA_DEVICE(0x0122, info), \ + INTEL_VGA_DEVICE(0x010A, info) + +#define INTEL_SNB_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0106, info), \ + INTEL_VGA_DEVICE(0x0116, info), \ + INTEL_VGA_DEVICE(0x0126, info) + +#define INTEL_IVB_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ + +#define INTEL_IVB_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ + +#define INTEL_HSW_IDS(info) \ + INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ + INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ + INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ + INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ + INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ + INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ + +#define INTEL_VLV_IDS(info) \ + INTEL_VGA_DEVICE(0x0f30, info), \ + INTEL_VGA_DEVICE(0x0f31, info), \ + INTEL_VGA_DEVICE(0x0f32, info), \ + INTEL_VGA_DEVICE(0x0f33, info), \ + INTEL_VGA_DEVICE(0x0157, info), \ + INTEL_VGA_DEVICE(0x0155, info) + +#define INTEL_BDW_GT12_IDS(info) \ + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ + INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ + INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ + INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ + INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ + INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ + +#define INTEL_BDW_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ + INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ + +#define INTEL_BDW_RSVD_IDS(info) \ + INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \ + INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ + +#define INTEL_BDW_IDS(info) \ + INTEL_BDW_GT12_IDS(info), \ + INTEL_BDW_GT3_IDS(info), \ + INTEL_BDW_RSVD_IDS(info) + +#define INTEL_CHV_IDS(info) \ + INTEL_VGA_DEVICE(0x22b0, info), \ + INTEL_VGA_DEVICE(0x22b1, info), \ + INTEL_VGA_DEVICE(0x22b2, info), \ + INTEL_VGA_DEVICE(0x22b3, info) + +#define INTEL_SKL_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ + INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ + +#define INTEL_SKL_GT2_IDS(info) \ + INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ + INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ + INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ + INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ + +#define INTEL_SKL_GT3_IDS(info) \ + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x192B, info) /* Halo GT3 */ \ + +#define INTEL_SKL_GT4_IDS(info) \ + INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ + INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ + INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ + +#define INTEL_SKL_IDS(info) \ + INTEL_SKL_GT1_IDS(info), \ + INTEL_SKL_GT2_IDS(info), \ + INTEL_SKL_GT3_IDS(info), \ + INTEL_SKL_GT4_IDS(info) + +#define INTEL_BXT_IDS(info) \ + INTEL_VGA_DEVICE(0x0A84, info), \ + INTEL_VGA_DEVICE(0x1A84, info), \ + INTEL_VGA_DEVICE(0x1A85, info), \ + INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ + INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ + +static const struct intel_pci_device_id pciidlist[] =3D { + INTEL_SNB_D_IDS(&intel_sandybridge_info), + INTEL_SNB_M_IDS(&intel_sandybridge_info), + INTEL_IVB_M_IDS(&intel_ivybridge_info), + INTEL_IVB_D_IDS(&intel_ivybridge_info), + INTEL_HSW_IDS(&intel_haswell_info), + INTEL_VLV_IDS(&intel_valleyview_info), + INTEL_BDW_GT12_IDS(&intel_broadwell_info), + INTEL_BDW_GT3_IDS(&intel_broadwell_info), + INTEL_BDW_RSVD_IDS(&intel_broadwell_info), + INTEL_CHV_IDS(&intel_cherryview_info), + INTEL_SKL_GT1_IDS(&intel_skylake_info), + INTEL_SKL_GT2_IDS(&intel_skylake_info), + INTEL_SKL_GT3_IDS(&intel_skylake_info), + INTEL_SKL_GT4_IDS(&intel_skylake_info), + INTEL_BXT_IDS(&intel_broxton_info), +}; + +const struct intel_device_info *intel_get_device_info(uint16_t device_id) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(pciidlist); i++) + if (pciidlist[i].device_id =3D=3D device_id) + return pciidlist[i].info; + + return NULL; +} diff --git a/hw/vfio/intel-platform.h b/hw/vfio/intel-platform.h new file mode 100644 index 0000000..7a2655e --- /dev/null +++ b/hw/vfio/intel-platform.h @@ -0,0 +1,38 @@ +/* + * Device descriptions for Intel platforms. + * + * Copyright Intel Coporation 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#ifndef HW_VFIO_INTEL_PLATFORM_H +#define HW_VFIO_INTEL_PLATFORM_H + +#include "qemu/osdep.h" + +enum intel_platform { + INTEL_PLATFORM_UNINITIALIZED =3D 0, + INTEL_SANDYBRIDGE, + INTEL_IVYBRIDGE, + INTEL_VALLEYVIEW, + INTEL_HASWELL, + INTEL_BROADWELL, + INTEL_CHERRYVIEW, + INTEL_SKYLAKE, + INTEL_BROXTON, + INTEL_MAX_PLATFORMS +}; + +struct intel_device_info { + uint8_t gen; + enum intel_platform platform; + uint32_t gtt_entry_size; + unsigned int (*get_stolen_size)(uint16_t gmch); + unsigned int (*get_gtt_size)(uint16_t gmch); +}; + +const struct intel_device_info *intel_get_device_info(uint16_t device_id); + +#endif /* HW_VFIO_INTEL_PLATFORM_H */ diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 349085e..71360ef 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -17,6 +17,7 @@ #include "hw/nvram/fw_cfg.h" #include "pci.h" #include "trace.h" +#include "intel-platform.h" =20 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match = hw */ static bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t dev= ice) @@ -1360,6 +1361,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) *host =3D NULL, *lpc =3D NULL; VFIOQuirk *quirk; VFIOIGDQuirk *igd; + const struct intel_device_info *info; PCIDevice *lpc_bridge; int i, ret, ggms_mb, gms_mb =3D 0, gen; uint64_t *bdsm_size; @@ -1380,6 +1382,20 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) } =20 /* + * IGD is not a standard, they like to change their specs often. We + * only attempt to support back to SandBridge and we hope that newer + * devices maintain compatibility with generation 8. + */ + info =3D intel_get_device_info(vdev->device_id); + if (!info) { + error_report("IGD device %s is unsupported in legacy mode, " + "try SandyBridge or newer", vdev->vbasedev.name); + return; + } + + gen =3D info->gen; + + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not * one we can hack on, legacy mode is no-go. Sorry Q35. @@ -1394,18 +1410,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) } =20 /* - * IGD is not a standard, they like to change their specs often. We - * only attempt to support back to SandBridge and we hope that newer - * devices maintain compatibility with generation 8. - */ - gen =3D igd_gen(vdev); - if (gen !=3D 6 && gen !=3D 8) { - error_report("IGD device %s is unsupported in legacy mode, " - "try SandyBridge or newer", vdev->vbasedev.name); - return; - } - - /* * Most of what we're doing here is to enable the ROM to run, so if * there's no ROM, there's no point in setting up this quirk. * NB. We only seem to get BIOS ROMs, so a UEFI VM would need CSM supp= ort. --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496046903069652.3336978659469; Mon, 29 May 2017 01:35:03 -0700 (PDT) Received: from localhost ([::1]:47462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG8j-0006kV-O1 for importer@patchew.org; Mon, 29 May 2017 04:35:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG72-0005h1-4N for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG71-0004sm-4k for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:16 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG70-0004sQ-SZ for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:15 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:13 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607766" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:32 +0800 Message-Id: <1496079043-26694-3-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 2/6] vfio: Setup IGD quirks earlier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Initialize IGD quirks a bit earlier since we're going to support IGD stolen memory under both primary mode (legacy mode) and secondary mode and we need one extra memory region from IGD quirks. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 71360ef..e0a0c13 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1395,6 +1395,14 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) =20 gen =3D info->gen; =20 + /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ + quirk =3D g_malloc0(sizeof(*quirk)); + igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); + igd->vdev =3D vdev; + igd->index =3D ~0; + igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); + igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not @@ -1502,23 +1510,19 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice= *vdev, int nr) goto out; } =20 - /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ - quirk =3D g_malloc0(sizeof(*quirk)); - quirk->mem =3D g_new0(MemoryRegion, 2); - quirk->nr_mem =3D 2; - igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); - igd->vdev =3D vdev; - igd->index =3D ~0; - igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); - igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ + quirk->mem =3D g_renew(MemoryRegion, quirk->mem, 2); + + memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), + &vfio_igd_index_quirk, igd, "vfio-igd-index-quir= k", + 4); =20 - memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_qu= irk, - igd, "vfio-igd-index-quirk", 4); memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 0, &quirk->mem[0], 1); =20 - memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_igd_data_qui= rk, - igd, "vfio-igd-data-quirk", 4); + memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), + &vfio_igd_data_quirk, igd, "vfio-igd-data-quirk", + 4); + memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 4, &quirk->mem[1], 1); =20 --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047271073761.1529923340478; Mon, 29 May 2017 01:41:11 -0700 (PDT) Received: from localhost ([::1]:47491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGEf-0003Hy-N5 for importer@patchew.org; Mon, 29 May 2017 04:41:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7F-0005pL-M6 for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG7E-00052P-M0 for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:29 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG7E-0004sQ-DI for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:28 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:28 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607908" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:39 +0800 Message-Id: <1496079043-26694-10-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 2/6] vfio: Setup IGD quirks earlier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Initialize IGD quirks a bit earlier since we're going to support IGD stolen memory under both primary mode (legacy mode) and secondary mode and we need one extra memory region from IGD quirks. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 71360ef..e0a0c13 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1395,6 +1395,14 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) =20 gen =3D info->gen; =20 + /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ + quirk =3D g_malloc0(sizeof(*quirk)); + igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); + igd->vdev =3D vdev; + igd->index =3D ~0; + igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); + igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not @@ -1502,23 +1510,19 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice= *vdev, int nr) goto out; } =20 - /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ - quirk =3D g_malloc0(sizeof(*quirk)); - quirk->mem =3D g_new0(MemoryRegion, 2); - quirk->nr_mem =3D 2; - igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); - igd->vdev =3D vdev; - igd->index =3D ~0; - igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); - igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ + quirk->mem =3D g_renew(MemoryRegion, quirk->mem, 2); + + memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), + &vfio_igd_index_quirk, igd, "vfio-igd-index-quir= k", + 4); =20 - memory_region_init_io(&quirk->mem[0], OBJECT(vdev), &vfio_igd_index_qu= irk, - igd, "vfio-igd-index-quirk", 4); memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 0, &quirk->mem[0], 1); =20 - memory_region_init_io(&quirk->mem[1], OBJECT(vdev), &vfio_igd_data_qui= rk, - igd, "vfio-igd-data-quirk", 4); + memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), + &vfio_igd_data_quirk, igd, "vfio-igd-data-quirk", + 4); + memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 4, &quirk->mem[1], 1); =20 --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047033641867.358278935109; Mon, 29 May 2017 01:37:13 -0700 (PDT) Received: from localhost ([::1]:47474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGAo-0008Mp-QZ for importer@patchew.org; Mon, 29 May 2017 04:37:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG73-0005hA-KT for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG72-0004uy-IS for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:17 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG72-0004sQ-6C for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:16 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:15 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607784" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:33 +0800 Message-Id: <1496079043-26694-4-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 3/6] vfio: Setup IGD stolen memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We still keep using VM dedicated memory for isolation to support IGD stolen in the guest. Becuase of the PA of the stolen memory can not be moved after the system is powered-up, we wish the PA of the guest stolen memory can sit in the same PA of host. A new memory region is allocated, and the memory region will be marked as reserved in guest E820 table. We don't need to take care of GGMS, as the accesses to GGMS from HW bypass IOMMU. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 83 ++++++++++++++++++------------------------------= ---- 1 file changed, 29 insertions(+), 54 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index e0a0c13..5a083c1 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -18,6 +18,7 @@ #include "pci.h" #include "trace.h" #include "intel-platform.h" +#include "hw/i386/pc.h" =20 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match = hw */ static bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t dev= ice) @@ -1362,9 +1363,10 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) VFIOQuirk *quirk; VFIOIGDQuirk *igd; const struct intel_device_info *info; + void *stolen; PCIDevice *lpc_bridge; - int i, ret, ggms_mb, gms_mb =3D 0, gen; - uint64_t *bdsm_size; + int i, ret; + uint64_t bdsm_size; uint32_t gmch; uint16_t cmd_orig, cmd; Error *err =3D NULL; @@ -1393,16 +1395,38 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice= *vdev, int nr) return; } =20 - gen =3D info->gen; - /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ quirk =3D g_malloc0(sizeof(*quirk)); + quirk->mem =3D g_new0(MemoryRegion, 1); + quirk->nr_mem =3D 1; + igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); igd->vdev =3D vdev; igd->index =3D ~0; igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ =20 + /* Setup stolen memory for IGD device. */ + gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); + bdsm_size =3D info->get_stolen_size(gmch); + + stolen =3D qemu_memalign(bdsm_size, bdsm_size); + + memory_region_init_ram_ptr(&quirk->mem[0], OBJECT(vdev), + "vfio-igd-stolen", bdsm_size, stolen); + memory_region_add_subregion_overlap(get_system_memory(), + igd->bdsm, &quirk->mem[0], 1); + + e820_add_entry(igd->bdsm, bdsm_size, E820_RESERVED); + + /* GMCH is read-only, emulated */ + pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); + pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); + + /* BDSM is read-only, emulated */ + pci_set_long(vdev->pdev.wmask + IGD_BDSM, 0); + pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not @@ -1472,8 +1496,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) goto out; } =20 - gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); - /* * If IGD VGA Disable is clear (expected) and VGA is not already enabl= ed, * try to enable it. Probably shouldn't be using legacy mode without = VGA, @@ -1528,53 +1550,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) =20 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); =20 - /* Determine the size of stolen memory needed for GTT */ - ggms_mb =3D (gmch >> (gen < 8 ? 8 : 6)) & 0x3; - if (gen > 6) { - ggms_mb =3D 1 << ggms_mb; - } - - /* - * Assume we have no GMS memory, but allow it to be overrided by device - * option (experimental). The spec doesn't actually allow zero GMS wh= en - * when IVD (IGD VGA Disable) is clear, but the claim is that it's unu= sed, - * so let's not waste VM memory for it. - */ - gmch &=3D ~((gen < 8 ? 0x1f : 0xff) << (gen < 8 ? 3 : 8)); - - if (vdev->igd_gms) { - if (vdev->igd_gms <=3D 0x10) { - gms_mb =3D vdev->igd_gms * 32; - gmch |=3D vdev->igd_gms << (gen < 8 ? 3 : 8); - } else { - error_report("Unsupported IGD GMS value 0x%x", vdev->igd_gms); - vdev->igd_gms =3D 0; - } - } - - /* - * Request reserved memory for stolen memory via fw_cfg. VM firmware - * must allocate a 1MB aligned reserved memory region below 4GB with - * the requested size (in bytes) for use by the Intel PCI class VGA - * device at VM address 00:02.0. The base address of this reserved - * memory region must be written to the device BDSM regsiter at PCI - * config offset 0x5C. - */ - bdsm_size =3D g_malloc(sizeof(*bdsm_size)); - *bdsm_size =3D cpu_to_le64((ggms_mb + gms_mb) * 1024 * 1024); - fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", - bdsm_size, sizeof(*bdsm_size)); - - /* GMCH is read-only, emulated */ - pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); - pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); - pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); - - /* BDSM is read-write, emulated. The BIOS needs to be able to write i= t */ - pci_set_long(vdev->pdev.config + IGD_BDSM, 0); - pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); - pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); - /* * This IOBAR gives us access to GTTADR, which allows us to write to * the GTT itself. So let's go ahead and write zero to all the GTT @@ -1606,7 +1581,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) vdev->vbasedev.name); } =20 - trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, ggms_mb + gms_mb); + trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, bdsm_size >> 20); =20 out: g_free(rom); --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047161633995.3975946431515; Mon, 29 May 2017 01:39:21 -0700 (PDT) Received: from localhost ([::1]:47482 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGCt-0001lg-UV for importer@patchew.org; Mon, 29 May 2017 04:39:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7K-0005sv-3F for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG7G-000563-VV for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:34 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG7G-0004sQ-KH for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:30 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:30 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607926" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:40 +0800 Message-Id: <1496079043-26694-11-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 3/6] vfio: Setup IGD stolen memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We still keep using VM dedicated memory for isolation to support IGD stolen in the guest. Becuase of the PA of the stolen memory can not be moved after the system is powered-up, we wish the PA of the guest stolen memory can sit in the same PA of host. A new memory region is allocated, and the memory region will be marked as reserved in guest E820 table. We don't need to take care of GGMS, as the accesses to GGMS from HW bypass IOMMU. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 83 ++++++++++++++++++------------------------------= ---- 1 file changed, 29 insertions(+), 54 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index e0a0c13..5a083c1 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -18,6 +18,7 @@ #include "pci.h" #include "trace.h" #include "intel-platform.h" +#include "hw/i386/pc.h" =20 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match = hw */ static bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t dev= ice) @@ -1362,9 +1363,10 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) VFIOQuirk *quirk; VFIOIGDQuirk *igd; const struct intel_device_info *info; + void *stolen; PCIDevice *lpc_bridge; - int i, ret, ggms_mb, gms_mb =3D 0, gen; - uint64_t *bdsm_size; + int i, ret; + uint64_t bdsm_size; uint32_t gmch; uint16_t cmd_orig, cmd; Error *err =3D NULL; @@ -1393,16 +1395,38 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice= *vdev, int nr) return; } =20 - gen =3D info->gen; - /* Setup our quirk to munge GTT addresses to the VM allocated buffer */ quirk =3D g_malloc0(sizeof(*quirk)); + quirk->mem =3D g_new0(MemoryRegion, 1); + quirk->nr_mem =3D 1; + igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); igd->vdev =3D vdev; igd->index =3D ~0; igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ =20 + /* Setup stolen memory for IGD device. */ + gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); + bdsm_size =3D info->get_stolen_size(gmch); + + stolen =3D qemu_memalign(bdsm_size, bdsm_size); + + memory_region_init_ram_ptr(&quirk->mem[0], OBJECT(vdev), + "vfio-igd-stolen", bdsm_size, stolen); + memory_region_add_subregion_overlap(get_system_memory(), + igd->bdsm, &quirk->mem[0], 1); + + e820_add_entry(igd->bdsm, bdsm_size, E820_RESERVED); + + /* GMCH is read-only, emulated */ + pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); + pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); + + /* BDSM is read-only, emulated */ + pci_set_long(vdev->pdev.wmask + IGD_BDSM, 0); + pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not @@ -1472,8 +1496,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) goto out; } =20 - gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); - /* * If IGD VGA Disable is clear (expected) and VGA is not already enabl= ed, * try to enable it. Probably shouldn't be using legacy mode without = VGA, @@ -1528,53 +1550,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) =20 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); =20 - /* Determine the size of stolen memory needed for GTT */ - ggms_mb =3D (gmch >> (gen < 8 ? 8 : 6)) & 0x3; - if (gen > 6) { - ggms_mb =3D 1 << ggms_mb; - } - - /* - * Assume we have no GMS memory, but allow it to be overrided by device - * option (experimental). The spec doesn't actually allow zero GMS wh= en - * when IVD (IGD VGA Disable) is clear, but the claim is that it's unu= sed, - * so let's not waste VM memory for it. - */ - gmch &=3D ~((gen < 8 ? 0x1f : 0xff) << (gen < 8 ? 3 : 8)); - - if (vdev->igd_gms) { - if (vdev->igd_gms <=3D 0x10) { - gms_mb =3D vdev->igd_gms * 32; - gmch |=3D vdev->igd_gms << (gen < 8 ? 3 : 8); - } else { - error_report("Unsupported IGD GMS value 0x%x", vdev->igd_gms); - vdev->igd_gms =3D 0; - } - } - - /* - * Request reserved memory for stolen memory via fw_cfg. VM firmware - * must allocate a 1MB aligned reserved memory region below 4GB with - * the requested size (in bytes) for use by the Intel PCI class VGA - * device at VM address 00:02.0. The base address of this reserved - * memory region must be written to the device BDSM regsiter at PCI - * config offset 0x5C. - */ - bdsm_size =3D g_malloc(sizeof(*bdsm_size)); - *bdsm_size =3D cpu_to_le64((ggms_mb + gms_mb) * 1024 * 1024); - fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", - bdsm_size, sizeof(*bdsm_size)); - - /* GMCH is read-only, emulated */ - pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); - pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); - pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); - - /* BDSM is read-write, emulated. The BIOS needs to be able to write i= t */ - pci_set_long(vdev->pdev.config + IGD_BDSM, 0); - pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); - pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); - /* * This IOBAR gives us access to GTTADR, which allows us to write to * the GTT itself. So let's go ahead and write zero to all the GTT @@ -1606,7 +1581,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) vdev->vbasedev.name); } =20 - trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, ggms_mb + gms_mb); + trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, bdsm_size >> 20); =20 out: g_free(rom); --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047032996854.530588492677; Mon, 29 May 2017 01:37:12 -0700 (PDT) Received: from localhost ([::1]:47475 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGAp-0008NQ-Gd for importer@patchew.org; Mon, 29 May 2017 04:37:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57040) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG75-0005iT-5w for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG74-0004wn-Fs for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:19 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG74-0004sQ-6B for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:18 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:17 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607814" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:34 +0800 Message-Id: <1496079043-26694-5-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 4/6] vfio: Refine GGTT clearing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Clear the whole GGTT page tables after the quirk is initialized. Obtain the total size of GGTT and the entry size of one GGTT entry from intel_device_info(). Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 5a083c1..618c43c 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1365,7 +1365,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) const struct intel_device_info *info; void *stolen; PCIDevice *lpc_bridge; - int i, ret; + int i, j, ret; uint64_t bdsm_size; uint32_t gmch; uint16_t cmd_orig, cmd; @@ -1570,9 +1570,11 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) vdev->vbasedev.name); } =20 - for (i =3D 1; i < vfio_igd_gtt_max(vdev); i +=3D 4) { - vfio_region_write(&vdev->bars[4].region, 0, i, 4); - vfio_region_write(&vdev->bars[4].region, 4, 0, 4); + for (i =3D 1; i < info->get_gtt_size(gmch); i +=3D info->gtt_entry_siz= e) { + for (j =3D 0; j < info->gtt_entry_size; j +=3D 4) { + vfio_region_write(&vdev->bars[4].region, 0, i + j, 4); + vfio_region_write(&vdev->bars[4].region, 4, 0, 4); + } } =20 if (pwrite(vdev->vbasedev.fd, &cmd_orig, sizeof(cmd_orig), --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047277898261.6453726368276; Mon, 29 May 2017 01:41:17 -0700 (PDT) Received: from localhost ([::1]:47493 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGEm-0003O7-GE for importer@patchew.org; Mon, 29 May 2017 04:41:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7K-0005sy-3U for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG7J-00059Y-5h for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:34 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG7I-0004sQ-S3 for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:33 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:32 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607942" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:41 +0800 Message-Id: <1496079043-26694-12-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 4/6] vfio: Refine GGTT clearing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Clear the whole GGTT page tables after the quirk is initialized. Obtain the total size of GGTT and the entry size of one GGTT entry from intel_device_info(). Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 5a083c1..618c43c 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1365,7 +1365,7 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *= vdev, int nr) const struct intel_device_info *info; void *stolen; PCIDevice *lpc_bridge; - int i, ret; + int i, j, ret; uint64_t bdsm_size; uint32_t gmch; uint16_t cmd_orig, cmd; @@ -1570,9 +1570,11 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) vdev->vbasedev.name); } =20 - for (i =3D 1; i < vfio_igd_gtt_max(vdev); i +=3D 4) { - vfio_region_write(&vdev->bars[4].region, 0, i, 4); - vfio_region_write(&vdev->bars[4].region, 4, 0, 4); + for (i =3D 1; i < info->get_gtt_size(gmch); i +=3D info->gtt_entry_siz= e) { + for (j =3D 0; j < info->gtt_entry_size; j +=3D 4) { + vfio_region_write(&vdev->bars[4].region, 0, i + j, 4); + vfio_region_write(&vdev->bars[4].region, 4, 0, 4); + } } =20 if (pwrite(vdev->vbasedev.fd, &cmd_orig, sizeof(cmd_orig), --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047155865645.0315667590653; Mon, 29 May 2017 01:39:15 -0700 (PDT) Received: from localhost ([::1]:47481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGCo-0001hI-AA for importer@patchew.org; Mon, 29 May 2017 04:39:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57060) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG78-0005lF-5Z for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG76-0004yH-IQ for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:22 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG76-0004sQ-6b for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:20 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:19 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607835" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:35 +0800 Message-Id: <1496079043-26694-6-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 5/6] vfio: Remove extra quirks and old definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove extra quirks, old definitions and functions. Once the new Intel platform definition is introduced, and the PA of guest stolen memory equals to the PA of host stolen memory, they are not necessary anymore. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 209 ++---------------------------------------------= ---- 1 file changed, 7 insertions(+), 202 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 618c43c..abfcec6 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -997,55 +997,6 @@ static void vfio_probe_rtl8168_bar2_quirk(VFIOPCIDevic= e *vdev, int nr) * headless setup is desired, the OpRegion gets in the way of that. */ =20 -/* - * This presumes the device is already known to be an Intel VGA device, so= we - * take liberties in which device ID bits match which generation. This sh= ould - * not be taken as an indication that all the devices are supported, or ev= en - * supportable, some of them don't even support VT-d. - * See linux:include/drm/i915_pciids.h for IDs. - */ -static int igd_gen(VFIOPCIDevice *vdev) -{ - if ((vdev->device_id & 0xfff) =3D=3D 0xa84) { - return 8; /* Broxton */ - } - - switch (vdev->device_id & 0xff00) { - /* Old, untested, unavailable, unknown */ - case 0x0000: - case 0x2500: - case 0x2700: - case 0x2900: - case 0x2a00: - case 0x2e00: - case 0x3500: - case 0xa000: - return -1; - /* SandyBridge, IvyBridge, ValleyView, Haswell */ - case 0x0100: - case 0x0400: - case 0x0a00: - case 0x0c00: - case 0x0d00: - case 0x0f00: - return 6; - /* BroadWell, CherryView, SkyLake, KabyLake */ - case 0x1600: - case 0x1900: - case 0x2200: - case 0x5900: - return 8; - } - - return 8; /* Assume newer is compatible */ -} - -typedef struct VFIOIGDQuirk { - struct VFIOPCIDevice *vdev; - uint32_t index; - uint32_t bdsm; -} VFIOIGDQuirk; - #define IGD_GMCH 0x50 /* Graphics Control Register */ #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ #define IGD_ASLS 0xfc /* ASL Storage Register */ @@ -1230,144 +1181,17 @@ static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vd= ev, return ret; } =20 -/* - * IGD Gen8 and newer support up to 8MB for the GTT and use a 64bit PTE - * entry, older IGDs use 2MB and 32bit. Each PTE maps a 4k page. Therefo= re - * we either have 2M/4k * 4 =3D 2k or 8M/4k * 8 =3D 16k as the maximum iob= ar index - * for programming the GTT. - * - * See linux:include/drm/i915_drm.h for shift and mask values. - */ -static int vfio_igd_gtt_max(VFIOPCIDevice *vdev) -{ - uint32_t gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(g= mch)); - int ggms, gen =3D igd_gen(vdev); - - gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(gmch)); - ggms =3D (gmch >> (gen < 8 ? 8 : 6)) & 0x3; - if (gen > 6) { - ggms =3D 1 << ggms; - } - - ggms *=3D 1024 * 1024; - - return (ggms / (4 * 1024)) * (gen < 8 ? 4 : 8); -} - -/* - * The IGD ROM will make use of stolen memory (GGMS) for support of VESA m= odes. - * Somehow the host stolen memory range is used for this, but how the ROM = gets - * it is a mystery, perhaps it's hardcoded into the ROM. Thankfully thoug= h, it - * reprograms the GTT through the IOBAR where we can trap it and transpose= the - * programming to the VM allocated buffer. That buffer gets reserved by t= he VM - * firmware via the fw_cfg entry added below. Here we're just monitoring = the - * IOBAR address and data registers to detect a write sequence targeting t= he - * GTTADR. This code is developed by observed behavior and doesn't have a - * direct spec reference, unfortunately. - */ -static uint64_t vfio_igd_quirk_data_read(void *opaque, - hwaddr addr, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D ~0; - - return vfio_region_read(&vdev->bars[4].region, addr + 4, size); -} - -static void vfio_igd_quirk_data_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - uint64_t val =3D data; - int gen =3D igd_gen(vdev); - - /* - * Programming the GGMS starts at index 0x1 and uses every 4th index (= ie. - * 0x1, 0x5, 0x9, 0xd,...). For pre-Gen8 each 4-byte write is a whole= PTE - * entry, with 0th bit enable set. For Gen8 and up, PTEs are 64bit, so - * entries 0x5 & 0xd are the high dword, in our case zero. Each PTE p= oints - * to a 4k page, which we translate to a page from the VM allocated re= gion, - * pointed to by the BDSM register. If this is not set, we fail. - * - * We trap writes to the full configured GTT size, but we typically on= ly - * see the vBIOS writing up to (nearly) the 1MB barrier. In fact it o= ften - * seems to miss the last entry for an even 1MB GTT. Doing a gratuito= us - * write of that last entry does work, but is hopefully unnecessary si= nce - * we clear the previous GTT on initialization. - */ - if ((igd->index % 4 =3D=3D 1) && igd->index < vfio_igd_gtt_max(vdev)) { - if (gen < 8 || (igd->index % 8 =3D=3D 1)) { - uint32_t base; - - base =3D pci_get_long(vdev->pdev.config + IGD_BDSM); - if (!base) { - hw_error("vfio-igd: Guest attempted to program IGD GTT bef= ore " - "BIOS reserved stolen memory. Unsupported BIOS?"= ); - } - - val =3D data - igd->bdsm + base; - } else { - val =3D 0; /* upper 32bits of pte, we only enable below 4G PTE= s */ - } - - trace_vfio_pci_igd_bar4_write(vdev->vbasedev.name, - igd->index, data, val); - } - - vfio_region_write(&vdev->bars[4].region, addr + 4, val, size); - - igd->index =3D ~0; -} - -static const MemoryRegionOps vfio_igd_data_quirk =3D { - .read =3D vfio_igd_quirk_data_read, - .write =3D vfio_igd_quirk_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static uint64_t vfio_igd_quirk_index_read(void *opaque, - hwaddr addr, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D ~0; - - return vfio_region_read(&vdev->bars[4].region, addr, size); -} - -static void vfio_igd_quirk_index_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D data; - - vfio_region_write(&vdev->bars[4].region, addr, data, size); -} - -static const MemoryRegionOps vfio_igd_index_quirk =3D { - .read =3D vfio_igd_quirk_index_read, - .write =3D vfio_igd_quirk_index_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr) { struct vfio_region_info *rom =3D NULL, *opregion =3D NULL, *host =3D NULL, *lpc =3D NULL; VFIOQuirk *quirk; - VFIOIGDQuirk *igd; const struct intel_device_info *info; void *stolen; PCIDevice *lpc_bridge; int i, j, ret; uint64_t bdsm_size; - uint32_t gmch; + uint32_t gmch, bdsm_base; uint16_t cmd_orig, cmd; Error *err =3D NULL; =20 @@ -1400,11 +1224,8 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) quirk->mem =3D g_new0(MemoryRegion, 1); quirk->nr_mem =3D 1; =20 - igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); - igd->vdev =3D vdev; - igd->index =3D ~0; - igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); - igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ + bdsm_base =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); + bdsm_base &=3D ~((1 << 20) - 1); /* 1MB aligned */ =20 /* Setup stolen memory for IGD device. */ gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); @@ -1415,9 +1236,11 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) memory_region_init_ram_ptr(&quirk->mem[0], OBJECT(vdev), "vfio-igd-stolen", bdsm_size, stolen); memory_region_add_subregion_overlap(get_system_memory(), - igd->bdsm, &quirk->mem[0], 1); + bdsm_base, &quirk->mem[0], 1); + + e820_add_entry(bdsm_base, bdsm_size, E820_RESERVED); =20 - e820_add_entry(igd->bdsm, bdsm_size, E820_RESERVED); + QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); =20 /* GMCH is read-only, emulated */ pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); @@ -1532,24 +1355,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) goto out; } =20 - quirk->mem =3D g_renew(MemoryRegion, quirk->mem, 2); - - memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), - &vfio_igd_index_quirk, igd, "vfio-igd-index-quir= k", - 4); - - memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, - 0, &quirk->mem[0], 1); - - memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), - &vfio_igd_data_quirk, igd, "vfio-igd-data-quirk", - 4); - - memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, - 4, &quirk->mem[1], 1); - - QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); - /* * This IOBAR gives us access to GTTADR, which allows us to write to * the GTT itself. So let's go ahead and write zero to all the GTT --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047454625889.5483067242111; Mon, 29 May 2017 01:44:14 -0700 (PDT) Received: from localhost ([::1]:47508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGHd-0005ia-8p for importer@patchew.org; Mon, 29 May 2017 04:44:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7Q-0005xS-0P for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG7L-0005Ds-D5 for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:40 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG7L-0004sQ-2x for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:35 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:34 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607959" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:42 +0800 Message-Id: <1496079043-26694-13-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 5/6] vfio: Remove extra quirks and old definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove extra quirks, old definitions and functions. Once the new Intel platform definition is introduced, and the PA of guest stolen memory equals to the PA of host stolen memory, they are not necessary anymore. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 209 ++---------------------------------------------= ---- 1 file changed, 7 insertions(+), 202 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 618c43c..abfcec6 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -997,55 +997,6 @@ static void vfio_probe_rtl8168_bar2_quirk(VFIOPCIDevic= e *vdev, int nr) * headless setup is desired, the OpRegion gets in the way of that. */ =20 -/* - * This presumes the device is already known to be an Intel VGA device, so= we - * take liberties in which device ID bits match which generation. This sh= ould - * not be taken as an indication that all the devices are supported, or ev= en - * supportable, some of them don't even support VT-d. - * See linux:include/drm/i915_pciids.h for IDs. - */ -static int igd_gen(VFIOPCIDevice *vdev) -{ - if ((vdev->device_id & 0xfff) =3D=3D 0xa84) { - return 8; /* Broxton */ - } - - switch (vdev->device_id & 0xff00) { - /* Old, untested, unavailable, unknown */ - case 0x0000: - case 0x2500: - case 0x2700: - case 0x2900: - case 0x2a00: - case 0x2e00: - case 0x3500: - case 0xa000: - return -1; - /* SandyBridge, IvyBridge, ValleyView, Haswell */ - case 0x0100: - case 0x0400: - case 0x0a00: - case 0x0c00: - case 0x0d00: - case 0x0f00: - return 6; - /* BroadWell, CherryView, SkyLake, KabyLake */ - case 0x1600: - case 0x1900: - case 0x2200: - case 0x5900: - return 8; - } - - return 8; /* Assume newer is compatible */ -} - -typedef struct VFIOIGDQuirk { - struct VFIOPCIDevice *vdev; - uint32_t index; - uint32_t bdsm; -} VFIOIGDQuirk; - #define IGD_GMCH 0x50 /* Graphics Control Register */ #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ #define IGD_ASLS 0xfc /* ASL Storage Register */ @@ -1230,144 +1181,17 @@ static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vd= ev, return ret; } =20 -/* - * IGD Gen8 and newer support up to 8MB for the GTT and use a 64bit PTE - * entry, older IGDs use 2MB and 32bit. Each PTE maps a 4k page. Therefo= re - * we either have 2M/4k * 4 =3D 2k or 8M/4k * 8 =3D 16k as the maximum iob= ar index - * for programming the GTT. - * - * See linux:include/drm/i915_drm.h for shift and mask values. - */ -static int vfio_igd_gtt_max(VFIOPCIDevice *vdev) -{ - uint32_t gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(g= mch)); - int ggms, gen =3D igd_gen(vdev); - - gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, sizeof(gmch)); - ggms =3D (gmch >> (gen < 8 ? 8 : 6)) & 0x3; - if (gen > 6) { - ggms =3D 1 << ggms; - } - - ggms *=3D 1024 * 1024; - - return (ggms / (4 * 1024)) * (gen < 8 ? 4 : 8); -} - -/* - * The IGD ROM will make use of stolen memory (GGMS) for support of VESA m= odes. - * Somehow the host stolen memory range is used for this, but how the ROM = gets - * it is a mystery, perhaps it's hardcoded into the ROM. Thankfully thoug= h, it - * reprograms the GTT through the IOBAR where we can trap it and transpose= the - * programming to the VM allocated buffer. That buffer gets reserved by t= he VM - * firmware via the fw_cfg entry added below. Here we're just monitoring = the - * IOBAR address and data registers to detect a write sequence targeting t= he - * GTTADR. This code is developed by observed behavior and doesn't have a - * direct spec reference, unfortunately. - */ -static uint64_t vfio_igd_quirk_data_read(void *opaque, - hwaddr addr, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D ~0; - - return vfio_region_read(&vdev->bars[4].region, addr + 4, size); -} - -static void vfio_igd_quirk_data_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - uint64_t val =3D data; - int gen =3D igd_gen(vdev); - - /* - * Programming the GGMS starts at index 0x1 and uses every 4th index (= ie. - * 0x1, 0x5, 0x9, 0xd,...). For pre-Gen8 each 4-byte write is a whole= PTE - * entry, with 0th bit enable set. For Gen8 and up, PTEs are 64bit, so - * entries 0x5 & 0xd are the high dword, in our case zero. Each PTE p= oints - * to a 4k page, which we translate to a page from the VM allocated re= gion, - * pointed to by the BDSM register. If this is not set, we fail. - * - * We trap writes to the full configured GTT size, but we typically on= ly - * see the vBIOS writing up to (nearly) the 1MB barrier. In fact it o= ften - * seems to miss the last entry for an even 1MB GTT. Doing a gratuito= us - * write of that last entry does work, but is hopefully unnecessary si= nce - * we clear the previous GTT on initialization. - */ - if ((igd->index % 4 =3D=3D 1) && igd->index < vfio_igd_gtt_max(vdev)) { - if (gen < 8 || (igd->index % 8 =3D=3D 1)) { - uint32_t base; - - base =3D pci_get_long(vdev->pdev.config + IGD_BDSM); - if (!base) { - hw_error("vfio-igd: Guest attempted to program IGD GTT bef= ore " - "BIOS reserved stolen memory. Unsupported BIOS?"= ); - } - - val =3D data - igd->bdsm + base; - } else { - val =3D 0; /* upper 32bits of pte, we only enable below 4G PTE= s */ - } - - trace_vfio_pci_igd_bar4_write(vdev->vbasedev.name, - igd->index, data, val); - } - - vfio_region_write(&vdev->bars[4].region, addr + 4, val, size); - - igd->index =3D ~0; -} - -static const MemoryRegionOps vfio_igd_data_quirk =3D { - .read =3D vfio_igd_quirk_data_read, - .write =3D vfio_igd_quirk_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static uint64_t vfio_igd_quirk_index_read(void *opaque, - hwaddr addr, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D ~0; - - return vfio_region_read(&vdev->bars[4].region, addr, size); -} - -static void vfio_igd_quirk_index_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - VFIOIGDQuirk *igd =3D opaque; - VFIOPCIDevice *vdev =3D igd->vdev; - - igd->index =3D data; - - vfio_region_write(&vdev->bars[4].region, addr, data, size); -} - -static const MemoryRegionOps vfio_igd_index_quirk =3D { - .read =3D vfio_igd_quirk_index_read, - .write =3D vfio_igd_quirk_index_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr) { struct vfio_region_info *rom =3D NULL, *opregion =3D NULL, *host =3D NULL, *lpc =3D NULL; VFIOQuirk *quirk; - VFIOIGDQuirk *igd; const struct intel_device_info *info; void *stolen; PCIDevice *lpc_bridge; int i, j, ret; uint64_t bdsm_size; - uint32_t gmch; + uint32_t gmch, bdsm_base; uint16_t cmd_orig, cmd; Error *err =3D NULL; =20 @@ -1400,11 +1224,8 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) quirk->mem =3D g_new0(MemoryRegion, 1); quirk->nr_mem =3D 1; =20 - igd =3D quirk->data =3D g_malloc0(sizeof(*igd)); - igd->vdev =3D vdev; - igd->index =3D ~0; - igd->bdsm =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); - igd->bdsm &=3D ~((1 << 20) - 1); /* 1MB aligned */ + bdsm_base =3D vfio_pci_read_config(&vdev->pdev, IGD_BDSM, 4); + bdsm_base &=3D ~((1 << 20) - 1); /* 1MB aligned */ =20 /* Setup stolen memory for IGD device. */ gmch =3D vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); @@ -1415,9 +1236,11 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) memory_region_init_ram_ptr(&quirk->mem[0], OBJECT(vdev), "vfio-igd-stolen", bdsm_size, stolen); memory_region_add_subregion_overlap(get_system_memory(), - igd->bdsm, &quirk->mem[0], 1); + bdsm_base, &quirk->mem[0], 1); + + e820_add_entry(bdsm_base, bdsm_size, E820_RESERVED); =20 - e820_add_entry(igd->bdsm, bdsm_size, E820_RESERVED); + QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); =20 /* GMCH is read-only, emulated */ pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); @@ -1532,24 +1355,6 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) goto out; } =20 - quirk->mem =3D g_renew(MemoryRegion, quirk->mem, 2); - - memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), - &vfio_igd_index_quirk, igd, "vfio-igd-index-quir= k", - 4); - - memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, - 0, &quirk->mem[0], 1); - - memory_region_init_io(&quirk->mem[quirk->nr_mem++], OBJECT(vdev), - &vfio_igd_data_quirk, igd, "vfio-igd-data-quirk", - 4); - - memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, - 4, &quirk->mem[1], 1); - - QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); - /* * This IOBAR gives us access to GTTADR, which allows us to write to * the GTT itself. So let's go ahead and write zero to all the GTT --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047272233641.9910370393961; Mon, 29 May 2017 01:41:12 -0700 (PDT) Received: from localhost ([::1]:47492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGEg-0003JP-P1 for importer@patchew.org; Mon, 29 May 2017 04:41:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57076) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7B-0005mu-Di for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG78-0004zM-Hr for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:25 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG78-0004sQ-9J for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:22 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:21 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607867" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:36 +0800 Message-Id: <1496079043-26694-7-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 6/6] vfio: Setup IGD stolen memory under secondary mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also setup IGD stolen memory under secondary mode as some HW functions might need the stolen memory anyway. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index abfcec6..6ddb59a 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1196,16 +1196,11 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice= *vdev, int nr) Error *err =3D NULL; =20 /* - * This must be an Intel VGA device at address 00:02.0 for us to even - * consider enabling legacy mode. The vBIOS has dependencies on the - * PCI bus address. + * This must be an Intel VGA device. */ if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || - !vfio_is_vga(vdev) || nr !=3D 4 || - &vdev->pdev !=3D pci_find_device(pci_device_root_bus(&vdev->pdev), - 0, PCI_DEVFN(0x2, 0))) { + !vfio_is_vga(vdev) || nr !=3D 4) return; - } =20 /* * IGD is not a standard, they like to change their specs often. We @@ -1251,6 +1246,15 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); =20 /* + * This must be an Intel VGA device at address 00:02.0 for us to even + * consider enabling legacy mode. The vBIOS has dependencies on the + * PCI bus address. + */ + if (&vdev->pdev !=3D pci_find_device(pci_device_root_bus(&vdev->pdev), + 0, PCI_DEVFN(0x2, 0))) + return; + + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not * one we can hack on, legacy mode is no-go. Sorry Q35. --=20 2.7.4 From nobody Sun Apr 28 21:33:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1496047377958834.2487979310423; Mon, 29 May 2017 01:42:57 -0700 (PDT) Received: from localhost ([::1]:47501 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFGGO-0004oj-9a for importer@patchew.org; Mon, 29 May 2017 04:42:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFG7O-0005vt-86 for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFG7N-0005HS-9Z for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:38 -0400 Received: from mga02.intel.com ([134.134.136.20]:12385) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFG7N-0004sQ-0M for qemu-devel@nongnu.org; Mon, 29 May 2017 04:33:37 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2017 01:33:36 -0700 Received: from inno-nuc.bj.intel.com ([10.238.154.169]) by fmsmga004.fm.intel.com with ESMTP; 29 May 2017 01:33:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,413,1491289200"; d="scan'208";a="267607968" From: Zhi Wang To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 01:30:43 +0800 Message-Id: <1496079043-26694-14-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> References: <1496079043-26694-1-git-send-email-zhi.a.wang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [RFC 6/6] vfio: Setup IGD stolen memory under secondary mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, daniel.vetter@ffwll.ch, joonas.lahtinen@linux.intel.com, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, chuanxiao.dong@intel.com, xiong.y.zhang@intel.com, Zhi Wang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also setup IGD stolen memory under secondary mode as some HW functions might need the stolen memory anyway. Suggested-by: Xiong Zhang Signed-off-by: Zhi Wang --- hw/vfio/pci-quirks.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index abfcec6..6ddb59a 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1196,16 +1196,11 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice= *vdev, int nr) Error *err =3D NULL; =20 /* - * This must be an Intel VGA device at address 00:02.0 for us to even - * consider enabling legacy mode. The vBIOS has dependencies on the - * PCI bus address. + * This must be an Intel VGA device. */ if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || - !vfio_is_vga(vdev) || nr !=3D 4 || - &vdev->pdev !=3D pci_find_device(pci_device_root_bus(&vdev->pdev), - 0, PCI_DEVFN(0x2, 0))) { + !vfio_is_vga(vdev) || nr !=3D 4) return; - } =20 /* * IGD is not a standard, they like to change their specs often. We @@ -1251,6 +1246,15 @@ static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice = *vdev, int nr) pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); =20 /* + * This must be an Intel VGA device at address 00:02.0 for us to even + * consider enabling legacy mode. The vBIOS has dependencies on the + * PCI bus address. + */ + if (&vdev->pdev !=3D pci_find_device(pci_device_root_bus(&vdev->pdev), + 0, PCI_DEVFN(0x2, 0))) + return; + + /* * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that= we * can stuff host values into, so if there's already one there and it'= s not * one we can hack on, legacy mode is no-go. Sorry Q35. --=20 2.7.4