From nobody Mon Apr 29 04:35:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495790665040303.25807719437455; Fri, 26 May 2017 02:24:25 -0700 (PDT) Received: from localhost ([::1]:35661 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dEBTr-0005mu-Fr for importer@patchew.org; Fri, 26 May 2017 05:24:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dEBR5-0002eA-NR for qemu-devel@nongnu.org; Fri, 26 May 2017 05:21:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dEBR4-0005Xk-MI for qemu-devel@nongnu.org; Fri, 26 May 2017 05:21:31 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:32788) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dEBR0-0005Wx-Ki; Fri, 26 May 2017 05:21:26 -0400 Received: by mail-pf0-x242.google.com with SMTP id f27so1524907pfe.0; Fri, 26 May 2017 02:21:26 -0700 (PDT) Received: from control2.hxtcorp.net ([223.203.96.18]) by smtp.gmail.com with ESMTPSA id b2sm602187pgc.16.2017.05.26.02.21.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 May 2017 02:21:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bUt5NIaPDgbeUnkAd4OiQa864lmc6FFoSXJdDknnrDI=; b=O4xluaH2kq86rcWGSMp0tOOjcO9hSvSfLjVCfeGe1iThR0G0beQ4XvmztcUuCGcqjd XL8PgQmLEX0pEhEB+nrctLA32vRhIH6I3h4lAgH2OuCZJ56zzgj454mQNRbWHvSl/1A3 4Tq9LNVIhYg1hNRrdhgZC24wwQI9Q9H1Lx0rFKRRyr/z6zvUKsSw6JuDATo/q6GvnjZB COMAesHJNnpkokpDI9ZH6oPFqBhbZE6TZNQtIPVLy8J9HiDjVmLOFGmW3+AcX8ITqsfC 9iTAUVW21fnypZaHNWwdkcR8/d/2JBXMswhZYuKpiztkY8l31wODuKuassx01hn3ifW5 C6/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bUt5NIaPDgbeUnkAd4OiQa864lmc6FFoSXJdDknnrDI=; b=XJcBTr8bPQJU7rrSCcy83diTSZPUfwxVDX4+Ex9aO2BCRMYW2d7eqCoXBPy1vcVkyR Gsj912ivDCjvgmt0BsqoPKaZqEy4pXm5Uh65wkYj8BLLyzuFuOm4IZshioao/2inFbHF kYj2rO7jyZTP+B8C3t/FueVB8n7hD82cMoxNhCc3piJQ+J3BbpvjA9FaJEdHQyMQ8X5z zQQr8yEz+/psKm/NMcHJ8VDdRN4qsZx1PuC5NtiWUc5IzUzeOdnmRQIR3RWltCKCWxkx s0Zz6nXvoP1LSGdF5EM9K5zGdENTxI9aCQBwKBEMU5HTTjS8vMX9O6dXbpBSixwEgJx7 5lzw== X-Gm-Message-State: AODbwcDkIgXMWzGGtXj/n50e6YmxWQr4PmKnoc58thSU3KLdDnVHFSIn M98G2Z1bvM2W7A== X-Received: by 10.98.71.84 with SMTP id u81mr1183225pfa.102.1495790485732; Fri, 26 May 2017 02:21:25 -0700 (PDT) From: Li Zhang To: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 26 May 2017 17:21:06 +0800 Message-Id: <1495790468-23862-2-git-send-email-zhlcindy@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495790468-23862-1-git-send-email-zhlcindy@gmail.com> References: <1495790468-23862-1-git-send-email-zhlcindy@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 1/3] arm/virt: Refine fdt_add_cpu_nodes code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Li Zhang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Li Zhang Refind fdt_add_cpu_nodes code and add a new function fdt_add_cpu_node, which can be called by hot_add_cpu function. Signed-off-by: Li Zhang --- hw/arm/virt.c | 106 +++++++++++++++++++++++++++++++++---------------------= ---- 1 file changed, 61 insertions(+), 45 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c7c8159..73c3cf7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -334,68 +334,84 @@ static void fdt_add_timer_nodes(const VirtMachineStat= e *vms) GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqfla= gs); } =20 -static void fdt_add_cpu_nodes(const VirtMachineState *vms) +/* + * From Documentation/devicetree/bindings/arm/cpus.txt + * On ARM v8 64-bit systems value should be set to 2, + * that corresponds to the MPIDR_EL1 register size. + * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + * in the system, #address-cells can be set to 1, since + * MPIDR_EL1[63:32] bits are not used for CPUs + * identification. + * + * Here we actually don't know whether our system is 32- or 64-bit one. + * The simplest way to go is to examine affinity IDs of all our CPUs. If + * at least one of them has Aff3 populated, we set #address-cells to 2. + */ + +static int fdt_get_addr_cells(const VirtMachineState *vms) { int cpu; int addr_cells =3D 1; - const MachineState *ms =3D MACHINE(vms); =20 - /* - * From Documentation/devicetree/bindings/arm/cpus.txt - * On ARM v8 64-bit systems value should be set to 2, - * that corresponds to the MPIDR_EL1 register size. - * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - * in the system, #address-cells can be set to 1, since - * MPIDR_EL1[63:32] bits are not used for CPUs - * identification. - * - * Here we actually don't know whether our system is 32- or 64-bit on= e. - * The simplest way to go is to examine affinity IDs of all our CPUs.= If - * at least one of them has Aff3 populated, we set #address-cells to = 2. - */ for (cpu =3D 0; cpu < vms->smp_cpus; cpu++) { ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); - if (armcpu->mp_affinity & ARM_AFF3_MASK) { addr_cells =3D 2; break; } } + return addr_cells; +} =20 - qemu_fdt_add_subnode(vms->fdt, "/cpus"); - qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); - qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); =20 - for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { - char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); - CPUState *cs =3D CPU(armcpu); +static void fdt_add_cpu_node(const VirtMachineState *vms, int cpu) +{ + char *nodename; + int addr_cells =3D fdt_get_addr_cells(vms); + const MachineState *ms =3D MACHINE(vms); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + CPUState *cs =3D CPU(armcpu); =20 - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", - armcpu->dtb_compatible); - - if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED - && vms->smp_cpus > 1) { - qemu_fdt_setprop_string(vms->fdt, nodename, - "enable-method", "psci"); - } + if (cpu < 0 || cpu >=3D max_cpus) { + error_report("Invalid cpu index."); + return; + } =20 - if (addr_cells =3D=3D 2) { - qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", - armcpu->mp_affinity); - } else { - qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", - armcpu->mp_affinity); - } + nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); =20 - if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { - qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", - ms->possible_cpus->cpus[cs->cpu_index].props.node_id); - } + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", + armcpu->dtb_compatible); + if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { + qemu_fdt_setprop_string(vms->fdt, nodename, "enable-method", "psci= "); + } =20 - g_free(nodename); + if (addr_cells =3D=3D 2) { + qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", armcpu->mp_affinit= y); + } else { + qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", armcpu->mp_affini= ty); + } + + if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", + ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + } + + g_free(nodename); +} + +static void fdt_add_cpu_nodes(const VirtMachineState *vms) +{ + int cpu; + int addr_cells =3D fdt_get_addr_cells(vms); + + qemu_fdt_add_subnode(vms->fdt, "/cpus"); + qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); + qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); + + for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { + fdt_add_cpu_node(vms, cpu); } } =20 --=20 2.7.4 From nobody Mon Apr 29 04:35:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; dkim=fail spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 2/3] arm/virt: Refine code of machvirt_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Li Zhang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Li Zhang This patch is to refine cpu related in machvirt_init and add virt_new_cpu function which can be called by hot_add_cpu. Signed-off-by: Li Zhang --- hw/arm/virt.c | 231 ++++++++++++++++++++++++++++++++----------------------= ---- 1 file changed, 128 insertions(+), 103 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 73c3cf7..31314c1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -110,6 +110,8 @@ static ARMPlatformBusSystemParams platform_bus_params; #define RAMLIMIT_GB 255 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) =20 +static MemoryRegion *secure_sysmem; + /* Addresses and sizes of our components. * 0..128MB is space for a flash device so we can run bootrom code such as= UEFI. * 128MB..256MB is used for miscellaneous device I/O. @@ -415,6 +417,116 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) } } =20 +static void virt_new_cpu(MachineState *ms, int id, Error **errp) +{ + const char *typename; + char **cpustr; + int node_id; + + ObjectClass *oc; + CPUClass *cc; + CPUState *cs; + Object *cpuobj; + const CPUArchIdList *possible_cpus; + + Error *err =3D NULL; + const char *cpu_model =3D ms->cpu_model; + MemoryRegion *sysmem =3D get_system_memory(); + + VirtMachineState *vms =3D VIRT_MACHINE(ms); + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(ms); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + CPU_FOREACH(cs) { + if (cs->cpu_index =3D=3D id) { + error_report("CPU %d has been created.", id); + return; + } + } + possible_cpus =3D mc->possible_cpu_arch_ids(ms); + /* Separate the actual CPU model name from any appended features */ + cpustr =3D g_strsplit(cpu_model, ",", 2); + if (!cpuname_valid(cpustr[0])) { + error_report("mach-virt: CPU %s not supported", cpustr[0]); + goto out; + } + oc =3D cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); + if (!oc) { + error_report("Unable to find CPU definition"); + goto out; + } + + typename =3D object_class_get_name(oc); + + cc =3D CPU_CLASS(oc); + cc->parse_features(typename, cpustr[1], &err); + if (err) { + error_report_err(err); + goto out; + } + + cpuobj =3D object_new(typename); + object_property_set_int(cpuobj, possible_cpus->cpus[id].arch_id, + "mp-affinity", NULL); + cs =3D CPU(cpuobj); + cs->cpu_index =3D id; + + node_id =3D possible_cpus->cpus[cs->cpu_index].props.node_id; + if (!possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + /* by default CPUState::numa_node was 0 if it's not set via CLI + * keep it this way for now but in future we probably should + * refuse to start up with incomplete numa mapping */ + node_id =3D 0; + } + if (cs->numa_node =3D=3D CPU_UNSET_NUMA_NODE_ID) { + cs->numa_node =3D node_id; + } else { + /* CPU isn't device_add compatible yet, this shouldn't happen */ + error_setg(&error_abort, "user set node-id not implemented"); + } + + if (!vms->secure) { + object_property_set_bool(cpuobj, false, "has_el3", NULL); + } + + if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { + object_property_set_bool(cpuobj, false, "has_el2", NULL); + } + + if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { + object_property_set_int(cpuobj, vms->psci_conduit, + "psci-conduit", NULL); + /* Secondary CPUs start in PSCI powered-down state */ + if (id > 0) { + object_property_set_bool(cpuobj, true, "start-powered-off", NU= LL); + } + } + + if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { + object_property_set_bool(cpuobj, false, "pmu", NULL); + } + + if (object_property_find(cpuobj, "reset-cbar", NULL)) { + object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, + "reset-cbar", &error_abort); + } + + object_property_set_link(cpuobj, OBJECT(sysmem), "memory", &error_abor= t); + + if (vms->secure) { + object_property_set_link(cpuobj, OBJECT(secure_sysmem), + "secure-memory", &error_abort); + } + + object_property_set_int(cpuobj, id, "id", NULL); + object_property_set_bool(cpuobj, true, "realized", NULL); + object_unref(cpuobj); + +out: + g_strfreev(cpustr); + error_propagate(errp, err); +} + static void fdt_add_its_gic_node(VirtMachineState *vms) { vms->msi_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); @@ -1237,35 +1349,29 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineSta= te *vms, int idx) static void machvirt_init(MachineState *machine) { VirtMachineState *vms =3D VIRT_MACHINE(machine); - VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(machine); MachineClass *mc =3D MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus; qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem =3D get_system_memory(); - MemoryRegion *secure_sysmem =3D NULL; int n, virt_max_cpus; MemoryRegion *ram =3D g_new(MemoryRegion, 1); const char *cpu_model =3D machine->cpu_model; - char **cpustr; - ObjectClass *oc; - const char *typename; - CPUClass *cc; Error *err =3D NULL; bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); =20 if (!cpu_model) { - cpu_model =3D "cortex-a15"; + cpu_model =3D kvm_enabled() ? "host" : "cortex-a15"; + machine->cpu_model =3D cpu_model; } =20 /* We can probe only here because during property set * KVM is not available yet */ + if (!vms->gic_version && !kvm_enabled()) { + error_report("gic-version=3Dhost requires KVM"); + exit(1); + } if (!vms->gic_version) { - if (!kvm_enabled()) { - error_report("gic-version=3Dhost requires KVM"); - exit(1); - } - vms->gic_version =3D kvm_arm_vgic_probe(); if (!vms->gic_version) { error_report("Unable to determine GIC version supported by hos= t"); @@ -1273,14 +1379,6 @@ static void machvirt_init(MachineState *machine) } } =20 - /* Separate the actual CPU model name from any appended features */ - cpustr =3D g_strsplit(cpu_model, ",", 2); - - if (!cpuname_valid(cpustr[0])) { - error_report("mach-virt: CPU %s not supported", cpustr[0]); - exit(1); - } - /* If we have an EL3 boot ROM then the assumption is that it will * implement PSCI itself, so disable QEMU's internal implementation * so it doesn't get in the way. Instead of starting secondary @@ -1328,12 +1426,12 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->secure) { - if (kvm_enabled()) { - error_report("mach-virt: KVM does not support Security extensi= ons"); - exit(1); - } + if (vms->secure && kvm_enabled()) { + error_report("mach-virt: KVM does not support Security extensions"= ); + exit(1); + } =20 + if (vms->secure) { /* The Secure view of the world is the same as the NonSecure, * but with a few extra devices. Create it as a container region * containing the system memory at low priority; any secure-only @@ -1347,91 +1445,18 @@ static void machvirt_init(MachineState *machine) =20 create_fdt(vms); =20 - oc =3D cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); - if (!oc) { - error_report("Unable to find CPU definition"); - exit(1); - } - typename =3D object_class_get_name(oc); - - /* convert -smp CPU options specified by the user into global props */ - cc =3D CPU_CLASS(oc); - cc->parse_features(typename, cpustr[1], &err); - g_strfreev(cpustr); - if (err) { - error_report_err(err); - exit(1); - } - possible_cpus =3D mc->possible_cpu_arch_ids(machine); for (n =3D 0; n < possible_cpus->len; n++) { - Object *cpuobj; - CPUState *cs; - int node_id; - if (n >=3D smp_cpus) { break; } - - cpuobj =3D object_new(typename); - object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, - "mp-affinity", NULL); - - cs =3D CPU(cpuobj); - cs->cpu_index =3D n; - - node_id =3D possible_cpus->cpus[cs->cpu_index].props.node_id; - if (!possible_cpus->cpus[cs->cpu_index].props.has_node_id) { - /* by default CPUState::numa_node was 0 if it's not set via CLI - * keep it this way for now but in future we probably should - * refuse to start up with incomplete numa mapping */ - node_id =3D 0; - } - if (cs->numa_node =3D=3D CPU_UNSET_NUMA_NODE_ID) { - cs->numa_node =3D node_id; - } else { - /* CPU isn't device_add compatible yet, this shouldn't happen = */ - error_setg(&error_abort, "user set node-id not implemented"); - } - - if (!vms->secure) { - object_property_set_bool(cpuobj, false, "has_el3", NULL); - } - - if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { - object_property_set_bool(cpuobj, false, "has_el2", NULL); - } - - if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { - object_property_set_int(cpuobj, vms->psci_conduit, - "psci-conduit", NULL); - - /* Secondary CPUs start in PSCI powered-down state */ - if (n > 0) { - object_property_set_bool(cpuobj, true, - "start-powered-off", NULL); - } - } - - if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { - object_property_set_bool(cpuobj, false, "pmu", NULL); - } - - if (object_property_find(cpuobj, "reset-cbar", NULL)) { - object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].b= ase, - "reset-cbar", &error_abort); - } - - object_property_set_link(cpuobj, OBJECT(sysmem), "memory", - &error_abort); - if (vms->secure) { - object_property_set_link(cpuobj, OBJECT(secure_sysmem), - "secure-memory", &error_abort); + virt_new_cpu(machine, n, &err); + if (err) { + error_report("mach-virt: creating a new cpu failed."); + exit(1); } - - object_property_set_bool(cpuobj, true, "realized", NULL); - object_unref(cpuobj); } + fdt_add_timer_nodes(vms); fdt_add_cpu_nodes(vms); fdt_add_psci_node(vms); --=20 2.7.4 From nobody Mon Apr 29 04:35:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 3/3] arm/virt: Implement hot_add_cpu interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Li Zhang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Li Zhang This patch is to add add_hot_cpu interface. Signed-off-by: Li Zhang --- hw/arm/virt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 31314c1..c7e8322 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -527,6 +527,24 @@ out: error_propagate(errp, err); } =20 +static void virt_hot_add_cpu(const int64_t id, Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + VirtMachineState *vms =3D VIRT_MACHINE(ms); + + if (id < 0 || id >=3D max_cpus) { + error_setg(errp, "Invalid CPU id: %" PRIi64, id); + return; + } + + virt_new_cpu(ms, id, errp); + if (errp) { + return; + } + + fdt_add_cpu_node(vms, id); +} + static void fdt_add_its_gic_node(VirtMachineState *vms) { vms->msi_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); @@ -1654,6 +1672,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) mc->minimum_page_bits =3D 12; mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; + mc->hot_add_cpu =3D virt_hot_add_cpu; } =20 static const TypeInfo virt_machine_info =3D { --=20 2.7.4