From nobody Mon May 6 08:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495739589140212.56365414417496; Thu, 25 May 2017 12:13:09 -0700 (PDT) Received: from localhost ([::1]:33329 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyC3-000566-DF for importer@patchew.org; Thu, 25 May 2017 15:13:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyAV-0003qj-0v for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDyAQ-0001hA-2b for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:31 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:54465 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dDyAP-0001h6-TR for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:26 -0400 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4PJ8gk5037032 for ; Thu, 25 May 2017 15:11:25 -0400 Received: from e24smtp02.br.ibm.com (e24smtp02.br.ibm.com [32.104.18.86]) by mx0b-001b2d01.pphosted.com with ESMTP id 2anxjnff55-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 25 May 2017 15:11:24 -0400 Received: from localhost by e24smtp02.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 25 May 2017 16:11:19 -0300 Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.8.31.93]) by d24relay04.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4PJBB355964102 for ; Thu, 25 May 2017 16:11:19 -0300 Received: from d24av02.br.ibm.com (localhost [127.0.0.1]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v4PJAlSZ013577 for ; Thu, 25 May 2017 16:10:47 -0300 Received: from pacoca.ibm.com ([9.85.147.99]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v4PJAfwZ013205; Thu, 25 May 2017 16:10:45 -0300 From: Jose Ricardo Ziviani To: qemu-devel@nongnu.org Date: Thu, 25 May 2017 16:10:20 -0300 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17052519-0020-0000-0000-000002AD13BF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052519-0021-0000-0000-000030CA9145 Message-Id: <1495739423-32326-2-git-send-email-joserz@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-25_15:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705250348 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH Risu v3 1/4] risugen_ppc64: Load random 128-bit data to vector registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, nikunj@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jose Ricardo Ziviani --- risugen_ppc64.pm | 42 +++++++++++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 341478c..1a3cd59 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -99,6 +99,29 @@ sub write_mov_ri64($$) insn32((0x3e << 26) | (20 << 21) | (1 << 16) | 0x10); } =20 +sub write_mov_ri128($$$$) +{ + my ($imhh, $imh, $iml, $imll) =3D @_; + + # store the lowest 32 bits + write_mov_ri32(20, $imll); + # stw r20, 16(r1) + insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x10); + # store the lower 32 bits + write_mov_ri32(20, $iml); + # stw r20, 20(r1) + insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x14); + # store the higher 32 bits + write_mov_ri32(20, $imh); + # stw r20, 24(r1) + insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x18); + # store the highest 32 bits + write_mov_ri32(20, $imhh); + # stw r20, 28(r1) + insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x1c); + +} + sub write_random_ppc64_fpdata() { for (my $i =3D 0; $i < 32; $i++) { @@ -106,22 +129,18 @@ sub write_random_ppc64_fpdata() write_mov_ri64(rand(0xfffff), rand(0xfffff)); # since the EA is r1+16, load such value in FP reg insn32((0x32 << 26) | ($i << 21) | (0x1 << 16) | 0x10); - insn32((0x39 << 26) | ($i << 21) | (0x1 << 16) | 0x12); - } } =20 -sub write_random_ppc64_fpdata_i() +sub write_random_ppc64_vrdata() { - # get an space from the stack - insn32(0x3ac10020); # addi r22, r1, 32 - insn32(0x3ee03ff0); # lis r23, 0x3ff0 - insn32(0x3af70000); # addi r23, r23, 0 - insn32(0xfaf60000); # std r23, 0(r22) - for (my $i =3D 0; $i < 32; $i++) { - # lfd f$i, 0(r22) - insn32((0x32 << 26 | $i << 21 | 0x16 << 16)); + # load a random doubleword value at r0 + write_mov_ri128(rand(0xffff), rand(0xffff), rand(0xfffff), rand(0x= fffff)); + # li r0, 16 + write_mov_ri16(0, 0x10); + # lvx vr$i, r1, r0 + insn32((0x1f << 26) | ($i << 21) | (0x1 << 16) | 0x2ce); } } =20 @@ -172,6 +191,7 @@ sub write_random_register_data($) =20 clear_vr_registers(); =20 + write_random_ppc64_vrdata(); if ($fp_enabled) { # load floating point / SIMD registers write_random_ppc64_fpdata(); --=20 2.7.4 From nobody Mon May 6 08:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495739591049401.0929268472879; Thu, 25 May 2017 12:13:11 -0700 (PDT) Received: from localhost ([::1]:33330 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyC5-0005F2-OF for importer@patchew.org; Thu, 25 May 2017 15:13:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyAX-0003sE-F3 for qemu-devel@nongnu.org; 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Violators will be prosecuted; Thu, 25 May 2017 16:11:22 -0300 Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.8.31.93]) by d24relay02.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4PJBDYg17170818 for ; Thu, 25 May 2017 16:11:21 -0300 Received: from d24av02.br.ibm.com (localhost [127.0.0.1]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v4PJAnZH013600 for ; Thu, 25 May 2017 16:10:49 -0300 Received: from pacoca.ibm.com ([9.85.147.99]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v4PJAfwa013205; Thu, 25 May 2017 16:10:47 -0300 From: Jose Ricardo Ziviani To: qemu-devel@nongnu.org Date: Thu, 25 May 2017 16:10:21 -0300 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17052519-0020-0000-0000-000002AD13C5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052519-0021-0000-0000-000030CA914B Message-Id: <1495739423-32326-3-git-send-email-joserz@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-25_15:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705250348 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH Risu v3 2/4] configure: Add initial support to PPC64 (big endian) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, nikunj@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Uses the same ppc64 source file for both BE/LE archs since they are essentially the same thing. Signed-off-by: Jose Ricardo Ziviani --- configure | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/configure b/configure index 055e6d6..dd64d8b 100755 --- a/configure +++ b/configure @@ -51,11 +51,7 @@ guess_arch() { elif check_define __aarch64__ ; then ARCH=3D"aarch64" elif check_define __powerpc64__ ; then - if check_define __BIG_ENDIAN__; then - ARCH=3D"ppc64" - else - ARCH=3D"ppc64le" - fi + ARCH=3D"ppc64le" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -127,6 +123,9 @@ OBJDUMP=3D"${OBJDUMP-${CROSS_PREFIX}objdump}" =20 if test "x${ARCH}" =3D "x"; then guess_arch +elif test "x${ARCH}" =3D "xppc64"; then + # ppc64 and ppc64le uses the same C source code + ARCH=3D"ppc64le" fi =20 generate_makefilein --=20 2.7.4 From nobody Mon May 6 08:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495739700610523.8618549829214; Thu, 25 May 2017 12:15:00 -0700 (PDT) Received: from localhost ([::1]:33344 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyDr-00085z-9e for importer@patchew.org; Thu, 25 May 2017 15:14:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyAa-0003uj-HG for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDyAW-0001hs-2r for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:36 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:54254) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dDyAV-0001hi-Op for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:31 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4PJ8Z6t056196 for ; Thu, 25 May 2017 15:11:30 -0400 Received: from e24smtp01.br.ibm.com (e24smtp01.br.ibm.com [32.104.18.85]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ap4gt1sk8-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 25 May 2017 15:11:30 -0400 Received: from localhost by e24smtp01.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 25 May 2017 16:11:25 -0300 Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.8.31.93]) by d24relay02.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4PJBGbs35782824 for ; Thu, 25 May 2017 16:11:25 -0300 Received: from d24av02.br.ibm.com (localhost [127.0.0.1]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v4PJAqFG013628 for ; Thu, 25 May 2017 16:10:53 -0300 Received: from pacoca.ibm.com ([9.85.147.99]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v4PJAfwb013205; Thu, 25 May 2017 16:10:50 -0300 From: Jose Ricardo Ziviani To: qemu-devel@nongnu.org Date: Thu, 25 May 2017 16:10:22 -0300 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17052519-1523-0000-0000-000002A31696 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052519-1524-0000-0000-00002A399AB1 Message-Id: <1495739423-32326-4-git-send-email-joserz@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-25_15:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705250348 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH Risu v3 3/4] risugen, risugen_ppc64.pm: Add support ppc64 (big-endian) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, nikunj@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit adds an option to risugen in order to give the opportunity to generated big-endian instructions. By passing --be, users force risugen to generated big-endian instructions for ppc64. ./risugen --be --numinsns 1000 --pattern "ADD" ppc64.risu test.bin ./risugen --numinsns 1000 --pattern "ADD" ppc64.risu test.bin Signed-off-by: Jose Ricardo Ziviani --- risugen | 6 +++++- risugen_ppc64.pm | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/risugen b/risugen index 6aad626..8b20425 100755 --- a/risugen +++ b/risugen @@ -264,6 +264,7 @@ Valid options: a general set you have excluded. --no-fp : disable floating point: no fp init, randomization etc. Useful to test before support for FP is available. + --be : generate instructions in Big-Endian byte order (ppc64 o= nly). --help : print this message EOT } @@ -274,6 +275,7 @@ sub main() my $condprob =3D 0; my $fpscr =3D 0; my $fp_enabled =3D 1; + my $big_endian =3D 0; my ($infile, $outfile); =20 GetOptions( "help" =3D> sub { usage(); exit(0); }, @@ -287,6 +289,7 @@ sub main() die "Value \"$condprob\" invalid for option condpr= ob (must be between 0 and 1)\n"; } }, + "be" =3D> sub { $big_endian =3D 1; }, "no-fp" =3D> sub { $fp_enabled =3D 0; }, ) or return 1; # allow "--pattern re,re" and "--pattern re --pattern re" @@ -317,7 +320,8 @@ sub main() 'not_pattern_re' =3D> \@not_pattern_re, 'details' =3D> \%insn_details, 'arch' =3D> $full_arch[0], - 'subarch' =3D> $full_arch[1] || '' + 'subarch' =3D> $full_arch[1] || '', + 'bigendian' =3D> $big_endian ); =20 write_test_code(\%params); diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 1a3cd59..c0e71cf 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -375,6 +375,10 @@ sub write_test_code($) my @not_pattern_re =3D @{ $params->{ 'not_pattern_re' } }; my %insn_details =3D %{ $params->{ 'details' } }; =20 + if ($params->{ 'bigendian' } eq 1) { + set_endian(1); + } + open_bin($outfile); =20 # convert from probability that insn will be conditional to --=20 2.7.4 From nobody Mon May 6 08:57:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1495739705286302.0920323458763; Thu, 25 May 2017 12:15:05 -0700 (PDT) Received: from localhost ([::1]:33345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyDv-00088s-RZ for importer@patchew.org; Thu, 25 May 2017 15:15:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDyAg-0003xE-5Z for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDyAa-0001iX-G6 for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:41 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:59253) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dDyAa-0001iM-2O for qemu-devel@nongnu.org; Thu, 25 May 2017 15:11:36 -0400 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4PJ8gT4136257 for ; Thu, 25 May 2017 15:11:34 -0400 Received: from e24smtp01.br.ibm.com (e24smtp01.br.ibm.com [32.104.18.85]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ap4wrrr7b-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 25 May 2017 15:11:34 -0400 Received: from localhost by e24smtp01.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 25 May 2017 16:11:28 -0300 Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.8.31.93]) by d24relay02.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4PJBJj418284824 for ; Thu, 25 May 2017 16:11:28 -0300 Received: from d24av02.br.ibm.com (localhost [127.0.0.1]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v4PJAtHI013688 for ; Thu, 25 May 2017 16:10:55 -0300 Received: from pacoca.ibm.com ([9.85.147.99]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v4PJAfwc013205; Thu, 25 May 2017 16:10:53 -0300 From: Jose Ricardo Ziviani To: qemu-devel@nongnu.org Date: Thu, 25 May 2017 16:10:23 -0300 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1495739423-32326-1-git-send-email-joserz@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17052519-1523-0000-0000-000002A31698 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052519-1524-0000-0000-00002A399AB5 Message-Id: <1495739423-32326-5-git-send-email-joserz@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-25_15:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705250348 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH Risu v3 4/4] build: Add support to PowerPC BE and remove ARCH X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, nikunj@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Essentialy the code for PowerPC BE and LE are the same, so this patch renames all *ppc64le.* files to *ppc64.* and reflects such in the Makefile. Due to the fact that all supported archs are covered by guess_arch function, this also drops the ARCH parameter from the Makefile. Signed-off-by: Jose Ricardo Ziviani --- build-all-archs | 2 +- configure | 13 +--- risu_ppc64.c | 40 ++++++++++ risu_ppc64le.c | 40 ---------- risu_reginfo_ppc64.c | 193 +++++++++++++++++++++++++++++++++++++++++++++= ++++ risu_reginfo_ppc64.h | 28 +++++++ risu_reginfo_ppc64le.c | 193 ---------------------------------------------= ---- risu_reginfo_ppc64le.h | 28 ------- test_ppc64.s | 49 +++++++++++++ test_ppc64le.s | 49 ------------- 10 files changed, 313 insertions(+), 322 deletions(-) create mode 100644 risu_ppc64.c delete mode 100644 risu_ppc64le.c create mode 100644 risu_reginfo_ppc64.c create mode 100644 risu_reginfo_ppc64.h delete mode 100644 risu_reginfo_ppc64le.c delete mode 100644 risu_reginfo_ppc64le.h create mode 100644 test_ppc64.s delete mode 100644 test_ppc64le.s diff --git a/build-all-archs b/build-all-archs index e98ab9d..2768727 100755 --- a/build-all-archs +++ b/build-all-archs @@ -25,7 +25,7 @@ program_exists() { =20 # powerpc64-linux-gnu doesn't work at the moment, so not yet listed. for triplet in aarch64-linux-gnu arm-linux-gnueabihf m68k-linux-gnu \ - powerpc64le-linux-gnu ; do + powerpc64le-linux-gnu powerpc64-linux-gnu ; do =20 if ! program_exists "${triplet}-gcc"; then echo "Skipping ${triplet}: no compiler found" diff --git a/configure b/configure index dd64d8b..180194a 100755 --- a/configure +++ b/configure @@ -51,7 +51,7 @@ guess_arch() { elif check_define __aarch64__ ; then ARCH=3D"aarch64" elif check_define __powerpc64__ ; then - ARCH=3D"ppc64le" + ARCH=3D"ppc64" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -87,9 +87,6 @@ Some influential environment variables: CROSS_PREFIX cross-compiler prefix, defaults to gcc and other tools prefixed with the given string. =20 - ARCH force target architecture instead of trying to detect it. - Valid values=3D[arm|aarch64|ppc64|ppc64le|m68k] - CC C compiler command CFLAGS C compiler flags CPPFLAGS C preprocessor flags, e.g. -I @@ -121,13 +118,7 @@ AS=3D"${AS-${CROSS_PREFIX}as}" OBJCOPY=3D"${OBJCOPY-${CROSS_PREFIX}objcopy}" OBJDUMP=3D"${OBJDUMP-${CROSS_PREFIX}objdump}" =20 -if test "x${ARCH}" =3D "x"; then - guess_arch -elif test "x${ARCH}" =3D "xppc64"; then - # ppc64 and ppc64le uses the same C source code - ARCH=3D"ppc64le" -fi - +guess_arch generate_makefilein =20 # Are we in a separate build tree? If so, link the Makefile diff --git a/risu_ppc64.c b/risu_ppc64.c new file mode 100644 index 0000000..b575078 --- /dev/null +++ b/risu_ppc64.c @@ -0,0 +1,40 @@ +/*************************************************************************= ***** + * Copyright (c) IBM Corp, 2016 + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Jose Ricardo Ziviani - initial implementation + * based on Claudio Fontana's risu_aarch64.c + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include "risu.h" + +void advance_pc(void *vuc) +{ + ucontext_t *uc =3D (ucontext_t*)vuc; + uc->uc_mcontext.regs->nip +=3D 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc =3D vuc; + uc->uc_mcontext.gp_regs[0] =3D value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->gregs[0]; +} + +int get_risuop(struct reginfo *ri) +{ + uint32_t insn =3D ri->faulting_insn; + uint32_t op =3D insn & 0xf; + uint32_t key =3D insn & ~0xf; + uint32_t risukey =3D 0x00005af0; + return (key !=3D risukey) ? -1 : op; +} diff --git a/risu_ppc64le.c b/risu_ppc64le.c deleted file mode 100644 index b575078..0000000 --- a/risu_ppc64le.c +++ /dev/null @@ -1,40 +0,0 @@ -/*************************************************************************= ***** - * Copyright (c) IBM Corp, 2016 - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * which accompanies this distribution, and is available at - * http://www.eclipse.org/legal/epl-v10.html - * - * Contributors: - * Jose Ricardo Ziviani - initial implementation - * based on Claudio Fontana's risu_aarch64.c - * based on Peter Maydell's risu_arm.c - *************************************************************************= ****/ - -#include "risu.h" - -void advance_pc(void *vuc) -{ - ucontext_t *uc =3D (ucontext_t*)vuc; - uc->uc_mcontext.regs->nip +=3D 4; -} - -void set_ucontext_paramreg(void *vuc, uint64_t value) -{ - ucontext_t *uc =3D vuc; - uc->uc_mcontext.gp_regs[0] =3D value; -} - -uint64_t get_reginfo_paramreg(struct reginfo *ri) -{ - return ri->gregs[0]; -} - -int get_risuop(struct reginfo *ri) -{ - uint32_t insn =3D ri->faulting_insn; - uint32_t op =3D insn & 0xf; - uint32_t key =3D insn & ~0xf; - uint32_t risukey =3D 0x00005af0; - return (key !=3D risukey) ? -1 : op; -} diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c new file mode 100644 index 0000000..ae86263 --- /dev/null +++ b/risu_reginfo_ppc64.c @@ -0,0 +1,193 @@ +/*************************************************************************= ***** + * Copyright (c) IBM Corp, 2016 + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Jose Ricardo Ziviani - initial implementation + * based on Claudio Fontana's risu_aarch64.c + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_ppc64.h" + +#define XER 37 +#define CCR 38 + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc) +{ + int i; + memset(ri, 0, sizeof(*ri)); + + ri->faulting_insn =3D *((uint32_t *)uc->uc_mcontext.regs->nip); + ri->nip =3D uc->uc_mcontext.regs->nip - image_start_address; + + for (i =3D 0; i < NGREG; i++) { + ri->gregs[i] =3D uc->uc_mcontext.gp_regs[i]; + } + + for (i =3D 0; i < NFPREG; i++) { + ri->fpregs[i] =3D uc->uc_mcontext.fp_regs[i]; + } + + for (i =3D 0; i < 32; i++) { + ri->vrregs.vrregs[i][0] =3D uc->uc_mcontext.v_regs->vrregs[i][0]; + ri->vrregs.vrregs[i][1] =3D uc->uc_mcontext.v_regs->vrregs[i][1]; + ri->vrregs.vrregs[i][2] =3D uc->uc_mcontext.v_regs->vrregs[i][2]; + ri->vrregs.vrregs[i][3] =3D uc->uc_mcontext.v_regs->vrregs[i][3]; + } + ri->vrregs.vscr =3D uc->uc_mcontext.v_regs->vscr; + ri->vrregs.vrsave =3D uc->uc_mcontext.v_regs->vrsave; +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *m, struct reginfo *a) +{ + int i; + for (i =3D 0; i < 32; i++) { + if (i =3D=3D 1 || i =3D=3D 13) { + continue; + } + + if (m->gregs[i] !=3D a->gregs[i]) { + return 0; + } + } + + if (m->gregs[XER] !=3D a->gregs[XER]) { + return 0; + } + + if ((m->gregs[CCR] & 0x10) !=3D (a->gregs[CCR] & 0x10)) { + return 0; + } + + for (i =3D 0; i < 32; i++) { + if (isnan(m->fpregs[i]) && isnan(a->fpregs[i])) { + continue; + } + + if (m->fpregs[i] !=3D a->fpregs[i]) { + return 0; + } + } + + for (i =3D 0; i < 32; i++) { + if (m->vrregs.vrregs[i][0] !=3D a->vrregs.vrregs[i][0] || + m->vrregs.vrregs[i][1] !=3D a->vrregs.vrregs[i][1] || + m->vrregs.vrregs[i][2] !=3D a->vrregs.vrregs[i][2] || + m->vrregs.vrregs[i][3] !=3D a->vrregs.vrregs[i][3]) { + return 0; + } + } + return 1; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE *f) +{ + int i; + + fprintf(f, " faulting insn 0x%x\n", ri->faulting_insn); + fprintf(f, " prev insn 0x%x\n", ri->prev_insn); + fprintf(f, " prev addr 0x%" PRIx64 "\n\n", ri->nip); + + for (i =3D 0; i < 16; i++) { + fprintf(f, "\tr%2d: %16lx\tr%2d: %16lx\n", i, ri->gregs[i], + i + 16, ri->gregs[i + 16]); + } + + fprintf(f, "\n"); + fprintf(f, "\tnip : %16lx\n", ri->gregs[32]); + fprintf(f, "\tmsr : %16lx\n", ri->gregs[33]); + fprintf(f, "\torig r3: %16lx\n", ri->gregs[34]); + fprintf(f, "\tctr : %16lx\n", ri->gregs[35]); + fprintf(f, "\tlnk : %16lx\n", ri->gregs[36]); + fprintf(f, "\txer : %16lx\n", ri->gregs[37]); + fprintf(f, "\tccr : %16lx\n", ri->gregs[38]); + fprintf(f, "\tmq : %16lx\n", ri->gregs[39]); + fprintf(f, "\ttrap : %16lx\n", ri->gregs[40]); + fprintf(f, "\tdar : %16lx\n", ri->gregs[41]); + fprintf(f, "\tdsisr : %16lx\n", ri->gregs[42]); + fprintf(f, "\tresult : %16lx\n", ri->gregs[43]); + fprintf(f, "\tdscr : %16lx\n\n", ri->gregs[44]); + + for (i =3D 0; i < 16; i++) { + fprintf(f, "\tf%2d: %.4f\tr%2d: %.4f\n", i, ri->fpregs[i], + i + 16, ri->fpregs[i + 16]); + } + fprintf(f, "\tfpscr: %f\n\n", ri->fpregs[32]); + + for (i =3D 0; i < 32; i++) { + fprintf(f, "vr%02d: %8x, %8x, %8x, %8x\n", i, + ri->vrregs.vrregs[i][0], ri->vrregs.vrregs[i][1], + ri->vrregs.vrregs[i][2], ri->vrregs.vrregs[i][3]); + } + + return !ferror(f); +} + +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) +{ + int i; + for (i =3D 0; i < 32; i++) { + if (i =3D=3D 1 || i =3D=3D 13) { + continue; + } + + if (m->gregs[i] !=3D a->gregs[i]) { + fprintf(f, "Mismatch: Register r%d\n", i); + fprintf(f, "master: [%lx] - apprentice: [%lx]\n", + m->gregs[i], a->gregs[i]); + } + } + + if (m->gregs[XER] !=3D a->gregs[XER]) { + fprintf(f, "Mismatch: XER\n"); + fprintf(f, "m: [%lx] !=3D a: [%lx]\n", + m->gregs[XER], a->gregs[XER]); + } + + if (m->gregs[CCR] !=3D a->gregs[CCR]) { + fprintf(f, "Mismatch: Cond. Register\n"); + fprintf(f, "m: [%lx] !=3D a: [%lx]\n", + m->gregs[CCR], a->gregs[CCR]); + } + + for (i =3D 0; i < 32; i++) { + if (isnan(m->fpregs[i]) && isnan(a->fpregs[i])) { + continue; + } + + if (m->fpregs[i] !=3D a->fpregs[i]) { + fprintf(f, "Mismatch: Register r%d\n", i); + fprintf(f, "m: [%f] !=3D a: [%f]\n", + m->fpregs[i], a->fpregs[i]); + } + } + + for (i =3D 0; i < 32; i++) { + if (m->vrregs.vrregs[i][0] !=3D a->vrregs.vrregs[i][0] || + m->vrregs.vrregs[i][1] !=3D a->vrregs.vrregs[i][1] || + m->vrregs.vrregs[i][2] !=3D a->vrregs.vrregs[i][2] || + m->vrregs.vrregs[i][3] !=3D a->vrregs.vrregs[i][3]) { + + fprintf(f, "Mismatch: Register vr%d\n", i); + fprintf(f, "m: [%x, %x, %x, %x] !=3D a: [%x, %x, %x, %x]\n", + m->vrregs.vrregs[i][0], m->vrregs.vrregs[i][1], + m->vrregs.vrregs[i][2], m->vrregs.vrregs[i][3], + a->vrregs.vrregs[i][0], a->vrregs.vrregs[i][1], + a->vrregs.vrregs[i][2], a->vrregs.vrregs[i][3]); + } + } + return !ferror(f); +} diff --git a/risu_reginfo_ppc64.h b/risu_reginfo_ppc64.h new file mode 100644 index 0000000..826143e --- /dev/null +++ b/risu_reginfo_ppc64.h @@ -0,0 +1,28 @@ +/*************************************************************************= ***** + * Copyright (c) IBM Corp, 2016 + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Jose Ricardo Ziviani - initial implementation + * based on Claudio Fontana's risu_reginfo_aarch64 + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#ifndef RISU_REGINFO_PPC64LE_H +#define RISU_REGINFO_PPC64LE_H + +struct reginfo +{ + uint32_t faulting_insn; + uint32_t prev_insn; + uint64_t nip; + uint64_t prev_addr; + gregset_t gregs; + fpregset_t fpregs; + vrregset_t vrregs; +}; + +#endif /* RISU_REGINFO_PPC64LE_H */ diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c deleted file mode 100644 index 9e673e1..0000000 --- a/risu_reginfo_ppc64le.c +++ /dev/null @@ -1,193 +0,0 @@ -/*************************************************************************= ***** - * Copyright (c) IBM Corp, 2016 - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * which accompanies this distribution, and is available at - * http://www.eclipse.org/legal/epl-v10.html - * - * Contributors: - * Jose Ricardo Ziviani - initial implementation - * based on Claudio Fontana's risu_aarch64.c - * based on Peter Maydell's risu_arm.c - *************************************************************************= ****/ - -#include -#include -#include -#include - -#include "risu.h" -#include "risu_reginfo_ppc64le.h" - -#define XER 37 -#define CCR 38 - -/* reginfo_init: initialize with a ucontext */ -void reginfo_init(struct reginfo *ri, ucontext_t *uc) -{ - int i; - memset(ri, 0, sizeof(*ri)); - - ri->faulting_insn =3D *((uint32_t *)uc->uc_mcontext.regs->nip); - ri->nip =3D uc->uc_mcontext.regs->nip - image_start_address; - - for (i =3D 0; i < NGREG; i++) { - ri->gregs[i] =3D uc->uc_mcontext.gp_regs[i]; - } - - for (i =3D 0; i < NFPREG; i++) { - ri->fpregs[i] =3D uc->uc_mcontext.fp_regs[i]; - } - - for (i =3D 0; i < 32; i++) { - ri->vrregs.vrregs[i][0] =3D uc->uc_mcontext.v_regs->vrregs[i][0]; - ri->vrregs.vrregs[i][1] =3D uc->uc_mcontext.v_regs->vrregs[i][1]; - ri->vrregs.vrregs[i][2] =3D uc->uc_mcontext.v_regs->vrregs[i][2]; - ri->vrregs.vrregs[i][3] =3D uc->uc_mcontext.v_regs->vrregs[i][3]; - } - ri->vrregs.vscr =3D uc->uc_mcontext.v_regs->vscr; - ri->vrregs.vrsave =3D uc->uc_mcontext.v_regs->vrsave; -} - -/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ -int reginfo_is_eq(struct reginfo *m, struct reginfo *a) -{ - int i; - for (i =3D 0; i < 32; i++) { - if (i =3D=3D 1 || i =3D=3D 13) { - continue; - } - - if (m->gregs[i] !=3D a->gregs[i]) { - return 0; - } - } - - if (m->gregs[XER] !=3D a->gregs[XER]) { - return 0; - } - - if ((m->gregs[CCR] & 0x10) !=3D (a->gregs[CCR] & 0x10)) { - return 0; - } - - for (i =3D 0; i < 32; i++) { - if (isnan(m->fpregs[i]) && isnan(a->fpregs[i])) { - continue; - } - - if (m->fpregs[i] !=3D a->fpregs[i]) { - return 0; - } - } - - for (i =3D 0; i < 32; i++) { - if (m->vrregs.vrregs[i][0] !=3D a->vrregs.vrregs[i][0] || - m->vrregs.vrregs[i][1] !=3D a->vrregs.vrregs[i][1] || - m->vrregs.vrregs[i][2] !=3D a->vrregs.vrregs[i][2] || - m->vrregs.vrregs[i][3] !=3D a->vrregs.vrregs[i][3]) { - return 0; - } - } - return 1; -} - -/* reginfo_dump: print state to a stream, returns nonzero on success */ -int reginfo_dump(struct reginfo *ri, FILE *f) -{ - int i; - - fprintf(f, " faulting insn 0x%x\n", ri->faulting_insn); - fprintf(f, " prev insn 0x%x\n", ri->prev_insn); - fprintf(f, " prev addr 0x%" PRIx64 "\n\n", ri->nip); - - for (i =3D 0; i < 16; i++) { - fprintf(f, "\tr%2d: %16lx\tr%2d: %16lx\n", i, ri->gregs[i], - i + 16, ri->gregs[i + 16]); - } - - fprintf(f, "\n"); - fprintf(f, "\tnip : %16lx\n", ri->gregs[32]); - fprintf(f, "\tmsr : %16lx\n", ri->gregs[33]); - fprintf(f, "\torig r3: %16lx\n", ri->gregs[34]); - fprintf(f, "\tctr : %16lx\n", ri->gregs[35]); - fprintf(f, "\tlnk : %16lx\n", ri->gregs[36]); - fprintf(f, "\txer : %16lx\n", ri->gregs[37]); - fprintf(f, "\tccr : %16lx\n", ri->gregs[38]); - fprintf(f, "\tmq : %16lx\n", ri->gregs[39]); - fprintf(f, "\ttrap : %16lx\n", ri->gregs[40]); - fprintf(f, "\tdar : %16lx\n", ri->gregs[41]); - fprintf(f, "\tdsisr : %16lx\n", ri->gregs[42]); - fprintf(f, "\tresult : %16lx\n", ri->gregs[43]); - fprintf(f, "\tdscr : %16lx\n\n", ri->gregs[44]); - - for (i =3D 0; i < 16; i++) { - fprintf(f, "\tf%2d: %.4f\tr%2d: %.4f\n", i, ri->fpregs[i], - i + 16, ri->fpregs[i + 16]); - } - fprintf(f, "\tfpscr: %f\n\n", ri->fpregs[32]); - - for (i =3D 0; i < 32; i++) { - fprintf(f, "vr%02d: %8x, %8x, %8x, %8x\n", i, - ri->vrregs.vrregs[i][0], ri->vrregs.vrregs[i][1], - ri->vrregs.vrregs[i][2], ri->vrregs.vrregs[i][3]); - } - - return !ferror(f); -} - -int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) -{ - int i; - for (i =3D 0; i < 32; i++) { - if (i =3D=3D 1 || i =3D=3D 13) { - continue; - } - - if (m->gregs[i] !=3D a->gregs[i]) { - fprintf(f, "Mismatch: Register r%d\n", i); - fprintf(f, "master: [%lx] - apprentice: [%lx]\n", - m->gregs[i], a->gregs[i]); - } - } - - if (m->gregs[XER] !=3D a->gregs[XER]) { - fprintf(f, "Mismatch: XER\n"); - fprintf(f, "m: [%lx] !=3D a: [%lx]\n", - m->gregs[XER], a->gregs[XER]); - } - - if (m->gregs[CCR] !=3D a->gregs[CCR]) { - fprintf(f, "Mismatch: Cond. Register\n"); - fprintf(f, "m: [%lx] !=3D a: [%lx]\n", - m->gregs[CCR], a->gregs[CCR]); - } - - for (i =3D 0; i < 32; i++) { - if (isnan(m->fpregs[i]) && isnan(a->fpregs[i])) { - continue; - } - - if (m->fpregs[i] !=3D a->fpregs[i]) { - fprintf(f, "Mismatch: Register r%d\n", i); - fprintf(f, "m: [%f] !=3D a: [%f]\n", - m->fpregs[i], a->fpregs[i]); - } - } - - for (i =3D 0; i < 32; i++) { - if (m->vrregs.vrregs[i][0] !=3D a->vrregs.vrregs[i][0] || - m->vrregs.vrregs[i][1] !=3D a->vrregs.vrregs[i][1] || - m->vrregs.vrregs[i][2] !=3D a->vrregs.vrregs[i][2] || - m->vrregs.vrregs[i][3] !=3D a->vrregs.vrregs[i][3]) { - - fprintf(f, "Mismatch: Register vr%d\n", i); - fprintf(f, "m: [%x, %x, %x, %x] !=3D a: [%x, %x, %x, %x]\n", - m->vrregs.vrregs[i][0], m->vrregs.vrregs[i][1], - m->vrregs.vrregs[i][2], m->vrregs.vrregs[i][3], - a->vrregs.vrregs[i][0], a->vrregs.vrregs[i][1], - a->vrregs.vrregs[i][2], a->vrregs.vrregs[i][3]); - } - } - return !ferror(f); -} diff --git a/risu_reginfo_ppc64le.h b/risu_reginfo_ppc64le.h deleted file mode 100644 index 826143e..0000000 --- a/risu_reginfo_ppc64le.h +++ /dev/null @@ -1,28 +0,0 @@ -/*************************************************************************= ***** - * Copyright (c) IBM Corp, 2016 - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * which accompanies this distribution, and is available at - * http://www.eclipse.org/legal/epl-v10.html - * - * Contributors: - * Jose Ricardo Ziviani - initial implementation - * based on Claudio Fontana's risu_reginfo_aarch64 - * based on Peter Maydell's risu_arm.c - *************************************************************************= ****/ - -#ifndef RISU_REGINFO_PPC64LE_H -#define RISU_REGINFO_PPC64LE_H - -struct reginfo -{ - uint32_t faulting_insn; - uint32_t prev_insn; - uint64_t nip; - uint64_t prev_addr; - gregset_t gregs; - fpregset_t fpregs; - vrregset_t vrregs; -}; - -#endif /* RISU_REGINFO_PPC64LE_H */ diff --git a/test_ppc64.s b/test_ppc64.s new file mode 100644 index 0000000..4af770c --- /dev/null +++ b/test_ppc64.s @@ -0,0 +1,49 @@ +/*************************************************************************= **** + * Copyright (c) IBM Corp, 2016 + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * Jose Ricardo Ziviani - ppc64le implementation + * based on Claudio Fontana + * based on test_arm.s by Peter Maydell + *************************************************************************= ****/ + +/* Initialise the gp regs */ +li 0, 0 +li 2, 2 +li 3, 3 +li 4, 4 +li 5, 5 +li 6, 6 +li 7, 7 +li 8, 8 +li 9, 9 +li 10, 10 +li 11, 11 +li 12, 12 +li 14, 14 +li 15, 15 +li 16, 16 +li 17, 17 +li 18, 18 +li 19, 19 +li 20, 20 +li 21, 21 +li 22, 22 +li 23, 23 +li 24, 24 +li 25, 25 +li 26, 26 +li 27, 27 +li 28, 28 +li 29, 29 +li 30, 30 +li 31, 31 + +/* do compare */ +.int 0x00005af0 +/* exit test */ +.int 0x00005af1 diff --git a/test_ppc64le.s b/test_ppc64le.s deleted file mode 100644 index 4af770c..0000000 --- a/test_ppc64le.s +++ /dev/null @@ -1,49 +0,0 @@ -/*************************************************************************= **** - * Copyright (c) IBM Corp, 2016 - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * which accompanies this distribution, and is available at - * http://www.eclipse.org/legal/epl-v10.html - * - * Contributors: - * Jose Ricardo Ziviani - ppc64le implementation - * based on Claudio Fontana - * based on test_arm.s by Peter Maydell - *************************************************************************= ****/ - -/* Initialise the gp regs */ -li 0, 0 -li 2, 2 -li 3, 3 -li 4, 4 -li 5, 5 -li 6, 6 -li 7, 7 -li 8, 8 -li 9, 9 -li 10, 10 -li 11, 11 -li 12, 12 -li 14, 14 -li 15, 15 -li 16, 16 -li 17, 17 -li 18, 18 -li 19, 19 -li 20, 20 -li 21, 21 -li 22, 22 -li 23, 23 -li 24, 24 -li 25, 25 -li 26, 26 -li 27, 27 -li 28, 28 -li 29, 29 -li 30, 30 -li 31, 31 - -/* do compare */ -.int 0x00005af0 -/* exit test */ -.int 0x00005af1 --=20 2.7.4