From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491924810324910.922599548173; Tue, 11 Apr 2017 08:33:30 -0700 (PDT) Received: from localhost ([::1]:39794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxnL-0000bF-3g for importer@patchew.org; Tue, 11 Apr 2017 11:33:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxkV-0006YX-V1 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxkS-0003YQ-PB for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:31 -0400 Received: from 5.mo173.mail-out.ovh.net ([46.105.40.148]:43511) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxkS-0003Wb-GK for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:28 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 1559D313C5 for ; Tue, 11 Apr 2017 17:30:27 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id EDC111800D3; Tue, 11 Apr 2017 17:30:20 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:29:59 +0200 Message-Id: <1491924606-20026-2-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17767544957382593510 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.40.148 Subject: [Qemu-devel] [PATCH v3 1/8] ppc/pnv: Add support for POWER8+ LPC Controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset - moved the IRQ handler in pnv_lpc.c - introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ] Signed-off-by: C=C3=A9dric Le Goater --- Changes since v2: - used PNV_LPC() macro to cast the 'opaque' parameter Changes since v1: - moved the IRQ handler in pnv_lpc.c - introduced pnv_lpc_isa_irq_create() to create the ISA IRQs=20 hw/ppc/pnv.c | 45 +++------------------- hw/ppc/pnv_lpc.c | 97 ++++++++++++++++++++++++++++++++++++++++++++= +++- include/hw/ppc/pnv_lpc.h | 8 ++++ 3 files changed, 108 insertions(+), 42 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 16f32c9bbd9d..27589b91d1cf 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -346,36 +346,6 @@ static void ppc_powernv_reset(void) cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); } =20 -/* If we don't use the built-in LPC interrupt deserializer, we need - * to provide a set of qirqs for the ISA bus or things will go bad. - * - * Most machines using pre-Naples chips (without said deserializer) - * have a CPLD that will collect the SerIRQ and shoot them as a - * single level interrupt to the P8 chip. So let's setup a hook - * for doing just that. - */ -static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) -{ - PnvMachineState *pnv =3D POWERNV_MACHINE(qdev_get_machine()); - uint32_t old_state =3D pnv->cpld_irqstate; - PnvChip *chip =3D opaque; - - if (level) { - pnv->cpld_irqstate |=3D 1u << n; - } else { - pnv->cpld_irqstate &=3D ~(1u << n); - } - if (pnv->cpld_irqstate !=3D old_state) { - pnv_psi_irq_set(&chip->psi, PSIHB_IRQ_EXTERNAL, - pnv->cpld_irqstate !=3D 0); - } -} - -static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) -{ - /* XXX TODO */ -} - static ISABus *pnv_isa_create(PnvChip *chip) { PnvLpcController *lpc =3D &chip->lpc; @@ -390,16 +360,7 @@ static ISABus *pnv_isa_create(PnvChip *chip) isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &error_fatal); =20 - /* Not all variants have a working serial irq decoder. If not, - * handling of LPC interrupts becomes a platform issue (some - * platforms have a CPLD to do it). - */ - if (pcc->chip_type =3D=3D PNV_CHIP_POWER8NVL) { - irqs =3D qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM= _IRQS); - } else { - irqs =3D qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip, - ISA_NUM_IRQS); - } + irqs =3D pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); =20 isa_bus_irqs(isa_bus, irqs); return isa_bus; @@ -699,6 +660,10 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); + + /* The LPC controller needs PSI to generate interrupts */ + object_property_add_const_link(OBJECT(&chip->lpc), "psi", + OBJECT(&chip->psi), &error_abort); } =20 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 78db52415b11..5d20c15e6729 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 +static void pnv_lpc_eval_irqs(PnvLpcController *lpc) +{ + bool lpc_to_opb_irq =3D false; + + /* Update LPC controller to OPB line */ + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { + uint32_t irqs; + + irqs =3D lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; + lpc_to_opb_irq =3D (irqs !=3D 0); + } + + /* We don't honor the polarity register, it's pointless and unused + * anyway + */ + if (lpc_to_opb_irq) { + lpc->opb_irq_input |=3D OPB_MASTER_IRQ_LPC; + } else { + lpc->opb_irq_input &=3D ~OPB_MASTER_IRQ_LPC; + } + + /* Update OPB internal latch */ + lpc->opb_irq_stat |=3D lpc->opb_irq_input & lpc->opb_irq_mask; + + /* Reflect the interrupt */ + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat !=3D 0); +} + static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) { PnvLpcController *lpc =3D opaque; @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, u= int64_t val, break; case LPC_HC_IRQSER_CTRL: lpc->lpc_hc_irqser_ctrl =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQMASK: lpc->lpc_hc_irqmask =3D val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQSTAT: lpc->lpc_hc_irqstat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_ERROR_ADDRESS: break; @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr add= r, switch (addr) { case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &=3D ~val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_MASK: - /* XXX Filter out reserved bits */ lpc->opb_irq_mask =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_POL: - /* XXX Filter out reserved bits */ lpc->opb_irq_pol =3D val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_INPUT: /* Read only */ @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops =3D { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc =3D PNV_LPC(dev); + Object *obj; + Error *error =3D NULL; =20 /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size =3D LPC_HC_FW_RD_4B; @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **= errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); + + /* get PSI object from chip */ + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + lpc->psi =3D PNV_PSI(obj); } =20 static void pnv_lpc_class_init(ObjectClass *klass, void *data) @@ -470,3 +513,53 @@ static void pnv_lpc_register_types(void) } =20 type_init(pnv_lpc_register_types) + +/* If we don't use the built-in LPC interrupt deserializer, we need + * to provide a set of qirqs for the ISA bus or things will go bad. + * + * Most machines using pre-Naples chips (without said deserializer) + * have a CPLD that will collect the SerIRQ and shoot them as a + * single level interrupt to the P8 chip. So let's setup a hook + * for doing just that. + */ +static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(qdev_get_machine()); + uint32_t old_state =3D pnv->cpld_irqstate; + PnvLpcController *lpc =3D PNV_LPC(opaque); + + if (level) { + pnv->cpld_irqstate |=3D 1u << n; + } else { + pnv->cpld_irqstate &=3D ~(1u << n); + } + + if (pnv->cpld_irqstate !=3D old_state) { + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != =3D 0); + } +} + +static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) +{ + PnvLpcController *lpc =3D PNV_LPC(opaque); + + /* The Naples HW latches the 1 levels, clearing is done by SW */ + if (level) { + lpc->lpc_hc_irqstat |=3D LPC_HC_IRQ_SERIRQ0 >> n; + pnv_lpc_eval_irqs(lpc); + } +} + +qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, + int nirqs) +{ + /* Not all variants have a working serial irq decoder. If not, + * handling of LPC interrupts becomes a platform issue (some + * platforms have a CPLD to do it). + */ + if (chip_type =3D=3D PNV_CHIP_POWER8NVL) { + return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs); + } else { + return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs= ); + } +} diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506975aa..ccf969af9448 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) =20 +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; =20 @@ -62,6 +64,12 @@ typedef struct PnvLpcController { =20 /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; =20 +qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, + int nirqs); + #endif /* _PPC_PNV_LPC_H */ --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491924914552512.6961258220146; Tue, 11 Apr 2017 08:35:14 -0700 (PDT) Received: from localhost ([::1]:39804 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxp3-0001yY-6D for importer@patchew.org; Tue, 11 Apr 2017 11:35:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38148) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxka-0006dM-71 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxkX-0003bm-2R for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:36 -0400 Received: from 4.mo173.mail-out.ovh.net ([46.105.34.219]:55037) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxkW-0003ax-Sd for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:33 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 85793313B4 for ; Tue, 11 Apr 2017 17:30:31 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 22A331800C5; Tue, 11 Apr 2017 17:30:27 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:00 +0200 Message-Id: <1491924606-20026-3-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17768670857253522406 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.34.219 Subject: [Qemu-devel] [PATCH v3 2/8] ppc/pnv: enable only one LPC bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The default LPC bus of a multichip system is on chip 0. It's recognized by the firmware (skiboot) using a "primary" property in the device tree. We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of a chip and set the property directly from the machine level. Signed-off-by: C=C3=A9dric Le Goater --- Changes since v2: - introduced a pnv_chip_lpc_offset() routine to locate the lpc node of a chip in the device tree and set the property from the machine =20 Changes since v1: - the device tree is populated for all LPC busses of the system but only the one on chip 0 has the "primary" property. hw/ppc/pnv.c | 22 ++++++++++++++++++++++ hw/ppc/pnv_lpc.c | 9 --------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 27589b91d1cf..9468e991bfb2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -255,6 +255,18 @@ static void powernv_populate_icp(PnvChip *chip, void *= fdt, uint32_t pir, g_free(reg); } =20 +static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) +{ + char *name; + int offset; + + name =3D g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", + (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_= BASE); + offset =3D fdt_path_offset(fdt, name); + g_free(name); + return offset; +} + static void powernv_populate_chip(PnvChip *chip, void *fdt) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); @@ -264,6 +276,16 @@ static void powernv_populate_chip(PnvChip *chip, void = *fdt) =20 pnv_xscom_populate(chip, fdt, 0); =20 + /* The default LPC bus of a multichip system is on chip 0. It's + * recognized by the firmware (skiboot) using a "primary" + * property. + */ + if (chip->chip_id =3D=3D 0x0) { + int lpc_offset =3D pnv_chip_lpc_offset(chip, fdt); + + _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); + } + for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); =20 diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 5d20c15e6729..f03a80a29bf6 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -92,14 +92,6 @@ enum { #define LPC_HC_REGS_OPB_SIZE 0x00001000 =20 =20 -/* - * TODO: the "primary" cell should only be added on chip 0. This is - * how skiboot chooses the default LPC controller on multichip - * systems. - * - * It would be easly done if we can change the populate() interface to - * replace the PnvXScomInterface parameter by a PnvChip one - */ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { const char compat[] =3D "ibm,power8-lpc\0ibm,lpc"; @@ -119,7 +111,6 @@ static int pnv_lpc_populate(PnvXScomInterface *dev, voi= d *fdt, int xscom_offset) _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); - _FDT((fdt_setprop(fdt, offset, "primary", NULL, 0))); _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); return 0; } --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491924897345417.81410649920065; Tue, 11 Apr 2017 08:34:57 -0700 (PDT) Received: from localhost ([::1]:39800 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxom-0001jm-1f for importer@patchew.org; Tue, 11 Apr 2017 11:34:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxkg-0006jQ-G2 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxkd-0003et-BE for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:42 -0400 Received: from 8.mo173.mail-out.ovh.net ([46.105.46.122]:36343) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxkc-0003di-Pu for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:39 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 4235D31468 for ; Tue, 11 Apr 2017 17:30:36 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 9481F18009E; Tue, 11 Apr 2017 17:30:31 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:01 +0200 Message-Id: <1491924606-20026-4-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17770078231068117990 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.46.122 Subject: [Qemu-devel] [PATCH v3 3/8] ppc/pnv: scan ISA bus to populate device tree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This is an empty shell that we will use to include nodes in the device tree for ISA devices. We expect RTC, UART and IPMI BT devices. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- Changes since v2: - used the pnv_chip_lpc_offset() routine to locate the lpc node of chip 0 in the device tree. This is more precise than looking for a "ibm,lpc" compatible property. =20 hw/ppc/pnv.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 9468e991bfb2..c445906358d7 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -303,6 +303,29 @@ static void powernv_populate_chip(PnvChip *chip, void = *fdt) g_free(typename); } =20 +typedef struct ForeachPopulateArgs { + void *fdt; + int offset; +} ForeachPopulateArgs; + +static int powernv_populate_isa_device(DeviceState *dev, void *opaque) +{ + return 0; +} + +static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset) +{ + ForeachPopulateArgs args =3D { + .fdt =3D fdt, + .offset =3D lpc_offset, + }; + + /* ISA devices are not necessarily parented to the ISA bus so we + * can not use object_child_foreach() */ + qbus_walk_children(BUS(bus), powernv_populate_isa_device, + NULL, NULL, NULL, &args); +} + static void *powernv_create_fdt(MachineState *machine) { const char plat_compat[] =3D "qemu,powernv\0ibm,powernv"; @@ -311,6 +334,7 @@ static void *powernv_create_fdt(MachineState *machine) char *buf; int off; int i; + int lpc_offset; =20 fdt =3D g_malloc0(FDT_MAX_SIZE); _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); @@ -350,6 +374,10 @@ static void *powernv_create_fdt(MachineState *machine) for (i =3D 0; i < pnv->num_chips; i++) { powernv_populate_chip(pnv->chips[i], fdt); } + + /* Populate ISA devices on chip 0 */ + lpc_offset =3D pnv_chip_lpc_offset(pnv->chips[0], fdt); + powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset); return fdt; } =20 --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491924897058365.5254176787457; Tue, 11 Apr 2017 08:34:57 -0700 (PDT) Received: from localhost ([::1]:39801 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxol-0001ll-JS for importer@patchew.org; Tue, 11 Apr 2017 11:34:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxkk-0006me-4Y for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxkg-0003gp-11 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:46 -0400 Received: from 7.mo173.mail-out.ovh.net ([46.105.44.159]:55155) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxkf-0003g6-NL for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:41 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id ADB9631169 for ; Tue, 11 Apr 2017 17:30:40 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 5037818009E; Tue, 11 Apr 2017 17:30:36 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:02 +0200 Message-Id: <1491924606-20026-5-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17771204132432219110 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.44.159 Subject: [Qemu-devel] [PATCH v3 4/8] ppc/pnv: populate device tree for RTC devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The code could be common to any ISA device but we are missing the IO length. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/ppc/pnv.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c445906358d7..8ab5bb179b2c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -303,6 +303,26 @@ static void powernv_populate_chip(PnvChip *chip, void = *fdt) g_free(typename); } =20 +static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) +{ + uint32_t io_base =3D d->ioport_id; + uint32_t io_regs[] =3D { + cpu_to_be32(1), + cpu_to_be32(io_base), + cpu_to_be32(2) + }; + char *name; + int node; + + name =3D g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); + node =3D fdt_add_subnode(fdt, lpc_off, name); + _FDT(node); + g_free(name); + + _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); + _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); +} + typedef struct ForeachPopulateArgs { void *fdt; int offset; @@ -310,6 +330,16 @@ typedef struct ForeachPopulateArgs { =20 static int powernv_populate_isa_device(DeviceState *dev, void *opaque) { + ForeachPopulateArgs *args =3D opaque; + ISADevice *d =3D ISA_DEVICE(dev); + + if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { + powernv_populate_rtc(d, args->fdt, args->offset); + } else { + error_report("unknown isa device %s@i%x", qdev_fw_name(dev), + d->ioport_id); + } + return 0; } =20 --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491925053835502.25980841372643; Tue, 11 Apr 2017 08:37:33 -0700 (PDT) Received: from localhost ([::1]:39825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxrF-0003uC-7Y for importer@patchew.org; Tue, 11 Apr 2017 11:37:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxkm-0006od-33 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxkl-0003iu-0S for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:48 -0400 Received: from 7.mo173.mail-out.ovh.net ([46.105.44.159]:38439) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxkk-0003iJ-Ow for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:46 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 4A3D93134C for ; Tue, 11 Apr 2017 17:30:45 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id BD3B31800B0; Tue, 11 Apr 2017 17:30:40 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:03 +0200 Message-Id: <1491924606-20026-6-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17772611507439176678 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.44.159 Subject: [Qemu-devel] [PATCH v3 5/8] ppc/pnv: populate device tree for serial devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- hw/ppc/pnv.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 8ab5bb179b2c..dfa21e4d740a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -323,6 +323,37 @@ static void powernv_populate_rtc(ISADevice *d, void *f= dt, int lpc_off) _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); } =20 +static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off) +{ + const char compatible[] =3D "ns16550\0pnpPNP,501"; + uint32_t io_base =3D d->ioport_id; + uint32_t io_regs[] =3D { + cpu_to_be32(1), + cpu_to_be32(io_base), + cpu_to_be32(8) + }; + char *name; + int node; + + name =3D g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); + node =3D fdt_add_subnode(fdt, lpc_off, name); + _FDT(node); + g_free(name); + + _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); + _FDT((fdt_setprop(fdt, node, "compatible", compatible, + sizeof(compatible)))); + + _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); + _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); + _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); + _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", + fdt_get_phandle(fdt, lpc_off)))); + + /* This is needed by Linux */ + _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); +} + typedef struct ForeachPopulateArgs { void *fdt; int offset; @@ -335,6 +366,8 @@ static int powernv_populate_isa_device(DeviceState *dev= , void *opaque) =20 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { powernv_populate_rtc(d, args->fdt, args->offset); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { + powernv_populate_serial(d, args->fdt, args->offset); } else { error_report("unknown isa device %s@i%x", qdev_fw_name(dev), d->ioport_id); --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491925208873501.16021456153237; Tue, 11 Apr 2017 08:40:08 -0700 (PDT) Received: from localhost ([::1]:39836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxtn-0006WK-LP for importer@patchew.org; Tue, 11 Apr 2017 11:40:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxks-0006v0-7E for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxkp-0003lY-3r for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:54 -0400 Received: from 9.mo173.mail-out.ovh.net ([46.105.72.44]:43472) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxko-0003kX-TJ for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:30:51 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id DE24F3144A for ; Tue, 11 Apr 2017 17:30:49 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id 5B9051800AB; Tue, 11 Apr 2017 17:30:45 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:04 +0200 Message-Id: <1491924606-20026-7-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17773737408461310950 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.72.44 Subject: [Qemu-devel] [PATCH v3 6/8] ppc/pnv: populate device tree for IPMI BT devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When an ipmi-bt device [1] is defined on the ISA bus, we need to populate the device tree with the object properties. Such devices are created with the command line options : -device ipmi-bmc-sim,id=3Dbmc0 -device isa-ipmi-bt,bmc=3Dbmc0,irq=3D10 [1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg03168.html Signed-off-by: C=C3=A9dric Le Goater --- Changes sinve v2: - removed the initializer of io_base Changes sinve v1: - reworked the assignement of the ISA IO base in the 'reg' array property =20 hw/ppc/pnv.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index dfa21e4d740a..977e126aca2c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -354,6 +354,39 @@ static void powernv_populate_serial(ISADevice *d, void= *fdt, int lpc_off) _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); } =20 +static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) +{ + const char compatible[] =3D "bt\0ipmi-bt"; + uint32_t io_base; + uint32_t io_regs[] =3D { + cpu_to_be32(1), + 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-= bt' */ + cpu_to_be32(3) + }; + uint32_t irq; + char *name; + int node; + + io_base =3D object_property_get_int(OBJECT(d), "ioport", &error_fatal); + io_regs[1] =3D cpu_to_be32(io_base); + + irq =3D object_property_get_int(OBJECT(d), "irq", &error_fatal); + + name =3D g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); + node =3D fdt_add_subnode(fdt, lpc_off, name); + _FDT(node); + g_free(name); + + fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)); + fdt_setprop(fdt, node, "compatible", compatible, sizeof(compatible)); + + /* Mark it as reserved to avoid Linux trying to claim it */ + _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); + _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); + _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", + fdt_get_phandle(fdt, lpc_off)))); +} + typedef struct ForeachPopulateArgs { void *fdt; int offset; @@ -368,6 +401,8 @@ static int powernv_populate_isa_device(DeviceState *dev= , void *opaque) powernv_populate_rtc(d, args->fdt, args->offset); } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { powernv_populate_serial(d, args->fdt, args->offset); + } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { + powernv_populate_ipmi_bt(d, args->fdt, args->offset); } else { error_report("unknown isa device %s@i%x", qdev_fw_name(dev), d->ioport_id); --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491925202056268.26460644495955; Tue, 11 Apr 2017 08:40:02 -0700 (PDT) Received: from localhost ([::1]:39834 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxtg-0006OB-B9 for importer@patchew.org; Tue, 11 Apr 2017 11:40:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxl1-00073h-PC for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:31:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxky-0003uC-L3 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:31:03 -0400 Received: from 10.mo173.mail-out.ovh.net ([46.105.74.148]:38319) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxky-0003tb-Aw for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:31:00 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id E2A1F3144A for ; Tue, 11 Apr 2017 17:30:54 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id EF6C91800AB; Tue, 11 Apr 2017 17:30:49 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:05 +0200 Message-Id: <1491924606-20026-8-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17775144782444530662 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.74.148 Subject: [Qemu-devel] [PATCH v3 7/8] ppc/pnv: add initial IPMI sensors for the BMC simulator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Skiboot, the firmware for the PowerNV platform, expects the BMC to provide some specific IPMI sensors. These sensors are exposed in the device tree and their values are updated by the firmware at boot time. Sensors of interest are : "FW Boot Progress" "Boot Count" As such a device is defined on the command line, we can only detect its presence at reset time. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- Changes since v1: - fixed test on sdr->header.rec_type which was incorrect - changed the type of the 'bmc' attribute of the machine and changed accordingly the prototype of the helper routines hw/ppc/Makefile.objs | 2 +- hw/ppc/pnv.c | 21 ++++++++++++++ hw/ppc/pnv_bmc.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/pnv.h | 9 ++++++ 4 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 hw/ppc/pnv_bmc.c diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index ef67ea820158..7efc68674819 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o spap= r_rtas.o obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o spapr_ovec.o # IBM PowerNV -obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.= o pnv_occ.o +obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.= o pnv_occ.o pnv_bmc.o ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) obj-y +=3D spapr_pci_vfio.o endif diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 977e126aca2c..685eb122d20c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -35,6 +35,7 @@ #include "qapi/visitor.h" #include "monitor/monitor.h" #include "hw/intc/intc.h" +#include "hw/ipmi/ipmi.h" =20 #include "hw/ppc/xics.h" #include "hw/ppc/pnv_xscom.h" @@ -476,16 +477,36 @@ static void *powernv_create_fdt(MachineState *machine) /* Populate ISA devices on chip 0 */ lpc_offset =3D pnv_chip_lpc_offset(pnv->chips[0], fdt); powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset); + + if (pnv->bmc) { + pnv_bmc_populate_sensors(pnv->bmc, fdt); + } + return fdt; } =20 static void ppc_powernv_reset(void) { MachineState *machine =3D MACHINE(qdev_get_machine()); + PnvMachineState *pnv =3D POWERNV_MACHINE(machine); void *fdt; + Object *obj; =20 qemu_devices_reset(); =20 + /* OpenPOWER systems have a BMC, which can be defined on the + * command line with: + * + * -device ipmi-bmc-sim,id=3Dbmc0 + * + * This is the internal simulator but it could also be an external + * BMC. + */ + obj =3D object_resolve_path_type("", TYPE_IPMI_BMC, NULL); + if (obj) { + pnv->bmc =3D IPMI_BMC(obj); + } + fdt =3D powernv_create_fdt(machine); =20 /* Pack resulting tree */ diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c new file mode 100644 index 000000000000..a0820dca559b --- /dev/null +++ b/hw/ppc/pnv_bmc.c @@ -0,0 +1,81 @@ +/* + * QEMU PowerNV, BMC related functions + * + * Copyright (c) 2016-2017, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "sysemu/sysemu.h" +#include "target/ppc/cpu.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/ipmi/ipmi.h" +#include "hw/ppc/fdt.h" + +#include "hw/ppc/pnv.h" + +#include + +/* TODO: include definition in ipmi.h */ +#define IPMI_SDR_FULL_TYPE 1 + +void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt) +{ + int offset; + int i; + const struct ipmi_sdr_compact *sdr; + uint16_t nextrec; + + offset =3D fdt_add_subnode(fdt, 0, "/bmc"); + _FDT(offset); + + _FDT((fdt_setprop_string(fdt, offset, "name", "bmc"))); + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1))); + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0))); + + offset =3D fdt_add_subnode(fdt, offset, "sensors"); + _FDT(offset); + + _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0x1))); + _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0x0))); + + for (i =3D 0; !ipmi_bmc_sdr_find(bmc, i, &sdr, &nextrec); i++) { + int off; + char *name; + + if (sdr->header.rec_type !=3D IPMI_SDR_COMPACT_TYPE && + sdr->header.rec_type !=3D IPMI_SDR_FULL_TYPE) { + continue; + } + + name =3D g_strdup_printf("sensor@%x", sdr->sensor_owner_number); + off =3D fdt_add_subnode(fdt, offset, name); + _FDT(off); + g_free(name); + + _FDT((fdt_setprop_cell(fdt, off, "reg", sdr->sensor_owner_number))= ); + _FDT((fdt_setprop_string(fdt, off, "name", "sensor"))); + _FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,ipmi-sensor"= ))); + _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-reading-type", + sdr->reading_type))); + _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-id", + sdr->entity_id))); + _FDT((fdt_setprop_cell(fdt, off, "ipmi-entity-instance", + sdr->entity_instance))); + _FDT((fdt_setprop_cell(fdt, off, "ipmi-sensor-type", + sdr->sensor_type))); + } +} diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index b45a0d91c813..02f6cf565ca4 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -118,6 +118,8 @@ typedef struct PnvChipClass { #define POWERNV_MACHINE(obj) \ OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) =20 +typedef struct IPMIBmc IPMIBmc; + typedef struct PnvMachineState { /*< private >*/ MachineState parent_obj; @@ -130,12 +132,19 @@ typedef struct PnvMachineState { =20 ISABus *isa_bus; uint32_t cpld_irqstate; + + IPMIBmc *bmc; } PnvMachineState; =20 #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL =20 /* + * BMC helpers + */ +void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt); + +/* * POWER8 MMIO base addresses */ #define PNV_XSCOM_SIZE 0x800000000ull --=20 2.7.4 From nobody Sun Apr 28 06:52:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1491925059234355.44145908102007; Tue, 11 Apr 2017 08:37:39 -0700 (PDT) Received: from localhost ([::1]:39826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxrN-00044X-JO for importer@patchew.org; Tue, 11 Apr 2017 11:37:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cxxl1-00073l-Q6 for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:31:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cxxky-0003uJ-LS for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:31:03 -0400 Received: from 2.mo173.mail-out.ovh.net ([178.33.251.49]:44312) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cxxky-0003te-Da for qemu-devel@nongnu.org; Tue, 11 Apr 2017 11:31:00 -0400 Received: from player778.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 33B9431543 for ; Tue, 11 Apr 2017 17:30:59 +0200 (CEST) Received: from zorba.ttt.fr.ibm.com (deibp9eh1--blueice3n3.emea.ibm.com [195.212.29.181]) (Authenticated sender: clg@kaod.org) by player778.ha.ovh.net (Postfix) with ESMTPSA id A4D541800D3; Tue, 11 Apr 2017 17:30:54 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Tue, 11 Apr 2017 17:30:06 +0200 Message-Id: <1491924606-20026-9-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491924606-20026-1-git-send-email-clg@kaod.org> References: <1491924606-20026-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17776552158257908710 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrudeggdekjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.251.49 Subject: [Qemu-devel] [PATCH v3 8/8] ppc/pnv: generate an OEM SEL event on shutdown X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" OpenPOWER systems expect to be notified with such an event before a shutdown or a reboot. An OEM SEL message is sent with specific identifiers and a user data containing the request : OFF or REBOOT. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: David Gibson --- Changes since v1: - changed the prototype of the helper routine hw/ppc/pnv.c | 14 ++++++++++++++ hw/ppc/pnv_bmc.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv.h | 2 ++ 3 files changed, 57 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 685eb122d20c..d4bcdb027f7c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -485,6 +485,15 @@ static void *powernv_create_fdt(MachineState *machine) return fdt; } =20 +static void pnv_powerdown_notify(Notifier *n, void *opaque) +{ + PnvMachineState *pnv =3D POWERNV_MACHINE(qdev_get_machine()); + + if (pnv->bmc) { + pnv_bmc_powerdown(pnv->bmc); + } +} + static void ppc_powernv_reset(void) { MachineState *machine =3D MACHINE(qdev_get_machine()); @@ -638,6 +647,11 @@ static void ppc_powernv_init(MachineState *machine) =20 /* Create an RTC ISA device too */ rtc_init(pnv->isa_bus, 2000, NULL); + + /* OpenPOWER systems use a IPMI SEL Event message to notify the + * host to powerdown */ + pnv->powerdown_notifier.notify =3D pnv_powerdown_notify; + qemu_register_powerdown_notifier(&pnv->powerdown_notifier); } =20 /* diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index a0820dca559b..7b60b4c36071 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -32,6 +32,47 @@ /* TODO: include definition in ipmi.h */ #define IPMI_SDR_FULL_TYPE 1 =20 +/* + * OEM SEL Event data packet sent by BMC in response of a Read Event + * Message Buffer command + */ +typedef struct OemSel { + /* SEL header */ + uint8_t id[2]; + uint8_t type; + uint8_t timestamp[4]; + uint8_t manuf_id[3]; + + /* OEM SEL data (6 bytes) follows */ + uint8_t netfun; + uint8_t cmd; + uint8_t data[4]; +} OemSel; + +#define SOFT_OFF 0x00 +#define SOFT_REBOOT 0x01 + +static void pnv_gen_oem_sel(IPMIBmc *bmc, uint8_t reboot) +{ + /* IPMI SEL Event are 16 bytes long */ + OemSel sel =3D { + .id =3D { 0x55 , 0x55 }, + .type =3D 0xC0, /* OEM */ + .manuf_id =3D { 0x0, 0x0, 0x0 }, + .timestamp =3D { 0x0, 0x0, 0x0, 0x0 }, + .netfun =3D 0x3A, /* IBM */ + .cmd =3D 0x04, /* AMI OEM SEL Power Notification */ + .data =3D { reboot, 0xFF, 0xFF, 0xFF }, + }; + + ipmi_bmc_gen_event(bmc, (uint8_t *) &sel, 0 /* do not log the event */= ); +} + +void pnv_bmc_powerdown(IPMIBmc *bmc) +{ + pnv_gen_oem_sel(bmc, SOFT_OFF); +} + void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt) { int offset; diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 02f6cf565ca4..c1288f974d4a 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -134,6 +134,7 @@ typedef struct PnvMachineState { uint32_t cpld_irqstate; =20 IPMIBmc *bmc; + Notifier powerdown_notifier; } PnvMachineState; =20 #define PNV_FDT_ADDR 0x01000000 @@ -143,6 +144,7 @@ typedef struct PnvMachineState { * BMC helpers */ void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt); +void pnv_bmc_powerdown(IPMIBmc *bmc); =20 /* * POWER8 MMIO base addresses --=20 2.7.4