From nobody Tue Apr 30 01:55:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1490700483435601.0757858816576; Tue, 28 Mar 2017 04:28:03 -0700 (PDT) Received: from localhost ([::1]:52499 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cspIA-0004Bl-Ci for importer@patchew.org; Tue, 28 Mar 2017 07:28:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52709) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cspH1-0003U2-Nv for qemu-devel@nongnu.org; Tue, 28 Mar 2017 07:26:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cspGy-00013I-FL for qemu-devel@nongnu.org; Tue, 28 Mar 2017 07:26:51 -0400 Received: from mx2.suse.de ([195.135.220.15]:44391) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cspGy-00012s-55 for qemu-devel@nongnu.org; Tue, 28 Mar 2017 07:26:48 -0400 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 26AD1AE10; Tue, 28 Mar 2017 11:26:47 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Alexander Graf To: qemu-devel@nongnu.org Date: Tue, 28 Mar 2017 13:27:06 +0200 Message-Id: <1490700426-222115-1-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.8.5.6 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] [fuzzy] X-Received-From: 195.135.220.15 Subject: [Qemu-devel] [PATCH v2] i386: Allow cpuid bit override X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" KVM has a feature bitmap of CPUID bits that it knows works for guests. QEMU removes bits that are not part of that bitmap automatically on VM start. However, some times we just don't list features in that list because they don't make sense for normal scenarios, but may be useful in specific, targeted workloads. For that purpose, add a new =3Dforce option to all CPUID feature flags in the CPU property. With that we can override the accel filtering and give users full control over the CPUID feature bits exposed into guests. Signed-off-by: Alexander Graf --- v1 -> v2: - Base on "i386: Replace uint32_t* with FeatureWord on feature getter/set= ter" --- target/i386/cpu.c | 25 ++++++++++++++++++++++--- target/i386/cpu.h | 3 +++ 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 13c0985..6105fc5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2229,7 +2229,7 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_fprin= tf) g_slist_foreach(list, x86_cpu_list_entry, &s); g_slist_free(list); =20 - (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n"); + (*cpu_fprintf)(f, "\nRecognized CPUID flags (=3Don|=3Doff|=3Dforce):\n= "); for (i =3D 0; i < ARRAY_SIZE(feature_word_info); i++) { FeatureWordInfo *fw =3D &feature_word_info[i]; =20 @@ -3464,6 +3464,7 @@ static int x86_cpu_filter_features(X86CPU *cpu) x86_cpu_get_supported_feature_word(w, false); uint32_t requested_features =3D env->features[w]; env->features[w] &=3D host_feat; + env->features[w] |=3D cpu->forced_features[w]; cpu->filtered_features[w] =3D requested_features & ~env->features[= w]; if (cpu->filtered_features[w]) { rv =3D 1; @@ -3706,8 +3707,17 @@ static void x86_cpu_get_bit_prop(Object *obj, Visito= r *v, const char *name, X86CPU *cpu =3D X86_CPU(obj); BitProperty *fp =3D opaque; uint32_t f =3D cpu->env.features[fp->w]; + uint32_t ff =3D cpu->forced_features[fp->w]; bool value =3D (f & fp->mask) =3D=3D fp->mask; - visit_type_bool(v, name, &value, errp); + bool forced =3D (ff & fp->mask) =3D=3D fp->mask; + char str[] =3D "force"; + char *strval =3D str; + + if (forced) { + visit_type_str(v, name, &strval, errp); + } else { + visit_type_bool(v, name, &value, errp); + } } =20 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, @@ -3717,6 +3727,7 @@ static void x86_cpu_set_bit_prop(Object *obj, Visitor= *v, const char *name, X86CPU *cpu =3D X86_CPU(obj); BitProperty *fp =3D opaque; Error *local_err =3D NULL; + char *strval =3D NULL; bool value; =20 if (dev->realized) { @@ -3724,7 +3735,15 @@ static void x86_cpu_set_bit_prop(Object *obj, Visito= r *v, const char *name, return; } =20 - visit_type_bool(v, name, &value, &local_err); + visit_type_str(v, name, &strval, &local_err); + if (!local_err && !strcmp(strval, "force")) { + value =3D true; + cpu->forced_features[fp->w] |=3D fp->mask; + } else { + local_err =3D NULL; + visit_type_bool(v, name, &value, &local_err); + } + if (local_err) { error_propagate(errp, local_err); return; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c4602ca..69efe6c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1230,6 +1230,9 @@ struct X86CPU { /* Features that were filtered out because of missing host capabilitie= s */ uint32_t filtered_features[FEATURE_WORDS]; =20 + /* Features that are force enabled despite incompatible accel */ + uint32_t forced_features[FEATURE_WORDS]; + /* Enable PMU CPUID bits. This can't be enabled by default yet because * it doesn't have ABI stability guarantees, as it passes all PMU CPUID * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and k= ernel --=20 1.8.5.6