From nobody Sat Sep 21 01:03:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487617803974274.27176147518253; Mon, 20 Feb 2017 11:10:03 -0800 (PST) Received: from localhost ([::1]:40562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftLW-00076X-Mu for importer@patchew.org; Mon, 20 Feb 2017 14:10:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftFo-0002S5-W4 for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cftFo-00068C-C5 for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:09 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48618) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cftFm-00064v-KE; Mon, 20 Feb 2017 14:04:06 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cfste-0005qA-9a; Mon, 20 Feb 2017 18:41:14 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 18:41:09 +0000 Message-Id: <1487616072-9226-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> References: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/4] arm: HVC and SMC encodings don't exist for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" M profile doesn't have the HVC or SMC encodings, so make them always UNDEF rather than generating calls to helper functions that assume A/R profile. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9fded03..895b399 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10365,6 +10365,9 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw goto illegal_op; =20 if (insn & (1 << 26)) { + if (arm_dc_feature(s, ARM_FEATURE_M)) { + goto illegal_op; + } if (!(insn & (1 << 20))) { /* Hypervisor call (v7) */ int imm16 =3D extract32(insn, 16, 4) << 12 --=20 2.7.4 From nobody Sat Sep 21 01:03:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487617576379795.9044120466899; Mon, 20 Feb 2017 11:06:16 -0800 (PST) Received: from localhost ([::1]:40542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftHo-0003gW-T3 for importer@patchew.org; Mon, 20 Feb 2017 14:06:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44222) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftFo-0002Rk-Jp for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cftFn-00067s-Rf for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:08 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48618) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cftFl-00064v-RE; Mon, 20 Feb 2017 14:04:05 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cfste-0005qQ-TT; Mon, 20 Feb 2017 18:41:14 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 18:41:10 +0000 Message-Id: <1487616072-9226-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> References: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/4] arm: Don't decode MRS(banked) or MSR(banked) for M profile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" M profile doesn't have the MSR(banked) and MRS(banked) instructions and uses the encodings for different kinds of M-profile MRS/MSR. Guard the relevant bits of the decode logic to make sure we don't accidentally fall into them by accident on M-profile. (The bit being checked for this (bit 5) is part of the SYSm field on M-profile, but since no currently allocated system registers have encodings with bit 5 of SYSm set, this hasn't been a problem in practice.) Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 895b399..0f8548f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10488,7 +10488,8 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw gen_exception_return(s, tmp); break; case 6: /* MRS */ - if (extract32(insn, 5, 1)) { + if (extract32(insn, 5, 1) && + !arm_dc_feature(s, ARM_FEATURE_M)) { /* MRS (banked) */ int sysm =3D extract32(insn, 16, 4) | (extract32(insn, 4, 1) << 4); @@ -10509,7 +10510,8 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw store_reg(s, rd, tmp); break; case 7: /* MRS */ - if (extract32(insn, 5, 1)) { + if (extract32(insn, 5, 1) && + !arm_dc_feature(s, ARM_FEATURE_M)) { /* MRS (banked) */ int sysm =3D extract32(insn, 16, 4) | (extract32(insn, 4, 1) << 4); --=20 2.7.4 From nobody Sat Sep 21 01:03:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487617771392977.5628539409878; Mon, 20 Feb 2017 11:09:31 -0800 (PST) Received: from localhost ([::1]:40561 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftL0-0006kr-6o for importer@patchew.org; Mon, 20 Feb 2017 14:09:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44196) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftFn-0002Qu-PK for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cftFn-00067O-2T for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:07 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48618) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cftFl-00064v-1m; Mon, 20 Feb 2017 14:04:05 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cfstf-0005qf-CG; Mon, 20 Feb 2017 18:41:15 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 18:41:11 +0000 Message-Id: <1487616072-9226-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> References: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/4] arm: Enforce should-be-1 bits in MRS decoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The MRS instruction requires that bits [19..16] are all 1s, and for A/R profile also that bits [7..0] are all 0s. At this point in the decode tree we have checked all of the rest of the instruction but were allowing these to be any value. If these bits are not set then the result is architecturally UNPREDICTABLE, but choosing to UNDEF is more helpful to the user and avoids unexpected odd behaviour if the encodings are used for some purpose in future architecture versions. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0f8548f..9090356 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10498,6 +10498,14 @@ static int disas_thumb2_insn(CPUARMState *env, Dis= asContext *s, uint16_t insn_hw break; } =20 + if (extract32(insn, 16, 4) !=3D 0xf) { + goto illegal_op; + } + if (!arm_dc_feature(s, ARM_FEATURE_M) && + extract32(insn, 0, 8) !=3D 0) { + goto illegal_op; + } + /* mrs cpsr */ tmp =3D tcg_temp_new_i32(); if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10525,6 +10533,12 @@ static int disas_thumb2_insn(CPUARMState *env, Dis= asContext *s, uint16_t insn_hw if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)= ) { goto illegal_op; } + + if (extract32(insn, 16, 4) !=3D 0xf || + extract32(insn, 0, 8) !=3D 0) { + goto illegal_op; + } + tmp =3D load_cpu_field(spsr); store_reg(s, rd, tmp); break; --=20 2.7.4 From nobody Sat Sep 21 01:03:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487617599156738.476611251531; Mon, 20 Feb 2017 11:06:39 -0800 (PST) Received: from localhost ([::1]:40545 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftID-00044F-SX for importer@patchew.org; Mon, 20 Feb 2017 14:06:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44171) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cftFn-0002QK-86 for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cftFm-00066t-Do for qemu-devel@nongnu.org; Mon, 20 Feb 2017 14:04:07 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48618) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cftFk-00064v-8I; Mon, 20 Feb 2017 14:04:04 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cfstf-0005r4-T5; Mon, 20 Feb 2017 18:41:15 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 20 Feb 2017 18:41:12 +0000 Message-Id: <1487616072-9226-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> References: <1487616072-9226-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/4] arm: Fix APSR writes via M profile MSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Our implementation of writes to the APSR for M-profile via the MSR instruction was badly broken. First and worst, we had the sense wrong on the test of bit 2 of the SYSm field -- this is supposed to request an APSR write if bit 2 is 0 but we were doing it if bit 2 was 1. This bug was introduced in commit 58117c9bb429cd, so hasn't been in a QEMU release. Secondly, the choice of exactly which parts of APSR should be written is defined by bits in the 'mask' field. We were not passing these through from instruction decode, making it impossible to check them in the helper. Pass the mask bits through from the instruction decode to the helper function and process them appropriately; fix the wrong sense of the SYSm bit 2 check. Invalid mask values and invalid combinations of mask and register number are UNPREDICTABLE; we choose to treat them as if the mask values were valid. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.c | 26 ++++++++++++++++++++++---- target/arm/translate.c | 3 ++- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 948aba2..8349e1f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8478,8 +8478,18 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t = reg) } } =20 -void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) -{ +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + /* We're passed bits [11..0] of the instruction; extract + * SYSm and the mask bits. + * Invalid combinations of SYSm and mask are UNPREDICTABLE; + * we choose to treat them as if the mask bits were valid. + * NB that the pseudocode 'mask' variable is bits [11..10], + * whereas ours is [11..8]. + */ + uint32_t mask =3D extract32(maskreg, 8, 4); + uint32_t reg =3D extract32(maskreg, 0, 8); + if (arm_current_el(env) =3D=3D 0 && reg > 7) { /* only xPSR sub-fields may be written by unprivileged */ return; @@ -8488,8 +8498,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg,= uint32_t val) switch (reg) { case 0 ... 7: /* xPSR sub-fields */ /* only APSR is actually writable */ - if (reg & 4) { - xpsr_write(env, val, 0xf8000000); /* APSR */ + if (!(reg & 4)) { + uint32_t apsrmask =3D 0; + + if (mask & 8) { + apsrmask |=3D 0xf8000000; /* APSR NZCVQ */ + } + if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + apsrmask |=3D 0x000f0000; /* APSR GE[3:0] */ + } + xpsr_write(env, val, apsrmask); } break; case 8: /* MSP */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 9090356..ce7f19f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10391,7 +10391,8 @@ static int disas_thumb2_insn(CPUARMState *env, Disa= sContext *s, uint16_t insn_hw case 0: /* msr cpsr. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { tmp =3D load_reg(s, rn); - addr =3D tcg_const_i32(insn & 0xff); + /* the constant is the mask and SYSm fields */ + addr =3D tcg_const_i32(insn & 0xfff); gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); tcg_temp_free_i32(tmp); --=20 2.7.4