[Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support

Suraj Jitindar Singh posted 10 patches 7 years, 1 month ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1487563478-22265-1-git-send-email-sjitindarsingh@gmail.com
Test checkpatch passed
Test docker passed
Test s390x failed
hw/ppc/spapr.c              |  47 ++++++
hw/ppc/spapr_cpu_core.c     |   3 +
include/hw/ppc/spapr.h      |   1 +
target/ppc/cpu-qom.h        |   5 +-
target/ppc/cpu.h            |  21 ++-
target/ppc/mmu-book3s-v3.h  |  50 ++++++
target/ppc/mmu-hash64.c     |  53 +++++-
target/ppc/mmu-hash64.h     |   4 +-
target/ppc/mmu_helper.c     |  44 ++++-
target/ppc/translate.c      |   7 +-
target/ppc/translate_init.c | 391 ++++++++++++++++++++++++++++++--------------
11 files changed, 485 insertions(+), 141 deletions(-)
create mode 100644 target/ppc/mmu-book3s-v3.h
[Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support
Posted by Suraj Jitindar Singh 7 years, 1 month ago
This is V3 of the patch series to implement tcg emulation support for a
POWER9 cpu model for the pseries machine type running a legacy kernel.
That is a kernel which doesn't use the new radix mmu mode or the new hash
mmu mode with segment tables.

To use a POWER9 cpu provide the command line option "-cpu POWER9".

This series attempts to avoid precluding KVM-HV support for the POWER9
cpu model but doesn't attempt to support KVM-PR or the powernv machine
for the POWER9 cpu model as these aren't currently supported or
implemented and further code changes will be required in the event these
are implemented.

This series is used as a base to implement radix support.

The changes from V2 are as follows:

 - Only migrate the partition table entry on non-zero value
 - Change how register generation works to simplify adding/removing
   registers
 - Rename mmu.h -> mmu-book3s-v3.h
 - Error report and abort on attempt to use segment tables

Suraj Jitindar Singh (10):
  target/ppc/POWER9: Add ISAv3.00 MMU definition
  target/ppc: Fix LPCR DPFD mask define
  target/ppc/POWER9: Adapt LPCR handling for POWER9
  target/ppc/POWER9: Direct all instr and data storage interrupts to the
    hypv
  target/ppc: Add patb_entry to sPAPRMachineState
  target/ppc: Don't gen an SDR1 on POWER9 and rework register creation
  target/ppc/POWER9: Add POWER9 mmu fault handler
  target/ppc/POWER9: Add POWER9 pa-features definition
  target/ppc/POWER9: Add cpu_has_work function for POWER9
  hw/ppc/spapr: Add POWER9 to pseries cpu models

 hw/ppc/spapr.c              |  47 ++++++
 hw/ppc/spapr_cpu_core.c     |   3 +
 include/hw/ppc/spapr.h      |   1 +
 target/ppc/cpu-qom.h        |   5 +-
 target/ppc/cpu.h            |  21 ++-
 target/ppc/mmu-book3s-v3.h  |  50 ++++++
 target/ppc/mmu-hash64.c     |  53 +++++-
 target/ppc/mmu-hash64.h     |   4 +-
 target/ppc/mmu_helper.c     |  44 ++++-
 target/ppc/translate.c      |   7 +-
 target/ppc/translate_init.c | 391 ++++++++++++++++++++++++++++++--------------
 11 files changed, 485 insertions(+), 141 deletions(-)
 create mode 100644 target/ppc/mmu-book3s-v3.h

-- 
2.5.5


Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support
Posted by David Gibson 7 years, 1 month ago
On Mon, Feb 20, 2017 at 03:04:28PM +1100, Suraj Jitindar Singh wrote:
> This is V3 of the patch series to implement tcg emulation support for a
> POWER9 cpu model for the pseries machine type running a legacy kernel.
> That is a kernel which doesn't use the new radix mmu mode or the new hash
> mmu mode with segment tables.
> 
> To use a POWER9 cpu provide the command line option "-cpu POWER9".
> 
> This series attempts to avoid precluding KVM-HV support for the POWER9
> cpu model but doesn't attempt to support KVM-PR or the powernv machine
> for the POWER9 cpu model as these aren't currently supported or
> implemented and further code changes will be required in the event these
> are implemented.
> 
> This series is used as a base to implement radix support.

This is looking pretty good.  Main thing is it will need some rework
to rebase on my HPT cleanup as discussed.  I've made a few other
comments, but they're all small things.
> 
> The changes from V2 are as follows:
> 
>  - Only migrate the partition table entry on non-zero value
>  - Change how register generation works to simplify adding/removing
>    registers
>  - Rename mmu.h -> mmu-book3s-v3.h
>  - Error report and abort on attempt to use segment tables
> 
> Suraj Jitindar Singh (10):
>   target/ppc/POWER9: Add ISAv3.00 MMU definition
>   target/ppc: Fix LPCR DPFD mask define
>   target/ppc/POWER9: Adapt LPCR handling for POWER9
>   target/ppc/POWER9: Direct all instr and data storage interrupts to the
>     hypv
>   target/ppc: Add patb_entry to sPAPRMachineState
>   target/ppc: Don't gen an SDR1 on POWER9 and rework register creation
>   target/ppc/POWER9: Add POWER9 mmu fault handler
>   target/ppc/POWER9: Add POWER9 pa-features definition
>   target/ppc/POWER9: Add cpu_has_work function for POWER9
>   hw/ppc/spapr: Add POWER9 to pseries cpu models
> 
>  hw/ppc/spapr.c              |  47 ++++++
>  hw/ppc/spapr_cpu_core.c     |   3 +
>  include/hw/ppc/spapr.h      |   1 +
>  target/ppc/cpu-qom.h        |   5 +-
>  target/ppc/cpu.h            |  21 ++-
>  target/ppc/mmu-book3s-v3.h  |  50 ++++++
>  target/ppc/mmu-hash64.c     |  53 +++++-
>  target/ppc/mmu-hash64.h     |   4 +-
>  target/ppc/mmu_helper.c     |  44 ++++-
>  target/ppc/translate.c      |   7 +-
>  target/ppc/translate_init.c | 391 ++++++++++++++++++++++++++++++--------------
>  11 files changed, 485 insertions(+), 141 deletions(-)
>  create mode 100644 target/ppc/mmu-book3s-v3.h
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson