From nobody Mon Apr 29 10:00:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487358148735172.03305031694902; Fri, 17 Feb 2017 11:02:28 -0800 (PST) Received: from localhost ([::1]:55306 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cennW-0008Ek-IN for importer@patchew.org; Fri, 17 Feb 2017 14:02:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59102) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceni2-00039h-4R for qemu-devel@nongnu.org; Fri, 17 Feb 2017 13:56:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ceni1-0007Ss-8B for qemu-devel@nongnu.org; Fri, 17 Feb 2017 13:56:46 -0500 Received: from mx1.redhat.com ([209.132.183.28]:38634) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cenhy-0007RH-OI; Fri, 17 Feb 2017 13:56:42 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BCFCCC04B92C; Fri, 17 Feb 2017 18:56:42 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1HIubLL022004; Fri, 17 Feb 2017 13:56:40 -0500 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Fri, 17 Feb 2017 19:56:33 +0100 Message-Id: <1487357795-52614-2-git-send-email-imammedo@redhat.com> In-Reply-To: <1487357795-52614-1-git-send-email-imammedo@redhat.com> References: <1487357795-52614-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Fri, 17 Feb 2017 18:56:42 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC 1/3] machine: call machine init from wrapper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , patches@linaro.org, "Michael S. Tsirkin" , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Marcel Apfelbaum , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" add machine_run_board_init() wrapper that calls machine init for now but in follow up patches it will be used to run generic code that should run before machine init. Signed-off-by: Igor Mammedov --- include/hw/boards.h | 1 + hw/core/machine.c | 6 ++++++ vl.c | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 269d0ba..04f5352 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -32,6 +32,7 @@ void memory_region_allocate_system_memory(MemoryRegion *m= r, Object *owner, MachineClass *find_default_machine(void); extern MachineState *current_machine; =20 +void machine_run_board_init(MachineState *machine); bool machine_usb(MachineState *machine); bool machine_kernel_irqchip_allowed(MachineState *machine); bool machine_kernel_irqchip_required(MachineState *machine); diff --git a/hw/core/machine.c b/hw/core/machine.c index 0699750..fe82529 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -575,6 +575,12 @@ bool machine_mem_merge(MachineState *machine) return machine->mem_merge; } =20 +void machine_run_board_init(MachineState *machine) +{ + MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); + machine_class->init(machine); +} + static void machine_class_finalize(ObjectClass *klass, void *data) { MachineClass *mc =3D MACHINE_CLASS(klass); diff --git a/vl.c b/vl.c index 93406ba..9af4462 100644 --- a/vl.c +++ b/vl.c @@ -4484,7 +4484,7 @@ int main(int argc, char **argv, char **envp) current_machine->boot_order =3D boot_order; current_machine->cpu_model =3D cpu_model; =20 - machine_class->init(current_machine); + machine_run_board_init(current_machine); =20 realtime_init(); =20 --=20 2.7.4 From nobody Mon Apr 29 10:00:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487357939224560.6817703523042; Fri, 17 Feb 2017 10:58:59 -0800 (PST) Received: from localhost ([::1]:55279 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cenk9-0004Yr-PA for importer@patchew.org; Fri, 17 Feb 2017 13:58:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceni4-0003BS-JV for qemu-devel@nongnu.org; Fri, 17 Feb 2017 13:56:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ceni3-0007UV-Mf for qemu-devel@nongnu.org; Fri, 17 Feb 2017 13:56:48 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47338) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ceni0-0007Ry-UO; Fri, 17 Feb 2017 13:56:45 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F2ED4804F3; Fri, 17 Feb 2017 18:56:44 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1HIubLM022004; Fri, 17 Feb 2017 13:56:42 -0500 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Fri, 17 Feb 2017 19:56:34 +0100 Message-Id: <1487357795-52614-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1487357795-52614-1-git-send-email-imammedo@redhat.com> References: <1487357795-52614-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Fri, 17 Feb 2017 18:56:45 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC 2/3] machine: generalize handling of default cpu_model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , patches@linaro.org, "Michael S. Tsirkin" , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Marcel Apfelbaum , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" currently all boards have opencoded default cpu_model selection. I most cases it's just a string and in others it's a 'function'. Add to machine callback that returns default cpu_model and make boards return it as const string. That allows to move detection of non specified cpu_model i.e. missing CLI '-cpu' option and move detection to generic machine code. And would allow to generalize parsing cpu features in follow up patch. TODO: complete conversion for all boards Signed-off-by: Igor Mammedov --- include/hw/boards.h | 1 + hw/arm/virt.c | 10 ++++++---- hw/core/machine.c | 7 +++++++ hw/i386/pc.c | 18 ++++++++++-------- hw/ppc/spapr.c | 11 +++++++---- 5 files changed, 31 insertions(+), 16 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 04f5352..9f2dbfd 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -141,6 +141,7 @@ struct MachineClass { DeviceState *dev); unsigned (*cpu_index_to_socket_id)(unsigned cpu_index); const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine); + const char *(*default_cpu_model)(MachineState *machine); }; =20 /** diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a98cb91..8380540 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1252,10 +1252,6 @@ static void machvirt_init(MachineState *machine) Error *err =3D NULL; bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); =20 - if (!cpu_model) { - cpu_model =3D "cortex-a15"; - } - /* We can probe only here because during property set * KVM is not available yet */ @@ -1564,6 +1560,11 @@ static const CPUArchIdList *virt_possible_cpu_arch_i= ds(MachineState *ms) return ms->possible_cpus; } =20 +static const char *virt_default_cpu_model(MachineState *machine) +{ + return "cortex-a15"; +} + static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1581,6 +1582,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ mc->minimum_page_bits =3D 12; mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; + mc->default_cpu_model =3D virt_default_cpu_model; } =20 static const TypeInfo virt_machine_info =3D { diff --git a/hw/core/machine.c b/hw/core/machine.c index fe82529..2a954f0 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -578,6 +578,13 @@ bool machine_mem_merge(MachineState *machine) void machine_run_board_init(MachineState *machine) { MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); + + /* Force all boards to provide default_cpu_model callback */ + assert(machine_class->default_cpu_model); + if (machine->cpu_model =3D=3D NULL) { + machine->cpu_model =3D machine_class->default_cpu_model(machine); + } + machine_class->init(machine); } =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index a8660d4..0073469 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1149,14 +1149,6 @@ void pc_cpus_init(PCMachineState *pcms) MachineClass *mc =3D MACHINE_GET_CLASS(pcms); =20 /* init CPUs */ - if (machine->cpu_model =3D=3D NULL) { -#ifdef TARGET_X86_64 - machine->cpu_model =3D "qemu64"; -#else - machine->cpu_model =3D "qemu32"; -#endif - } - model_pieces =3D g_strsplit(machine->cpu_model, ",", 2); if (!model_pieces[0]) { error_report("Invalid/empty CPU model name"); @@ -2296,6 +2288,15 @@ static void x86_nmi(NMIState *n, int cpu_index, Erro= r **errp) } } =20 +static const char *pc_default_cpu_model(MachineState *machine) +{ +#ifdef TARGET_X86_64 + return "qemu64"; +#else + return "qemu32"; +#endif +} + static void pc_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -2324,6 +2325,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->default_boot_order =3D "cad"; mc->hot_add_cpu =3D pc_hot_add_cpu; mc->max_cpus =3D 255; + mc->default_cpu_model =3D pc_default_cpu_model; mc->reset =3D pc_machine_reset; hc->pre_plug =3D pc_machine_device_pre_plug_cb; hc->plug =3D pc_machine_device_plug_cb; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6f37288..8f30765 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1920,10 +1920,6 @@ static void ppc_spapr_init(MachineState *machine) } =20 /* init CPUs */ - if (machine->cpu_model =3D=3D NULL) { - machine->cpu_model =3D kvm_enabled() ? "host" : smc->tcg_default_c= pu; - } - ppc_cpu_parse_features(machine->cpu_model); =20 spapr_init_cpus(spapr); @@ -2861,6 +2857,12 @@ static void spapr_phb_placement(sPAPRMachineState *s= papr, uint32_t index, *mmio64 =3D SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; } =20 +static const char *spapr_default_cpu_model(MachineState *machine) +{ + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(machine); + return machine->cpu_model =3D kvm_enabled() ? "host" : smc->tcg_defaul= t_cpu; +} + static void spapr_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -2893,6 +2895,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) hc->unplug =3D spapr_machine_device_unplug; mc->cpu_index_to_socket_id =3D spapr_cpu_index_to_socket_id; mc->possible_cpu_arch_ids =3D spapr_possible_cpu_arch_ids; + mc->default_cpu_model =3D spapr_default_cpu_model; hc->unplug_request =3D spapr_machine_device_unplug_request; =20 smc->dr_lmb_enabled =3D true; --=20 2.7.4 From nobody Mon Apr 29 10:00:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487357930269502.5178603321127; Fri, 17 Feb 2017 10:58:50 -0800 (PST) Received: from localhost ([::1]:55278 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cenk0-0004RU-Uv for importer@patchew.org; Fri, 17 Feb 2017 13:58:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceniB-0003HP-0W for qemu-devel@nongnu.org; Fri, 17 Feb 2017 13:56:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ceni9-0007Xu-Eg for qemu-devel@nongnu.org; Fri, 17 Feb 2017 13:56:55 -0500 Received: from mx1.redhat.com ([209.132.183.28]:39932) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ceni3-0007Ti-9T; Fri, 17 Feb 2017 13:56:47 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 41514C05AA43; Fri, 17 Feb 2017 18:56:47 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1HIubLN022004; Fri, 17 Feb 2017 13:56:45 -0500 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Fri, 17 Feb 2017 19:56:35 +0100 Message-Id: <1487357795-52614-4-git-send-email-imammedo@redhat.com> In-Reply-To: <1487357795-52614-1-git-send-email-imammedo@redhat.com> References: <1487357795-52614-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 17 Feb 2017 18:56:47 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC 3/3] machine: generilize cpu_model parsing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , patches@linaro.org, "Michael S. Tsirkin" , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Marcel Apfelbaum , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Parse cpu_model string into cpu_type and [=3D-]foo features in common machine code instead of doing the same on every board. TODO: patch handles only virt-arm/spapr/pc boards, but to avoid bisection breakage it should take care of all boards. Signed-off-by: Igor Mammedov --- include/hw/boards.h | 3 +++ include/hw/ppc/ppc.h | 2 -- hw/arm/virt.c | 36 ++++-------------------------------- hw/core/machine.c | 44 +++++++++++++++++++++++++++++++++++++++++++- hw/i386/pc.c | 24 +++--------------------- hw/ppc/ppc.c | 25 ------------------------- hw/ppc/spapr.c | 3 +-- 7 files changed, 54 insertions(+), 83 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 9f2dbfd..3374a49 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -136,12 +136,14 @@ struct MachineClass { bool rom_file_has_mr; int minimum_page_bits; bool has_hotpluggable_cpus; + const char *base_cpu_type; =20 HotplugHandler *(*get_hotplug_handler)(MachineState *machine, DeviceState *dev); unsigned (*cpu_index_to_socket_id)(unsigned cpu_index); const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine); const char *(*default_cpu_model)(MachineState *machine); + bool (*cpu_model_valid)(MachineState *machine, const char *cpu_model); }; =20 /** @@ -182,6 +184,7 @@ struct MachineState { char *kernel_cmdline; char *initrd_filename; const char *cpu_model; + const char *cpu_typename; AccelState *accelerator; CPUArchIdList *possible_cpus; }; diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 4e7fe11..ff0ac30 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -105,6 +105,4 @@ enum { =20 /* ppc_booke.c */ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags); - -void ppc_cpu_parse_features(const char *cpu_model); #endif diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8380540..d767200 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -169,7 +169,7 @@ static const char *valid_cpus[] =3D { "host", }; =20 -static bool cpuname_valid(const char *cpu) +static bool cpuname_valid(MachineState *machine, const char *cpu) { int i; =20 @@ -1244,12 +1244,6 @@ static void machvirt_init(MachineState *machine) MemoryRegion *secure_sysmem =3D NULL; int n, virt_max_cpus; MemoryRegion *ram =3D g_new(MemoryRegion, 1); - const char *cpu_model =3D machine->cpu_model; - char **cpustr; - ObjectClass *oc; - const char *typename; - CPUClass *cc; - Error *err =3D NULL; bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); =20 /* We can probe only here because during property set @@ -1268,14 +1262,6 @@ static void machvirt_init(MachineState *machine) } } =20 - /* Separate the actual CPU model name from any appended features */ - cpustr =3D g_strsplit(cpu_model, ",", 2); - - if (!cpuname_valid(cpustr[0])) { - error_report("mach-virt: CPU %s not supported", cpustr[0]); - exit(1); - } - /* If we have an EL3 boot ROM then the assumption is that it will * implement PSCI itself, so disable QEMU's internal implementation * so it doesn't get in the way. Instead of starting secondary @@ -1342,22 +1328,6 @@ static void machvirt_init(MachineState *machine) =20 create_fdt(vms); =20 - oc =3D cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); - if (!oc) { - error_report("Unable to find CPU definition"); - exit(1); - } - typename =3D object_class_get_name(oc); - - /* convert -smp CPU options specified by the user into global props */ - cc =3D CPU_CLASS(oc); - cc->parse_features(typename, cpustr[1], &err); - g_strfreev(cpustr); - if (err) { - error_report_err(err); - exit(1); - } - mc->possible_cpu_arch_ids(machine); for (n =3D 0; n < machine->possible_cpus->len; n++) { Object *cpuobj; @@ -1367,7 +1337,7 @@ static void machvirt_init(MachineState *machine) break; } =20 - cpuobj =3D object_new(typename); + cpuobj =3D object_new(machine->cpu_typename); object_property_set_int(cpuobj, machine->possible_cpus->cpus[n].ar= ch_id, "mp-affinity", NULL); =20 @@ -1583,6 +1553,8 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) mc->minimum_page_bits =3D 12; mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; mc->default_cpu_model =3D virt_default_cpu_model; + mc->cpu_model_valid =3D cpuname_valid; + mc->base_cpu_type =3D TYPE_ARM_CPU; } =20 static const TypeInfo virt_machine_info =3D { diff --git a/hw/core/machine.c b/hw/core/machine.c index 2a954f0..42923b1 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -575,8 +575,12 @@ bool machine_mem_merge(MachineState *machine) return machine->mem_merge; } =20 -void machine_run_board_init(MachineState *machine) +static void machine_parse_cpu_model(MachineState *machine) { + ObjectClass *oc; + char **cpustr; + CPUClass *cc; + Error *err =3D NULL; MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); =20 /* Force all boards to provide default_cpu_model callback */ @@ -585,6 +589,44 @@ void machine_run_board_init(MachineState *machine) machine->cpu_model =3D machine_class->default_cpu_model(machine); } =20 + /* Separate the actual CPU model name from any appended features */ + cpustr =3D g_strsplit(machine->cpu_model, ",", 2); + if (!cpustr[0]) { + error_setg(&err, "Invalid/empty CPU model name"); + goto out; + } + + if (machine_class->cpu_model_valid && + !machine_class->cpu_model_valid(machine, cpustr[0])) { + error_report("CPU %s not supported", cpustr[0]); + exit(1); + } + + /* Force all boards to provide base_cpu_type */ + assert(machine_class->base_cpu_type); + oc =3D cpu_class_by_name(machine_class->base_cpu_type, cpustr[0]); + if (!oc) { + error_report("Unable to find CPU definition: %s", cpustr[0]); + exit(1); + } + machine->cpu_typename =3D object_class_get_name(oc); + + /* convert -smp CPU options specified by the user into global props */ + cc =3D CPU_CLASS(oc); + cc->parse_features(machine->cpu_typename, cpustr[1], &err); +out: + g_strfreev(cpustr); + if (err) { + error_report_err(err); + exit(1); + } +} + +void machine_run_board_init(MachineState *machine) +{ + MachineClass *machine_class =3D MACHINE_GET_CLASS(machine); + + machine_parse_cpu_model(machine); machine_class->init(machine); } =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 0073469..9e6149f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1140,31 +1140,11 @@ void pc_hot_add_cpu(const int64_t id, Error **errp) void pc_cpus_init(PCMachineState *pcms) { int i; - CPUClass *cc; - ObjectClass *oc; - const char *typename; - gchar **model_pieces; const CPUArchIdList *possible_cpus; MachineState *machine =3D MACHINE(pcms); MachineClass *mc =3D MACHINE_GET_CLASS(pcms); =20 /* init CPUs */ - model_pieces =3D g_strsplit(machine->cpu_model, ",", 2); - if (!model_pieces[0]) { - error_report("Invalid/empty CPU model name"); - exit(1); - } - - oc =3D cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); - if (oc =3D=3D NULL) { - error_report("Unable to find CPU definition: %s", model_pieces[0]); - exit(1); - } - typename =3D object_class_get_name(oc); - cc =3D CPU_CLASS(oc); - cc->parse_features(typename, model_pieces[1], &error_fatal); - g_strfreev(model_pieces); - /* Calculates the limit to CPU APIC ID values * * Limit for the APIC ID value, so that all @@ -1175,7 +1155,8 @@ void pc_cpus_init(PCMachineState *pcms) pcms->apic_id_limit =3D x86_cpu_apic_id_from_index(max_cpus - 1) + 1; possible_cpus =3D mc->possible_cpu_arch_ids(machine); for (i =3D 0; i < smp_cpus; i++) { - pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal); + pc_new_cpu(machine->cpu_typename, + possible_cpus->cpus[i].arch_id, &error_fatal); } } =20 @@ -2326,6 +2307,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->hot_add_cpu =3D pc_hot_add_cpu; mc->max_cpus =3D 255; mc->default_cpu_model =3D pc_default_cpu_model; + mc->base_cpu_type =3D TYPE_X86_CPU; mc->reset =3D pc_machine_reset; hc->pre_plug =3D pc_machine_device_pre_plug_cb; hc->plug =3D pc_machine_device_plug_cb; diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index d171e60..8587173 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1364,28 +1364,3 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id) =20 return NULL; } - -void ppc_cpu_parse_features(const char *cpu_model) -{ - CPUClass *cc; - ObjectClass *oc; - const char *typename; - gchar **model_pieces; - - model_pieces =3D g_strsplit(cpu_model, ",", 2); - if (!model_pieces[0]) { - error_report("Invalid/empty CPU model name"); - exit(1); - } - - oc =3D cpu_class_by_name(TYPE_POWERPC_CPU, model_pieces[0]); - if (oc =3D=3D NULL) { - error_report("Unable to find CPU definition: %s", model_pieces[0]); - exit(1); - } - - typename =3D object_class_get_name(oc); - cc =3D CPU_CLASS(oc); - cc->parse_features(typename, model_pieces[1], &error_fatal); - g_strfreev(model_pieces); -} diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 8f30765..181ea9b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1920,8 +1920,6 @@ static void ppc_spapr_init(MachineState *machine) } =20 /* init CPUs */ - ppc_cpu_parse_features(machine->cpu_model); - spapr_init_cpus(spapr); =20 if (kvm_enabled()) { @@ -2896,6 +2894,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) mc->cpu_index_to_socket_id =3D spapr_cpu_index_to_socket_id; mc->possible_cpu_arch_ids =3D spapr_possible_cpu_arch_ids; mc->default_cpu_model =3D spapr_default_cpu_model; + mc->base_cpu_type =3D TYPE_POWERPC_CPU; hc->unplug_request =3D spapr_machine_device_unplug_request; =20 smc->dr_lmb_enabled =3D true; --=20 2.7.4