From nobody Mon Apr 29 13:34:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487366259023588.6118731077817; Fri, 17 Feb 2017 13:17:39 -0800 (PST) Received: from localhost ([::1]:56039 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cepuJ-0004AL-S4 for importer@patchew.org; Fri, 17 Feb 2017 16:17:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cemna-0003yf-DA for qemu-devel@nongnu.org; Fri, 17 Feb 2017 12:58:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cemnX-0003fP-9h for qemu-devel@nongnu.org; Fri, 17 Feb 2017 12:58:26 -0500 Received: from smtp-p01.blackberry.com ([208.65.78.88]:30227) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cemnX-0003cB-35; Fri, 17 Feb 2017 12:58:23 -0500 Received: from mhs101cnc.rim.net ([10.65.141.79]) by mhs210cnc-app.rim.net with ESMTP; 17 Feb 2017 12:58:16 -0500 Received: from unknown (HELO BB2299038558.rim.net) ([10.65.140.253]) by mhs101cnc.rim.net with ESMTP; 17 Feb 2017 17:58:16 +0000 From: Nick Reilly To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 17 Feb 2017 12:58:04 -0500 Message-Id: <1487354284-7587-1-git-send-email-nreilly@blackberry.com> X-Mailer: git-send-email 1.9.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 208.65.78.88 X-Mailman-Approved-At: Fri, 17 Feb 2017 16:15:52 -0500 Subject: [Qemu-devel] [PATCH] Add missing fp_access_check() to aarch64 crypto instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Nick Reilly Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The aarch64 crypto instructions for AES and SHA are missing the check for if the FPU is enabled. Signed-off-by: Nick Reilly --- target/arm/translate-a64.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e61bbd6..8105e7e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10929,6 +10929,10 @@ static void disas_crypto_aes(DisasContext *s, uint= 32_t insn) return; } =20 + if (!fp_access_check(s)) { + return; + } + /* Note that we convert the Vx register indexes into the * index within the vfp.regs[] array, so we can share the * helper with the AArch32 instructions. @@ -10993,6 +10997,10 @@ static void disas_crypto_three_reg_sha(DisasContex= t *s, uint32_t insn) return; } =20 + if (!fp_access_check(s)) { + return; + } + tcg_rd_regno =3D tcg_const_i32(rd << 1); tcg_rn_regno =3D tcg_const_i32(rn << 1); tcg_rm_regno =3D tcg_const_i32(rm << 1); @@ -11056,6 +11064,10 @@ static void disas_crypto_two_reg_sha(DisasContext = *s, uint32_t insn) return; } =20 + if (!fp_access_check(s)) { + return; + } + tcg_rd_regno =3D tcg_const_i32(rd << 1); tcg_rn_regno =3D tcg_const_i32(rn << 1); =20 --=20 1.9.1