From nobody Sun Apr 28 05:18:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487218039748853.5526883803774; Wed, 15 Feb 2017 20:07:19 -0800 (PST) Received: from localhost ([::1]:44481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceDLg-00083R-Lw for importer@patchew.org; Wed, 15 Feb 2017 23:07:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58449) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceDKj-0007Iu-AA for qemu-devel@nongnu.org; Wed, 15 Feb 2017 23:06:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ceDKg-0005yg-5U for qemu-devel@nongnu.org; Wed, 15 Feb 2017 23:06:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:38364) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ceDKf-0005xk-VJ for qemu-devel@nongnu.org; Wed, 15 Feb 2017 23:06:14 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7E3456AAC1; Thu, 16 Feb 2017 04:06:13 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-8-36.pek2.redhat.com [10.72.8.36]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v1G468gS022192; Wed, 15 Feb 2017 23:06:10 -0500 From: Peter Xu To: qemu-devel@nongnu.org Date: Thu, 16 Feb 2017 12:06:01 +0800 Message-Id: <1487217961-885-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 16 Feb 2017 04:06:13 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2] pcie: simplify pcie_add_capability() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Alex Williamson , caoj.fnst@cn.fujitsu.com, peterx@redhat.com, "\\ Michael S . Tsirkin \\ " Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When we add PCIe extended capabilities, we should be following the rule that we add the head extended cap (at offset 0x100) first, then the rest of them. Meanwhile, we are always adding new capability bits at the end of the list. Here the "next" looks meaningless in all cases since it should always be zero (along with the "header"). Simplify the function a bit, and it looks more readable now. Signed-off-by: Peter Xu --- v2: - rebased to mst's patch "pci/pcie: don't assume cap id 0 is reserved" - avoid having side-effect code in assertion. [Marcel] (I removed it directly since after mst's fix it would never return nonzero now) --- hw/pci/pcie.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index f4dd177..fc54bfd 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -665,32 +665,24 @@ void pcie_add_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_ver, uint16_t offset, uint16_t size) { - uint32_t header; - uint16_t next; - assert(offset >=3D PCI_CONFIG_SPACE_SIZE); assert(offset < offset + size); assert(offset + size <=3D PCIE_CONFIG_SPACE_SIZE); assert(size >=3D 8); assert(pci_is_express(dev)); =20 - if (offset =3D=3D PCI_CONFIG_SPACE_SIZE) { - header =3D pci_get_long(dev->config + offset); - next =3D PCI_EXT_CAP_NEXT(header); - } else { + if (offset !=3D PCI_CONFIG_SPACE_SIZE) { uint16_t prev; =20 /* * 0xffffffff is not a valid cap id (it's a 16 bit field). use * internally to find the last capability in the linked list. */ - next =3D pcie_find_capability_list(dev, 0xffffffff, &prev); - + pcie_find_capability_list(dev, 0xffffffff, &prev); assert(prev >=3D PCI_CONFIG_SPACE_SIZE); - assert(next =3D=3D 0); pcie_ext_cap_set_next(dev, prev, offset); } - pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); + pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); =20 /* Make capability read-only by default */ memset(dev->wmask + offset, 0, size); --=20 2.7.4