From nobody Sat Apr 27 17:20:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487058755867319.1598137759895; Mon, 13 Feb 2017 23:52:35 -0800 (PST) Received: from localhost ([::1]:33248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdXuc-0003bX-F4 for importer@patchew.org; Tue, 14 Feb 2017 02:52:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44066) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdXtn-0002qU-NL for qemu-devel@nongnu.org; Tue, 14 Feb 2017 02:51:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cdXti-0000vO-QK for qemu-devel@nongnu.org; Tue, 14 Feb 2017 02:51:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:44920) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cdXti-0000v9-KQ for qemu-devel@nongnu.org; Tue, 14 Feb 2017 02:51:38 -0500 Received: from smtp.corp.redhat.com (int-mx16.intmail.prod.int.phx2.redhat.com [10.5.11.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B960FC0567B2 for ; Tue, 14 Feb 2017 07:51:38 +0000 (UTC) Received: from pxdev.xzpeter.org.com (dhcp-14-110.nay.redhat.com [10.66.14.110]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0F8E9653E5; Tue, 14 Feb 2017 07:51:36 +0000 (UTC) From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 14 Feb 2017 15:51:32 +0800 Message-Id: <1487058692-2789-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.74 on 10.5.11.28 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 14 Feb 2017 07:51:38 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] pcie: simplify pcie_add_capability() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcel Apfelbaum , Alex Williamson , peterx@redhat.com, "\\ Michael S . Tsirkin \\ " Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When we add PCIe extended capabilities, we should be following the rule that we add the head extended cap (at offset 0x100) first, then the rest of them. Meanwhile, we are always adding new capability bits at the end of the list. Here the "next" looks meaningless in all cases since it should always be zero (along with the "header"). Simplify the function a bit, and it looks more readable now. Signed-off-by: Peter Xu --- hw/pci/pcie.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index cbd4bb4..e0e6f6a 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -664,30 +664,23 @@ void pcie_add_capability(PCIDevice *dev, uint16_t cap_id, uint8_t cap_ver, uint16_t offset, uint16_t size) { - uint32_t header; - uint16_t next; - assert(offset >=3D PCI_CONFIG_SPACE_SIZE); assert(offset < offset + size); assert(offset + size <=3D PCIE_CONFIG_SPACE_SIZE); assert(size >=3D 8); assert(pci_is_express(dev)); =20 - if (offset =3D=3D PCI_CONFIG_SPACE_SIZE) { - header =3D pci_get_long(dev->config + offset); - next =3D PCI_EXT_CAP_NEXT(header); - } else { + if (offset !=3D PCI_CONFIG_SPACE_SIZE) { uint16_t prev; =20 /* 0 is reserved cap id. use internally to find the last capability in the linked list */ - next =3D pcie_find_capability_list(dev, 0, &prev); - + assert(pcie_find_capability_list(dev, 0, &prev) =3D=3D 0); assert(prev >=3D PCI_CONFIG_SPACE_SIZE); - assert(next =3D=3D 0); pcie_ext_cap_set_next(dev, prev, offset); } - pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next)); + + pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0)); =20 /* Make capability read-only by default */ memset(dev->wmask + offset, 0, size); --=20 2.7.4