From nobody Mon Apr 29 15:08:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486360601006933.6543653185015; Sun, 5 Feb 2017 21:56:41 -0800 (PST) Received: from localhost ([::1]:45673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cacI2-0003Tl-34 for importer@patchew.org; Mon, 06 Feb 2017 00:56:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cacH5-00038t-7T for qemu-devel@nongnu.org; Mon, 06 Feb 2017 00:55:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cacH2-0003Zg-LD for qemu-devel@nongnu.org; Mon, 06 Feb 2017 00:55:39 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:52552) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cacH2-0003Xj-Cy for qemu-devel@nongnu.org; Mon, 06 Feb 2017 00:55:36 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v165rdBH058785 for ; Mon, 6 Feb 2017 00:55:32 -0500 Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by mx0a-001b2d01.pphosted.com with ESMTP id 28d8qruvys-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 06 Feb 2017 00:55:32 -0500 Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 6 Feb 2017 11:25:25 +0530 Received: from d28relay01.in.ibm.com (d28relay01.in.ibm.com [9.184.220.58]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 8432F125801B; Mon, 6 Feb 2017 11:27:14 +0530 (IST) Received: from d28av02.in.ibm.com (d28av02.in.ibm.com [9.184.220.64]) by d28relay01.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v165tPDn36569236; Mon, 6 Feb 2017 11:25:25 +0530 Received: from d28av02.in.ibm.com (localhost [127.0.0.1]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v165tOWr024608; Mon, 6 Feb 2017 11:25:24 +0530 Received: from bharata.in.ibm.com ([9.124.35.202]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v165tNJ9024601; Mon, 6 Feb 2017 11:25:23 +0530 From: Bharata B Rao To: qemu-devel@nongnu.org Date: Mon, 6 Feb 2017 11:25:15 +0530 X-Mailer: git-send-email 2.7.4 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17020605-0004-0000-0000-0000053593D1 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17020605-0005-0000-0000-0000132EB1F6 Message-Id: <1486360515-22989-1-git-send-email-bharata@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-06_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=1 spamscore=1 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702060060 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v3] softfloat: Add round-to-odd rounding mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, nikunj@linux.vnet.ibm.com, qemu-ppc@nongnu.org, Bharata B Rao , david@gibson.dropbear.id.au, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- Tested the corner cases for round-to-odd and the default round-to-nearest-e= ven by comparing the results of QEMU with a known good implementation of PowerPC ISA 3.0 for the following instructions: xsaddqp[o], xsdivqp[o], xsmulqp[o] and xscvqpdp[o]. Changes in v3: - Limited the recalculation of roundIncrement in 64bit rounding only to round-to-odd case and hence dropped the separate patch which did this for all rounding modes earlier. (Peter Maydell) - Resorted to QEMU codying style in softfloat.c v2: https://www.mail-archive.com/qemu-devel@nongnu.org/msg425741.html fpu/softfloat.c | 21 ++++++++++++++++++++- include/fpu/softfloat.h | 2 ++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c295f31..5ccba76 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -623,6 +623,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp= , uint64_t zSig, case float_round_down: roundIncrement =3D zSign ? 0x3ff : 0; break; + case float_round_to_odd: + roundIncrement =3D (zSig & 0x400) ? 0 : 0x3ff; + break; default: abort(); } @@ -632,8 +635,10 @@ static float64 roundAndPackFloat64(flag zSign, int zEx= p, uint64_t zSig, || ( ( zExp =3D=3D 0x7FD ) && ( (int64_t) ( zSig + roundIncrement ) < 0 ) ) ) { + bool overflow_to_inf =3D roundingMode !=3D float_round_to_odd = && + roundIncrement !=3D 0; float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat64( zSign, 0x7FF, - ( roundIncrement =3D=3D 0 = )); + return packFloat64(zSign, 0x7FF, -(!overflow_to_inf)); } if ( zExp < 0 ) { if (status->flush_to_zero) { @@ -651,6 +656,13 @@ static float64 roundAndPackFloat64(flag zSign, int zEx= p, uint64_t zSig, if (isTiny && roundBits) { float_raise(float_flag_underflow, status); } + if (roundingMode =3D=3D float_round_to_odd) { + /* + * For round-to-odd case, the roundIncrement depends on + * zSig which just changed. + */ + roundIncrement =3D (zSig & 0x400) ? 0 : 0x3ff; + } } } if (roundBits) { @@ -1149,6 +1161,9 @@ static float128 roundAndPackFloat128(flag zSign, int3= 2_t zExp, case float_round_down: increment =3D zSign && zSig2; break; + case float_round_to_odd: + increment =3D !(zSig1 & 0x1) && zSig2; + break; default: abort(); } @@ -1168,6 +1183,7 @@ static float128 roundAndPackFloat128(flag zSign, int3= 2_t zExp, if ( ( roundingMode =3D=3D float_round_to_zero ) || ( zSign && ( roundingMode =3D=3D float_round_up ) ) || ( ! zSign && ( roundingMode =3D=3D float_round_down ) ) + || (roundingMode =3D=3D float_round_to_odd) ) { return packFloat128( @@ -1215,6 +1231,9 @@ static float128 roundAndPackFloat128(flag zSign, int3= 2_t zExp, case float_round_down: increment =3D zSign && zSig2; break; + case float_round_to_odd: + increment =3D !(zSig1 & 0x1) && zSig2; + break; default: abort(); } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 842ec6b..8a39028 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -180,6 +180,8 @@ enum { float_round_up =3D 2, float_round_to_zero =3D 3, float_round_ties_away =3D 4, + /* Not an IEEE rounding mode: round to the closest odd mantissa value = */ + float_round_to_odd =3D 5, }; =20 /*------------------------------------------------------------------------= ---- --=20 2.7.4