From nobody Thu May 2 01:08:32 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@gnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@gnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1506716249792790.898028399117; Fri, 29 Sep 2017 13:17:29 -0700 (PDT) Received: from localhost ([::1]:36939 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dy1il-0002ya-NG for importer@patchew.org; Fri, 29 Sep 2017 16:17:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dy1hy-0002cO-T4 for qemu-devel@nongnu.org; Fri, 29 Sep 2017 16:16:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dy1hu-0005Bj-L4 for qemu-devel@nongnu.org; Fri, 29 Sep 2017 16:16:26 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:38982) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dy1hu-00058q-EY for qemu-devel@nongnu.org; Fri, 29 Sep 2017 16:16:22 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 79FE9D9C6B5DE; Fri, 29 Sep 2017 21:16:08 +0100 (IST) Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 29 Sep 2017 21:16:12 +0100 From: James Hogan To: Aurelien Jarno , Yongbok Kim Date: Fri, 29 Sep 2017 21:15:56 +0100 Message-ID: <0cadfe03c2cd47171767e374764c4641a00c841f.1506716058.git-series.james.hogan@imgtec.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PATCH] target/mips: Preserve read-only CP0_WatchHi bits X-BeenThere: qemu-devel@gnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Hogan , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@gnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently all read-only bits of the CP0_WatchHi registers are cleared by MTC0, including the M bit which indicates whether more watch registers exist, and the IRW bits which would be set when a watch is hit (if watchpoints were actually fully supported by QEMU) and are only cleared when 1 is written to them. Fix it so that the read-only bits are properly preserved. Reported-by: Tam Robb Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Yongbok Kim Cc: qemu-devel@nongnu.org --- target/mips/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 320f2b0dc473..f7d740118f8b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1662,7 +1662,7 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ul= ong arg1, uint32_t sel) void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) { int mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); - env->CP0_WatchHi[sel] =3D arg1 & mask; + env->CP0_WatchHi[sel] ^=3D (env->CP0_WatchHi[sel] ^ arg1) & mask; env->CP0_WatchHi[sel] &=3D ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } =20 --=20 git-series 0.8.10