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[42.2.10.203]) by smtp.gmail.com with ESMTPSA id rm10-20020a17090b3eca00b00202618f0df4sm1041389pjb.0.2022.09.28.01.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 01:54:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1664355261; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding:list-id:list-help: list-unsubscribe:list-subscribe:list-post; bh=IVN9s3vxDZcYinL9quHWnkpr5bs6J5lu9frAO8dF6yo=; b=HwSlVcjkktL3G77cbaA2smG5ekOH9j81mSE0aH/gHWmpUyczaRu2XIlX3/33sG8qqqSRbS pfkHMNsxRYKM+yO6t4CjDeb36dteyQYfl/fzwq74HcCJhPQi7gqT9+YsHnG3HN+gg02YcB jhBKBA/a58l4wHd12ubyYgdQ2RPTJEE= X-MC-Unique: iQhexnzyM-qu7wLXSfpzyA-1 X-Original-To: libvir-list@listman.corp.redhat.com X-MC-Unique: ImDi87fiO-KITcNEq_grUg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=IVN9s3vxDZcYinL9quHWnkpr5bs6J5lu9frAO8dF6yo=; b=VwSJxdYgpHu7/ofhBVYWr8Lp/GYDgZ+bDgJIgL7MgXKNJfEqN3qrOS0J5Y5FPELlOK m3v7Ovj+FrDqVUHbnL8PTct4GRqNXCXPkTkHhIV7MsBVUoRGSyq1AV2xqWNCSY7JaTuL TdXfg29Cf76eQNGP/yiHZE92vfaEQpJYFusPjJueewztiu2dxpvY2+YJr6uGTQCEDgCT e4iXe3mbpXR/XoKBWOUEEv6mapVGSMwCRBqgbbmINDpmMoHo8npd5R9nTSh6NzMJv01M xRpf3WY/uWBth6DDUBJuu4QFqj8v+Iy08X7DXMNYX+lMCMEFG3F9IF1q+2zT6S5HH4FH +PlA== X-Gm-Message-State: ACrzQf2fK/LSlRDr74XO71vJKJMYDDlhFWX6CW88/FpcQwn3l9RQvZFX z09exhey7c32DLsbRHZ49xkhBGa6UTZKzq5T X-Google-Smtp-Source: AMsMyM4FwQpjEW31TTnQ9PO3DPDex7Hftxt5+j2hhq1cKzNh8oCrozF7wYVqA6RPoBkjKvONBpMOhg== X-Received: by 2002:a63:4c5f:0:b0:439:49b4:809f with SMTP id m31-20020a634c5f000000b0043949b4809fmr27372594pgl.382.1664355249258; Wed, 28 Sep 2022 01:54:09 -0700 (PDT) From: Yu Gu To: libvir-list@redhat.com Subject: [libvirt PATCH v2] Add basically RISC-V support Date: Wed, 28 Sep 2022 16:54:06 +0800 Message-Id: <20220928085406.2790794-1-guyu2876@gmail.com> MIME-Version: 1.0 X-Mimecast-Impersonation-Protect: Policy=CLT - Impersonation Protection Definition; Similar Internal Domain=false; Similar Monitored External Domain=false; Custom External Domain=false; Mimecast External Domain=false; Newly Observed Domain=false; Internal User Name=false; Custom Display Name List=false; Reply-to Address Mismatch=false; Targeted Threat Dictionary=false; Mimecast Threat Dictionary=false; Custom Threat Dictionary=false X-Mimecast-Spam-Signature: yes X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 X-BeenThere: libvir-list@redhat.com X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development discussions about the libvirt library & tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yu Gu Errors-To: libvir-list-bounces@redhat.com Sender: "libvir-list" X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1664355264430100001 Content-Type: text/plain; charset="utf-8"; x-default="true" This patch provides basic support for the RISC-V architecture, so libvirt can run in RISC-V machine. Signed-off-by: Yu Gu --- po/POTFILES | 1 + src/cpu/cpu.c | 2 + src/cpu/cpu.h | 2 + src/cpu/cpu_riscv64.c | 118 +++++++++++++++++++++++++++++++ src/cpu/cpu_riscv64.h | 28 ++++++++ src/cpu/cpu_riscv64_data.h | 40 +++++++++++ src/cpu/meson.build | 1 + src/cpu_map/index.xml | 4 ++ src/cpu_map/meson.build | 1 + src/cpu_map/riscv64_vendors.xml | 3 + src/util/virarch.c | 2 + src/util/virhostcpu.c | 2 +- src/util/virsysinfo.c | 121 ++++++++++++++++++++++++++++++++ 13 files changed, 324 insertions(+), 1 deletion(-) create mode 100644 src/cpu/cpu_riscv64.c create mode 100644 src/cpu/cpu_riscv64.h create mode 100644 src/cpu/cpu_riscv64_data.h create mode 100644 src/cpu_map/riscv64_vendors.xml diff --git a/po/POTFILES b/po/POTFILES index 169e2a41dc..a52795e7c1 100644 --- a/po/POTFILES +++ b/po/POTFILES @@ -72,6 +72,7 @@ src/cpu/cpu_map.c src/cpu/cpu_ppc64.c src/cpu/cpu_s390.c src/cpu/cpu_x86.c +src/cpu/cpu_riscv64.c src/datatypes.c src/driver.c src/esx/esx_driver.c diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index d97ef5e873..8fdc42e719 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -27,6 +27,7 @@ #include "cpu_ppc64.h" #include "cpu_s390.h" #include "cpu_arm.h" +#include "cpu_riscv64.h" #include "capabilities.h" =20 =20 @@ -39,6 +40,7 @@ static struct cpuArchDriver *drivers[] =3D { &cpuDriverPPC64, &cpuDriverS390, &cpuDriverArm, + &cpuDriverRISCV64, }; =20 =20 diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h index 41a62ce486..6e0a06fce4 100644 --- a/src/cpu/cpu.h +++ b/src/cpu/cpu.h @@ -27,6 +27,7 @@ #include "cpu_x86_data.h" #include "cpu_ppc64_data.h" #include "cpu_arm_data.h" +#include "cpu_riscv64_data.h" =20 =20 typedef struct _virCPUData virCPUData; @@ -36,6 +37,7 @@ struct _virCPUData { virCPUx86Data x86; virCPUppc64Data ppc64; virCPUarmData arm; + virCPUriscv64Data riscv64; /* generic driver needs no data */ } data; }; diff --git a/src/cpu/cpu_riscv64.c b/src/cpu/cpu_riscv64.c new file mode 100644 index 0000000000..21f7178cc2 --- /dev/null +++ b/src/cpu/cpu_riscv64.c @@ -0,0 +1,118 @@ +/* + * cpu_riscv64.c: CPU driver for riscv64(x) CPUs + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library. If not, see + * . + */ + +#include + +#include "cpu.h" + + +#define VIR_FROM_THIS VIR_FROM_CPU + +static const virArch archs[] =3D { VIR_ARCH_RISCV64 }; + +static virCPUCompareResult +virCPUriscv64Compare(virCPUDef *host G_GNUC_UNUSED, + virCPUDef *cpu G_GNUC_UNUSED, + bool failMessages G_GNUC_UNUSED) +{ + /* riscv64 relies on QEMU to perform all runability checking. Return + * VIR_CPU_COMPARE_IDENTICAL to bypass Libvirt checking. + */ + return VIR_CPU_COMPARE_IDENTICAL; +} + +static int +virCPUriscv64Update(virCPUDef *guest, + const virCPUDef *host, + bool relative) +{ + g_autoptr(virCPUDef) updated =3D NULL; + size_t i; + + if (!relative) + return 0; + + if (guest->mode =3D=3D VIR_CPU_MODE_CUSTOM) { + if (guest->match =3D=3D VIR_CPU_MATCH_MINIMUM) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("match mode %s not supported"), + virCPUMatchTypeToString(guest->match)); + } else { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("optional CPU features are not supported")); + } + return -1; + } + + if (!host) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, "%s", + _("unknown host CPU model")); + return -1; + } + + if (!(updated =3D virCPUDefCopyWithoutModel(guest))) + return -1; + + updated->mode =3D VIR_CPU_MODE_CUSTOM; + if (virCPUDefCopyModel(updated, host, true) < 0) + return -1; + + for (i =3D 0; i < guest->nfeatures; i++) { + if (virCPUDefUpdateFeature(updated, + guest->features[i].name, + guest->features[i].policy) < 0) + return -1; + } + + virCPUDefStealModel(guest, updated, false); + guest->mode =3D VIR_CPU_MODE_CUSTOM; + guest->match =3D VIR_CPU_MATCH_EXACT; + + return 0; +} + + +static int +virCPUriscv64ValidateFeatures(virCPUDef *cpu) +{ + size_t i; + + for (i =3D 0; i < cpu->nfeatures; i++) { + if (cpu->features[i].policy =3D=3D VIR_CPU_FEATURE_OPTIONAL) { + virReportError(VIR_ERR_CONFIG_UNSUPPORTED, + _("only cpu feature policies 'require' and " + "'disable' are supported for %s"), + cpu->features[i].name); + return -1; + } + } + + return 0; +} + +struct cpuArchDriver cpuDriverRISCV64 =3D { + .name =3D "riscv64", + .arch =3D archs, + .narch =3D G_N_ELEMENTS(archs), + .compare =3D virCPUriscv64Compare, + .decode =3D NULL, + .encode =3D NULL, + .baseline =3D NULL, + .update =3D virCPUriscv64Update, + .validateFeatures =3D virCPUriscv64ValidateFeatures, +}; diff --git a/src/cpu/cpu_riscv64.h b/src/cpu/cpu_riscv64.h new file mode 100644 index 0000000000..67528415fe --- /dev/null +++ b/src/cpu/cpu_riscv64.h @@ -0,0 +1,28 @@ +/* + * cpu_riscv64.h: CPU driver for 64-bit RISC-V CPUs + * + * Copyright (C) Copyright (C) IBM Corporation, 2010 + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library. If not, see + * . + */ + +#ifndef __VIR_CPU_RISCV64_H__ +# define __VIR_CPU_RISCV64_H__ + +# include "cpu.h" + +extern struct cpuArchDriver cpuDriverRISCV64; + +#endif diff --git a/src/cpu/cpu_riscv64_data.h b/src/cpu/cpu_riscv64_data.h new file mode 100644 index 0000000000..819b9e8fde --- /dev/null +++ b/src/cpu/cpu_riscv64_data.h @@ -0,0 +1,40 @@ +/* + * cpu_riscv64_data.h: 64-bit riscv64 CPU specific data + * + * Copyright (C) 2012 IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; If not, see + * . + */ + +#ifndef __VIR_CPU_RISCV64_DATA_H__ +# define __VIR_CPU_RISCV64_DATA_H__ + +# include + +typedef struct _virCPUriscv64Prid virCPUriscv64Prid; +struct _virCPUriscv64Prid { + uint32_t value; + uint32_t mask; +}; + +# define VIR_CPU_riscv64_DATA_INIT { 0 } + +typedef struct _virCPUriscv64Data virCPUriscv64Data; +struct _virCPUriscv64Data { + size_t len; + virCPUriscv64Prid *prid; +}; + +#endif diff --git a/src/cpu/meson.build b/src/cpu/meson.build index b4ad95e46d..eba1d45743 100644 --- a/src/cpu/meson.build +++ b/src/cpu/meson.build @@ -5,6 +5,7 @@ cpu_sources =3D [ 'cpu_ppc64.c', 'cpu_s390.c', 'cpu_x86.c', + 'cpu_riscv64.c', ] =20 cpu_lib =3D static_library( diff --git a/src/cpu_map/index.xml b/src/cpu_map/index.xml index d533a28865..f2c4b1c62a 100644 --- a/src/cpu_map/index.xml +++ b/src/cpu_map/index.xml @@ -89,6 +89,10 @@ =20 + + + + diff --git a/src/cpu_map/meson.build b/src/cpu_map/meson.build index 99264289e2..1a02df8268 100644 --- a/src/cpu_map/meson.build +++ b/src/cpu_map/meson.build @@ -19,6 +19,7 @@ cpumap_data =3D [ 'ppc64_POWERPC_e5500.xml', 'ppc64_POWERPC_e6500.xml', 'ppc64_vendors.xml', + 'riscv64_vendors.xml', 'x86_486.xml', 'x86_athlon.xml', 'x86_Broadwell-IBRS.xml', diff --git a/src/cpu_map/riscv64_vendors.xml b/src/cpu_map/riscv64_vendors.= xml new file mode 100644 index 0000000000..478a23a467 --- /dev/null +++ b/src/cpu_map/riscv64_vendors.xml @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/src/util/virarch.c b/src/util/virarch.c index 2134dd6a9d..3d14ecd193 100644 --- a/src/util/virarch.c +++ b/src/util/virarch.c @@ -190,6 +190,8 @@ virArch virArchFromHost(void) return VIR_ARCH_ALPHA; case PROCESSOR_ARCHITECTURE_PPC: return VIR_ARCH_PPC; + case PROCESSOR_ARCHITECTURE_RISCV: + return VIR_ARCH_RISCV64; case PROCESSOR_ARCHITECTURE_SHX: return VIR_ARCH_SH4; case PROCESSOR_ARCHITECTURE_ARM: diff --git a/src/util/virhostcpu.c b/src/util/virhostcpu.c index c1e8dc8078..08c2290f00 100644 --- a/src/util/virhostcpu.c +++ b/src/util/virhostcpu.c @@ -544,7 +544,7 @@ virHostCPUParseFrequency(FILE *cpuinfo, char line[1024]; =20 /* No sensible way to retrieve CPU frequency */ - if (ARCH_IS_ARM(arch)) + if (ARCH_IS_ARM(arch) || ARCH_IS_RISCV(arch)) return 0; =20 if (ARCH_IS_X86(arch)) diff --git a/src/util/virsysinfo.c b/src/util/virsysinfo.c index 376d5d4816..e281d928c7 100644 --- a/src/util/virsysinfo.c +++ b/src/util/virsysinfo.c @@ -623,6 +623,125 @@ virSysinfoReadS390(void) return g_steal_pointer(&ret); } =20 +#if 0 +static int +virSysinfoParseRISCVSystem(const char *base, virSysinfoSystemDef **sysdef) +{ + int ret =3D -1; + virSysinfoSystemDef *def; + + def =3D g_new0(virSysinfoSystemDef, 1); + +#if 0 + if (!virSysinfoParseS390Line(base, "Manufacturer", &def->manufacturer)) + goto cleanup; + + if (!virSysinfoParseS390Line(base, "Type", &def->family)) + goto cleanup; +#endif + def->manufacturer =3D g_strndup("Virt-RISC-V", sizeof("Virt RISC-V")); + + if (!def->manufacturer && !def->product && !def->version && + !def->serial && !def->uuid && !def->sku && !def->family) { + g_clear_pointer(&def, virSysinfoSystemDefFree); + } + + *sysdef =3D g_steal_pointer(&def); + ret =3D 0; + cleanup: + virSysinfoSystemDefFree(def); + return ret; +} +#endif + +static int +virSysinfoParseRISCVProcessor(const char *base, virSysinfoDef *ret) +{ + const char *tmp_base; + char *manufacturer =3D NULL; + char *procline =3D NULL; + char *ncpu =3D NULL; + int result =3D -1; + virSysinfoProcessorDef *processor; + + if (!(tmp_base =3D virSysinfoParseS390Line(base, "uarch", &manufacture= r))) + goto error; + + /* Find processor N: line and gather the processor manufacturer, + version, serial number, and family */ + while ((tmp_base =3D strstr(tmp_base, "processor ")) + && (tmp_base =3D virSysinfoParseS390Line(tmp_base, "processor ", + &procline))) { + VIR_EXPAND_N(ret->processor, ret->nprocessor, 1); + processor =3D &ret->processor[ret->nprocessor - 1]; + processor->processor_manufacturer =3D g_strdup(manufacturer); + + VIR_FREE(procline); + } + + /* now, for each processor found, extract the frequency information */ + tmp_base =3D base; + + while ((tmp_base =3D strstr(tmp_base, "hart")) && + (tmp_base =3D virSysinfoParseS390Line(tmp_base, "hart", &ncpu))= ) { + unsigned int n; + char *mhz =3D NULL; + + if (virStrToLong_uip(ncpu, NULL, 10, &n) < 0) + goto error; + + if (n >=3D ret->nprocessor) { + VIR_DEBUG("CPU number '%u' out of range", n); + goto cleanup; + } + + VIR_FREE(ncpu); + } + + cleanup: + result =3D 0; + + error: + VIR_FREE(manufacturer); + VIR_FREE(procline); + VIR_FREE(ncpu); + return result; +} + +virSysinfoDef * +virSysinfoReadRISCV(void) +{ + g_autoptr(virSysinfoDef) ret =3D NULL; + g_autofree char *outbuf =3D NULL; + + ret =3D g_new0(virSysinfoDef, 1); + + /* Gather info from /proc/cpuinfo */ + if (virFileReadAll(CPUINFO, CPUINFO_FILE_LEN, &outbuf) < 0) { + virReportError(VIR_ERR_INTERNAL_ERROR, + _("Failed to open %s"), CPUINFO); + return NULL; + } + + if (virSysinfoParseRISCVProcessor(outbuf, ret) < 0) + return NULL; + + /* Free buffer before reading next file */ + VIR_FREE(outbuf); + +#if 0 + /* Gather info from /proc/sysinfo */ + if (virFileReadAll(SYSINFO, 8192, &outbuf) < 0) { + virReportError(VIR_ERR_INTERNAL_ERROR, + _("Failed to open %s"), SYSINFO); + return NULL; + } + + if (virSysinfoParseRISCVSystem(outbuf, &ret->system) < 0) + return NULL; +#endif + return g_steal_pointer(&ret); +} =20 static int virSysinfoParseBIOS(const char *base, virSysinfoBIOSDef **bios) @@ -1243,6 +1362,8 @@ virSysinfoRead(void) return virSysinfoReadPPC(); #elif defined(__arm__) || defined(__aarch64__) return virSysinfoReadARM(); +#elif defined(__riscv) && __riscv_xlen =3D=3D 64 + return virSysinfoReadRISCV(); #elif defined(__s390__) || defined(__s390x__) return virSysinfoReadS390(); #elif !defined(WIN32) && \ --=20 2.37.3