From nobody Fri May 17 05:00:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+105813+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105813+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1686080462; cv=none; d=zohomail.com; s=zohoarc; b=KeJTGAuTMf+7Lh9xoSEoOnTOiasS0xgMvZdfyqApOyTme0yhaqjYs4QB+ZlwWx46xCgV28yZ1klLLCOMARR7O2mPdDYRm21eUxVPJOiVOMTqxCebJVU9JOUeBujo+6nBZubN6eE9I833hlRX+ob0ZRRF12jwkw+4TgRdCLGCMv4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686080462; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=bKPjdboH1goayfLDVX77/AyLesq1XLllGOoVirJIFnk=; b=B9wNMUgfFYJfSVqUn061+JpLiUQVxzkBsxQH6kxeFVdt8cGCAS0eoemeHbXJ+L0Z1fV0gQTSiTLJiALC7q4ZB3S/tbppt7U+q8uGmtLHz/lMyfvEpfLyW5M2G925wanM7EUqhrYXJTyhAtKo9FjuGdm0wxzHlJ+ZOd6oxAtDV8o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+105813+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1686080462403741.7788642829862; Tue, 6 Jun 2023 12:41:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9C2EYY1788612xR8OzUc0knj; Tue, 06 Jun 2023 12:41:02 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.6513.1686080461026144573 for ; Tue, 06 Jun 2023 12:41:01 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10733"; a="359245830" X-IronPort-AV: E=Sophos;i="6.00,221,1681196400"; d="scan'208";a="359245830" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2023 12:40:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10733"; a="833372335" X-IronPort-AV: E=Sophos;i="6.00,221,1681196400"; d="scan'208";a="833372335" X-Received: from fmbiosdev02.amr.corp.intel.com ([10.121.58.124]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2023 12:40:54 -0700 From: "Saloni Kasbekar" To: devel@edk2.groups.io Cc: Saloni Kasbekar , Sai Chaganty , Nate DeSimone , Isaac Oram , Rosen Chuang Subject: [edk2-devel] [edk2-platforms] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Date: Tue, 6 Jun 2023 12:40:37 -0700 Message-Id: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,saloni.kasbekar@intel.com X-Gm-Message-State: R9pwqltBlFM5PeDGUBc3LF84x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1686080462; bh=A7YI34PQi3Q5DajaYDOUacdu05Xv7l7ZpqCfIeldc08=; h=Cc:Date:From:Reply-To:Subject:To; b=JHgzImySlr1v98IGPW7t2phZ96LFx6QZflmRy/U93OoSwSK2vNC3fWRC0xW6N0SEgmA 61gvPuvzRdQEJ280mOAeHd7MHrq/VWbj9/WwkdjEj7P4NW5/NPgOm4UFcm3zXBywX7+Hj X6BhpegCD78BXQqMvRyrj/TfghFFJajMgUg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1686080463463100001 Content-Type: text/plain; charset="utf-8" Adds the following library instances: AlderlakePRvp/Library/BoardAcpiLib AlderlakePRvp/Library/BoardInitLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Library/BoardAcpiLib/BaseAcpiTableLib.c | 30 ++ .../BaseMultiBoardAcpiSupportLib.c | 53 +++ .../BaseMultiBoardAcpiSupportLib.inf | 43 +++ .../Library/BoardInitLib/Dxe/DxeInitLib.c | 178 ++++++++++ .../BoardInitLib/Dxe/DxeMultiBoardInitLib.c | 65 ++++ .../BoardInitLib/Dxe/DxeMultiBoardInitlib.inf | 97 ++++++ .../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 131 ++++++++ .../BoardInitLib/Pei/BoardSaConfigPreMem.h | 81 +++++ .../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 245 ++++++++++++++ .../BoardInitLib/Pei/GpioTableAdlPPostMem.h | 25 ++ .../Library/BoardInitLib/Pei/PeiDetect.c | 63 ++++ .../BoardInitLib/Pei/PeiInitPostMemLib.c | 306 ++++++++++++++++++ .../BoardInitLib/Pei/PeiInitPreMemLib.c | 236 ++++++++++++++ .../Pei/PeiMultiBoardInitPostMemLib.c | 50 +++ .../Pei/PeiMultiBoardInitPostMemLib.inf | 156 +++++++++ .../Pei/PeiMultiBoardInitPreMemLib.c | 105 ++++++ .../Pei/PeiMultiBoardInitPreMemLib.inf | 230 +++++++++++++ 17 files changed, 2094 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardAcpiLib/BaseAcpiTableLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Dxe/DxeInitLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Dxe/DxeMultiBoardInitLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Dxe/DxeMultiBoardInitlib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/BoardPchInitPreMemLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/BoardSaConfigPreMem.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/BoardSaInitPreMemLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/GpioTableAdlPPostMem.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiDetect.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiInitPostMemLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiInitPreMemLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Libr= ary/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdAcpiLib/BaseAcpiTableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Alderla= kePRvp/Library/BoardAcpiLib/BaseAcpiTableLib.c new file mode 100644 index 0000000000..c8154b84c7 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiL= ib/BaseAcpiTableLib.c @@ -0,0 +1,30 @@ +/** @file + Board ACPI Table Library + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + Update ACPI Table + + @param[in, out] Table Pointer to table, need to be update in Acpi ta= ble. + @param[in, out] Version ACPI table version + + @retval EFI_SUCCESS The function always return successfully. +**/ +EFI_STATUS +EFIAPI +AdlPBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdAcpiLib/BaseMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoar= dPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..c78bee4b0a --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiL= ib/BaseMultiBoardAcpiSupportLib.c @@ -0,0 +1,53 @@ +/** @file + Multi-Board ACPI Support Library + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +AdlPBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +BOARD_ACPI_TABLE_FUNC mAdlPBoardAcpiTableFunc =3D { + AdlPBoardUpdateAcpiTable +}; + +/** + The constructor function to register mAdlPBoardAcpiTableFunc function. + + @retval EFI_SUCCESS This constructor always return EFI_SUCCESS. + It will ASSERT on errors. +**/ +EFI_STATUS +EFIAPI +AdlPBaseMultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + UINT8 SkuType; + SkuType =3D PcdGet8 (PcdSkuType); + + if (SkuType=3D=3DAdlPSkuType) { + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + return RegisterBoardAcpiTableFunc (&mAdlPBoardAcpiTableFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdAcpiLib/BaseMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBo= ardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.inf new file mode 100644 index 0000000000..6289b23a96 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiL= ib/BaseMultiBoardAcpiSupportLib.inf @@ -0,0 +1,43 @@ +### @file +# Multi-Board ACPI Support Library +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D AdlPBaseMultiBoardAcpiTableLib + FILE_GUID =3D 8E6A3B38-53E0-48C0-970F-058F380FCB80 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D AdlPBaseMultiBoardAcpiSupportLibConst= ructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + AslUpdateLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + AlderlakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + BaseAcpiTableLib.c + BaseMultiBoardAcpiSupportLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSkuType \ No newline at end of file diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Dxe/DxeInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Alderlake= PRvp/Library/BoardInitLib/Dxe/DxeInitLib.c new file mode 100644 index 0000000000..3e023a9b02 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Dxe/DxeInitLib.c @@ -0,0 +1,178 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +/** + Retimer Platform Specific Data +**/ + + +EFI_STATUS +PatchConfigurationDataInit ( + IN CONFIG_PATCH_STRUCTURE *ConfigPatchStruct, + IN UINTN ConfigPatchStructSize + ); + + +VOID +AdlPInitCommonPlatformPcd ( + VOID + ) +{ + + PcdSetBoolS (PcdPssReadSN, TRUE); + PcdSet8S (PcdPssI2cSlaveAddress, 0x6E); + PcdSet8S (PcdPssI2cBusNumber, 0x05); + PcdSetBoolS (PcdSpdAddressOverride, FALSE); + +} + +VOID +AdlPUpdateDimmPopulation ( + VOID + ) +{ + MEMORY_INFO_DATA_HOB *MemInfo; + UINT8 Slot0; + UINT8 Slot1; + UINT8 Slot2; + UINT8 Slot3; + CONTROLLER_INFO *ControllerInfo; + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob =3D NULL; + MemInfo =3D NULL; + GuidHob =3D GetFirstGuidHob (&gSiMemoryInfoDataGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob !=3D NULL) { + MemInfo =3D (MEMORY_INFO_DATA_HOB *) GET_GUID_HOB_DATA (GuidHob); + } + if (MemInfo !=3D NULL) { + if ( PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorDesktop || + PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorUpServer || + PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorWorkstation + ) { + ControllerInfo =3D &MemInfo->Controller[0]; + Slot0 =3D ControllerInfo->ChannelInfo[0].DimmInfo[0].Status; + Slot1 =3D ControllerInfo->ChannelInfo[0].DimmInfo[1].Status; + Slot2 =3D ControllerInfo->ChannelInfo[1].DimmInfo[0].Status; + Slot3 =3D ControllerInfo->ChannelInfo[1].DimmInfo[1].Status; + + // + // Channel 0 Channel 1 + // Slot0 Slot1 Slot0 Slot1 - Population AIO= board + // 0 0 0 0 - Invalid - In= valid + // 0 0 0 1 - Valid - In= valid + // 0 0 1 0 - Invalid - Va= lid + // 0 0 1 1 - Valid - Va= lid + // 0 1 0 0 - Valid - In= valid + // 0 1 0 1 - Valid - In= valid + // 0 1 1 0 - Invalid - In= valid + // 0 1 1 1 - Valid - In= valid + // 1 0 0 0 - Invalid - Va= lid + // 1 0 0 1 - Invalid - In= valid + // 1 0 1 0 - Invalid - Va= lid + // 1 0 1 1 - Invalid - Va= lid + // 1 1 0 0 - Valid - Va= lid + // 1 1 0 1 - Valid - In= valid + // 1 1 1 0 - Invalid - Va= lid + // 1 1 1 1 - Valid - Va= lid + // + if ((Slot0 && (Slot1 =3D=3D 0)) || (Slot2 && (Slot3 =3D=3D 0))) { + PcdSetBoolS (PcdDimmPopulationError, TRUE); + } + } + } +} + +/** + Enable Tier2 GPIO Sci wake capability. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +AdlPTier2GpioWakeSupport ( + VOID + ) +{ + BOOLEAN Tier2GpioWakeEnable; + + Tier2GpioWakeEnable =3D FALSE; + PcdSetBoolS (PcdGpioTier2WakeEnable, Tier2GpioWakeEnable); + + return EFI_SUCCESS; +} + + +/** + A hook for board-specific initialization after PCI enumeration. + + @retval EFI_SUCCESS The board initialization was successful. +**/ +EFI_STATUS +EFIAPI +AdlPBoardInitAfterPciEnumeration ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "AdlPBoardInitAfterPciEnumeration\n")); + + AdlPTier2GpioWakeSupport (); + AdlPInitCommonPlatformPcd (); + + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ReadyToBoot event. + + @retval EFI_SUCCESS The board initialization was successful. +**/ +EFI_STATUS +EFIAPI +AdlPBoardInitReadyToBoot ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "AdlPBoardInitReadyToBoot\n")); + + AdlPUpdateDimmPopulation (); + + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ExitBootServices event. + + @retval EFI_SUCCESS The board initialization was successful. +**/ +EFI_STATUS +EFIAPI +AdlPBoardInitEndOfFirmware ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "AdlPBoardInitEndOfFirmware\n")); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Dxe/DxeMultiBoardInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg= /AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitLib.c new file mode 100644 index 0000000000..0cdf405502 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Dxe/DxeMultiBoardInitLib.c @@ -0,0 +1,65 @@ +/** @file + DXE Multi-Board Initilialization Library + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +AdlPBoardInitAfterPciEnumeration ( + VOID + ); + +EFI_STATUS +EFIAPI +AdlPBoardInitReadyToBoot ( + VOID + ); + +EFI_STATUS +EFIAPI +AdlPBoardInitEndOfFirmware ( + VOID + ); + +BOARD_NOTIFICATION_INIT_FUNC mAdlPBoardDxeInitFunc =3D { + AdlPBoardInitAfterPciEnumeration, + AdlPBoardInitReadyToBoot, + AdlPBoardInitEndOfFirmware +}; + +/** + The constructor determines which board init functions should be register= ed. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +DxeAdlPMultiBoardInitLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT8 SkuType; + SkuType =3D PcdGet8 (PcdSkuType); + + if (SkuType=3D=3DAdlPSkuType) { + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + return RegisterBoardNotificationInit (&mAdlPBoardDxeInitFunc); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Dxe/DxeMultiBoardInitlib.inf b/Platform/Intel/AlderlakeOpenBoardP= kg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitlib.inf new file mode 100644 index 0000000000..2ab57da8be --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Dxe/DxeMultiBoardInitlib.inf @@ -0,0 +1,97 @@ +## @file +# Component information file for Alderlake Multi-Board Initialization in D= XE phase. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeAdlPMultiBoardInitLib + FILE_GUID =3D E7D21F79-1126-4B45-987C-41FF30AC0EC2 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D DxeAdlPMultiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + BaseMemoryLib + MemoryAllocationLib + HobLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + PchPcieRpLib + PciSegmentLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[Sources] + DxeInitLib.c + DxeMultiBoardInitLib.c + +[Protocols] + +[Guids] + gSiMemoryInfoDataGuid ## CONSUMES + gSetupVariableGuid ## CONSUMES + gSaSetupVariableGuid ## CONSUMES + gCpuSetupVariableGuid ## CONSUMES + gPchSetupVariableGuid ## CONSUMES + gMeSetupVariableGuid ## CONSUMES + gSiSetupVariableGuid ## CONSUMES + +[Pcd] + # Board Init Table List + gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature + gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile + + gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature + + gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride + + gBoardModuleTokenSpaceGuid.PcdBatteryPresent + gBoardModuleTokenSpaceGuid.PcdRealBattery1Control + gBoardModuleTokenSpaceGuid.PcdRealBattery2Control + + gBoardModuleTokenSpaceGuid.PcdH8S2113SIO + gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM + gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO + gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON + + gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin + + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport + + gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport + gBoardModuleTokenSpaceGuid.PcdVirtualGpioButtonSupport + gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin + gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport + gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport + + gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardBomId + gBoardModuleTokenSpaceGuid.PcdSkuType + + gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable ## PRO= DUCES + + gBoardModuleTokenSpaceGuid.PcdPssReadSN + gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber + gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress + + gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable + gBoardModuleTokenSpaceGuid.PcdDimmPopulationError + + gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES \ No newline at end of file diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/BoardPchInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPk= g/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c new file mode 100644 index 0000000000..753b686de5 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/BoardPchInitPreMemLib.c @@ -0,0 +1,131 @@ +/** @file + Source code for the board PCH configuration Pcd init functions for Pre-Me= mory Init phase. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/** + Board Root Port Clock Info configuration init function for PEI pre-memor= y phase. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +AdlPRootPortClkInfoInit ( + VOID + ) +{ + PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS]; + UINT32 Index; + PCIE_CLOCKS_USAGE *PcieClocks; + + PcieClocks =3D NULL; + + // + //The default clock assignment will be NOT_USED, which corresponds to Pc= hClockUsageNotUsed. This will prevent clocks drawing Power by default.=20 + //If Platform code doesn't contain port-clock map for a given board, the= clocks will be NOT_USED, preventing PCIe devices not to operate.=20 + //To prevent this, remember to provide port-clock map for every board. + // + for (Index =3D 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) { + Clock[Index].PcieClock.ClkReqSupported =3D TRUE; + Clock[Index].PcieClock.ClockUsage =3D NOT_USED; + } + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. + /// + + PcieClocks =3D PcdGetPtr(VpdPcdPcieClkUsageMap); + if (PcieClocks =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Clock[0].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[0]; + Clock[1].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[1]; + Clock[2].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[2]; + Clock[3].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[3]; + Clock[4].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[4]; + Clock[5].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[5]; + Clock[6].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[6]; + Clock[7].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[7]; + Clock[8].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[8]; + Clock[9].PcieClock.ClockUsage =3D PcieClocks->ClockUsage[9]; + + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock10, Clock[10].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock11, Clock[11].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock12, Clock[12].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock13, Clock[13].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock14, Clock[14].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + PcdSet64S (PcdPcieClock15, Clock[15].Blob); // @todo Those individual PC= Ds should probably be replaced with something like a VOID* that can be iter= ated over + return EFI_SUCCESS; +} + +/** + Board USB related configuration init function for PEI pre-memory phase. + + @param[in] VOID + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +AdlPUsbConfigInit ( + VOID + ) +{ + USB_OC_MAP_TABLE *Usb2OcMappingTable; + USB_OC_MAP_TABLE *Usb3OcMappingTable; + + // + // USB Port Over Current Pin + // + Usb2OcMappingTable =3D PcdGetPtr(VpdPcdUSB2OCMap); + Usb3OcMappingTable =3D PcdGetPtr(VpdPcdUSB3OCMap); + + PcdSet32S (PcdUsb2OverCurrentPinTable, (UINT32) Usb2OcMappingTable); + PcdSet32S (PcdUsb3OverCurrentPinTable, (UINT32) Usb3OcMappingTable); + + return EFI_SUCCESS; +} + +/** + Board GPIO Group Tier configuration init function for PEI pre-memory pha= se. +**/ +VOID +AdlPGpioGroupTierInit ( + VOID + ) +{ + // + // GPIO Group Tier + // + PcdSet32S (PcdGpioGroupToGpeDw0, 0); + PcdSet32S (PcdGpioGroupToGpeDw1, 0); + PcdSet32S (PcdGpioGroupToGpeDw2, 0); + + return; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/BoardSaConfigPreMem.h b/Platform/Intel/AlderlakeOpenBoardPkg/= AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h new file mode 100644 index 0000000000..372897705d --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/BoardSaConfigPreMem.h @@ -0,0 +1,81 @@ +/** @file + PEI Boards Configurations for PreMem phase. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_ +#define _BOARD_SA_CONFIG_PRE_MEM_H_ + +#include +#include + +// +// LPDDR3 / LPDDR4 RVP boards (memory soldered down) +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR3/4 is 1DPC o= nly) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 +#define SA_MRC_MAX_RCOMP_TARGETS (5) + +// +// Reference RCOMP resistors on motherboard - MRC will set automatically +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 AdlPRcompResistorZero =3D 0; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - MRC wi= ll set automatically +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAdlP[SA_MRC_MAX_RCOM= P_TARGETS] =3D { 0, 0, 0, 0, 0 }; + +// +// DQ byte mapping to CMD/CTL/CLK, from the CPU side +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapAdlP[2][6][2] =3D { + // Channel 0: + { + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] + { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:= 4] + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0x00, 0x00 }, // Unused in ICL MRC + { 0x00, 0x00 }, // Unused in ICL MRC + { 0x00, 0x00 }, // Unused in ICL MRC + }, + // Channel 1: + { + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] + { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:= 4] + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0x00, 0x00 }, // Unused in ICL MRC + { 0x00, 0x00 }, // Unused in ICL MRC + { 0x00, 0x00 }, // Unused in ICL MRC + } +}; + +// +// Display DDI settings for Adl-P Ddr5 Rvp Edp + DP +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlPDdr5RvpDisplayDdiConfig[16]= =3D { + = DdiPortEdp, // DDI Port A Config : DdiPortDisabled =3D No LFP is = Connected, DdiPortEdp =3D eDP, DdiPortMipiDsi =3D MIPI DSI + = DdiPortDisabled, // DDI Port B Config : DdiPortDisabled =3D No LFP is = Connected, DdiPortEdp =3D eDP, DdiPortMipiDsi =3D MIPI DSI + = DdiHpdDisable, // DDI Port A HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiHpdDisable, // DDI Port 1 HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable =3D Disable, DdiHpd= Enable =3D Enable HPD + = DdiDisable, // DDI Port A DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC + = DdiDisable, // DDI Port B DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC + = DdiDisable, // DDI Port C DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC + = DdiDisable, // DDI Port 1 DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC + = DdiDisable, // DDI Port 2 DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC + = DdiDisable, // DDI Port 3 DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC + = DdiDisable // DDI Port 4 DDC : DdiDisable =3D Disable, DdiDdcEna= ble =3D Enable DDC +}; + +#endif // _BOARD_SA_CONFIG_PRE_MEM_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/BoardSaInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg= /AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c new file mode 100644 index 0000000000..2fea5bc675 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/BoardSaInitPreMemLib.c @@ -0,0 +1,245 @@ +/** @file + Source code for the board SA configuration Pcd init functions in Pre-Memo= ry init phase. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "BoardSaConfigPreMem.h" +#include +#include +#include +#include +#include +#include +#include +#include +/** + MRC configuration init function for PEI pre-memory phase. + + @param[in] VOID + + @retval VOID +**/ +VOID +AdlPSaMiscConfigInit ( + VOID + ) +{ + // Type4 RVP + PcdSet8S (PcdSaMiscUserBd, 6); // btUlxUltType4 + PcdSet16S (PcdSaDdrFreqLimit, 0); + + return; +} + +/** + Board Memory Init related configuration init function for PEI pre-memory= phase. + + @param[in] VOID + + @retval VOID +**/ +VOID +AdlPMrcConfigInit ( + VOID + ) +{ + UINT16 BoardId; + BOOLEAN ExternalSpdPresent; + MRC_DQS *MrcDqs; + MRC_DQ *MrcDq; + SPD_DATA *SpdData; + + BoardId =3D PcdGet16(PcdBoardId); + + // SPD is the same size for all boards + PcdSet16S (PcdMrcSpdDataSize, 512); + + ExternalSpdPresent =3D PcdGetBool (PcdSpdPresent); + + // Assume internal SPD is used + PcdSet8S (PcdMrcSpdAddressTable0, 0); + PcdSet8S (PcdMrcSpdAddressTable1, 0); + PcdSet8S (PcdMrcSpdAddressTable2, 0); + PcdSet8S (PcdMrcSpdAddressTable3, 0); + PcdSet8S (PcdMrcSpdAddressTable4, 0); + PcdSet8S (PcdMrcSpdAddressTable5, 0); + PcdSet8S (PcdMrcSpdAddressTable6, 0); + PcdSet8S (PcdMrcSpdAddressTable7, 0); + PcdSet8S (PcdMrcSpdAddressTable8, 0); + PcdSet8S (PcdMrcSpdAddressTable9, 0); + PcdSet8S (PcdMrcSpdAddressTable10, 0); + PcdSet8S (PcdMrcSpdAddressTable11, 0); + PcdSet8S (PcdMrcSpdAddressTable12, 0); + PcdSet8S (PcdMrcSpdAddressTable13, 0); + PcdSet8S (PcdMrcSpdAddressTable14, 0); + PcdSet8S (PcdMrcSpdAddressTable15, 0); + + // Check for external SPD presence + if (ExternalSpdPresent) { + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); + PcdSet8S (PcdMrcSpdAddressTable8, 0xA4); + PcdSet8S (PcdMrcSpdAddressTable9, 0xA6); + break; + default: + break; + } + } + + // Setting the default DQ Byte Map. It may be overriden to board specifi= c settings below. + PcdSet32S (PcdMrcDqByteMap, (UINTN) DqByteMapAdlP); + PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapAdlP)); + + // ADL uses the same RCOMP resistors for all DDR types + PcdSet32S (PcdMrcRcompResistor, (UINTN) AdlPRcompResistorZero); + + // Use default RCOMP target values for all boards + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAdlP); + + // Default is NIL + PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE); + PcdSetBoolS (PcdMrcDqPinsInterleaved, FALSE); + + // DqsMapCpu2Dram is the same size for all boards + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (MRC_DQS)); + // DqMapCpu2Dram is the same size for all boards + PcdSet16S (PcdMrcDqMapCpu2DramSize, sizeof (MRC_DQ)); + PcdSet8S (PcdMrcLp5CccConfig, 0x0); + + // CPU-DRAM DQ mapping + MrcDq =3D PcdGetPtr (VpdPcdMrcDqMapCpu2Dram); + if (MrcDq !=3D NULL) { + PcdSet32S (PcdMrcDqMapCpu2Dram, (UINTN)MrcDq->DqMapCpu2Dram); + } + + // CPU-DRAM DQS mapping + MrcDqs =3D PcdGetPtr (VpdPcdMrcDqsMapCpu2Dram); + if (MrcDqs !=3D NULL) { + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)MrcDqs->DqsMapCpu2Dram); + } + + // DRAM SPD Data + SpdData =3D PcdGetPtr (VpdPcdMrcSpdData); + if (SpdData !=3D NULL) { + if (SpdData->OverrideSpd =3D=3D TRUE) { + PcdSet32S (PcdMrcSpdData, (UINTN)SpdData->SpdData); + } + } + + // + // CA Vref routing: board-dependent + // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L) + // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used) + // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4) + // + // Set it to 2 for all our DDR4 boards; it is ignored for LPDDR4 + // + PcdSet8S (PcdMrcCaVrefConfig, 2); + + return; +} + +/** + Board SA related GPIO configuration init function for PEI pre-memory pha= se. + + @param[in] VOID + + @retval VOID +**/ +VOID +AdlPSaGpioConfigInit ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16(PcdBoardId); + // + // Assigning default values to PCIE RTD3 GPIOs + // + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + PcdSet8S (PcdRootPortIndex, 4); + PcdSet8S (PcdPcieSlot1GpioSupport, 1); + PcdSet8S (PcdPcieSlot1PwrEnableExpanderNo, 0); + // + // Configure CPU M.2 SSD 1 GPIO PCDs + // + PcdSetBoolS (PcdPcieSsd2PwrEnableGpioPolarity, PIN_GPIO_ACTIVE_HIGH); + // + // Configure CPU M.2 SSD 2 GPIO PCDs + // + PcdSet32S (PcdPcieSsd3PwrEnableGpioNo, GPIO_VER2_LP_GPP_C2); + PcdSetBoolS (PcdPcieSsd3PwrEnableGpioPolarity, PIN_GPIO_ACTIVE_HIGH); + break; + default: + break; + } + return; +} + +/** + SA Display DDI configuration init function for PEI pre-memory phase. + + @param[in] VOID + + @retval VOID +**/ +VOID +AdlPSaDisplayConfigInit ( + VOID + ) +{ + UINT16 BoardId; + UINT16 DisplayId; + + BoardId =3D PcdGet16 (PcdBoardId); + DisplayId =3D PcdGet16 (PcdDisplayId); + + DEBUG ((DEBUG_INFO, "BoardId =3D 0x%x DisplayId =3D 0x%x\n",BoardId,Disp= layId)); + + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + DEBUG ((DEBUG_INFO, "DDI Configuration ADLP Edp DP\n")); + PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mAdlPDdr5RvpDisplayDdi= Config); + PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mAdlPDdr5RvpDispla= yDdiConfig)); + break; + default: + break; + } + + return; +} + +/** + Board USB related configuration init function for PEI pre-memory phase. + + @param[in] VOID + + @retval VOID +**/ +VOID +AdlPSaUsbConfigInit ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16(PcdBoardId); + + switch (BoardId) { + // + // Override ALL port setting if required. + // + case BoardIdAdlPDdr5Rvp: + PcdSet8S (PcdCpuXhciPortSupportMap, 0x0F); + break; + } + // + // Update Cpu Xhci Port Enable Map PCD + // + TcssUpdateCpuXhciPortEnableMapPcd (); +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/GpioTableAdlPPostMem.h b/Platform/Intel/AlderlakeOpenBoardPkg= /AlderlakePRvp/Library/BoardInitLib/Pei/GpioTableAdlPPostMem.h new file mode 100644 index 0000000000..e40e2f860e --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/GpioTableAdlPPostMem.h @@ -0,0 +1,25 @@ +/** @file + GPIO definition table for AlderLake P + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _ALDERLAKE_P_GPIO_TABLE_H_ +#define _ALDERLAKE_P_GPIO_TABLE_H_ + +/// + +/// !!! For those GPIO pins are designed as native function, BIOS CAN NOT = configure the pins to Native function in GPIO init table!!! + +/// BIOS has to leave the native pins programming to Silicon Code(based on= BIOS policies setting) or soft strap(set by CSME in FITc). + +/// Configuring pins to native function in GPIO table would cause BIOS per= form multiple programming the pins and then related function might be abnor= mal. + +/// + +#include +#include +#include + +#endif // _ALDERLAKE_P_GPIO_TABLE_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiDetect.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakeP= Rvp/Library/BoardInitLib/Pei/PeiDetect.c new file mode 100644 index 0000000000..452c291753 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiDetect.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +BOOLEAN +IsAdlP ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16 (PcdBoardId); + if (BoardId =3D=3D 0) { + DEBUG ((DEBUG_INFO, "Let's get Board information first ...\n")); + GetBoardConfig (); + BoardId =3D PcdGet16 (PcdBoardId); + } + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + DEBUG ((DEBUG_INFO, "AlderLake P Board detected\n")); + + // set sku type to ADL P + PcdSet8S (PcdSkuType, AdlPSkuType); + return TRUE; + break; + default: + return FALSE; + } +} + +EFI_STATUS +EFIAPI +AdlPBoardDetect ( + VOID + ) +{ + UINTN SkuId; + SkuId =3D 0; + + if (LibPcdGetSku () !=3D 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "AlderLakeP Board Detection Callback\n")); + + if (IsAdlP ()) { + SkuId =3D (UINTN) (PcdGet16 (PcdBoardBomId) << 16) | (PcdGet16 (PcdBoa= rdRev) << 8) | (PcdGet16 (PcdBoardId)); + LibPcdSetSku (SkuId); + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Al= derlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c new file mode 100644 index 0000000000..6fae54d0dd --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiInitPostMemLib.c @@ -0,0 +1,306 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include +#include "GpioTableAdlPPostMem.h" +#include +#include +#include +#include +#include +#include +#include +#include + + + +/** + Alderlake P boards configuration init function for PEI post memory phase. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +AdlPInit ( + VOID + ) +{ + UINT16 GpioCount; + UINTN Size; + EFI_STATUS Status; + GPIO_INIT_CONFIG *GpioTable; + // + // GPIO Table Init + // + Status =3D EFI_SUCCESS; + GpioCount =3D 0; + Size =3D 0; + GpioTable =3D NULL; + // + // GPIO Table Init + // + // + // GPIO Table Init, Update PostMem GPIO table to PcdBoardGpioTable + // + GpioTable =3D (GPIO_INIT_CONFIG *)PcdGetPtr(VpdPcdBoardGpioTable); + + GetGpioTableSize (GpioTable, &GpioCount); + // + // Increase GpioCount for the zero terminator. + // + GpioCount ++; + Size =3D (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG)); + Status =3D PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable); + ASSERT_EFI_ERROR (Status); + + PcdSet8S (PcdSataPortsEnable0, 0x1); + + return Status; +} + +/** + Board I2C pads termination configuration init function for PEI pre-memor= y phase. +**/ +VOID +AdlPSerialIoI2cPadsTerminationInit ( + VOID + ) +{ +} + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Misc. init function for PEI post memory phase. +**/ +VOID +AdlPBoardMiscInit ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16 (PcdBoardId); + + PcdSetBoolS (PcdSataLedEnable, FALSE); + PcdSetBoolS (PcdVrAlertEnable, FALSE); + + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + PcdSet8S (PcdPcieSlot1RootPort, 8); + PcdSetBoolS (PcdPcieSlot1PwrEnableGpioPolarity, PIN_GPIO_ACTIVE_LOW); + break; + } + // + // MIPI CAM + // + PcdSetBoolS (PcdMipiCamGpioEnable, TRUE); + + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + // + // PCH M.2 SSD and Sata port + // + PcdSet32S (PcdPchSsd1PwrEnableGpioNo, GPIO_VER2_LP_GPP_D16); = // PCH M.2 SSD power enable gpio pin + PcdSetBoolS (PcdPchSsd1PwrEnableGpioPolarity, PIN_GPIO_ACTIVE_HIGH);= // PCH M.2 SSD power enable gpio pin polarity + + break; + } + + + return; +} + +/** + PMC-PD solution enable init lib +**/ +VOID +AdlPBoardPmcPdInit ( + VOID + ) +{ + PcdSetBoolS (PcdBoardPmcPdEnable, 1); +} + + +/** + Configure GPIO, TouchPanel, HDA, PMC, TBT etc. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +AdlPBoardInitBeforeSiliconInit ( + VOID + ) +{ + AdlPInit (); + + AdlPSerialIoI2cPadsTerminationInit (); + AdlPBoardMiscInit (); + AdlPBoardPmcPdInit (); + GpioInit (PcdGetPtr (PcdBoardGpioTable)); + + + + return EFI_SUCCESS; +} +VOID +AdlPBoardSpecificGpioInitPostMem ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16 (PcdBoardId); + // + // Assign FingerPrint, Gnss, Bluetooth & TouchPanel relative GPIO. + // + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + // + //Update PcdBoardRtd3TableSignature per Setup + // + PcdSet64S (PcdBoardRtd3TableSignature, SIGNATURE_64 ('A', 'd', 'l', = 'P', '_', 'R', 'v', 'p')); + // + // Update OEM table ID + // + PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_', '= a', 'd', 'l', 'L', 'P')); + break; + default: + // + //Update PcdBoardRtd3TableSignature per Setup + // + PcdSet64S (PcdBoardRtd3TableSignature, SIGNATURE_64 ('A', 'd', 'l', = 'P', '_', 'R', 'v', 'p')); + // + // Update OEM table ID + // + PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_', '= a', 'd', 'l', 'L', 'P')); + break; + } + //Modify Preferred_PM_Profile field based on Board SKU's. Default is set= to Mobile + // + PcdSet8S (PcdPreferredPmProfile, EFI_ACPI_2_0_PM_PROFILE_MOBILE); + if (PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorUpServer) { + PcdSet8S (PcdPreferredPmProfile, EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SE= RVER); + } +} + +VOID +AdlPInitCommonPlatformPcdPostMem ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16(PcdBoardId); + + PcdSetBoolS (PcdPssReadSN, TRUE); + PcdSet8S (PcdPssI2cSlaveAddress, 0x6E); + PcdSet8S (PcdPssI2cBusNumber, 0x05); + PcdSetBoolS (PcdSpdAddressOverride, FALSE); + + // + // Battery Present + // Real & Virtual battery is need to supported in all except Desktop + // + PcdSet8S (PcdBatteryPresent, BOARD_REAL_BATTERY_SUPPORTED | BOARD_VI= RTUAL_BATTERY_SUPPORTED); + // + // Real Battery 1 Control & Real Battery 2 Control + // + PcdSet8S (PcdRealBattery1Control, 1); + PcdSet8S (PcdRealBattery2Control, 2); + + + // + // H8S2113 SIO, UART + // + PcdSetBoolS (PcdH8S2113SIO, FALSE); + PcdSetBoolS (PcdH8S2113UAR, FALSE); + // + // NCT6776F COM, SIO & HWMON + // + PcdSetBoolS (PcdNCT6776FCOM, FALSE); + PcdSetBoolS (PcdNCT6776FSIO, FALSE); + PcdSetBoolS (PcdNCT6776FHWMON, FALSE); + // + // SMC Runtime Sci Pin + // EC will use eSpi interface to generate SCI + // + PcdSet32S (PcdSmcRuntimeSciPin, 0x00); + + // + // Virtual Button Volume Up & Done Support + // Virtual Button Home Button Support + // Virtual Button Rotation Lock Support + // + PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, TRUE); + PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, TRUE); + PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, TRUE); + PcdSetBoolS (PcdVirtualButtonRotationLockSupport, TRUE); + // + // Slate Mode Switch Support + // + PcdSetBoolS (PcdSlateModeSwitchSupport, TRUE); + // + // Virtual Gpio Button Support + // + PcdSetBoolS (PcdVirtualGpioButtonSupport, TRUE); + + // + // Acpi Enable All Button Support + // + PcdSetBoolS (PcdAcpiEnableAllButtonSupport, TRUE); + // + // Acpi Hid Driver Button Support + // + PcdSetBoolS (PcdAcpiHidDriverButtonSupport, TRUE); + + // + // ADL-P supports EC-PD design, for communication between EC and PD. + // + PcdSetBoolS (PcdUsbcEcPdNegotiation, TRUE); + + +} + +/** + Board init for PEI after Silicon initialized + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +AdlPBoardInitAfterSiliconInit ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "ADLPBoardInitAfterSiliconInit \n")); + //AdlPBoardSpecificGpioInitPostMem (); + AdlPInitCommonPlatformPcdPostMem (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Ald= erlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c new file mode 100644 index 0000000000..904f98b905 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiInitPreMemLib.c @@ -0,0 +1,236 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static EFI_PEI_PPI_DESCRIPTOR mSetupVariablesReadyPpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gSetupVariablesReadyPpiGuid, + NULL +}; + +/** + Alderlake P boards configuration init function for PEI pre-memory phase. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +AdlPInitPreMem ( + VOID + ) +{ + UINT8 MorControl; + + // + // MOR + // + MorControl =3D 0; + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + PcdSet8S (PcdCleanMemory, MorControl & MOR_CLEAR_MEMORY_BIT_MASK); + } + + PcdSet32S (PcdStackBase, PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdT= emporaryRamSize) - (PcdGet32 (PcdFspTemporaryRamSize) + PcdGet32 (PcdFspRes= ervedBufferSize))); + PcdSet32S (PcdStackSize, PcdGet32 (PcdFspTemporaryRamSize)); + + PcdSet8S (PcdCpuRatio, 0x0); + + return EFI_SUCCESS; +} + + +VOID +AdlPMrcConfigInit ( + VOID + ); + +VOID +AdlPSaMiscConfigInit ( + VOID + ); + +VOID +AdlPSaGpioConfigInit ( + VOID + ); + +VOID +AdlPSaDisplayConfigInit ( + VOID + ); + +VOID +AdlPSaUsbConfigInit ( + VOID + ); + +EFI_STATUS +AdlPRootPortClkInfoInit ( + VOID + ); + +EFI_STATUS +AdlPUsbConfigInit ( + VOID + ); + +VOID +AdlPGpioGroupTierInit ( + VOID + ); + + +/** + Notifies the gPatchConfigurationDataPreMemPpiGuid has been Installed + + @param[in] PeiServices General purpose services available to ev= ery PEIM. + @param[in] NotifyDescriptor The notification structure this PEIM reg= istered on install. + @param[in] Ppi The memory discovered PPI. Not used. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +AdlPBoardPatchConfigurationDataPreMemCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + PeiServicesInstallPpi (&mSetupVariablesReadyPpi); + + return RETURN_SUCCESS; +} + +/** + Board Misc init function for PEI pre-memory phase. +**/ +VOID +AdlPBoardMiscInitPreMem ( + VOID + ) +{ + UINT16 BoardId; + BoardId =3D PcdGet16(PcdBoardId); + + // + // OddPower Init + // + PcdSetBoolS (PcdOddPowerInitEnable, FALSE); + + // + // Pc8374SioKbc Present + // + PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE); + + // + // Smbus Alert function Init. + // + PcdSetBoolS (PcdSmbusAlertEnable, FALSE); +} + + +/** + A hook for board-specific initialization prior to memory initialization. + + @retval EFI_SUCCESS The board initialization was successful. +**/ +EFI_STATUS +EFIAPI +AdlPBoardInitBeforeMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "AdlPBoardInitBeforeMemoryInit\n")); + + GetBiosId (NULL); + + AdlPInitPreMem (); + + AdlPBoardMiscInitPreMem (); + + AdlPGpioGroupTierInit (); + + + AdlPMrcConfigInit (); + AdlPSaGpioConfigInit (); + AdlPSaMiscConfigInit (); + Status =3D AdlPRootPortClkInfoInit (); + Status =3D AdlPUsbConfigInit (); + AdlPSaDisplayConfigInit (); + AdlPSaUsbConfigInit (); + if (PcdGetPtr (PcdBoardGpioTableEarlyPreMem) !=3D 0) { + GpioInit (PcdGetPtr (PcdBoardGpioTableEarlyPreMem)); + + MicroSecondDelay (15 * 1000); // 15 ms Delay + } + // Configure GPIO Before Memory + GpioInit (PcdGetPtr (PcdBoardGpioTablePreMem)); + + return EFI_SUCCESS; +} + + +/** + This board service initializes board-specific debug devices. + + @retval EFI_SUCCESS Board-specific debug initialization was successful. +**/ +EFI_STATUS +EFIAPI +AdlPBoardDebugInit ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "AdlPBoardDebugInit\n")); + + return EFI_SUCCESS; +} + +/** + This board service detects the boot mode. + + @retval EFI_BOOT_MODE The boot mode. +**/ +EFI_BOOT_MODE +EFIAPI +AdlPBoardBootModeDetect ( + VOID + ) +{ + EFI_BOOT_MODE BootMode; + + DEBUG ((DEBUG_INFO, "AdlPBoardBootModeDetect\n")); + BootMode =3D DetectBootMode (); + DEBUG ((DEBUG_INFO, "BootMode: 0x%02X\n", BootMode)); + + return BootMode; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/AlderlakeOpenB= oardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 0000000000..f47fc473f2 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,50 @@ +/** @file + PEI Multi-Board Initialization in Post-Memory PEI Library + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +AdlPBoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +AdlPBoardInitAfterSiliconInit ( + VOID + ); + +BOARD_POST_MEM_INIT_FUNC mAdlPBoardInitFunc =3D { + AdlPBoardInitBeforeSiliconInit, + AdlPBoardInitAfterSiliconInit, +}; + +EFI_STATUS +EFIAPI +PeiAdlPMultiBoardInitLibConstructor ( + VOID + ) +{ + UINT8 SkuType; + SkuType =3D PcdGet8 (PcdSkuType); + + if (SkuType=3D=3DAdlPSkuType) { + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + return RegisterBoardPostMemInit (&mAdlPBoardInitFunc); + } + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/AlderlakeOpe= nBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLi= b.inf new file mode 100644 index 0000000000..7bbfbfc7fb --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,156 @@ +## @file +# Component information file for Alderlake Multi-Board Initialization in P= EI post memory phase. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiAdlPMultiBoardInitLib + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiAdlPMultiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + MultiBoardInitSupportLib + PciSegmentLib + GpioLib + HobLib + BoardConfigLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + +[Sources] + PeiInitPostMemLib.c + PeiMultiBoardInitPostMemLib.c + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdSetupEnable + +[Guids] + gPchSetupVariableGuid ## CONSUMES + gSetupVariableGuid ## CONSUMES + +[Pcd] + # Board GPIO Table + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdSataPortsEnable0 + gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile + gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdBoardPmcPdEnable + gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable + + # CPU USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.VpdPcdCpuUsb3OcMap + + + gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation + + # TPM interrupt + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum + + gBoardModuleTokenSpaceGuid.PcdBatteryPresent ## PRODUCE + gBoardModuleTokenSpaceGuid.PcdRealBattery1Control ## PRODUCE + gBoardModuleTokenSpaceGuid.PcdRealBattery2Control ## PRODUCE + #Misc Config + gBoardModuleTokenSpaceGuid.PcdSataLedEnable + gBoardModuleTokenSpaceGuid.PcdVrAlertEnable + gBoardModuleTokenSpaceGuid.PcdBoardBomId + + #TouchPanel Config + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1 + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1Size + + #CVF Config + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvf + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvfSize + + + # PCIE SLOT 1 - X4 CONNECTOR + gBoardModuleTokenSpaceGuid.PcdPcieSlot1WakeGpioPin + gBoardModuleTokenSpaceGuid.PcdPcieSlot1RootPort + gBoardModuleTokenSpaceGuid.PcdDg1VramSRGpio + gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioPolarity + + + # PCIE SLOT 2 - X1 CONNECTOR + gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot2PwrEnableGpioPolarity + gBoardModuleTokenSpaceGuid.PcdPcieSlot2WakeGpioPin + gBoardModuleTokenSpaceGuid.PcdPcieSlot2RootPort + + # PCIE SLOT 3 + gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot3PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot3PwrEnableGpioPolarity + gBoardModuleTokenSpaceGuid.PcdPcieSlot3WakeGpioPin + gBoardModuleTokenSpaceGuid.PcdPcieSlot3RootPort + + # PCH M.2 SSD RTD3 + gBoardModuleTokenSpaceGuid.PcdPchSsd1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPchSsd1PwrEnableGpioPolarity + + # PCH SATA port RTD3 + gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioPolarity + + # PCIe x4 M.2 SSD RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioPolarity + + # I2C Touch Panel 0 & 1 RTD3 + gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress ## PRODUC + gBoardModuleTokenSpaceGuid.PcdPssReadSN + gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber + gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride + + gBoardModuleTokenSpaceGuid.PcdBoardId + gBoardModuleTokenSpaceGuid.PcdSkuType + gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable + + gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature + gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature + + gBoardModuleTokenSpaceGuid.PcdH8S2113SIO + gBoardModuleTokenSpaceGuid.PcdH8S2113UAR + gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM + gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO + gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON + + gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin + + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport + + gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport + gBoardModuleTokenSpaceGuid.PcdVirtualGpioButtonSupport + gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin + gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport + gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport + + + # eDP Display Mux GPIO + gBoardModuleTokenSpaceGuid.PcdDisplayMuxGpioNo + + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBo= ardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 0000000000..3b0ab9fe9b --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,105 @@ +/** @file + PEI Multi-Board Initialization in Pre-Memory PEI Library + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +AdlPBoardDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +AdlPMultiBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +AdlPBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +AdlPBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +AdlPBoardInitBeforeMemoryInit ( + VOID + ); + + +EFI_STATUS +EFIAPI +AdlPBoardPatchConfigurationDataPreMemCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +static EFI_PEI_NOTIFY_DESCRIPTOR mOtherBoardPatchConfigurationDataPreMemNo= tifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gPatchConfigurationDataPreMemPpiGuid, + AdlPBoardPatchConfigurationDataPreMemCallback +}; + +BOARD_DETECT_FUNC mAdlPBoardDetectFunc =3D { + AdlPMultiBoardDetect +}; + +BOARD_PRE_MEM_INIT_FUNC mAdlPBoardPreMemInitFunc =3D { + AdlPBoardDebugInit, + AdlPBoardBootModeDetect, + AdlPBoardInitBeforeMemoryInit, + NULL, // BoardInitBeforeTempRamExit + NULL, // BoardInitAfterTempRamExit +}; + +EFI_STATUS +EFIAPI +AdlPMultiBoardDetect ( + VOID + ) +{ + UINT8 SkuType; + DEBUG ((DEBUG_INFO, " In AdlPMultiBoardDetect \n")); + + AdlPBoardDetect (); + + SkuType =3D PcdGet8 (PcdSkuType); + if (SkuType=3D=3DAdlPSkuType) { + RegisterBoardPreMemInit (&mAdlPBoardPreMemInitFunc); + PeiServicesNotifyPpi (&mOtherBoardPatchConfigurationDataPreMemNotifyLi= st); + } else { + DEBUG ((DEBUG_WARN,"Not a Valid Alderlake P Board\n")); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PeiAdlPMultiBoardInitPreMemLibConstructor ( + VOID + ) +{ + return RegisterBoardDetect (&mAdlPBoardDetectFunc); +} \ No newline at end of file diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/Boa= rdInitLib/Pei/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/AlderlakeOpen= BoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.= inf new file mode 100644 index 0000000000..edc78c1b85 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitL= ib/Pei/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,230 @@ +## @file +# Component information file for PEI Alderlake P Board Init Pre-Mem Library +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiAdlPMultiBoardInitPreMemLib + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiAdlPMultiBoardInitPreMemLibConstru= ctor + +[LibraryClasses] + BaseLib + BiosIdLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + MultiBoardInitSupportLib + PeiLib + BoardConfigLib + PeiBootModeLib + PchInfoLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + AlderlakeSiliconPkg/SiPkg.dec + BoardModulePkg/BoardModulePkg.dec + +[Sources] + PeiInitPreMemLib.c + PeiMultiBoardInitPreMemLib.c + PeiDetect.c + BoardSaInitPreMemLib.c + BoardPchInitPreMemLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdData00 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData01 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData10 + gBoardModuleTokenSpaceGuid.PcdMrcSpdData11 + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15 + + #MRC Config + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + + #MISC + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent + gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable + gBoardModuleTokenSpaceGuid.PcdWakeupType + gBoardModuleTokenSpaceGuid.PcdSetupEnable + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb2OverCurrentPinTable + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb3OverCurrentPinTable + + #Board Information + gBoardModuleTokenSpaceGuid.PcdPlatformGeneration + gBoardModuleTokenSpaceGuid.PcdSpdPresent + gBoardModuleTokenSpaceGuid.PcdPlatformType + gBoardModuleTokenSpaceGuid.PcdPlatformFlavor + gBoardModuleTokenSpaceGuid.PcdBoardRev + gBoardModuleTokenSpaceGuid.PcdBoardId + gBoardModuleTokenSpaceGuid.PcdSkuType + gBoardModuleTokenSpaceGuid.PcdBoardBomId + gBoardModuleTokenSpaceGuid.PcdBoardType + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap + gBoardModuleTokenSpaceGuid.VpdPcdUSB2OCMap + gBoardModuleTokenSpaceGuid.VpdPcdUSB3OCMap + gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData + gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdDisplayId ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdCpuRatio + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdStackBase + gBoardModuleTokenSpaceGuid.PcdStackSize + gBoardModuleTokenSpaceGuid.PcdNvsBufferPtr + gBoardModuleTokenSpaceGuid.PcdCleanMemory + + #SA GPIO Config + gBoardModuleTokenSpaceGuid.PcdRootPortIndex + + # PCIE Slot1 (x4 Connector) GPIO PCDs + gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioPolarity + + + # PCIe x4 M.2 SSD1 RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioPolarity + + # PCIe x4 M.2 SSD2 RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioPolarity + + # CPU PCIe x8 DG RTD3 + gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioPolarity + gBoardModuleTokenSpaceGuid.PcdPcieDG2WakeGpioPin + + # CPU PEG Slot1 RTD3 + gBoardModuleTokenSpaceGuid.PcdPegSlot1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPegSlot1PwrEnableGpioPolarity + gBoardModuleTokenSpaceGuid.PcdPegSlot1WakeGpioPin + gBoardModuleTokenSpaceGuid.PcdPegSlot1RootPort + + # CPU PEG Slot2 RTD3 + gBoardModuleTokenSpaceGuid.PcdPegSlot2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPegSlot2PwrEnableGpioPolarity + gBoardModuleTokenSpaceGuid.PcdPegSlot2WakeGpioPin + gBoardModuleTokenSpaceGuid.PcdPegSlot2RootPort + + #SA USB Config + gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap + + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 + gBoardModuleTokenSpaceGuid.PcdPcieClock1 + gBoardModuleTokenSpaceGuid.PcdPcieClock2 + gBoardModuleTokenSpaceGuid.PcdPcieClock3 + gBoardModuleTokenSpaceGuid.PcdPcieClock4 + gBoardModuleTokenSpaceGuid.PcdPcieClock5 + gBoardModuleTokenSpaceGuid.PcdPcieClock6 + gBoardModuleTokenSpaceGuid.PcdPcieClock7 + gBoardModuleTokenSpaceGuid.PcdPcieClock8 + gBoardModuleTokenSpaceGuid.PcdPcieClock9 + gBoardModuleTokenSpaceGuid.PcdPcieClock10 + gBoardModuleTokenSpaceGuid.PcdPcieClock11 + gBoardModuleTokenSpaceGuid.PcdPcieClock12 + gBoardModuleTokenSpaceGuid.PcdPcieClock13 + gBoardModuleTokenSpaceGuid.PcdPcieClock14 + gBoardModuleTokenSpaceGuid.PcdPcieClock15 + + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + + + # WWAN Full Card Power Off and reset pins + gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## = PRODUCES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem ## = PRODUCES + + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSU= MES + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSU= MES + + gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES + +[Guids] + gFspNonVolatileStorageHobGuid + gEfiMemoryOverwriteControlDataGuid + gSetupVariableGuid + gSaSetupVariableGuid + gCpuSetupVariableGuid + gPchSetupVariableGuid + gMeSetupVariableGuid + gSiSetupVariableGuid + +[Ppis] + gPatchConfigurationDataPreMemPpiGuid ## NOTIFY + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gSetupVariablesReadyPpiGuid ## PRODUCES --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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