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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,AbdulLateef.Attar@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 2FSri3hec522tc4f2Xjo1Zj0x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705550070302100001 Content-Type: text/plain; charset="utf-8" From: Abdul Lateef Attar Adds cpuid macro for AMD extended CPU topology. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Abdul Lateef Attar Acked-by: Michael D Kinney --- MdePkg/Include/Register/Amd/Cpuid.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/= Amd/Cpuid.h index 44394fc7a4..add43c40aa 100644 --- a/MdePkg/Include/Register/Amd/Cpuid.h +++ b/MdePkg/Include/Register/Amd/Cpuid.h @@ -6,7 +6,7 @@ If a register returned is a single 32-bit value, then a data structure is not provided for that register. =20 - Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ Copyright (c) 2017 - 2024, Advanced Micro Devices. All rights reserved.<= BR> =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -42,6 +42,27 @@ CPUID Signature Information /// @} /// =20 +/** + CPUID Extended Topology Enumeration + + @note + Reference: AMD64 Architecture Programmer=E2=80=99s Manual Volume 3: Gene= ral-Purpose and System Instructions, + Revision 3.35 Appendix E, + E.4.24 Function 8000_0026=E2=80=94Extended CPU Topology: + CPUID Fn8000_0026 reports extended topology information for logical pr= ocessors, including + asymmetric and heterogenous topology descriptions. Individual logical = processors may report + different values in systems with asynchronous and heterogeneous topolo= gies. + The topology level is selected by the value passed to the instruction = in ECX. To discover the topology + of a system, software should execute CPUID Fn8000_0026 with increasing= ECX values, starting with + a value of zero, until the returned hierarchy level type (CPUID Fn8000= _0026_ECX[LevelType]) is + equal to zero. It is not guaranteed that all topology level types are = present in the system + + @param EAX AMD_CPUID_EXTENDED_TOPOLOGY (0x80000026) + @param ECX Level number + +**/ +#define AMD_CPUID_EXTENDED_TOPOLOGY 0x80000026 + /** CPUID Extended Processor Signature and Features =20 --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 18 Jan 2024 03:54:27 +0000 X-Received: from SATLEXMB08.amd.com (10.181.40.132) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 17 Jan 2024 21:54:27 -0600 X-Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Wed, 17 Jan 2024 19:54:26 -0800 X-Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 17 Jan 2024 21:54:24 -0600 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Michael D Kinney , Liming Gao , Zhiguang Liu , Ray Ni , "Rahul Kumar" , Gerd Hoffmann Subject: [edk2-devel] [PATCH RESEND v2 2/2] UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology Date: Thu, 18 Jan 2024 09:24:09 +0530 Message-ID: In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|DM4PR12MB6376:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d5f4d3f-c15c-4ecc-4f58-08dc17d92aef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: HTSAO5TBTmx8VoFrFMvDLz2Kzt3Hf4jU/EAy9eHb8fNWNDXKn7tJ4AsODNcasRb/399xxZI5VUSurzVEKf1syehX6rylR0+aIfZ/LRkOKu/oBT3p7P7jWOSbwcIOUKflwblBllJilER00291zv6b6ftezIRDxz9IS7lPSiiywvF4HVgTxxohwwnI9pZ+NUl5sPkiYsdUtrNJfqtUQ/QxxeGV5MyVtp1bIkq3HKF1LlpdbaXX0JTxf4yMVoOM5yoi+j0kciMlzKlpJfSDVRyESu6imt37Ik+6QjhUTO+fjQo8XSh86YO5XQ7IZh1nl6+PqPSj3ivBP05eJnAD+MtUQs68VavATV9kJniO7oS5KL4fCLyn7wwG4YD8ybO/0GISWAORFz9SZjwRM6YGzPDDfg9q4qQlTALykkKyXrbpXtDyt0qDt/B++A5tCU5vKgJIjTGSlr6VvHyS9ioVG5VmQ6Utug4FHN0eW+hxJ2GU160bHvXBVoO0P1i7j/hyuaZIYpukioBE2n3YI32vKnXHSOn0KsihJ5bR16n+A1aV5g8KjHr/cA++rHjG11y45Frs7wLz+s3sHBp22kMsENjWo/c7LLjaBsR6dO6+tgDv3sTH1uhgA2Fo9I+kFl8BzLsid5HUCXutt3EvWjGfBTz8lXiWjqp4Awy49IbY8rCyD7qMPhQ+SAQjyRZtICWAxLg7G+60VYL3y/FO0dv8HQOe+sJfXzfTYQZlWpQlVmlGLfccvPSCeJRaWPV9q77k049iqKBwVY2qObzEQvtRMUrGKQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2024 03:54:27.4811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d5f4d3f-c15c-4ecc-4f58-08dc17d92aef X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6376 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,AbdulLateef.Attar@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: OmitOPNJVlf01jtLQa80chS9x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705550073968100011 Content-Type: text/plain; charset="utf-8" From: Abdul Lateef Attar This patch adds support for AMD's new extended topology. If processor supports CPUID 80000026 leaf then obtain the topology information using new method. Algorithm: if CPUID is AMD: then check for AMD's extended cpu tology leaf. if yes then extract cpu tology based on AMD programmer manual's instruction. else then fallback to existing topology function. endif endif Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Abdul Lateef Attar --- .../Library/BaseXApicLib/BaseXApicLib.c | 126 +++++++++++++++++- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 126 +++++++++++++++++- 2 files changed, 250 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index efb9d71ca1..c4457d98b3 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
- Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1157,6 +1157,125 @@ GetProcessorLocationByApicId ( } } =20 +/** + Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor fam= ily. + + The algorithm assumes the target system has symmetry across physical + package boundaries with respect to the number of threads per core, numbe= r of + cores per module, number of modules per die, number + of dies per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Die Returns the processor die ID. + @param[out] Tile Returns zero. + @param[out] Module Returns the processor module ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +AmdGetProcessorLocation2ByApicId ( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Die OPTIONAL, + OUT UINT32 *Tile OPTIONAL, + OUT UINT32 *Module OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxExtendedCpuIdIndex; + UINT32 TopologyLevel; + UINT32 PreviousLevel; + UINT32 Data; + + if (Die !=3D NULL) { + *Die =3D 0; + } + + if (Tile !=3D NULL) { + *Tile =3D 0; + } + + if (Module !=3D NULL) { + *Module =3D 0; + } + + PreviousLevel =3D 0; + TopologyLevel =3D 0; + + /// Check if extended toplogy supported + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); + if (MaxExtendedCpuIdIndex >=3D AMD_CPUID_EXTENDED_TOPOLOGY) { + do { + AsmCpuidEx ( + AMD_CPUID_EXTENDED_TOPOLOGY, + TopologyLevel, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + + if (ExtendedTopologyEbx.Bits.LogicalProcessors =3D=3D CPUID_EXTENDED= _TOPOLOGY_LEVEL_TYPE_INVALID) { + /// if this fails at first level + /// then will fall back to non-extended topology + break; + } + + Data =3D InitialApicId >> PreviousLevel; + Data &=3D (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLeve= l)) - 1; + + switch (ExtendedTopologyEcx.Bits.LevelType) { + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT: + if (Thread !=3D NULL) { + *Thread =3D Data; + } + + break; + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE: + if (Core !=3D NULL) { + *Core =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE: + if (Module !=3D NULL) { + *Module =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE: + if (Die !=3D NULL) { + *Die =3D Data; + } + + break; + default: + break; + } + + TopologyLevel++; + PreviousLevel =3D ExtendedTopologyEax.Bits.ApicIdShift; + } while (ExtendedTopologyEbx.Bits.LogicalProcessors !=3D CPUID_EXTENDE= D_TOPOLOGY_LEVEL_TYPE_INVALID); + + if (Package !=3D NULL) { + *Package =3D InitialApicId >> PreviousLevel; + } + } + + /// If extended topology CPUID is not supported + /// OR, execution of AMD_CPUID_EXTENDED_TOPOLOGY at level 0 fails(return= 0). + if (TopologyLevel =3D=3D 0) { + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); + } + + return; +} + /** Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor. =20 @@ -1194,6 +1313,11 @@ GetProcessorLocation2ByApicId ( UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_= DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_= TYPE_DIE + 2]; =20 + if (StandardSignatureIsAuthenticAMD ()) { + AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, M= odule, Core, Thread); + return; + } + for (LevelType =3D 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] =3D 0; } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index c0a8475833..0560d38ce5 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,7 +5,7 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
- Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1396,6 +1396,125 @@ GetProcessorLocationByApicId ( } } =20 +/** + Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor fam= ily. + + The algorithm assumes the target system has symmetry across physical + package boundaries with respect to the number of threads per core, numbe= r of + cores per module, number of modules per die, number + of dies per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Die Returns the processor die ID. + @param[out] Tile Returns zero. + @param[out] Module Returns the processor module ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +AmdGetProcessorLocation2ByApicId ( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Die OPTIONAL, + OUT UINT32 *Tile OPTIONAL, + OUT UINT32 *Module OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxExtendedCpuIdIndex; + UINT32 TopologyLevel; + UINT32 PreviousLevel; + UINT32 Data; + + if (Die !=3D NULL) { + *Die =3D 0; + } + + if (Tile !=3D NULL) { + *Tile =3D 0; + } + + if (Module !=3D NULL) { + *Module =3D 0; + } + + PreviousLevel =3D 0; + TopologyLevel =3D 0; + + /// Check if extended toplogy supported + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); + if (MaxExtendedCpuIdIndex >=3D AMD_CPUID_EXTENDED_TOPOLOGY) { + do { + AsmCpuidEx ( + AMD_CPUID_EXTENDED_TOPOLOGY, + TopologyLevel, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + + if (ExtendedTopologyEbx.Bits.LogicalProcessors =3D=3D CPUID_EXTENDED= _TOPOLOGY_LEVEL_TYPE_INVALID) { + /// if this fails at first level + /// then will fall back to non-extended topology + break; + } + + Data =3D InitialApicId >> PreviousLevel; + Data &=3D (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLeve= l)) - 1; + + switch (ExtendedTopologyEcx.Bits.LevelType) { + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT: + if (Thread !=3D NULL) { + *Thread =3D Data; + } + + break; + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE: + if (Core !=3D NULL) { + *Core =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE: + if (Module !=3D NULL) { + *Module =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE: + if (Die !=3D NULL) { + *Die =3D Data; + } + + break; + default: + break; + } + + TopologyLevel++; + PreviousLevel =3D ExtendedTopologyEax.Bits.ApicIdShift; + } while (ExtendedTopologyEbx.Bits.LogicalProcessors !=3D CPUID_EXTENDE= D_TOPOLOGY_LEVEL_TYPE_INVALID); + + if (Package !=3D NULL) { + *Package =3D InitialApicId >> PreviousLevel; + } + } + + /// If extended topology CPUID is not supported + /// OR, execution of AMD_CPUID_EXTENDED_TOPOLOGY at level 0 fails(return= 0). + if (TopologyLevel =3D=3D 0) { + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); + } + + return; +} + /** Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor. =20 @@ -1433,6 +1552,11 @@ GetProcessorLocation2ByApicId ( UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_= DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_= TYPE_DIE + 2]; =20 + if (StandardSignatureIsAuthenticAMD ()) { + AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, M= odule, Core, Thread); + return; + } + for (LevelType =3D 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] =3D 0; } --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113983): https://edk2.groups.io/g/devel/message/113983 Mute This Topic: https://groups.io/mt/103802342/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-