From nobody Wed May 22 03:25:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98399+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98399+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673567816; cv=none; d=zohomail.com; s=zohoarc; b=QzAAZhol2GG68BLSpdOIQl+clbmidFLEDwaqQgSV50kTfTHyK31R3ptssw3yg2INYDIyeDyPpwSxbMuxK5PhAC8C0VzFBloI6xGQWQuQeozkRfbcN6MGmpP2glVutcVckB6owp5m5z+sFKHzL1o5VeLbR4n35OvugNZ5zYc0GLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673567816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Q4tcAeYYqbutQZ78BTKzPF3fur9BCInq6cipSFUsskk=; b=ZpazJQtNrmgEgXpsagQaw1ytuq8O5coizPvf9AQ5QchvBKIPIKXs/l8VQcJPSEkHR5G1CJBfwXZ6k756+drbmjjHlwHoNB858fY/WDh0KA1qm9dU88o9sQVMObvXIDLRlw667IarfROdf1EQPZyRDV8RbbyUOs66S/6BElKlH/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98399+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673567816883234.6469865650206; Thu, 12 Jan 2023 15:56:56 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id rgzUYY1788612x4VY6ZPLsy3; Thu, 12 Jan 2023 15:56:56 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.73051.1673567815893727645 for ; Thu, 12 Jan 2023 15:56:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410100303" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="410100303" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 15:56:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="607972202" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="607972202" X-Received: from iworam-desk.amr.corp.intel.com ([10.24.80.243]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 15:56:54 -0800 From: "Isaac Oram" To: devel@edk2.groups.io Cc: Isaac Oram , Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg: Update to Whitley FSP 4.2.0.2A Date: Thu, 12 Jan 2023 15:56:34 -0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: fYYlqTsgqopBK5jNXDegimYpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673567816; bh=pxWLFwnc51QZ3VE04BxH5Av5cu2iC3yYFQ+Hn9twz2A=; h=Cc:Date:From:Reply-To:Subject:To; b=jYBEnP/biOgkBGeLIcKlqFnpjNiZPn8wCaZkJf7eSfa5zT9mEkO0IMxzarx9XMEZsnl 1dq4vmsvsbqj9Ro5HcQZ0fKEZGAsUuXafGyECga5jQdWTebQWWV2x2910g2orJjYVFbvf XPgHGuJJMlfIaG539Y5qao+HIFQHdfoPnBU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673567817790100001 Content-Type: text/plain; charset="utf-8" This contains binary interface changes and requires FSP 4.2.0.2A or later Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram Reviewed-by: Nate DeSimone --- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 23 +++++++++------- .../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 4 ++- .../Cpu/Include/CpuPolicyPeiDxeCommon.h | 2 +- .../WhitleySiliconPkg/Include/BdatSchema.h | 16 +++++++----- .../Include/Guid/MemoryMapData.h | 4 ++- .../Include/Guid/SocketIioVariable.h | 13 +++++++--- .../Include/Guid/SocketMemoryVariable.h | 3 +++ .../Include/Guid/SocketPciResourceData.h | 4 ++- .../Guid/SocketPowermanagementVariable.h | 2 ++ .../Guid/SocketProcessorCoreVariable.h | 2 +- .../WhitleySiliconPkg/Include/IioConfig.h | 11 +++----- .../Intel/WhitleySiliconPkg/Include/IioRegs.h | 1 - .../Include/Library/EnhancedWarningLogLib.h | 2 -- .../Include/PlatformInfoTypes.h | 16 +++++++----- .../Include/Ppi/MemoryPolicyPpi.h | 10 +++++++ .../Include/Ppi/RasImcS3Data.h | 6 ----- .../WhitleySiliconPkg/Include/Upi/KtiHost.h | 2 -- .../Core/Include/DataTypes.h | 10 ++++++- .../BaseMemoryCoreLib/Core/Include/MemHost.h | 6 +---- .../BaseMemoryCoreLib/Platform/PlatformHost.h | 5 ---- .../Include/Private/Library/PchSpiCommonLib.h | 1 - .../Product/Whitley/SiliconPkg10nmPcds.dsc | 5 ++++ .../SecurityIp/SecurityIpSgxTem1v0_Inputs.h | 2 +- .../SecurityIp/SecurityIpSgxTem1v0_Outputs.h | 2 +- .../Intel/WhitleySiliconPkg/SiliconPkg.dec | 26 ++++++++++++------- 25 files changed, 106 insertions(+), 72 deletions(-) diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/Wh= itleySiliconPkg/CpRcPkg.dec index 2ccdbffa35..db61caf399 100644 --- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec @@ -252,9 +252,9 @@ WhitleySiliconPkg/CpRcPkg.dec } gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0 - gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|4 gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2 - gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x003a + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x002A =20 # # MRC DEFAULT SETTINGS @@ -273,7 +273,7 @@ # gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | = 0| UINT8|0x00000040 =20 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE= |BOOLEAN|0x0000003A + gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | = FALSE|BOOLEAN|0x0000003A =20 =20 gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | = FALSE|BOOLEAN|0x00000060 @@ -285,7 +285,7 @@ gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | = 0x2| UINT8|0x00000066 gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | = FALSE|BOOLEAN|0x00000067 gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | = 0x6| UINT8|0x00000068 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOO= LEAN|0x00000069 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | = TRUE|BOOLEAN|0x00000069 gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | = TRUE| UINT8|0x0000006A =20 =20 @@ -293,10 +293,10 @@ gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHea= lthConfig"| VOID*|0x00000070 gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | = FALSE|BOOLEAN|0x00000071 gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | = FALSE|BOOLEAN|0x00000072 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | = 1| UINT8|0x00000073 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | = 1| UINT8|0x00000074 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2= | UINT8|0x0000011F - gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE= |BOOLEAN|0x00000120 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | = 1| UINT8|0x00000073 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | = 1| UINT8|0x00000074 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | = 2| UINT8|0x0000011F + gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | = TRUE|BOOLEAN|0x00000120 gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | = FALSE|BOOLEAN|0x00000075 #option to choose Mem Boot Health configuration type. 00=3D>Auto (Use de= faults), 01=3D>Manual (Override defaults with setup option), 02=3D>Disable = (Disable feature) gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | = 00| UINT8|0x00000076 @@ -360,6 +360,11 @@ # Ctl timing: CtlAll gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | = 5| UINT8|0x00000131 =20 + #MC VC0 Deadlock Breaker + gEfiCpRcPkgTokenSpaceGuid.PcdKeepStarveSettings | = TRUE| BOOLEAN|0x00000132 + gEfiCpRcPkgTokenSpaceGuid.PcdStarveTimer | = 18| UINT8|0x00000133 + gEfiCpRcPkgTokenSpaceGuid.PcdStarveThreshold | = 4| UINT8|0x00000134 + #Reset on Critical Margin failure to perform Memory Training from scratch gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | = 1| UINT8|0x00000087 =20 @@ -526,7 +531,7 @@ gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000= 036 gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x0= 0000118 ## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor - gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C + gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xC|UINT16|0x0000003C gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D =20 [PcdsDynamicEx] diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Int= el/WhitleySiliconPkg/Cpu/CpuRcPkg.dec index 7b027b58c6..763b9d31e4 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec @@ -91,7 +91,9 @@ # @Prompt CPU Config Register Table Entry Maximum Count. gCpuPkgTokenSpaceGuid.PcdCpuConfigRegTblEntryMaxCount|0x64|UINT16|0x6000= 0022 =20 -[PcdsDynamic, PcdsDynamicEx] + gCpuPkgTokenSpaceGuid.PcdCpuLowestApicIdAsBsp|TRUE|BOOLEAN|0x60000023 + +[PcdsDynamicEx] gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 =20 gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012 diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCom= mon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h index 6e84e0f7a6..dc5e09ea19 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h @@ -52,7 +52,7 @@ typedef struct { UINT8 CpuMtoIWa; BOOLEAN RunCpuPpmInPei; BOOLEAN AcExceptionOnSplitLockEnable; - BOOLEAN CpuCrashLogGprs; + BOOLEAN CpuCrashDataGprs; } CPU_POLICY_COMMON; =20 #endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h b/Silicon= /Intel/WhitleySiliconPkg/Include/BdatSchema.h index 0b80015c65..010e8183af 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h @@ -131,12 +131,16 @@ typedef struct { // List of all entry types supported by this revision of memory training d= ata structure // typedef enum { - MemTrainingDataCapability =3D 0, - MemTrainingDataIoGroup =3D 1, - MemTrainingDataDram =3D 2, - MemTrainingDataRcd =3D 3, - MemTrainingDataIoSignal =3D 4, - MemTrainingDataIoLatency =3D 5, + MemTrainingDataCapability =3D 0, + MemTrainingDataIoGroup =3D 1, + MemTrainingDataDram =3D 2, + MemTrainingDataRcd =3D 3, + MemTrainingDataIoSignal =3D 4, + MemTrainingDataIoLatency =3D 5, + MemTrainingDataPpin =3D 6, + MemTrainingDataBoardUuid =3D 7, + MemTrainingDataTurnaround =3D 8, + MemTrainingDataDcPmmTurnaround =3D 9, =20 MemTrainingDataTypeMax, MemTrainingDataTypeDelim =3D MAX_INT32 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b= /Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h index 73f303594a..f7a14ff5f4 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h @@ -85,7 +85,9 @@ struct ChannelDevice { UINT8 SpareLogicalRank[MAX_SPARE_RANK]; = // Logical rank, selected as Spare UINT8 SparePhysicalRank[MAX_SPARE_RANK]; = // Physical rank, selected as spare UINT16 SpareRankSize[MAX_SPARE_RANK]; = // spare rank size - UINT8 EnabledLogicalRanks; // Bitmap of Lo= gical ranks that are enabled + UINT8 EnabledLogicalRanks; = // Bitmap of Logical ranks that are enabled + UINT8 DdrPopulationMap; = // Bitmap to indicate location of DDR DIMMs within the channel memory slots= (BIT0: Ch.D0, BIT1: CH.D1) + UINT8 PmemPopulationMap; = // Bitmap to indicate location of PMem modules within the channel memory sl= ots (BIT0: Ch.D0, BIT1: CH.D1) MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM]; }; =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable= .h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h index a820cc6c25..0fafd00c98 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h @@ -133,8 +133,8 @@ typedef struct { UINT8 PcieSubSystemMode[TOTAL_IOU_VAR]; UINT8 CompletionTimeoutGlobal; UINT8 CompletionTimeoutGlobalValue; - UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup - UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 ReservedCto[MAX_SOCKET]; // On Setup + UINT8 ReservedCtov[MAX_SOCKET]; // On Setup UINT8 CoherentReadPart; UINT8 CoherentReadFull; UINT8 PcieGlobalAspm; @@ -372,7 +372,7 @@ typedef struct { UINT8 ReservedS19; // On Setup UINT8 ReservedS20; // On Setup UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup - UINT8 ReservedS22[TOTAL_PORTS_VAR]; // On Setup + UINT8 CompletionTimeoutValue[TOTAL_PORTS_VAR]; // On = Setup =20 UINT8 ReservedS23[TOTAL_PORTS_VAR]; //On Setup UINT8 ReservedS24[TOTAL_PORTS_VAR]; //On Setup @@ -437,7 +437,12 @@ typedef struct { UINT8 VtdPciAcsCtlBit2; UINT8 VtdPciAcsCtlBit3; UINT8 VtdPciAcsCtlBit4; - UINT8 AltAttenTable[TOTAL_PORTS_VAR]; //On Setup + UINT8 AltAttenTable[TOTAL_PORTS_VAR]; + UINT8 PciePort10bitTag[TOTAL_PORTS_VAR]; // Controls port support for= 10-bit Tag + + UINT8 MaskPcieRpWarmResetMcaWa; //on Setup + UINT8 PostedInterruptThrottle; + } SOCKET_IIO_CONFIGURATION; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVaria= ble.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h index 533489fafc..f8710ee7bb 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h @@ -469,6 +469,9 @@ typedef struct { UINT8 RmtMinimumMarginCheck; =20 UINT8 ReservedS149; + UINT8 pTRR; + UINT8 AdrPatrolScrubDisable; + } SOCKET_MEMORY_CONFIGURATION; =20 #pragma pack() diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResource= Data.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData= .h index 567a44e73f..439f61c88d 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h @@ -41,11 +41,13 @@ typedef struct { // If anything changed reset the system PCI resource configuration. // UINT64 MmioHBase; - UINT64 MmioHLimit; + UINT64 MmioHGranularity; UINT32 MmioLBase; UINT32 MmioLLimit; + UINT32 MmioLGranularity; UINT16 IoBase; UINT16 IoLimit; + UINT16 IoGranularity; UINT16 StackPresentBitmap[MAX_SOCKET]; // // Used by the PciHostBridge DXE driver, these variables don't need to b= e exposed through setup options diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanage= mentVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowerma= nagementVariable.h index 460e6e300b..c29bf51cb6 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVar= iable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVar= iable.h @@ -290,6 +290,8 @@ typedef struct { UINT8 RunCpuPpmInPei; =20 UINT8 UncoreFreqRaplLimit; + + UINT8 PrgTjOffsetEn; } SOCKET_POWERMANAGEMENT_CONFIGURATION; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCo= reVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessor= CoreVariable.h index 52ab370ce7..ca4ebd4d4a 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVaria= ble.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVaria= ble.h @@ -136,7 +136,7 @@ typedef struct { UINT8 CFRS3mManualCommit; UINT8 CFRPucodeEnable; UINT8 CFRPucodeManualCommit; - UINT8 CpuCrashLogGprs; + UINT8 CpuCrashDataGprs; } SOCKET_PROCESSORCORE_CONFIGURATION; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/= Intel/WhitleySiliconPkg/Include/IioConfig.h index a8e3e69255..385db192d2 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h @@ -45,6 +45,7 @@ typedef struct { UINT8 PcieAspm[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup UINT8 PcieTxRxDetPoll[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; + UINT8 PciePort10bitTag[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; UINT8 PciePtm; UINT8 PcieHotPlugEnable; UINT8 PCIe_LTR; @@ -104,8 +105,7 @@ typedef struct { =20 UINT8 CompletionTimeoutGlobal; UINT8 CompletionTimeoutGlobalValue; - UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup - UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; /= / On Setup UINT8 CoherentReadPart; UINT8 CoherentReadFull; UINT8 PcieGlobalAspm; @@ -124,7 +124,6 @@ typedef struct { UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup - UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup @@ -273,6 +272,7 @@ typedef struct { UINT8 ProblematicPort; //on Setup UINT8 DmiAllocatingFlow; //on Setup UINT8 PcieAllocatingFlow; //on Setup + UINT8 MaskPcieRpWarmResetMcaWa; //on Setup UINT8 PcieAcpiHotPlugEnable; //on Setup BOOLEAN PcieLowLatencyRetimersEnabled; UINT8 HaltOnDmiDegraded; //on Setup @@ -335,13 +335,10 @@ typedef struct { UINT32 ReservedAC[MAX_SOCKET][NUM_DEVHIDE_UNCORE_STACKS][NUM_DEVHIDE_RE= GS_PER_STACK]; UINT32 ReservedAD[MAX_SOCKET][NUM_DEVHIDE_IIO_STACKS][NUM_DEVHIDE_REGS_= PER_STACK]; =20 - UINT8 ReservedAE[MAX_TOTAL_PORTS]; // On Setup - UINT8 ReservedAF[MAX_TOTAL_PORTS]; UINT8 ReservedAG[MAX_TOTAL_PORTS]; // On Setup BOOLEAN ReservedAH; // On Setup =20 - /** =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO = Global Performance Tuner Related Setup Options =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -374,7 +371,6 @@ typedef struct { UINT8 MSINFATEN[MAX_TOTAL_PORTS]; UINT8 MSICOREN[MAX_TOTAL_PORTS]; UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; - UINT8 DISL0STx[MAX_TOTAL_PORTS]; UINT8 P2PRdDis[MAX_TOTAL_PORTS]; UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; UINT8 ACPIHP[MAX_TOTAL_PORTS]; @@ -393,6 +389,7 @@ typedef struct { IIO_PCIE_CONFIG_DATA IioPcieConfig; =20 UINT32 VtdDisabledBitmask[MAX_SOCKET]; + UINT8 PostedInterruptThrottle; } IIO_CONFIG; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/In= tel/WhitleySiliconPkg/Include/IioRegs.h index 37a1e627da..66cb1e3dfc 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h @@ -128,7 +128,6 @@ #define PCIE_PORT_0_FUNC_0 0x00 =20 #define PCIE_PORT_1A_DEV_1 0x02 -#define PCIE_PORT_1A_FUNC_1 0x00 #define PCIE_PORT_1B_DEV_1 0x03 #define PCIE_PORT_1C_DEV_1 0x04 #define PCIE_PORT_1D_DEV_1 0x05 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarnin= gLogLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarning= LogLib.h index 211dc48c86..745a52dafe 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib= .h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib= .h @@ -191,9 +191,7 @@ typedef struct { UINT32 EccS; UINT32 Chunk; UINT32 Column; - UINT32 ColumnExt; UINT32 Row; - UINT32 RowExt; UINT32 Bank; UINT32 Rank; UINT32 Subrank; diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index 8fc0efec24..0c14a2409f 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -41,10 +41,10 @@ typedef enum { TypeWilsonCityModular, TypeCoyotePass, TypeIdaville, - TypeMoroCityRP, - TypeBrightonCityRp, + TypeMoroCityRP =3D 0x0E, //maps to PcdDefaultBoardId + TypeBrightonCityRp =3D 0x0F, //maps to PcdDefaultBoardId value TypeJacobsville, - TypeSnrSvp, + TypeSnrSvp =3D 0x11, //maps to PcdDefaultBoardId TypeSnrSvpSodimm, TypeJacobsvilleMDV, TypeFrostCreekRP, @@ -64,13 +64,15 @@ typedef enum { TypeArcherCityXPV, TypeBigPineKey, TypeExperWorkStationRP, - TypeJunctionCity, - TypeAowanda, + TypeAmericanPass, EndOfEfiPlatformTypeEnum, // // Vendor board range currently starts at 0x80 // - TypeBoardPortTemplate // 0x80 + TypeBoardPortTemplate, // 0x80 + TypeJunctionCity, + TypeAowanda, + EndOfVendorPlatformTypeEnum } EFI_PLATFORM_TYPE; =20 #define TypePlatformUnknown 0xFF @@ -78,7 +80,7 @@ typedef enum { #define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 #define TypePlatformDefault TypeWilsonPointRP #define TypePlatformVendorMin 0x80 -#define TypePlatformVendorMax TypeBoardPortTemplate - 1 +#define TypePlatformVendorMax EndOfVendorPlatformTypeEnum - 1 =20 // // CPU type: Standard (no MCP), -F, etc diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h = b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h index 38b90713f7..7a86804d9b 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h @@ -1905,6 +1905,7 @@ struct memSetup { /// 1 =3D High
/// 2 =3D Low
UINT8 PanicWm; + UINT8 pTRR; =20 /// @brief /// Enable/Disable LRDIMM DB DFE.
@@ -1923,6 +1924,15 @@ struct memSetup { // UINT8 VirtualNumaEnable; =20 + /// + /// @brief + /// Enable/Disable patrol scrub when entering the ADR.
+ /// @details + /// 0 - disable.
+ /// 1 - enable.
+ // + UINT8 AdrPatrolScrubDisable; + /// /// @brief /// Smart Test Key pattern.
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h b/S= ilicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h index 2198f8516a..82725bc84e 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h @@ -44,13 +44,7 @@ EFI_STATUS OUT VOID *Data ); =20 -/** - RAS IMC S3 Data PPI -**/ struct _RAS_IMC_S3_DATA_PPI { - /** - Retrieves data for S3 saved memory RAS features from non-volatile stor= age. - **/ RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA GetImcS3RasData; }; =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h b/Silico= n/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h index 09a3f37edf..5cadda4907 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h @@ -300,12 +300,10 @@ typedef struct { =20 Contains a pointer to a 24 byte fixed length array. The array contains the 3 instances of the following c-struct - ~~~ typedef struct { UINT32 CfrImagePtr; UINT32 CfrImageSize; } - ~~~ This allows a maximum of 3 CFR/SINIT binaries to be provided by platfo= rm code. **/ UINT32 CFRImagePtr; diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/DataTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCo= reLib/Core/Include/DataTypes.h index eb4bd92a1d..ef1775e1ed 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/DataTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/DataTypes.h @@ -12,11 +12,17 @@ =20 #include =20 +/// +/// 8-byte DWORD addressable unsigned value. +/// typedef struct u64_struct { UINT32 lo; UINT32 hi; } UINT64_STRUCT, *PUINT64_STRUCT; =20 +/// +/// 8-byte DWORD addressable unsigned value. +/// typedef union { struct { UINT32 Low; @@ -25,7 +31,9 @@ typedef union { UINT64 Data; } UINT64_DATA; =20 - +/// +/// 16-byte DWORD addressable unsigned value. +/// typedef struct u128_struct { UINT32 one; UINT32 two; diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/MemHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCore= Lib/Core/Include/MemHost.h index 8eaea40f72..3ae5bcb612 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MemHost.h +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MemHost.h @@ -641,11 +641,9 @@ struct rankDevice { /// typedef struct dimmDevice { INT32 minTCK; ///< minimum tCK for this DIMM (SPD_MIN_= TCK) -#ifdef DEBUG_CODE_BLOCK UINT32 tCL; UINT16 tRCD; UINT16 tRP; -#endif // DEBUG_CODE_BLOCK UINT16 NVmemSize; UINT16 memSize; ///< Memory size for this DIMM (64MB gra= nularity) UINT16 UnmappedMemSize; @@ -653,6 +651,7 @@ typedef struct dimmDevice { struct FmcCacheSt FmcCache[MAX_FMC_CACHE]; ///< FMC cache info/status UINT8 SPDPartitionRatio[MAX_SOCKET * MAX_IMC]; ///< NVM DI= MM partitionRatios UINT8 CachedLrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MA= X_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB + BOOLEAN TrainingModeEnabled; //Training Mode for BPS BOOLEAN FmcWdbFlushFailed; /// < 0 =3D WDB flush failed on p= revious boot, 1 =3D WDB flush completed w/o errors on previous boot BOOLEAN EadrFlushFailed; /// < 0 =3D Extended ADR flush fa= iled on previous boot, 1 =3D Extended ADR flush completed w/o errors on pre= vious boot } DIMM_DEVICE_INFO_STRUCT; //struct dimmDevice @@ -919,9 +918,7 @@ typedef struct memVar { UINT8 callingTrngOffstCfgOnce; ///
- # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) - # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) - # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. - # BIT3: Enable GENPROTRANGEs as PMRs replacement for IOMMU based DMA Pr= otection - # @Prompt The policy for VTd driver behavior. - gSiPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|0x00|UINT8|0x00000002 =20 ## Declares VTd PEI DMA buffer size.

# When this PCD value is referred by platform to calculate the required @@ -840,7 +833,7 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, gSiPkgTokenSpaceGuid.PcdTempRefreshOption |0|UINT8|0x7000000A =20 # Temperature refresh value default, Values are in Celcius - gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x19|UINT8|0x7000= 0001 + gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x00|UINT8|0x7000= 0001 gSiPkgTokenSpaceGuid.PcdTwoxRefreshValue |0x53|UINT8|0x7000= 0002 gSiPkgTokenSpaceGuid.PcdFourxRefreshValue |0x5F|UINT8|0x7000= 0003 =20 @@ -933,6 +926,8 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, # VTD PCDs End # =20 + gSiPkgTokenSpaceGuid.PcdPcieMultiVcEnable|FALSE|BOOLEAN|0xF0000038 + [PcdsDynamicEx] gReferenceCodePolicyTokenSpaceGuid.PcdEvMode |0x00|UINT8|0x00010= 001 # ReservedC: The Mailbox Command which it gona to assert. @@ -958,12 +953,26 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f= 43, {0x8d, 0xef, 0xa7, 0x43, # gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E =20 + # + # RAS: PcdRasIerrPresent - TRUE: IERR has occured need reset; FALSE: No = IERR + # + gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002 + [PcdsDynamicEx] gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007 gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D gPlatformTokenSpaceGuid.PcdFlashSecOverridden|FALSE|BOOLEAN|0x6000001B =20 +## Will be set if platform is WS else remains FALSE for Server platform. + gPlatformTokenSpaceGuid.PcdIsCPUWsType|FALSE|BOOLEAN|0x6000001A + +## C2F +## Will be set if platform is resuming from a global reset after ADR trig= ger. + # C2F driver will read the PCD and determine whether to perform C2f Entr= y. + # @Prompt Provide status if Adr resume or not + + gPlatformTokenSpaceGuid.PcdAdrResumeStatus|0|UINT8|0x0000104A ## ## ME ## @@ -979,7 +988,6 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, ## RAS ## gSiPkgTokenSpaceGuid.PcdRasGlobaldataTableAddress|0x0|UINT64|0x20000001 - gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002 =20 [PcdsFeatureFlag] ## This PCD used by FPGA drivers to decide to install FPGA features. --=20 2.39.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Thu, 12 Jan 2023 15:56:59 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410100322" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="410100322" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 15:56:58 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="607972208" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="607972208" X-Received: from iworam-desk.amr.corp.intel.com ([10.24.80.243]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 15:56:58 -0800 From: "Isaac Oram" To: devel@edk2.groups.io Cc: Isaac Oram , Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg: Update to Whitley FSP 4.2.0.2A Date: Thu, 12 Jan 2023 15:56:35 -0800 Message-Id: <5c28730bf5ced6977d849ac2bf716271b515c0a5.1673561471.git.isaac.w.oram@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: exZg34eb22da1p4UqA9YDbx2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673567819; bh=I1XvncTda3qGXR4uCSg55iTjvALEvk8AhYT+T7nUmDw=; h=Cc:Date:From:Reply-To:Subject:To; b=tp8i1Ngch9mwzHq9l6/sCVgLdyI7Qb8X/3SZPcleSuMqJE+jZjcMSKCORt++pRcEdjE jMbU1MDi8v6IGE18470AcMiqXURMMnYANj/Jafnex860dylsSKYpvsCap+gpV+5ZQmHL1 mY+qbThUdIHpStcxBNmZ9rPaiCw8V0h099A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673567821793100001 Content-Type: text/plain; charset="utf-8" This contains binary interface changes and requires FSP 4.2.0.2A or later Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram Reviewed-by: Nate DeSimone --- .../Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c | 2 +- .../AcpiTables/Dsdt/CommonPlatform10nm.asi | 1 + .../Pci/Dxe/PciHostBridge/PciRebalance.c | 243 ++++++++++-------- .../Include/Dsc/BuildOptions.dsc | 2 +- .../Include/Dsc/EnableRichDebugMessages.dsc | 9 + .../Include/Guid/SetupVariable.h | 3 + .../SiliconPolicyUpdateLib.c | 2 +- .../SiliconPolicyUpdateLibFsp.c | 2 +- .../WhitleyOpenBoardPkg/PlatformPkgConfig.dsc | 6 +- .../WhitleyOpenBoardPkg/StructurePcd.dsc | 173 ++++++++++++- .../WhitleyOpenBoardPkg/StructurePcdCpx.dsc | 91 ++++++- 11 files changed, 415 insertions(+), 119 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/P= latformCpuPolicy.c b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpu= Policy/PlatformCpuPolicy.c index d2a7b811dc..a9728edf61 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/Platform= CpuPolicy.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/Platform= CpuPolicy.c @@ -364,7 +364,7 @@ PlatformCpuPolicyEntryPoint ( mCpuPolicyConfiguration.Policy.CpuExpandedIioLlcWaysBitMask =3D SetupDat= a.SocketConfig.SocketProcessorCoreConfiguration.ExpandedIioLlcWaysMask; mCpuPolicyConfiguration.Policy.CpuRemoteWaysBitMask =3D SetupDat= a.SocketConfig.SocketProcessorCoreConfiguration.RemoteWaysMask; mCpuPolicyConfiguration.Policy.CpuRrqCountThreshold =3D mIioUds-= >PlatformData.RemoteRequestThreshold; - mCpuPolicyConfiguration.Policy.CpuCrashLogGprs =3D (SetupData.SocketConf= ig.SocketProcessorCoreConfiguration.CpuCrashLogGprs > 0) ? TRUE : FALSE; + mCpuPolicyConfiguration.Policy.CpuCrashDataGprs =3D (SetupData.SocketCon= fig.SocketProcessorCoreConfiguration.CpuCrashDataGprs > 0) ? TRUE : FALSE; =20 //CSR SAPM CTL for( socket =3D 0; socket < MAX_SOCKET; socket++) { diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Ds= dt/CommonPlatform10nm.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acp= i/AcpiTables/Dsdt/CommonPlatform10nm.asi index 28a997b102..714a5ddbb0 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Comm= onPlatform10nm.asi +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Comm= onPlatform10nm.asi @@ -186,6 +186,7 @@ If(LEqual(And(CPBF, 0x00000040), 0x00000040)) { Store(1,HWPS) } + } If (CondRefOf (\_SB.OSPC)) { Return (\_SB.OSPC(Arg0, Arg1, Arg2, Arg3)) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBri= dge/PciRebalance.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/Pc= iHostBridge/PciRebalance.c index b32f0bf835..24f047c237 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= Rebalance.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/Pci= Rebalance.c @@ -419,7 +419,7 @@ AdjustSocketResources ( Status =3D AdjustSocketMmioH (SocketResources, ResourceType, ValidSo= ckets); break; default: - DEBUG((DEBUG_ERROR, "ERROR: Resource Type Unknown =3D %x\n",Resource= Type)); + DEBUG((DEBUG_ERROR, "[PCI] ERROR: Resource Type Unknown =3D %x\n", R= esourceType)); Status =3D EFI_INVALID_PARAMETER; break; } // switch @@ -429,7 +429,7 @@ AdjustSocketResources ( =20 =20 /** - Calculate current system resource map with retrieved NVRAM variable to s= ee if stored settings were applied + Compare current system resource map with rebalance request NVRAM variabl= e to see if stored settings were applied. =20 @param[in] SocketPciResourceData - Pointer to stored CPU resource map =20 @@ -488,7 +488,8 @@ IsResourceMapRejected ( PCIDEBUG ("[%d.%d] Current I/O: 0x%04X..0x%04X\n", Socket, Stack, IioUdsStackLimits->PciResourceIoBase, IioUdsStackLimit= s->PciResourceIoLimit); PCIDEBUG ("[%d.%d] Saved I/O: 0x%04X..0x%04X %a\n", Socket, St= ack, - StackLimits->Io.Base, StackLimits->Io.Limit, Rejected ?= "rejected" : ""); + StackLimits->Io.Base, StackLimits->Io.Limit, + (StackLimits->Io.Limit !=3D 0 && Rejected) ? "rejected"= : ""); =20 if (IioUdsStackLimits->Mmio32Base !=3D StackLimits->LowMmio.Base= && StackLimits->LowMmio.Base !=3D 0) { Rejected =3D TRUE; @@ -499,7 +500,8 @@ IsResourceMapRejected ( PCIDEBUG ("[%d.%d] Current MMIOL: 0x%08X..0x%08X\n", Socket, Sta= ck, IioUdsStackLimits->Mmio32Base, IioUdsStackLimits->Mmio= 32Limit); PCIDEBUG ("[%d.%d] Saved MMIOL: 0x%08X..0x%08X %a\n", Socket, = Stack, - StackLimits->LowMmio.Base, StackLimits->LowMmio.Limit,= Rejected ? "rejected" : ""); + StackLimits->LowMmio.Base, StackLimits->LowMmio.Limit, + (StackLimits->LowMmio.Limit !=3D 0 && Rejected) ? "rej= ected" : ""); =20 if (IioUdsStackLimits->Mmio64Base !=3D StackLimits->HighMmio.Bas= e && StackLimits->HighMmio.Base !=3D 0) { Rejected =3D TRUE; @@ -510,7 +512,8 @@ IsResourceMapRejected ( PCIDEBUG ("[%d.%d] Current MMIOH: 0x%012llX..0x%012llX\n", Socke= t, Stack, IioUdsStackLimits->Mmio64Base, IioUdsStackLimits->Mmio= 64Limit); PCIDEBUG ("[%d.%d] Saved MMIOH: 0x%012llX..0x%012llX %a\n", So= cket, Stack, - StackLimits->HighMmio.Base, StackLimits->HighMmio.Limi= t, Rejected ? "rejected" : ""); + StackLimits->HighMmio.Base, StackLimits->HighMmio.Limi= t, + (StackLimits->HighMmio.Limit !=3D 0 && Rejected) ? "re= jected" : ""); } } // @@ -525,7 +528,8 @@ IsResourceMapRejected ( PCIDEBUG("[%d] Current I/O: 0x%04X..0x%04X\n", Socket, IioUdsSocketLimits->PciResourceIoBase, IioUdsSocketLimits->= PciResourceIoLimit); PCIDEBUG("[%d] Saved I/O: 0x%04X..0x%04X %a\n", Socket, - SocketLimits->Io.Base, SocketLimits->Io.Limit, Rejected ? "= rejected" : ""); + SocketLimits->Io.Base, SocketLimits->Io.Limit, + (SocketLimits->Io.Limit !=3D 0 && Rejected) ? "rejected" : = ""); =20 if (IioUdsSocketLimits->Mmio32Base !=3D SocketLimits->LowMmio.Base &= & SocketLimits->LowMmio.Base !=3D 0) { Rejected =3D TRUE; @@ -536,7 +540,8 @@ IsResourceMapRejected ( PCIDEBUG ("[%d] Current MMIOL: 0x%08X..0x%08X\n", Socket, IioUdsSocketLimits->Mmio32Base, IioUdsSocketLimits->Mmio32L= imit); PCIDEBUG ("[%d] Saved MMIOL: 0x%08X..0x%08X %a\n", Socket, - SocketLimits->LowMmio.Base, SocketLimits->LowMmio.Limit, R= ejected ? "rejected" : ""); + SocketLimits->LowMmio.Base, SocketLimits->LowMmio.Limit, + (SocketLimits->LowMmio.Limit !=3D 0 && Rejected) ? "reject= ed" : ""); =20 if (IioUdsSocketLimits->Mmio64Base !=3D SocketLimits->HighMmio.Base = && SocketLimits->HighMmio.Base !=3D 0) { Rejected =3D TRUE; @@ -547,7 +552,8 @@ IsResourceMapRejected ( PCIDEBUG ("[%d] Current MMIOH: 0x%012llX..0x%012llX\n", Socket, IioUdsSocketLimits->Mmio64Base, IioUdsSocketLimits->Mmio64L= imit); PCIDEBUG ("[%d] Saved MMIOH: 0x%012llX..0x%012llX %a\n", Socket, - SocketLimits->HighMmio.Base, SocketLimits->HighMmio.Limit,= Rejected ? "rejected" : ""); + SocketLimits->HighMmio.Base, SocketLimits->HighMmio.Limit, + (SocketLimits->HighMmio.Limit !=3D 0 && Rejected) ? "rejec= ted" : ""); =20 if (IioUdsUboxStackLimits->Mmio64Base !=3D UboxStackLimits->HighMmio= .Base && UboxStackLimits->HighMmio.Base !=3D 0) { Rejected =3D TRUE; @@ -558,7 +564,8 @@ IsResourceMapRejected ( PCIDEBUG ("[%d] Current UBOX: 0x%08X..0x%08X\n", Socket, IioUdsUboxStackLimits->Mmio64Base, IioUdsUboxStackLimits->= Mmio64Limit); PCIDEBUG ("[%d] Saved UBOX: 0x%08X..0x%08X %a\n", Socket, - UboxStackLimits->HighMmio.Base, UboxStackLimits->HighMmio.= Limit, Rejected ? "rejected" : ""); + UboxStackLimits->HighMmio.Base, UboxStackLimits->HighMmio.= Limit, + (UboxStackLimits->HighMmio.Limit !=3D 0 && Rejected) ? "re= jected" : ""); } } DEBUG ((DEBUG_INFO, "[PCI] Resource rebalance rejected ? %a\n", Rejected= ? "TRUE" : "FALSE")); @@ -567,91 +574,67 @@ IsResourceMapRejected ( =20 =20 /** - Read SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME variable from flash and = verify its content. + Verify whether system resource map changed comparing to the state when re= balance request was created. =20 - If the variable does not exist, or is not valid for current system config= uration - the buffer at *PciResConfigPtr is just cleared. + @param[in] PciResConfigPtr - Buffer with the rebalance request. =20 - @param[out] PciResConfigPtr - Buffer for the resource configuration varia= ble. - - @retval EFI_SUCCESS The function completed successfully. - @retval EFI_NOT_FOUND The variable was not found. - @retval EFI_DEVICE_ERROR The variable could not be retrieved due to= a hardware error. - @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to= an authentication failure. + @return If current map is different than the one used when rebalance was = created true is returned, + otherwise false. **/ -EFI_STATUS -PciHostReadResourceConfig ( - OUT SYSTEM_PCI_BASE_LIMITS *PciResConfigPtr +BOOLEAN +IsSystemMapChanged ( + IN SYSTEM_PCI_BASE_LIMITS *PciResConfigPtr ) { - UINTN VarSize; - EFI_STATUS Status; - UINT8 Socket; + UINT8 Socket; =20 - VarSize =3D sizeof(*PciResConfigPtr); - Status =3D gRT->GetVariable (SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME= , &gEfiSocketPciResourceDataGuid, - NULL, &VarSize, PciResConfigPtr); - if (EFI_ERROR (Status) && Status !=3D EFI_BUFFER_TOO_SMALL) { - goto ErrExit; - } - if (Status =3D=3D EFI_BUFFER_TOO_SMALL || VarSize !=3D sizeof(*PciResCon= figPtr)) { - - PCIDEBUG ("Got variable '%s' of unexpected size %d (expect %d) - overw= rite\n", - SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, VarSize, sizeof= (*PciResConfigPtr)); - Status =3D EFI_NOT_FOUND; - goto ErrExit; - } - // - // If any of the below checks fails clear the buffer and return EFI_NOT_= FOUND. - // - Status =3D EFI_NOT_FOUND; if (PciResConfigPtr->MmioHBase !=3D mIioUds->IioUdsPtr->PlatformData.Pla= tGlobalMmio64Base || - PciResConfigPtr->MmioHLimit !=3D mIioUds->IioUdsPtr->PlatformData.Pl= atGlobalMmio64Limit) { + PciResConfigPtr->MmioHGranularity !=3D *(UINT64*)&mIioUds->IioUdsPtr= ->PlatformData.MmiohGranularity) { =20 - PCIDEBUG ("%s: Memory map changed (MMIOH %012llX..%012llX !=3D %012llX= ..%012llX) - overwrite\n", - SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, - PciResConfigPtr->MmioHBase, PciResConfigPtr->MmioHLimit, - mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base, - mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Limit); - goto ErrExit; + DEBUG ((DEBUG_ERROR, "[PCI] %s: MMIOH Base %012llX [%llX] !=3D %012llX= [%llX] - system map changed\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + PciResConfigPtr->MmioHBase, PciResConfigPtr->MmioHGranularity, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base, + *(UINT64*)&mIioUds->IioUdsPtr->PlatformData.MmiohGranularity)); + return TRUE; } if (PciResConfigPtr->MmioLBase !=3D mIioUds->IioUdsPtr->PlatformData.Pla= tGlobalMmio32Base || - PciResConfigPtr->MmioLLimit !=3D mIioUds->IioUdsPtr->PlatformData.Pl= atGlobalMmio32Limit) { + PciResConfigPtr->MmioLLimit !=3D mIioUds->IioUdsPtr->PlatformData.Pl= atGlobalMmio32Limit || + PciResConfigPtr->MmioLGranularity !=3D mIioUds->IioUdsPtr->PlatformD= ata.MmiolGranularity) { =20 - PCIDEBUG ("%s: Memory map changed (MMIOL %08X..%08X !=3D %08X..%08X) -= overwrite\n", - SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, - PciResConfigPtr->MmioLBase, PciResConfigPtr->MmioLLimit, - mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base, - mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit); - goto ErrExit; + DEBUG ((DEBUG_ERROR, "[PCI] %s: MMIOL %08X..%08X [%X] !=3D %08X..%08X = [%X] - system map changed\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + PciResConfigPtr->MmioLBase, PciResConfigPtr->MmioLLimit, PciRe= sConfigPtr->MmioLGranularity, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit, + mIioUds->IioUdsPtr->PlatformData.MmiolGranularity)); + return TRUE; } if (PciResConfigPtr->IoBase !=3D mIioUds->IioUdsPtr->PlatformData.PlatGl= obalIoBase || - PciResConfigPtr->IoLimit !=3D mIioUds->IioUdsPtr->PlatformData.PlatG= lobalIoLimit) { + PciResConfigPtr->IoLimit !=3D mIioUds->IioUdsPtr->PlatformData.PlatG= lobalIoLimit || + PciResConfigPtr->IoGranularity !=3D mIioUds->IioUdsPtr->PlatformData= .IoGranularity) { =20 - PCIDEBUG ("%s: Memory map changed (I/O %04X..%04X !=3D %04X..%04X) - o= verwrite\n", - SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, - PciResConfigPtr->IoBase, PciResConfigPtr->IoLimit, - mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase, - mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit); - goto ErrExit; + DEBUG ((DEBUG_ERROR, "[PCI] %s: I/O %04X..%04X [%X] !=3D %04X..%04X [%= X] - system map changed\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, + PciResConfigPtr->IoBase, PciResConfigPtr->IoLimit, PciResConfi= gPtr->IoGranularity, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase, + mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit, + mIioUds->IioUdsPtr->PlatformData.IoGranularity)); + return TRUE; } for (Socket =3D 0; Socket < NELEMENTS (PciResConfigPtr->Socket); Socket+= +) { =20 if (PciResConfigPtr->StackPresentBitmap[Socket] !=3D mIioUds->IioUdsPtr->Platform= Data.CpuQpiInfo[Socket].stackPresentBitmap) { =20 - PCIDEBUG ("%s: Stack bitmap mismach (%04X !=3D %04X) in socket %d - = overwrite\n", - SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, PciResConfigP= tr->StackPresentBitmap[Socket], - mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackP= resentBitmap, Socket); - goto ErrExit; + DEBUG ((DEBUG_ERROR, "[PCI] %s: Stack bitmap mismach (%04X !=3D %04X= ) in socket %d - system map changed\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, PciResConfigPtr= ->StackPresentBitmap[Socket], + mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap, Socket)); + return TRUE; } } - return EFI_SUCCESS; - - ErrExit: - ZeroMem (PciResConfigPtr, sizeof(*PciResConfigPtr)); - return Status; -} // PciHostReadResourceConfig() + return FALSE; +} // IsSystemMapChanged() =20 =20 /** @@ -689,6 +672,7 @@ AdjustResourceAmongRootBridges ( UINT8 TypeIndex; UINT8 ChangedBitMap; EFI_STATUS Status; + UINTN VarSize; SYSTEM_PCI_BASE_LIMITS SocketPciResourceData; UINT8 Stack; UINT8 LastStack; @@ -717,28 +701,47 @@ AdjustResourceAmongRootBridges ( MmiohGranularity |=3D ((UINT64)mIioUds->IioUdsPtr->PlatformData.MmiohGra= nularity.hi) << 32; ZeroMem (&SocketResources[0], sizeof(SocketResources)); // - // Read the system resource cfg from NVRAM. If the variable does not exi= st, or is - // not valid for current system configuration the buffer SocketPciResour= ceData - // is just cleared. + // Read the system resource cfg from NVRAM. If the variable does not exi= st just create new one. + // If variable exists, check if it was applied by KTI. If not we got two= options possible: + // (1) it is not valid because system resource map changed, or + // (2) it is not valid because of unknown reason. + // The first case is detected and new request shall be created for rebal= ance. + // In the second case just continue boot to avoid reboot loop. // - Status =3D PciHostReadResourceConfig (&SocketPciResourceData); - if (EFI_ERROR (Status)) { + VarSize =3D sizeof(SocketPciResourceData); + ZeroMem (&SocketPciResourceData, sizeof(SocketPciResourceData)); + Status =3D gRT->GetVariable (SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME= , &gEfiSocketPciResourceDataGuid, + NULL, &VarSize, &SocketPciResourceData); + if (EFI_ERROR (Status) && Status !=3D EFI_NOT_FOUND && Status !=3D EFI_B= UFFER_TOO_SMALL) { =20 - if (Status !=3D EFI_NOT_FOUND) { - - ASSERT_EFI_ERROR (Status); - return; - } - // - // Variable is not initialized yet, go with empty structure. - // - } else if (IsResourceMapRejected (&SocketPciResourceData)) { - // - // If variable is already initialized, but rejected by KTI do not rebo= ot to avoid loop. - // + ASSERT_EFI_ERROR (Status); return; } + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { =20 + VarSize +=3D 1; // Make it not equal to sizeof(SocketPciResourceData) + } + if (VarSize !=3D sizeof(SocketPciResourceData)) { + + PCIDEBUG ("Got variable '%s' of unexpected size %d (expect %d)\n", + SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, VarSize, sizeof= (SocketPciResourceData)); + } + if (Status !=3D EFI_NOT_FOUND) { + // + // Variable exists, let's check if it was applied by KTI. + // + if (IsResourceMapRejected (&SocketPciResourceData)) { + // + // Rejected so check if system resources map was changed. + // + if (!IsSystemMapChanged (&SocketPciResourceData) && VarSize =3D=3D = sizeof(SocketPciResourceData)) { + + DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Resource rebalance rejected by = KTI - continue without rebalance\n")); + return; + } + ZeroMem (&SocketPciResourceData, sizeof(SocketPciResourceData)); + } + } UboxMmioSize =3D mIioUds->IioUdsPtr->PlatformData.UboxMmioSize; PlatGlobalMmiolBase =3D mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio3= 2Base; ValidSockets =3D 0; @@ -918,6 +921,13 @@ AdjustResourceAmongRootBridges ( NewLength +=3D Alignment; } =20 + // + // Check if new length is big enough to support PEI MMIO resource as= sigment for the stacks + // + if (NewLength < mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket= ].StackRes[Stack].Mmio32MinSize) { + NewLength =3D mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket= ].StackRes[Stack].Mmio32MinSize; + } + if (NewLength !=3D 0) { // // At least 4MB align per KTI requirement. Add the length requeste= d with given alignment. @@ -1036,6 +1046,9 @@ AdjustResourceAmongRootBridges ( Remainder =3D MmiohGranularity - (NewLength % MmiohGranularity); NewLength +=3D Remainder; } + + NewLength =3D ALIGN_VALUE (NewLength, Alignment); + // // Store length as length - 1 for handling // @@ -1134,31 +1147,44 @@ AdjustResourceAmongRootBridges ( } } } - } else if (OutOfResources && ChangedTypeOOR[TypeMem64]){ - // - // Allow mmioh to be adjusted to access max available physical address= range. - // - Status =3D AdjustSocketResources (SocketResources, TypeMem64, ValidSoc= kets); - if (Status =3D=3D EFI_SUCCESS) { - ChangedBitMap |=3D (1 << TypeIndex); - } else { - ChangedBitMap &=3D ~(1 << TypeIndex); + } else if (OutOfResources) { + if (ChangedTypeOOR[TypeMem64]) { + // + // Allow mmioh to be adjusted to access max available physical addre= ss range. + // + Status =3D AdjustSocketResources (SocketResources, TypeMem64, ValidS= ockets); + if (Status =3D=3D EFI_SUCCESS) { + ChangedBitMap |=3D (1 << TypeIndex); + } else { + ChangedBitMap &=3D ~(1 << TypeIndex); + } + } + if (ChangedTypeOOR[TypeIo] || ChangedTypeOOR[TypeMem32]) { + DEBUG ((DEBUG_ERROR, "Clearing %s request\n", mPciResourceTypeStr[Ty= peIo])); + DEBUG ((DEBUG_ERROR, "Clearing %s request\n", mPciResourceTypeStr[Ty= peMem32])); + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + SocketResources[Socket].StackRes[Stack].NeedIoUpdate =3D 0; + SocketResources[Socket].StackRes[Stack].MmiolUpdate =3D 0; + } + } } } - + // // Update changed resource type. // OemGetResourceMapUpdate() will only update changed resource type so i= t is alright if data is zero. + // if (ChangedBitMap !=3D 0) { =20 for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { =20 SocketPciResourceData.StackPresentBitmap[Socket] =3D mIioUds->IioUds= Ptr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap; for (Stack =3D 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPre= sentBitmap & (1 << Stack))) { continue; } CurStackLimits =3D &SocketPciResourceData.Socket[Socket].StackLimi= ts[Stack]; - // // Disable stacks that have no resources and are assigned none. // Reaching this far means the stack is valid and should be disabl= ed if base equals limit and @@ -1293,9 +1319,10 @@ AdjustResourceAmongRootBridges ( CurSocketLimits->HighMmio.Base =3D SocketResources[Socket].MmiohB= ase; CurSocketLimits->HighMmio.Limit =3D SocketResources[Socket].MmiohL= imit; } - - DEBUG((DEBUG_INFO, "\nSocketResources[%x].UboxBase =3D%x\n",Socket,U= boxStackLimits->LowMmio.Base)); - DEBUG((DEBUG_INFO, "SocketResources[%x].UboxLimit =3D%x\n",Socket,Ub= oxStackLimits->LowMmio.Limit)); + DEBUG((DEBUG_INFO, "\nSocketResources[%x].UboxBase =3D %x\n", + Socket, SocketPciResourceData.Socket[Socket].StackLimits[UBOX= _STACK].LowMmio.Base)); + DEBUG((DEBUG_INFO, "SocketResources[%x].UboxLimit =3D %x\n", + Socket, SocketPciResourceData.Socket[Socket].StackLimits[UBOX= _STACK].LowMmio.Limit)); DEBUG((DEBUG_INFO, "\nSocketResources[%x].IoBase =3D%x\n",Socket,Soc= ketResources[Socket].IoBase)); DEBUG((DEBUG_INFO, "SocketResources[%x].IoLimit =3D%x\n",Socket,Sock= etResources[Socket].IoLimit)); DEBUG((DEBUG_INFO, "SocketResources[%x].MmiolBase =3D%x\n",Socket,So= cketResources[Socket].MmiolBase)); @@ -1304,16 +1331,18 @@ AdjustResourceAmongRootBridges ( DEBUG((DEBUG_INFO, "SocketResources[%x].MmiohLimit =3D%lx\n",Socket,= SocketResources[Socket].MmiohLimit)); } // for Socket SocketPciResourceData.MmioHBase =3D mIioUds->IioUdsPtr->PlatformData.P= latGlobalMmio64Base; - SocketPciResourceData.MmioHLimit =3D mIioUds->IioUdsPtr->PlatformData.= PlatGlobalMmio64Limit; + SocketPciResourceData.MmioHGranularity =3D *(UINT64*)&mIioUds->IioUdsP= tr->PlatformData.MmiohGranularity; SocketPciResourceData.MmioLBase =3D mIioUds->IioUdsPtr->PlatformData.P= latGlobalMmio32Base; SocketPciResourceData.MmioLLimit =3D mIioUds->IioUdsPtr->PlatformData.= PlatGlobalMmio32Limit; + SocketPciResourceData.MmioLGranularity =3D mIioUds->IioUdsPtr->Platfor= mData.MmiolGranularity; SocketPciResourceData.IoBase =3D mIioUds->IioUdsPtr->PlatformData.Plat= GlobalIoBase; SocketPciResourceData.IoLimit =3D mIioUds->IioUdsPtr->PlatformData.Pla= tGlobalIoLimit; + SocketPciResourceData.IoGranularity =3D mIioUds->IioUdsPtr->PlatformDa= ta.IoGranularity; =20 PCIDEBUG("Writing resource rebalance request '%s':\n", SYSTEM_PCI_RESO= URCE_CONFIGURATION_DATA_NAME); - PCIDEBUG("System I/O : %04X..%04X\n", SocketPciResourceData.IoBase, S= ocketPciResourceData.IoLimit); - PCIDEBUG("System MMIOL: %08X..%08X\n", SocketPciResourceData.MmioLBase= , SocketPciResourceData.MmioLLimit); - PCIDEBUG("System MMIOH: %012llX..%012llX\n", SocketPciResourceData.Mmi= oHBase, SocketPciResourceData.MmioHLimit); + PCIDEBUG("System I/O : %04X..%04X [%X]\n", SocketPciResourceData.IoBa= se, SocketPciResourceData.IoLimit, SocketPciResourceData.IoGranularity); + PCIDEBUG("System MMIOL: %08X..%08X [%X]\n", SocketPciResourceData.Mmio= LBase, SocketPciResourceData.MmioLLimit, SocketPciResourceData.MmioLGranula= rity); + PCIDEBUG("System MMIOH: %012llX [%llX]\n", SocketPciResourceData.MmioH= Base, SocketPciResourceData.MmioHGranularity); for (Socket =3D 0; Socket < NELEMENTS (SocketPciResourceData.Socket); = Socket++) { =20 PCIDEBUG("[%d] StackPresent: 0x%04X\n", Socket, SocketPciResourceDat= a.StackPresentBitmap[Socket]); diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.ds= c b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc index 9213507b98..f4bcd60ced 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc @@ -16,7 +16,7 @@ !endif =20 !if $(DEBUG_FLAGS_ENABLE) =3D=3D TRUE - DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D DEBUG_CODE_BLOCK=3D1 -D PLATFORM= _VARIABLE_ATTRIBUTES=3D0x3 + DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D PLATFORM_VARIABLE_ATTRIBUTES=3D0= x3 !else DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D SILENT_MODE -D PLATFORM_VARIABLE= _ATTRIBUTES=3D0x3 !endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebug= Messages.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDeb= ugMessages.dsc index 6a66f2ebbb..be423da00a 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessage= s.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessage= s.dsc @@ -14,6 +14,15 @@ # Customize debug messages # [PcdsFixedAtBuild] + ## The mask is used to control DebugLib behavior.

+ # BIT0 - Enable Debug Assert.
+ # BIT1 - Enable Debug Print.
+ # BIT2 - Enable Debug Code.
+ # BIT3 - Enable Clear Memory.
+ # BIT4 - Enable BreakPoint as ASSERT.
+ # BIT5 - Enable DeadLoop as ASSERT.
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # = Enable asserts, prints, code, clear memory, and deadloops on asserts. + ## This flag is used to control the built in Debug messages. # BIT0 - Initialization message.
# BIT1 - Warning message.
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.= h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h index c47f040ca3..5a22a2f61b 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h @@ -670,6 +670,9 @@ typedef struct { // TCC Mode // UINT8 TccMode; + // RAS Fast string Disable option + // + UINT8 DisableFastString; } SYSTEM_CONFIGURATION; =20 typedef struct { diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/S= iliconPolicyUpdateLib/SiliconPolicyUpdateLib.c index 08144936dd..35268a76c7 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLib.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLib.c @@ -553,7 +553,7 @@ Returns: // // Update SPI policies // - PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + PchPolicy->SpiConfig.ShowSpiController =3D FALSE; =20 PchPolicy->PmConfig.PmcReadDisable =3D TRUE; =20 diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdate= Lib/SiliconPolicyUpdateLibFsp.c b/Platform/Intel/WhitleyOpenBoardPkg/Librar= y/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c index f7e4ee5e2f..21a5444884 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLibFsp.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/Sil= iconPolicyUpdateLibFsp.c @@ -561,7 +561,7 @@ Returns: // // Update SPI policies // - PchPolicy->SpiConfig.ShowSpiController =3D TRUE; + PchPolicy->SpiConfig.ShowSpiController =3D FALSE; =20 PchPolicy->PmConfig.PmcReadDisable =3D TRUE; =20 diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc b/Pla= tform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc index c9620f11d8..73739e4070 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc @@ -13,7 +13,11 @@ =20 [Defines] DEFINE CRB_FLAG_ENABLE =3D TRUE -DEFINE DEBUG_FLAGS_ENABLE =3D FALSE +!if $(TARGET) =3D=3D "RELEASE" + DEFINE DEBUG_FLAGS_ENABLE =3D FALSE +!else + DEFINE DEBUG_FLAGS_ENABLE =3D TRUE +!endif =20 DEFINE SERVER_BIOS_ENABLE =3D TRUE DEFINE PCH_SERVER_BIOS_ENABLE =3D TRUE diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc b/Platform= /Intel/WhitleyOpenBoardPkg/StructurePcd.dsc index 9437686fcb..0c0ffde53e 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc @@ -1049,6 +1049,7 @@ gStructPcdTokenSpaceGuid.PcdSetup.DdrtInternalAlertEn= |0x1 gStructPcdTokenSpaceGuid.PcdSetup.ReservedS2|0x2 gStructPcdTokenSpaceGuid.PcdSetup.ReservedS1|0x0 gStructPcdTokenSpaceGuid.PcdSetup.ReservedS3|0x2 +gStructPcdTokenSpaceGuid.PcdSetup.DisableFastString|0x0 = # Disable Fast String after first poison error gStructPcdTokenSpaceGuid.PcdSetup.DisableMAerrorLoggingDueToLER|0x1 = # LER MA Error Logging gStructPcdTokenSpaceGuid.PcdSetup.EdpcEn|0x0 = # IIO eDPC Support gStructPcdTokenSpaceGuid.PcdSetup.EdpcErrCorMsg|0x1 = # IIO eDPC ERR_COR Message @@ -1700,6 +1701,86 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Completi= onTimeoutValue[0]|0x9 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 = # PCI-E Completion Timeout gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 = # PCI-E Completion Timeout gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[4]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[5]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[6]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[7]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[8]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[9]|0x9 = # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[10]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[11]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[12]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[13]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[14]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[15]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[16]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[17]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[18]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[19]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[20]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[21]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[22]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[23]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[24]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[25]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[26]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[27]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[28]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[29]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[30]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[31]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[32]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[33]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[34]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[35]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[36]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[37]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[38]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[39]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[40]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[41]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[42]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[43]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[44]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[45]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[46]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[47]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[48]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[49]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[50]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[51]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[52]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[53]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[54]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[55]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[56]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[57]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[58]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[59]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[60]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[61]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[62]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[63]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[64]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[65]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[66]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[67]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[68]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[69]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[70]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[71]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[72]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[73]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[74]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[75]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[76]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[77]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[78]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[79]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[80]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[81]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[82]|0x9= # PCI-E Completion Timeout +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[83]|0x9= # PCI-E Completion Timeout gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[0]|0x0 = # Compliance Mode gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[1]|0x0 = # Compliance Mode gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[2]|0x0 = # Compliance Mode @@ -6396,6 +6477,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort= LinkSpeed[80]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[81]|0x0 = # Link Speed gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[82]|0x0 = # Link Speed gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[83]|0x0 = # Link Speed +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[0]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[1]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[2]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[3]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[4]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[5]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[6]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[7]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[8]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[9]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[10]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[11]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[12]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[13]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[14]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[15]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[16]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[17]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[18]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[19]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[20]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[21]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[22]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[23]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[24]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[25]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[26]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[27]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[28]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[29]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[30]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[31]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[32]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[33]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[34]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[35]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[36]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[37]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[38]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[39]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[40]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[41]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[42]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[43]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[44]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[45]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[46]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[47]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[48]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[49]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[50]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[51]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[52]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[53]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[54]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[55]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[56]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[57]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[58]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[59]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[60]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[61]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[62]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[63]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[64]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[65]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[66]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[67]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[68]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[69]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[70]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[71]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[72]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[73]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[74]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[75]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[76]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[77]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[78]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[79]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[80]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[81]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[82]|0x2 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[83]|0x2 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x2 = # PCIe PTM Support gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 = # Pcie Relaxed Ordering gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotItemCtrl|0x0 = # PCIe Slot Item Control @@ -6600,6 +6765,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmi= oReadEn[21]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[22]|0x0 = # Enable MMIO read cmpl poison for STACK_4 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[23]|0x0 = # Enable MMIO read cmpl poison for STACK_5 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterrupt|0x1 = # Posted Interrupt +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterruptThrottle|0x1 = # Posted Interrupt Throttle gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PrioritizeTPH|0x0 = # Prioritize TPH gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ProblematicPort|0x0 = # Problematic port gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[2]|0= x0 # - Override @@ -7411,6 +7577,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADDDCE= n|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2 = # ADR Data Save Mode gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1 = # Enable ADR gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1 = # Enable ADDDC Error Injection +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdrPatrolScrubDisable|0x0 = # ADR Patrol Scrub Disable gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186a0= # Adv MemTest Pause gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTrefi|0x3cf0 = # Adv MemTest tREFI gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTwr|0xa = # Adv MemTest tWR @@ -7479,6 +7646,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrMem= oryType|0x2 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtCkeEn|0x1 = # PMem CKE gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtSrefEn|0x0 = # PMem SELF REFRESH gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DfeGainBias|0x0 = # DfeGainBias +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS48|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS127|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS122|0x1 @@ -7529,7 +7697,6 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Reserv= edS137|0x2 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS128|0x2 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS123|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x8 -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS125|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS64|0x7ff gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS113|0x1 @@ -7782,6 +7949,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.multiS= paringRanks|0x2 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.normOppInterval|0x400 = # Normal Operation Duration gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oneRankTimingMode|0x1 = # One Rank Timing Mode gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oppReadInWmm|0x1 = # Opp read during WMM +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pTRR|0x0 = # pTRR gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsad0|0x0 = # Mirror TAD0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[0]|0x0 = # Partial Mirror 1 Size (GB) gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[1]|0x0 = # Partial Mirror 2 Size (GB) @@ -8406,6 +8574,7 @@ gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConf= ig.SnpLatVal|0x0 gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVld|0x0 = # Snoop Latency Override gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SwLtrOvrdCtl|0x0 = # PCIe LTR Override Control gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TCCActivationOffse= t|0x0 # TCC Activation Offset +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PrgTjOffsetEn|0x0 = # Programmable TJ Offset Enable gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TStateEnable|0x0 = # Software Controlled T-States gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStat= usFilter|0x0 # Therm-Monitor-Status Filter gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStat= usFilterTimeWindow|0x9 # Therm-Monitor-Status Filter Time Window @@ -8451,7 +8620,7 @@ gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig= .CoreDisableMask[1]|0x0 gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[2]|0= x0 # Disable Bitmap gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[3]|0= x0 # Disable Bitmap gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreFailover|0x1 = # Core Failover -gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuCrashLogGprs|0x0 = # Cpu CrashLog Gprs +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuCrashDataGprs|0x0= # Cpu Crash Data Gprs gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuDbpEnable|0x0 = # DBP-F gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuL1NextPagePrefetc= herDisable|0x0 # L1 Next Page Prefetcher gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuMtoIWa|0x1 = # MtoI Workaround diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc b/Platf= orm/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc index 0c166ade00..a9311f3e9b 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc @@ -76,10 +76,6 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbDmaMultiCa= stEnable|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherencySupport|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobal|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobalValue|0= x9 -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9 -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[0]|0xFF gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[1]|0xFF gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[2]|0xFF @@ -1664,6 +1660,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieComm= onClock[80]|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[81]|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[82]|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[83]|0x1 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[4]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[5]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[6]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[7]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[8]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[9]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[10]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[11]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[12]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[13]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[14]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[15]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[16]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[17]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[18]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[19]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[20]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[21]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[22]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[23]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[24]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[25]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[26]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[27]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[28]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[29]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[30]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[31]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[32]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[33]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[34]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[35]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[36]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[37]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[38]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[39]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[40]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[41]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[42]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[43]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[44]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[45]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[46]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[47]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[48]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[49]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[50]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[51]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[52]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[53]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[54]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[55]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[56]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[57]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[58]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[59]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[60]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[61]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[62]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[63]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[64]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[65]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[66]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[67]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[68]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[69]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[70]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[71]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[72]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[73]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[74]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[75]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[76]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[77]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[78]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[79]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[80]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[81]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[82]|0x9 +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[83]|0x9 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[0]|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[1]|0x1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEna= ble[2]|0x1 @@ -2445,6 +2525,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5= ReservedS191|0x2 gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS246|0x2 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdrPatrolScrubDisable|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondition|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186A0 @@ -2523,7 +2604,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Reserv= edS141|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS142|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS75|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x4 -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1 +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[0]|0xFF gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[1]|0xFF gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[2]|0xFF --=20 2.39.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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