From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92920+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92920+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1661805423; cv=none; d=zohomail.com; s=zohoarc; b=YDFNVcD48NvjroC31j7449Wjgy5VHK92v+8l91MZTfP1WtpLAWmujczf/rcuX85exUrnIxhWQrd3KJv4JsIr6jQnISRIualSB+ibEbX9fR5MV7JLnGt2aMcUcCvMvtrW/RNgHjX8ONy+8/l0dq8Mb8xNW105D8ub6roiSGOKQOc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661805423; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=T7pus2tqPcp90/NtUcH3SFXjEMJJU1RImXECnzkj7MA=; b=Wv64zQ+lXMCX32rDHEgumczYdklC++r5hsSzPxWO4CK/pYHEI4T5MxT8io+EZYgnPAEDxV0CRU0nzvzomQSmmTAyVGJETungtEbnU7x7z4fcTKnBxxYsbixWltiNNOYvO39qH9pcpNuL6LLQ7k0h5b3uYP8CCtRBoores0z6n3M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92920+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1661805423895706.9178769658946; Mon, 29 Aug 2022 13:37:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cGrtYY1788612xfCMqYwrAfU; Mon, 29 Aug 2022 13:37:02 -0700 X-Received: from mail-qv1-f52.google.com (mail-qv1-f52.google.com [209.85.219.52]) by mx.groups.io with SMTP id smtpd.web08.3375.1661805421708539112 for ; Mon, 29 Aug 2022 13:37:01 -0700 X-Received: by mail-qv1-f52.google.com with SMTP id jy14so1433121qvb.12 for ; Mon, 29 Aug 2022 13:37:01 -0700 (PDT) X-Gm-Message-State: SaUjYa6yjijyPORfRSNoIfbTx1787277AA= X-Google-Smtp-Source: AA6agR6+60tUhCurwNVNbo1Hdxa6w7Dxn0/6VxmnQpRjAhy4G5keb9jvcxeP1iKqJpr47B+383qI2A== X-Received: by 2002:a05:6214:3010:b0:496:e381:e33 with SMTP id ke16-20020a056214301000b00496e3810e33mr12326125qvb.2.1661805420378; Mon, 29 Aug 2022 13:37:00 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:36:59 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Ray Ni , Rangasai V Chaganty , Isaac Oram Subject: [edk2-devel][edk2-platforms][PATCH v1 1/5] IntelSiliconPkg/Feature/PeiSmmAccessLibSmramc: Implement chipset support Date: Mon, 29 Aug 2022 16:36:16 -0400 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805422; bh=InT+kDGECZYa8cDrvkTBJBSjIB3JTfZBP2q8xneRwsg=; h=Cc:Date:From:Reply-To:Subject:To; b=hnUvw14gpVAJ88hpJdZ1BXsu53ZVK3U4yrnuVG7mCKv42oaFoIrkrFcU8wiedrEcSxf K32/Sfbk26+QplZEcottNnZKvGuUA4T6AbFGvfUHk5y6Dm1O9ufPsH7/OMwF8QqR203r9 mfCldJI2qxNVcO8d1mfRbA/H2hhjT/cvBfY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805425374100005 Content-Type: text/plain; charset="utf-8" SMRAM must be opened to retrieve the lockbox for S3, and SMM communication depends on this PPI. For security purposes, SMRAM lock must be performed before EndOfPei (although FSP notify performs lockdown too). It seems to me that this library is generic and applicable to all Intel platforms in the tree using the MCH SMRAMC register. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron Reviewed-by: Isaac Oram --- .../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++ .../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 41 ++ 2 files changed, 471 insertions(+) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library= /PeiSmmAccessLibSmramc/PeiSmmAccessLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library= /PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmm= AccessLibSmramc/PeiSmmAccessLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/S= mmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c new file mode 100644 index 000000000000..5b472bf86abf --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessL= ibSmramc/PeiSmmAccessLib.c @@ -0,0 +1,430 @@ +/** @file + This is to publish the SMM Access Ppi instance. + + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a') + +/// +/// Private data +/// +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_PEI_MM_ACCESS_PPI SmmAccess; + // + // Local Data for SMM Access interface goes here + // + UINTN NumberRegions; + EFI_SMRAM_DESCRIPTOR *SmramDesc; +} SMM_ACCESS_PRIVATE_DATA; + +#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \ + CR (a, \ + SMM_ACCESS_PRIVATE_DATA, \ + SmmAccess, \ + SMM_ACCESS_PRIVATE_DATA_SIGNATURE \ + ) + +// +// Common registers: +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +/// +/// Description: +/// The SMRAMC register controls how accesses to Compatible SMRAM spaces = are treated. The Open, Close and Lock bits function only when G_SMRAME bit= is set to 1. Also, the Open bit must be reset before the Lock bit is set. +/// +#define R_SA_SMRAMC (0x88) +#define B_SA_SMRAMC_D_LCK_MASK (0x10) +#define B_SA_SMRAMC_D_CLS_MASK (0x20) +#define B_SA_SMRAMC_D_OPEN_MASK (0x40) + +/** + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all PEIM + and SMM agents. + + @param[in] PeiServices - General purpose services available to = every PEIM. + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Open. + + @retval EFI_SUCCESS - The region was successfully opened. + @retval EFI_DEVICE_ERROR - The region could not be opened because= locked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Open ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINT8 Index; + UINT64 Address; + UINT8 SmramControl; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + if (DescriptorIndex >=3D SmmAccess->NumberRegions) { + DEBUG ((DEBUG_WARN, "SMRAM region out of range\n")); + + return EFI_INVALID_PARAMETER; + } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM= _LOCKED) { + // + // Cannot open a "locked" region + // + DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n")); + + return EFI_DEVICE_ERROR; + } + + /// + /// BEGIN CHIPSET CODE + /// + /// + /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit) + /// + Address =3D PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN,= R_SA_SMRAMC); + SmramControl =3D PciSegmentRead8 (Address); + /// + /// Is SMRAM locked? + /// + if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) { + /// + /// Cannot Open a locked region + /// + for (Index =3D 0; Index < SmmAccess->NumberRegions; Index++) { + SmmAccess->SmramDesc[Index].RegionState |=3D EFI_SMRAM_LOCKED; + } + DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n")); + return EFI_DEVICE_ERROR; + } + /// + /// Open SMRAM region + /// + SmramControl |=3D B_SA_SMRAMC_D_OPEN_MASK; + SmramControl &=3D ~(B_SA_SMRAMC_D_CLS_MASK); + + PciSegmentWrite8 (Address, SmramControl); + /// + /// END CHIPSET CODE + /// + + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~(EFI_SM= RAM_CLOSED | EFI_ALLOCATED); + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT64) EFI_SMRA= M_OPEN; + SmmAccess->SmmAccess.OpenState =3D TRUE; + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "close" a region of SMRAM. This is va= lid for + compatible SMRAM region. + + @param[in] PeiServices - General purpose services available to = every PEIM. + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Close. + + @retval EFI_SUCCESS - The region was successfully closed. + @retval EFI_DEVICE_ERROR - The region could not be closed because= locked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Close ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + BOOLEAN OpenState; + UINT8 Index; + UINT64 Address; + UINT8 SmramControl; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + if (DescriptorIndex >=3D SmmAccess->NumberRegions) { + DEBUG ((DEBUG_WARN, "SMRAM region out of range\n")); + + return EFI_INVALID_PARAMETER; + } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM= _LOCKED) { + // + // Cannot close a "locked" region + // + DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n")); + + return EFI_DEVICE_ERROR; + } + + if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED= ) { + return EFI_DEVICE_ERROR; + } + + /// + /// BEGIN CHIPSET CODE + /// + /// + /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit) + /// + Address =3D PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN,= R_SA_SMRAMC); + SmramControl =3D PciSegmentRead8 (Address); + /// + /// Is SMRAM locked? + /// + if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) { + /// + /// Cannot Close a locked region + /// + for (Index =3D 0; Index < SmmAccess->NumberRegions; Index++) { + SmmAccess->SmramDesc[Index].RegionState |=3D EFI_SMRAM_LOCKED; + } + DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n")); + return EFI_DEVICE_ERROR; + } + /// + /// Close SMRAM region + /// + SmramControl &=3D ~(B_SA_SMRAMC_D_OPEN_MASK); + + PciSegmentWrite8 (Address, SmramControl); + /// + /// END CHIPSET CODE + /// + + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~EFI_SMR= AM_OPEN; + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT64) (EFI_SMR= AM_CLOSED | EFI_ALLOCATED); + + // + // Find out if any regions are still open + // + OpenState =3D FALSE; + for (Index =3D 0; Index < SmmAccess->NumberRegions; Index++) { + if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) =3D=3D = EFI_SMRAM_OPEN) { + OpenState =3D TRUE; + } + } + + SmmAccess->SmmAccess.OpenState =3D OpenState; + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to PEIM. + + @param[in] PeiServices - General purpose services available to e= very PEIM. + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Lock. + + @retval EFI_SUCCESS - The region was successfully locked. + @retval EFI_DEVICE_ERROR - The region could not be locked because= at least + one range is still open. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Lock ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINT64 Address; + UINT8 SmramControl; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + if (DescriptorIndex >=3D SmmAccess->NumberRegions) { + DEBUG ((DEBUG_WARN, "SMRAM region out of range\n")); + + return EFI_INVALID_PARAMETER; + } else if (SmmAccess->SmmAccess.OpenState) { + DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still op= en\n")); + + return EFI_DEVICE_ERROR; + } + + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT64) EFI_SMRA= M_LOCKED; + SmmAccess->SmmAccess.LockState =3D TRUE; + + /// + /// BEGIN CHIPSET CODE + /// + /// + /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit) + /// + Address =3D PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN,= R_SA_SMRAMC); + SmramControl =3D PciSegmentRead8 (Address); + + /// + /// Lock the SMRAM + /// + SmramControl |=3D B_SA_SMRAMC_D_LCK_MASK; + + PciSegmentWrite8 (Address, SmramControl); + /// + /// END CHIPSET CODE + /// + + return EFI_SUCCESS; +} + +/** + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + @param[in] PeiServices - General purpose services available to ev= ery PEIM. + @param[in] This - Pointer to the SMRAM Access Interface. + @param[in, out] SmramMapSize - Pointer to the variable containing size= of the + buffer to contain the description infor= mation. + @param[in, out] SmramMap - Buffer containing the data describing t= he Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient b= uffer. + @retval EFI_SUCCESS - The user provided a sufficiently-sized = buffer. +**/ +EFI_STATUS +EFIAPI +GetCapabilities ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_ACCESS_PPI *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap + ) +{ + EFI_STATUS Status; + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINTN NecessaryBufferSize; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + NecessaryBufferSize =3D SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DES= CRIPTOR); + if (*SmramMapSize < NecessaryBufferSize) { + DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n")); + + Status =3D EFI_BUFFER_TOO_SMALL; + } else { + CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize); + Status =3D EFI_SUCCESS; + } + + *SmramMapSize =3D NecessaryBufferSize; + return Status; +} + +/** + This function is to install an SMM Access PPI + - Introduction \n + An API to install an instance of EFI_PEI_MM_ACCESS_PPI. This PPI is co= mmonly used to control SMM mode memory access for S3 resume. + + @retval EFI_SUCCESS - Ppi successfully started and installed. + @retval EFI_NOT_FOUND - Ppi can't be found. + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver. +**/ +EFI_STATUS +EFIAPI +PeiInstallSmmAccessPpi ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock; + SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate; + VOID *HobList; + + // + // Initialize private data + // + SmmAccessPrivate =3D AllocateZeroPool (sizeof (*SmmAccessPrivate)); + ASSERT (SmmAccessPrivate !=3D NULL); + if (SmmAccessPrivate =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + PpiList =3D AllocateZeroPool (sizeof (*PpiList)); + ASSERT (PpiList !=3D NULL); + if (PpiList =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SmmAccessPrivate->Signature =3D SMM_ACCESS_PRIVATE_DATA_SIGNATURE; + SmmAccessPrivate->Handle =3D NULL; + + // + // Get Hob list + // + HobList =3D GetFirstGuidHob (&gEfiSmmSmramMemoryGuid); + if (HobList =3D=3D NULL) { + DEBUG ((DEBUG_WARN, "SmramMemoryReserve HOB not found\n")); + return EFI_NOT_FOUND; + } + + DescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobLis= t + sizeof (EFI_HOB_GUID_TYPE)); + + // + // Alloc space for SmmAccessPrivate->SmramDesc + // + SmmAccessPrivate->SmramDesc =3D AllocateZeroPool ((DescriptorBlock->Numb= erOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR)); + if (SmmAccessPrivate->SmramDesc =3D=3D NULL) { + DEBUG ((DEBUG_WARN, "Alloc SmmAccessPrivate->SmramDesc fail.\n")); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n")); + + // + // use the hob to publish SMRAM capabilities + // + for (Index =3D 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; I= ndex++) { + SmmAccessPrivate->SmramDesc[Index].PhysicalStart =3D DescriptorBlock-= >Descriptor[Index].PhysicalStart; + SmmAccessPrivate->SmramDesc[Index].CpuStart =3D DescriptorBlock-= >Descriptor[Index].CpuStart; + SmmAccessPrivate->SmramDesc[Index].PhysicalSize =3D DescriptorBlock-= >Descriptor[Index].PhysicalSize; + SmmAccessPrivate->SmramDesc[Index].RegionState =3D DescriptorBlock-= >Descriptor[Index].RegionState; + } + + SmmAccessPrivate->NumberRegions =3D Index; + SmmAccessPrivate->SmmAccess.Open =3D Open; + SmmAccessPrivate->SmmAccess.Close =3D Close; + SmmAccessPrivate->SmmAccess.Lock =3D Lock; + SmmAccessPrivate->SmmAccess.GetCapabilities =3D GetCapabilities; + SmmAccessPrivate->SmmAccess.LockState =3D FALSE; + SmmAccessPrivate->SmmAccess.OpenState =3D FALSE; + + // + // Install PPI + // + PpiList->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR= _TERMINATE_LIST); + PpiList->Guid =3D &gEfiPeiMmAccessPpiGuid; + PpiList->Ppi =3D &SmmAccessPrivate->SmmAccess; + + Status =3D PeiServicesInstallPpi (PpiList); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmm= AccessLibSmramc/PeiSmmAccessLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature= /SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf new file mode 100644 index 000000000000..916346aacff3 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessL= ibSmramc/PeiSmmAccessLib.inf @@ -0,0 +1,41 @@ +## @file +# Library description file for the SmmAccess PPI +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiSmmAccessLibSmramc +FILE_GUID =3D 3D28FD4B-F46F-4E24-88AA-9DA09C51BE87 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D SmmAccessLib + + +[LibraryClasses] +BaseMemoryLib +MemoryAllocationLib +DebugLib +HobLib +PciSegmentLib +PeiServicesLib + + +[Packages] +MdePkg/MdePkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + + +[Sources] +PeiSmmAccessLib.c + + +[Ppis] +gEfiPeiMmAccessPpiGuid ## PRODUCES + + +[Guids] +gEfiSmmSmramMemoryGuid --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92920): https://edk2.groups.io/g/devel/message/92920 Mute This Topic: https://groups.io/mt/93335518/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92921+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92921+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1661805424; cv=none; d=zohomail.com; s=zohoarc; b=KrHIErmk0Gel+5N7jtWOJj/rvMo4sf72Y5sDop6y/6xut6L54t9o0/P2jPMpa1c4jcT7YN7XyB0kuTKeyzmkzhViJ8mfhwTJogF34ZLQfEOhaNoKc5UuUD8c9zEyVmal/LmFKZYQ0IJv7DDorTn06uvtDPcOQ2Kvn/zscsi/AN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661805424; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pCXPWY1J4qiS+34oQyM2F8z2mc+4ZBTNIUape1MC5kc=; b=gQDo/jSAZ5BPtAwRPmZmE50Ktf2XopygXhI7iZk2LOTq6B+oVPpI8IosZBKegameYXvzfwycjr9UDLQp9MEVN+rY8wIHfGj3YyeKMY7dhaKR9rB3dqMXHVisFmdk3ioH+hKSc5NxIsf14CIbp4Ev+tU6GOAHYr/qOoz6vu75wbM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92921+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1661805424088714.3114321975155; Mon, 29 Aug 2022 13:37:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id mZXJYY1788612xEVqiXLbnjf; Mon, 29 Aug 2022 13:37:03 -0700 X-Received: from mail-qk1-f181.google.com (mail-qk1-f181.google.com [209.85.222.181]) by mx.groups.io with SMTP id smtpd.web12.3512.1661805422881041328 for ; Mon, 29 Aug 2022 13:37:03 -0700 X-Received: by mail-qk1-f181.google.com with SMTP id g21so6989260qka.5 for ; Mon, 29 Aug 2022 13:37:02 -0700 (PDT) X-Gm-Message-State: PYzGsqMu3bMlrpjysBTEQj6Hx1787277AA= X-Google-Smtp-Source: AA6agR451g6yO3EMLnK4otBmFH27t9owGx6nyEyspIYaHP89ilO4ejJHdu8YaxYBPPseCqu+j6eKhQ== X-Received: by 2002:a05:620a:2a0a:b0:6bb:d296:3196 with SMTP id o10-20020a05620a2a0a00b006bbd2963196mr9751310qkp.785.1661805421677; Mon, 29 Aug 2022 13:37:01 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:01 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Ray Ni , Rangasai V Chaganty , Isaac Oram Subject: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port SmmControl protocol to PPI for S3 Date: Mon, 29 Aug 2022 16:36:17 -0400 Message-Id: <5d3ee2d57676168af4d0a001683a719a5e57b66a.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805423; bh=8ztWi2Son6J4/U+ZQN5EeGU0Jr2xMaQh825gISPaXa0=; h=Cc:Date:From:Reply-To:Subject:To; b=u+4YUmkG6T5hQB0Kxmoaa7PcLDPV2EAfo3RCb/tu+9KMVwNwlgDW32n9d9M7iwYoe5g YZ8kLekoXCgNtdRHk9eZsIXFyPK6+pERc7lpBxYsrcvnROqTYUIckKVlYpmh/r3AXBSeT blVzKrYhXtfvzJx62xkS3B5ZCi9+OMK1yJY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805425379100006 Content-Type: text/plain; charset="utf-8" S3 resume may require communication with SMM, for which we need the SmmControl PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access. As the registers are common across Intel platforms in the tree, while a helper function definition is not, implement a new library as a compatibility shim. Tested, working on Kabylake. Further testing required after the refactor for compatibility. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../BaseIntelCompatShimLibCfl.c | 24 ++ .../BaseIntelCompatShimLibCfl.inf | 24 ++ .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++ .../PeiSmmControlLib/PeiSmmControlLib.inf | 36 ++ .../Include/Library/IntelCompatShimLib.h | 20 ++ .../Include/Library/SmmControlLib.h | 26 ++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + .../BaseIntelCompatShimLibKbl.c | 29 ++ .../BaseIntelCompatShimLibKbl.inf | 24 ++ 9 files changed, 496 insertions(+) create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCom= patShimLibCfl/BaseIntelCompatShimLibCfl.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCom= patShimLibCfl/BaseIntelCompatShimLibCfl.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/IntelComp= atShimLib.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmContro= lLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompa= tShimLibKbl/BaseIntelCompatShimLibKbl.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompa= tShimLibKbl/BaseIntelCompatShimLibKbl.inf diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShim= LibCfl/BaseIntelCompatShimLibCfl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Lib= rary/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c new file mode 100644 index 000000000000..5353126267e6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/= BaseIntelCompatShimLibCfl.c @@ -0,0 +1,24 @@ +/** @file + A Coffeelake+ compatibility shim + + Copyright (c) 2022, Baruch Binyamin Doron
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +EFIAPI +CompatShimGetAcpiBase ( + VOID + ) +{ + return PmcGetAcpiBase (); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShim= LibCfl/BaseIntelCompatShimLibCfl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/L= ibrary/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf new file mode 100644 index 000000000000..48b071ed05ae --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibCfl/= BaseIntelCompatShimLibCfl.inf @@ -0,0 +1,24 @@ +## @file +# Library description file for the Coffeelake+ compatibility shim +# +# Copyright (c) 2022, Baruch Binyamin Doron
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseIntelCompatShimLibCfl +FILE_GUID =3D 3D0BB32E-D328-4615-ADFC-782CECC68D53 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D IntelCompatShimLib + +[LibraryClasses] +PmcLib + +[Packages] +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +BaseIntelCompatShimLibCfl.c diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmC= ontrol/Library/PeiSmmControlLib/PeiSmmControlLib.c new file mode 100644 index 000000000000..80c2c1be90b1 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContro= lLib/PeiSmmControlLib.c @@ -0,0 +1,309 @@ +/** @file + This is to publish the SMM Control Ppi instance. + + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', '= c') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_PEI_MM_CONTROL_PPI SmmControl; +} SMM_CONTROL_PRIVATE_DATA; + +#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \ + CR (a, \ + SMM_CONTROL_PRIVATE_DATA, \ + SmmControl, \ + SMM_CONTROL_DEV_SIGNATURE \ + ) + +// +// Common registers: +// +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_PCH_ACPI_PM1_STS 0x00 +#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11 + +#define R_PCH_SMI_EN 0x30 + +#define R_PCH_SMI_STS 0x34 +#define B_PCH_SMI_STS_APM BIT5 +#define B_PCH_SMI_EN_APMC BIT5 +#define B_PCH_SMI_EN_EOS BIT1 +#define B_PCH_SMI_EN_GBL_SMI BIT0 + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI = data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + UINT8 Data + ) +{ + UINT16 ABase; + UINT32 OutputData; + UINT32 OutputPort; + + ABase =3D CompatShimGetAcpiBase (); + + /// + /// Enable the APMC SMI + /// + OutputPort =3D ABase + R_PCH_SMI_EN; + OutputData =3D IoRead32 ((UINTN) OutputPort); + OutputData |=3D (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI); + DEBUG ( + (DEBUG_EVENT, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + OutputPort =3D R_PCH_APM_CNT; + OutputData =3D Data; + + /// + /// Generate the APMC SMI + /// + IoWrite8 ( + (UINTN) OutputPort, + (UINT8) (OutputData) + ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ) +{ + UINT16 ABase; + UINT32 OutputData; + UINT32 OutputPort; + + ABase =3D CompatShimGetAcpiBase (); + + /// + /// Clear the Power Button Override Status Bit, it gates EOS from being = set. + /// + OutputPort =3D ABase + R_PCH_ACPI_PM1_STS; + OutputData =3D B_PCH_ACPI_PM1_STS_PRBTNOR; + DEBUG ( + (DEBUG_EVENT, + "The PM1 Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite16 ( + (UINTN) OutputPort, + (UINT16) (OutputData) + ); + + /// + /// Clear the APM SMI Status Bit + /// + OutputPort =3D ABase + R_PCH_SMI_STS; + OutputData =3D B_PCH_SMI_STS_APM; + DEBUG ( + (DEBUG_EVENT, + "The SMI Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// Set the EOS Bit + /// + OutputPort =3D ABase + R_PCH_SMI_EN; + OutputData =3D IoRead32 ((UINTN) OutputPort); + OutputData |=3D B_PCH_SMI_EN_EOS; + DEBUG ( + (DEBUG_EVENT, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// There is no need to read EOS back and check if it is set. + /// This can lead to a reading of zero if an SMI occurs right after the = SMI_EN port read + /// but before the data is returned to the CPU. + /// SMM Dispatcher should make sure that EOS is set after all SMI source= s are processed. + /// + return EFI_SUCCESS; +} + +/** + This routine generates an SMI + + @param[in] This The EFI SMM Control protocol insta= nce + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the opera= tion + @retval EFI_INVALID_PARAMETER Some parameter value passed is not= supported +**/ +EFI_STATUS +EFIAPI +Activate ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ) +{ + EFI_STATUS Status; + UINT8 Data; + + if (Periodic) { + DEBUG ((DEBUG_WARN, "Invalid parameter\n")); + return EFI_INVALID_PARAMETER; + } + + // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicationPei + if (ArgumentBuffer =3D=3D NULL) { + Data =3D 0xFF; + } else { + if (ArgumentBufferSize =3D=3D NULL || *ArgumentBufferSize !=3D 1) { + return EFI_INVALID_PARAMETER; + } + + Data =3D *ArgumentBuffer; + } + /// + /// Clear any pending the APM SMI + /// + Status =3D SmmClear (); + if (EFI_ERROR (Status)) { + return Status; + } + + return SmmTrigger (Data); +} + +/** + This routine clears an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +Deactivate ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return SmmClear (); +} + +/** + This function is to install an SMM Control PPI + - Introduction \n + An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI prov= ides a standard + way for other modules to trigger software SMIs. + + @retval EFI_SUCCESS - Ppi successfully started and installed. + @retval EFI_NOT_FOUND - Ppi can't be found. + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver. +**/ +EFI_STATUS +EFIAPI +PeiInstallSmmControlPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate; + + // + // Initialize private data + // + SmmControlPrivate =3D AllocateZeroPool (sizeof (*SmmControlPrivate)); + ASSERT (SmmControlPrivate !=3D NULL); + if (SmmControlPrivate =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + PpiList =3D AllocateZeroPool (sizeof (*PpiList)); + ASSERT (PpiList !=3D NULL); + if (PpiList =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SmmControlPrivate->Signature =3D SMM_CONTROL_PRIVATE_DATA_SIGNATURE; + SmmControlPrivate->Handle =3D NULL; + + SmmControlPrivate->SmmControl.Trigger =3D Activate; + SmmControlPrivate->SmmControl.Clear =3D Deactivate; + + // + // Install PPI + // + PpiList->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR= _TERMINATE_LIST); + PpiList->Guid =3D &gEfiPeiMmControlPpiGuid; + PpiList->Ppi =3D &SmmControlPrivate->SmmControl; + + Status =3D PeiServicesInstallPpi (PpiList); + ASSERT_EFI_ERROR (Status); + + // Unlike driver, do not disable SMIs as S3 resume continues + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Sm= mControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf new file mode 100644 index 000000000000..92f2879d82ab --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContro= lLib/PeiSmmControlLib.inf @@ -0,0 +1,36 @@ +## @file +# Library description file for the SmmControl PPI +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiSmmControlLib +FILE_GUID =3D F45D521A-C0DF-4283-A3CA-65AD01B479E7 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D SmmControlLib + + +[LibraryClasses] +IntelCompatShimLib +IoLib +DebugLib +MemoryAllocationLib +PeiServicesLib + + +[Packages] +MdePkg/MdePkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + + +[Sources] +PeiSmmControlLib.c + + +[Ppis] +gEfiPeiMmControlPpiGuid ## PRODUCES diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimL= ib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h new file mode 100644 index 000000000000..f8621d92e41a --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h @@ -0,0 +1,20 @@ +/** @file + Library description file for compatibility shim + + Copyright (c) 2022, Baruch Binyamin Doron
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +EFIAPI +CompatShimGetAcpiBase ( + VOID + ); diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h = b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h new file mode 100644 index 000000000000..b532dd13f373 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h @@ -0,0 +1,26 @@ +/** @file + This is to publish the SMM Control Ppi instance. + + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SMM_CONTROL_LIB_H_ +#define _SMM_CONTROL_LIB_H_ + +/** + This function is to install an SMM Control PPI + - Introduction \n + An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI prov= ides a standard + way for other modules to trigger software SMIs. + + @retval EFI_SUCCESS - Ppi successfully started and installed. + @retval EFI_NOT_FOUND - Ppi can't be found. + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver. +**/ +EFI_STATUS +EFIAPI +PeiInstallSmmControlPpi ( + VOID + ); +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index c36d130a0197..fc27b394d267 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -35,6 +35,10 @@ # SmmAccessLib|Include/Library/SmmAccessLib.h =20 + ## @libraryclass Provides services to trigger SMI + # + SmmControlLib|Include/Library/SmmControlLib.h + ## @libraryclass Provides services to access config block # ConfigBlockLib|Include/Library/ConfigBlockLib.h diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.c b/Silicon/Intel/KabylakeSiliconPkg/Library= /BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.c new file mode 100644 index 000000000000..573f67555aa3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/Ba= seIntelCompatShimLibKbl.c @@ -0,0 +1,29 @@ +/** @file + A Kabylake compatibility shim + + Copyright (c) 2022, Baruch Binyamin Doron
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +EFIAPI +CompatShimGetAcpiBase ( + VOID + ) +{ + UINT16 Address; + + Address =3D 0; + PchAcpiBaseGet (&Address); + + return Address; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.inf b/Silicon/Intel/KabylakeSiliconPkg/Libra= ry/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf new file mode 100644 index 000000000000..af3e5a4726e6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/Ba= seIntelCompatShimLibKbl.inf @@ -0,0 +1,24 @@ +## @file +# Library description file for the Kabylake compatibility shim +# +# Copyright (c) 2022, Baruch Binyamin Doron
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseIntelCompatShimLibKbl +FILE_GUID =3D B4A2193E-CF3E-46E6-8617-49E48143B5AB +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D IntelCompatShimLib + +[LibraryClasses] +PchCycleDecodingLib + +[Packages] +KabylakeSiliconPkg/SiPkg.dec + +[Sources] +BaseIntelCompatShimLibKbl.c --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92921): https://edk2.groups.io/g/devel/message/92921 Mute This Topic: https://groups.io/mt/93335519/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92922+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92922+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1661805425; cv=none; d=zohomail.com; s=zohoarc; b=ne2RFfbk5u86fEXDxU4/9bSq52n4eRNAcqIkF/1ZYwD0O8k31wfvy1gEdpryMCYmEnwfa391c97o6HZNLCDZFkMVDpW0GvllBwSQdk2nA8xPAQ8kXEZEvgZV9a8VjCPeTfNRnh+kd5Tc7ZBSz8WmIK6Zn3ty0V8WCvbhrYm8Oq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661805425; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sqZi2rPqxFywukJjQrlm7ak/QkqBUYbVHASXqGLCNqk=; b=AbPI6GckAYPD7PvmsW/ffV7O57a2zrJP4YCV38AF3y4DR7RagGZIYYaLNqxo8s1GAVqg33xuowe7+8CBXcVJLAJMHly6NZelHeX+6gSP8VcPRJVInSsBDod0mJixPqOuDoDkzh/TRuCUlcOqgY81HcjvRMIsUNzflfSkYkU4Ro0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92922+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1661805425492557.206502923825; Mon, 29 Aug 2022 13:37:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id X8icYY1788612xdOAnNbQ02S; Mon, 29 Aug 2022 13:37:05 -0700 X-Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) by mx.groups.io with SMTP id smtpd.web09.3365.1661805424342333299 for ; Mon, 29 Aug 2022 13:37:04 -0700 X-Received: by mail-qk1-f180.google.com with SMTP id f14so7009879qkm.0 for ; Mon, 29 Aug 2022 13:37:04 -0700 (PDT) X-Gm-Message-State: GyH0gMThfi22eYR8jrICr5vjx1787277AA= X-Google-Smtp-Source: AA6agR6q9I89pA3Dq5OCBqY1uJUu+N+cO9ChT/HtQbEoeyYfVLKQcXU4lMWfVlc70kOCxsGVtcUXgw== X-Received: by 2002:a05:620a:408a:b0:6bb:584a:fb49 with SMTP id f10-20020a05620a408a00b006bb584afb49mr9905236qko.468.1661805423114; Mon, 29 Aug 2022 13:37:03 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:02 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Sai Chaganty , Isaac Oram , Liming Gao Subject: [edk2-devel][edk2-platforms][PATCH v1 3/5] S3FeaturePkg: Implement working S3 resume Date: Mon, 29 Aug 2022 16:36:18 -0400 Message-Id: <23fd6d63ba743cfbfa994dda115437719dbc2b4f.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805425; bh=LDfiHMBLb/2Q1WtO/skG/t8XZpCk2jJhsHjeIjdsZOc=; h=Cc:Date:From:Reply-To:Subject:To; b=JK4j50EyzIFv5Fo8rVEC9cN8kU2671rwnVHcW9/AIc+tk12SZTW6NpkBkmhbV1OgkcX dLZDAWN/O7Ff5HxeboIwk9Wcc9znLKEaj3mpZj9F9TFk13DYMl2Z8y19a7lC+oaIS2sP8 CagajNO6hYk89l9TUkclbovpyRRV0eXIpBU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805427383100014 Content-Type: text/plain; charset="utf-8" Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries (policy overrides) required for successful S3 resume. Factored allocation logic into new module to avoid MinPlatform dependency on S3Feature package. TODO: Can optimise required size. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Signed-off-by: Benjamin Doron --- .../S3FeaturePkg/Include/PostMemory.fdf | 15 ++ .../S3FeaturePkg/Include/PreMemory.fdf | 8 +- .../S3FeaturePkg/Include/S3Feature.dsc | 42 ++++- .../S3FeaturePkg/S3Dxe/S3Dxe.c | 156 ++++++++++++++++++ .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++ .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++- .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- .../Include/AcpiS3MemoryNvData.h | 22 +++ 8 files changed, 375 insertions(+), 8 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .c create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .inf create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvDat= a.h diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory= .fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf index 9e17f853c630..5d3d96f4f317 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf @@ -2,7 +2,22 @@ # FDF file for post-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +## Dependencies + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + +## Save-state module stack + INF S3FeaturePkg/S3Dxe/S3Dxe.inf + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + # FSP may perform CPU finalisation, requires CpuInitDxe from closed code + # - Presently, PiSmmCpuDxeSmm shall perform finalisation with this data + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + +## Restore-state module stack + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor= Dxe.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.= fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index fdd16a4e0356..e130fa5f098d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -2,9 +2,15 @@ # FDF file for pre-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 -INF S3FeaturePkg/S3Pei/S3Pei.inf +## Dependencies + INF S3FeaturePkg/S3Pei/S3Pei.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + +## Restore-state module stack + INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.= dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index cc34e785076a..bf45b56258ff 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -7,6 +7,7 @@ # for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,6 +26,10 @@ !error "DXE_ARCH must be specified to build this feature!" !endif =20 +[PcdsFixedAtBuild] + # Attempts to improve performance at the cost of more DRAM usage + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE + ##########################################################################= ###### # # Library Class section - list of all Library Classes needed by this featu= re. @@ -32,7 +37,15 @@ ##########################################################################= ###### =20 [LibraryClasses.common.PEIM] - SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf + #SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibS= mramc/PeiSmmAccessLib.inf + SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLi= b/PeiSmmControlLib.inf + #IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.inf + +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf =20 ##########################################################################= ###### # @@ -65,3 +78,30 @@ =20 # Add components here that should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf + +# +# Feature DXE Components +# + +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308 +# is completed. +[Components.X64] + ##################################### + # S3 Feature Package + ##################################### + + # Add library instances here that are not included in package components= and should be tested + # in the package build. + + # Add components here that should be included in the package build. + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + S3FeaturePkg/S3Dxe/S3Dxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + # NOTE: RSC will be after end-of-BS, use DebugLibSerialPort + # - No gBS in SerialPortInitialize() + # - No global assigns after ReadyToLock possible, due to LockBox copy + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c new file mode 100644 index 000000000000..b3fb63e2bc33 --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c @@ -0,0 +1,156 @@ +/** @file + Source code file for S3 DXE module + +Copyright (c) 2022, Baruch Binyamin Doron.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Get the mem size in memory type infromation table. + + @return the mem size in memory type infromation table. +**/ +UINT64 +EFIAPI +GetMemorySizeInMemoryTypeInformation ( + VOID + ) +{ + EFI_STATUS Status; + EFI_MEMORY_TYPE_INFORMATION *MemoryData; + UINT8 Index; + UINTN TempPageNum; + + Status =3D EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGui= d, (VOID **) &MemoryData); + + if (EFI_ERROR (Status) || MemoryData =3D=3D NULL) { + return 0; + } + + TempPageNum =3D 0; + for (Index =3D 0; MemoryData[Index].Type !=3D EfiMaxMemoryType; Index++)= { + // + // Accumulate default memory size requirements + // + TempPageNum +=3D MemoryData[Index].NumberOfPages; + } + + return TempPageNum * EFI_PAGE_SIZE; +} + +/** + Get the mem size need to be consumed and reserved for PEI phase resume. + + @return the mem size to be reserved for PEI phase resume. +**/ +UINT64 +EFIAPI +GetPeiMemSize ( + VOID + ) +{ + #define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE) + + UINT64 Size; + + Size =3D GetMemorySizeInMemoryTypeInformation (); + + return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +/** + Allocate EfiACPIMemoryNVS below 4G memory address. + + This function allocates EfiACPIMemoryNVS below 4G memory address. + + @param Size Size of memory to allocate. + + @return Allocated address for output. + +**/ +VOID * +EFIAPI +AllocateAcpiNvsMemoryBelow4G ( + IN UINTN Size + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + VOID *Buffer; + + Pages =3D EFI_SIZE_TO_PAGES (Size); + Address =3D 0xffffffff; + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + ASSERT_EFI_ERROR (Status); + + Buffer =3D (VOID *)(UINTN)Address; + ZeroMem (Buffer, Size); + + return Buffer; +} + +/** + Allocates memory to use on S3 resume. + + @param[in] ImageHandle Not used. + @param[in] SystemTable General purpose services available to e= very DXE driver. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +S3DxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT64 S3PeiMemSize; + UINT64 S3PeiMemBase; + ACPI_S3_MEMORY S3MemoryInfo; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__)); + + S3PeiMemSize =3D GetPeiMemSize (); + S3PeiMemBase =3D (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize); + ASSERT (S3PeiMemBase !=3D 0); + + S3MemoryInfo.S3PeiMemBase =3D S3PeiMemBase; + S3MemoryInfo.S3PeiMemSize =3D S3PeiMemSize; + + DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase)); + DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize)); + + // TODO: LockBox is potentially superior, though requires static location + Status =3D gRT->SetVariable ( + ACPI_S3_MEMORY_NV_NAME, + &gEfiAcpiVariableGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACC= ESS, + sizeof (S3MemoryInfo), + &S3MemoryInfo + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__)); + return EFI_SUCCESS; +} diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf new file mode 100644 index 000000000000..28589c2c869b --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf @@ -0,0 +1,49 @@ +### @file +# Component information file for the S3 DXE module. +# +# Copyright (c) 2022, Baruch Binyamin Doron.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D S3Dxe + FILE_GUID =3D 30926F92-CC83-4381-9F70-AC96EDB5BEE0 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + ENTRY_POINT =3D S3DxeEntryPoint + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + DebugLib + PcdLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + S3FeaturePkg/S3FeaturePkg.dec + +[Sources] + S3Dxe.c + +[Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize + +[FeaturePcd] + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable + +[Guids] + gEfiMemoryTypeInformationGuid ## CONSUMES + gEfiAcpiVariableGuid ## CONSUMES + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c index b0aaa04962c8..6acb894b6fc9 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c @@ -2,12 +2,87 @@ Source code file for S3 PEI module =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Baruch Binyamin Doron.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 +#include +#include +#include #include #include +#include + +// TODO: Finalise implementation factoring +#define R_SA_PAM0 (0x80) +#define R_SA_PAM5 (0x85) +#define R_SA_PAM6 (0x86) + +/** + This function is called after FspSiliconInitDone installed PPI. + For FSP API mode, this is when FSP-M HOBs are installed into EDK2. + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Always return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +FspSiliconInitDoneNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT64 MchBaseAddress; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // Enable PAM regions for AP wakeup vector (resume) + // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here? + // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (te= st resume). Should we? + // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defin= ed for KabylakeSiliconPkg. + // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - th= is does not mean + // that the memory is unusable, perhaps this is precisely because it w= ill contain + // the AP wakeup vector. + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + MchBaseAddress =3D PCI_LIB_ADDRESS (0, 0, 0, 0); + PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33); + PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33); + PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33); + } + + // + // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case + // + Status =3D PeiInstallSmmAccessPpi (); + ASSERT_EFI_ERROR (Status); + + // + // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case + // + Status =3D PeiInstallSmmControlPpi (); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gFspSiliconInitDonePpiGuid, + FspSiliconInitDoneNotify +}; =20 /** S3 PEI module entry point @@ -25,12 +100,10 @@ S3PeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; + EFI_STATUS Status; =20 - // - // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case - // - Status =3D PeiInstallSmmAccessPpi (); + Status =3D PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc); + ASSERT_EFI_ERROR (Status); =20 return Status; } diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf index e485eac9521f..173919bb881e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -18,10 +18,13 @@ [LibraryClasses] PeimEntryPoint PeiServicesLib + DebugLib SmmAccessLib + SmmControlLib =20 [Packages] MdePkg/MdePkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/S3FeaturePkg.dec =20 @@ -31,5 +34,8 @@ [FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =20 +[Ppis] + gFspSiliconInitDonePpiGuid + [Depex] - gEfiPeiMemoryDiscoveredPpiGuid + TRUE diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/P= latform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h new file mode 100644 index 000000000000..0d75af8e9a03 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h @@ -0,0 +1,22 @@ +/** @file + Header file for NV data structure definition. + +Copyright (c) 2021, Baruch Binyamin Doron +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ACPI_S3_MEMORY_NV_DATA_H__ +#define __ACPI_S3_MEMORY_NV_DATA_H__ + +// +// NV data structure +// +typedef struct { + UINT64 S3PeiMemBase; + UINT64 S3PeiMemSize; +} ACPI_S3_MEMORY; + +#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo" + +#endif --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:03 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Ankit Sinha , Isaac Oram , Liming Gao , Eric Dong Subject: [edk2-devel][edk2-platforms][PATCH v1 4/5] MinPlatformPkg: Implement working S3 resume Date: Mon, 29 Aug 2022 16:36:19 -0400 Message-Id: <3473a10f0459bc0d23bd496753ee3179e1860c50.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805426; bh=sUD4SddtSl/oTfWAqkLOTuYCmOKdjgOdiPxQN46YC40=; h=Cc:Date:From:Reply-To:Subject:To; b=hgDWWbM2hmm4FjYd1y2qqSt64V8IYWbjJWJY/sWPt5EmwPs3nxt67V8laFik4OUJl2x pwiiLWPtvp/FwYtri82V1dM6dtW8lKTZhUCXFA1RE0DoIy1FtuYQAFETASs3OqDygjRQx bwmwO92j5tHQC2ivpokEFyqh3yMKV3SlHog= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805427359100013 Content-Type: text/plain; charset="utf-8" Consume S3 resume memory allocation on resume flow. Also, include complementary FirmwarePerformanceDataTablePei module in MinPlatform FV for S3 resume performance measurement. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Cc: Isaac Oram Cc: Liming Gao Cc: Eric Dong Signed-off-by: Benjamin Doron --- .../FspWrapperHobProcessLib.c | 70 ++++++++++++++++++- .../PeiFspWrapperHobProcessLib.inf | 2 + .../Include/Dsc/CorePeiInclude.dsc | 4 ++ .../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++ 4 files changed, 79 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapper= HobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/Fsp= Wrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c index 7ee4d3a31c49..992ec5d41bd8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/FspWrapperHobProcessLib.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/FspWrapperHobProcessLib.c @@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include #include #include #include +#include =20 #include +#include =20 // // Additional pages are used by DXE memory manager. @@ -130,6 +133,55 @@ GetPeiMemSize ( return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE; } =20 +/** + Get S3 PEI memory information. + + @note At this point, memory is ready, and PeiServices are available to u= se. + Platform can get some data from SMRAM directly. + + @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase. + @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase. + + @return If S3 PEI memory information is got successfully. +**/ +EFI_STATUS +EFIAPI +GetS3MemoryInfo ( + OUT UINT64 *S3PeiMemSize, + OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; + UINTN DataSize; + ACPI_S3_MEMORY S3MemoryInfo; + + *S3PeiMemBase =3D 0; + *S3PeiMemSize =3D 0; + + Status =3D PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NU= LL, (VOID **) &VariablePpi); + ASSERT_EFI_ERROR (Status); + + DataSize =3D sizeof (S3MemoryInfo); + Status =3D VariablePpi->GetVariable ( + VariablePpi, + ACPI_S3_MEMORY_NV_NAME, + &gEfiAcpiVariableGuid, + NULL, + &DataSize, + &S3MemoryInfo + ); + ASSERT_EFI_ERROR (Status); + + if (EFI_ERROR (Status)) { + return Status; + } + + *S3PeiMemBase =3D S3MemoryInfo.S3PeiMemBase; + *S3PeiMemSize =3D S3MemoryInfo.S3PeiMemSize; + return EFI_SUCCESS; +} + /** Post FSP-M HOB process for Memory Resource Descriptor. =20 @@ -280,7 +332,7 @@ PostFspmHobProcess ( 0x1000 ); =20 - + if (BootMode !=3D BOOT_ON_S3_RESUME) { // // Capsule mode // @@ -337,7 +389,23 @@ PostFspmHobProcess ( if (Capsule !=3D NULL) { Status =3D Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, C= apsuleBuffer, CapsuleBufferLength); } + } else { + // TODO: Must BuildResourceDescriptorHob()? + Status =3D GetS3MemoryInfo (&PeiMemSize, &PeiMemBase); + ASSERT_EFI_ERROR (Status); =20 + DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBa= se)); + DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSi= ze)); + + // + // Install efi memory + // + Status =3D PeiServicesInstallPeiMemory ( + PeiMemBase, + PeiMemSize + ); + ASSERT_EFI_ERROR (Status); + } =20 // // Create a memory allocation HOB at fixed location for MP Services PPI = AP wait loop. diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapper= HobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPk= g/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.= inf index b846e7af1d2d..e2aac36bf018 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf @@ -75,7 +75,9 @@ gZeroGuid gEfiGraphicsInfoHobGuid gEfiGraphicsDeviceInfoHobGuid + gEfiAcpiVariableGuid =20 [Ppis] gEfiPeiCapsulePpiGuid ## CONSUMES + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES gEdkiiSiliconInitializedPpiGuid ## PRODUCES diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b= /Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc index 08e50cac075f..0eb0cc8306ee 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc +++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc @@ -41,3 +41,7 @@ NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf } !endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE && gS3Fe= aturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerf= ormancePei.inf +!endif diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclud= e.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf index 3c2716d6728a..d8fb6683f7d4 100644 --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf @@ -6,3 +6,7 @@ # SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE && gS3Fe= aturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/Firmwar= ePerformancePei.inf +!endif --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92923): https://edk2.groups.io/g/devel/message/92923 Mute This Topic: https://groups.io/mt/93335522/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 18:35:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92924+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92924+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1661805428; cv=none; d=zohomail.com; s=zohoarc; b=JeVbxHSlD89Y8xGpOVgPmdxiJDdooRlvYPs+3g5EcQfvd7bmoEuFffPowZ7eXLARvVDH9ZdSpgREz3mNjG5PhMlslSF78CDe6kbxUKzBG+kTE7vxQE6mPLmJfI8hXHoYT3C/iGatX7CmbiwwSBXDUYIYVJf8RCTdf7GcBafThpc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661805428; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GsYaRvZAHdG+LqZZeUYI1gGKDUFcS/NEPNOj/aHomj0=; b=X0r9rNPXL32YdWjiQ9yC7t+8o6F9BJQqZHSs4cMSd7oWLtl1Uk6oQKXhgY58iE1+Y6BnUviSsTE2TKPsvznXvnds1nJGJVWLkRCkcQrM8OsqMjMxm4eI48Uo7UKiVPoXW9qHXDm7B0aBUZcoxm2c64hffqXqVaM9viTNShIlDuc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92924+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1661805428189911.8718153492415; Mon, 29 Aug 2022 13:37:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id y7kNYY1788612xt9Ag4p8HME; Mon, 29 Aug 2022 13:37:07 -0700 X-Received: from mail-qt1-f176.google.com (mail-qt1-f176.google.com [209.85.160.176]) by mx.groups.io with SMTP id smtpd.web11.3426.1661805426850280479 for ; Mon, 29 Aug 2022 13:37:07 -0700 X-Received: by mail-qt1-f176.google.com with SMTP id cb8so7130608qtb.0 for ; Mon, 29 Aug 2022 13:37:06 -0700 (PDT) X-Gm-Message-State: TqQzapswJiU509YOIANjd8q5x1787277AA= X-Google-Smtp-Source: AA6agR7EbTNkxlvfbbKHHvkL5R9/rg3EOZG5R7EYThiGZBz7kUMUOQGoKU4vBIbtpgfmUvnl5cGEPg== X-Received: by 2002:ac8:690b:0:b0:343:5bc0:78a0 with SMTP id bt11-20020ac8690b000000b003435bc078a0mr11665188qtb.535.1661805425589; Mon, 29 Aug 2022 13:37:05 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:05 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Chasel Chiu , Jeremy Soller , Sai Chaganty , Isaac Oram Subject: [edk2-devel][edk2-platforms][PATCH v1 5/5] KabylakeOpenBoardPkg: Example of board S3 Date: Mon, 29 Aug 2022 16:36:20 -0400 Message-Id: <9825213b3cbe2814c9b4418570cdeca3fe49bc90.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805427; bh=gYJKzITnaJtSkXCPezwEWhNn3Lw93RA7vRWEZwiRfSY=; h=Cc:Date:From:Reply-To:Subject:To; b=PZs+5XxWb3SMcIzURBqlNicDRY/qQuzx/sBiaoAytfuxoxKOLDkk1s7rDIIiVGKnCvP HKzE4GdLoQWJIJlHG+w6+0H23s4nThNj7Ktfy6pDWt9JHqAnHuCPcZ1Li2cOghkadoI1S MPDsKeGY+vUG0tyTONt6l5JnIcehUiI9L1k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805431518100002 Content-Type: text/plain; charset="utf-8" Use silicon code to detect S3 resume state. Apply some relevant policy modifications. PcdPeiMemSize must be in common scope, for a DXE module to allocate required memory. Libraries that produce required PPIs are defined. BootScriptExecutorDxe should only be linked against a functionally compatible debug stack. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Chasel Chiu Cc: Jeremy Soller Cc: Sai Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../PeiFspMiscUpdUpdateLib.c | 12 +++- .../PeiSaPolicyUpdate.c | 12 +++- .../PeiAspireVn7Dash572GInitPreMemLib.c | 61 ++++++++++++++----- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 + .../AspireVn7Dash572G/OpenBoardPkg.dsc | 18 ++++++ .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 7 +-- .../PeiSiliconPolicyUpdateLib.c | 11 +++- .../PeiSiliconPolicyUpdateLib.inf | 1 + .../PeiFspMiscUpdUpdateLib.c | 11 +++- .../PeiSaPolicyUpdate.c | 12 +++- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 +++++++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../GalagoPro3/OpenBoardPkg.dsc | 16 +++++ .../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +- .../PeiFspMiscUpdUpdateLib.c | 12 +++- .../PeiSaPolicyUpdate.c | 12 +++- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../PeiKabylakeRvp3InitPreMemLib.c | 27 +++++++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../KabylakeRvp3/OpenBoardPkg.dsc | 13 ++++ .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +- .../PeiSiliconPolicyUpdateLib.c | 11 +++- .../PeiSiliconPolicyUpdateLib.inf | 1 + 24 files changed, 242 insertions(+), 33 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform= /Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index a9b7e446c8d6..7e4194bf4fe6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include + #include #include #include @@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c index 4621cbd3ca3a..1299bf504fbd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -40,7 +46,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeO= penBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInit= PreMemLib.c index 1c9a65399b54..1b4c6b484b43 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c @@ -11,7 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include +#include #include #include #include @@ -248,6 +250,8 @@ AspireVn7Dash572GBoardDebugInit ( VOID ) { + UINT16 ABase; + /// /// Do Early PCH init /// @@ -258,6 +262,16 @@ AspireVn7Dash572GBoardDebugInit ( // - Alternatively, move the preceding calls to BoardDetect() AspireVn7Dash572GBoardDetect (); =20 + // Dump relevant registers + // - TODO: Remove after debugging + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_A)))); + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_B)))); + + PchAcpiBaseGet (&ABase); + DEBUG ((DEBUG_INFO, "ABase PM1_STS=3D 0x%x\n", IoRead16 (ABase))); + DEBUG ((DEBUG_INFO, "ABase PM1_EN=3D 0x%x\n", IoRead16 (ABase + R_PCH_AC= PI_PM1_EN))); + DEBUG ((DEBUG_INFO, "ABase PM1_CNT=3D 0x%x\n", IoRead32 (ABase + R_PCH_A= CPI_PM1_CNT))); + return EFI_SUCCESS; } =20 @@ -267,25 +281,42 @@ AspireVn7Dash572GBoardBootModeDetect ( VOID ) { - UINT16 ABase; + EFI_BOOT_MODE BootMode; UINT32 SleepType; + UINT16 ABase; =20 DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); =20 - // TODO: Perform advanced detection (recovery/capsule) - // FIXME: This violates PI specification? But BOOT_WITH* would always ta= ke precedence - // over BOOT_ON_S{4,5}... - PchAcpiBaseGet (&ABase); - SleepType =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT= _SLP_TYP; + // Known sane defaults; TODO: Consider "default"? + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; =20 - switch (SleepType) { - case V_PCH_ACPI_PM1_CNT_S3: - return BOOT_ON_S3_RESUME; - case V_PCH_ACPI_PM1_CNT_S4: - return BOOT_ON_S4_RESUME; -// case V_PCH_ACPI_PM1_CNT_S5: -// return BOOT_ON_S5_RESUME; - default: - return BOOT_WITH_FULL_CONFIGURATION; + // TODO: Perform advanced detection (capsule/recovery) + // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assu= me" + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + // Dump relevant registers + // - TODO: Remove after debugging + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_A)))); + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_B)))); + + PchAcpiBaseGet (&ABase); + DEBUG ((DEBUG_INFO, "ABase PM1_STS=3D 0x%x\n", IoRead16 (ABase))); + DEBUG ((DEBUG_INFO, "ABase PM1_EN=3D 0x%x\n", IoRead16 (ABase + R_PCH_AC= PI_PM1_EN))); + DEBUG ((DEBUG_INFO, "ABase PM1_CNT=3D 0x%x\n", IoRead32 (ABase + R_PCH_A= CPI_PM1_CNT))); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index cd9f979d313c..c53114e15450 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf @@ -25,11 +25,14 @@ TimerLib PchCycleDecodingLib PchResetLib + PciLib IoLib EcLib BoardEcLib GpioLib PeiLib + PeiServicesLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.dsc index 261f141056f5..f4664985f947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -150,6 +150,7 @@ ####################################### ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf =20 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # @@ -238,6 +239,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -662,6 +664,22 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Library cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # Reverse-ranked priority list +# TODO: Requires testing +# - Strongly suspect DebugLibSerialPort constructor presents PeiDxeSerialP= ortLibMem dependency on services as a bug +!if FALSE # $(USE_MEMORY_LOGGING) =3D=3D TRUE + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialP= ortLibMem.inf +!endif + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoa= rdPkgPcd.dsc index 822040c06f32..df2cc81ae801 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc @@ -127,10 +127,7 @@ # PcdIpmiFeatureEnable will not be enabled (no BMC) # TODO: Can be build-time (user) choice gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable = |FALSE - # TODO: Continue developing support. Broken at present. - # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub - # - May require a PeiSmmControlLib to SMM communicate - gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |FALSE + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |TRUE # TODO: Definitions (now added SmbiosDxe) gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable = |TRUE # Requires actual hook-up @@ -360,6 +357,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -442,7 +440,6 @@ # Edk2 Configuration ###################################### gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp= dateLib/PeiSiliconPolicyUpdateLib.c index 3764f7c3ac09..ab8abac6be1c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; @@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem ( =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + GtConfig =3D NULL; Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig); ASSERT_EFI_ERROR (Status); @@ -571,7 +576,11 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf index 1ce26fc3dcec..31a45292209d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib MemoryAllocationLib PeiLib + PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/= KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLi= bFsp/PeiFspMiscUpdUpdateLib.c index dbc84631acaa..ce309bd378d2 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include @@ -36,11 +37,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -75,7 +80,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/Kabyl= akeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/= PeiSaPolicyUpdate.c index 133b8c963f65..48899aa63b4f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Galag= oPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index d6c91cd2b94b..5b3a6921d0ee 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf @@ -23,6 +23,7 @@ PcdLib SiliconInitLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Ga= lagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c index 051dac0b204d..1cd2baf4a4dd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiGalagoPro3InitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiGalagoPro3InitPreMemLib.c @@ -14,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -236,5 +237,29 @@ GalagoPro3BoardBootModeDetect ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; + EFI_BOOT_MODE BootMode; + UINT32 SleepType; + + DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); + + // Known sane defaults + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } + } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/= GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index fe31f421356e..20ddac1d994d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf @@ -25,6 +25,7 @@ SiliconInitLib MultiBoardInitSupportLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 2e3c6d3ca506..097d20f34b4e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -108,6 +108,7 @@ ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf =20 ##################################### # Platform Package @@ -177,6 +178,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -488,6 +490,20 @@ NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf !endif } + +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Libraries cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # Reverse-ranked priority list +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdI2cHdmiDebugPortEnable =3D=3D T= RUE + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPo= rtLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf +!endif + } +!endif MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouter= Smm.inf { DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index 4a37d6157b95..618a70910536 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -305,6 +305,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -405,7 +406,6 @@ ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Inte= l/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpda= teLibFsp/PeiFspMiscUpdUpdateLib.c index 699f4297fad6..71b03f2da464 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include #include - #include #include #include @@ -36,11 +36,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -73,7 +77,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/Kab= ylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLib= Fsp/PeiSaPolicyUpdate.c index d6ec3e38dd7e..b69abd11cbce 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Kab= ylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 850fc514188b..e0022e8d6118 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf @@ -24,6 +24,7 @@ SiliconInitLib EcLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c index 87ae3b531ed6..02cd37227e50 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -330,5 +331,29 @@ KabylakeRvp3BoardBootModeDetect ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; + EFI_BOOT_MODE BootMode; + UINT32 SleepType; + + DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); + + // Known sane defaults + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } + } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index 23fe6b6f03c5..0112bf84a193 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf @@ -26,6 +26,7 @@ MultiBoardInitSupportLib EcLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 26a54b0dc7cc..dbffa2918df7 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -138,6 +138,7 @@ ####################################### ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf =20 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # @@ -201,6 +202,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -505,6 +507,17 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Libraries cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # TODO: Insert a reverse-ranked priority list of compatible librarie= s here + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index bdd5bc412795..82bf55f4cce1 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -305,6 +305,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -375,7 +376,6 @@ ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/Ka= bylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/Pe= iSiliconPolicyUpdateLib.c index 22aadc0221df..2061efb2445c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -513,6 +514,7 @@ SiliconPolicyUpdatePostMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; @@ -521,6 +523,9 @@ SiliconPolicyUpdatePostMem ( =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + GtConfig =3D NULL; Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig); ASSERT_EFI_ERROR (Status); @@ -535,7 +540,11 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/= PeiSiliconPolicyUpdateLib.inf index 25eae88f5989..e9a23593e133 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib MemoryAllocationLib PeiLib + PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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