From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87328+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87328+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646706998; cv=none; d=zohomail.com; s=zohoarc; b=B/0naEqm4DTt6Ydj3DdTObHILfRJ6GnQ2sBvzeOlp7ktxowKXkLsARDwJLSsw+lECE7AkTSWC9Uojb4Ddr8M3kLfEzSbG1jXNF2jYd3r32zNVeuoFRhxOvumHOkTP5bRFqFsuaAJpJvFkezHZ47zgDxfZ9awJoV7dZF4DZNPtBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646706998; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=eMNc3tQ9b9ETXYYa0RzCMXHukGr8ilriw5WNfnmRzvc=; b=PUIV9UGpgBTceUPmh3IrzmDBB0TKuN4QQXbEOZtmqrMLYvet1Tkf6XuVUj1psuubuymybkzdvV5HQxEblDQoP7gcxfUvceC9Z5GFm7qKqNAS2nV+KX6HdUnW+hVD896aeElRoLjCz3gc01T65dVO6t9Fn/BoLDbqfYDedPIa7oA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87328+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646706998253749.3599167582921; Mon, 7 Mar 2022 18:36:38 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4LStYY1788612xxTbqoDsTPu; Mon, 07 Mar 2022 18:36:37 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:37 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317800924" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317800924" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:36 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432580" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:31 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH 01/14] OvmfPkg: Create initial version of PlatformInitLib Date: Tue, 8 Mar 2022 10:36:02 +0800 Message-Id: <7052c14164fe2696378c7e6087d16b0a9f6dcf73.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: rCwqSJ2J0tKb1W3596ENMGS1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646706997; bh=iV8xnALqfsA70BnwB7wKNIliaQ9cF37c59z/DYrkRMI=; h=Cc:Date:From:Reply-To:Subject:To; b=g9Uo0DZKxaATFTCu0MwKErh+/+29TwOGFyml9g2KFTTfGUCLCxzFpzRyMjAW/8AP7ck 4KDksMXTXzCwPe+/9yftRyEqOezVUz38nBqiFVzNHzyQr1g5jZG3sDGCHCxwftnOncWYP 3fZOTqLp4DJYexWB+SouZGTlziMwJpa4bMc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707000216100005 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 There are 3 variants of PlatformPei in OvmfPkg: - OvmfPkg/PlatformPei - OvmfPkg/XenPlatformPei - OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf These PlatformPeis can share many common codes, such as Cmos / Hob / Memory / Platform related functions. This commit (and its following several patches) are to create a PlatformInitLib which wraps the common code called in above PlatformPeis. In this initial version of PlatformInitLib, below Cmos related functions are introduced: - PlatformCmosRead8 - PlatformCmosWrite8 - PlatformDebugDumpCmos They correspond to the functions in OvmfPkg/PlatformPei: - CmosRead8 - CmosWrite8 - DebugDumpCmos Considering this PlatformInitLib will be used in SEC phase, global variables and dynamic PCDs are avoided. We use PlatformInfoHob to exchange information between functions. EFI_HOB_PLATFORM_INFO is the data struct which contains the platform information, such as HostBridgeDevId, BootMode, S3Supported, SmmSmramRequire, etc. After PlatformInitLib is created, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/Include/Library/PlatformInitLib.h | 99 +++++++++++++++++++ .../PlatformInitLib}/Cmos.c | 32 +++++- .../PlatformInitLib/PlatformInitLib.inf | 36 +++++++ OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkg.dec | 4 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/PlatformPei/Cmos.h | 48 --------- OvmfPkg/PlatformPei/MemDetect.c | 8 +- OvmfPkg/PlatformPei/Platform.c | 29 +----- OvmfPkg/PlatformPei/PlatformPei.inf | 3 +- 14 files changed, 183 insertions(+), 82 deletions(-) create mode 100644 OvmfPkg/Include/Library/PlatformInitLib.h rename OvmfPkg/{PlatformPei =3D> Library/PlatformInitLib}/Cmos.c (61%) create mode 100644 OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf delete mode 100644 OvmfPkg/PlatformPei/Cmos.h diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index fd56176796d5..785049c88962 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -280,6 +280,7 @@ !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLi= b.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index b4d855d80f56..b8a82380202c 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -307,6 +307,7 @@ !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLi= b.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h new file mode 100644 index 000000000000..2ebac5ccb013 --- /dev/null +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -0,0 +1,99 @@ +/** @file + PlatformInitLib header file. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_INIT_LIB_H_ +#define PLATFORM_INIT_LIB_H_ + +#include + +#pragma pack(1) +typedef struct { + EFI_HOB_GUID_TYPE GuidHeader; + UINT16 HostBridgeDevId; + + UINT64 PcdConfidentialComputingGuestAttr; + BOOLEAN SevEsIsEnabled; + + UINT32 BootMode; + BOOLEAN S3Supported; + + BOOLEAN SmmSmramRequire; + BOOLEAN Q35SmramAtDefaultSmbase; + UINT16 Q35TsegMbytes; + + UINT64 FirstNonAddress; + UINT8 PhysMemAddressWidth; + UINT32 Uc32Base; + UINT32 Uc32Size; + + BOOLEAN PcdSetNxForStack; + UINT64 PcdTdxSharedBitMask; + + UINT64 PcdPciMmio64Base; + UINT64 PcdPciMmio64Size; + UINT32 PcdPciMmio32Base; + UINT32 PcdPciMmio32Size; + UINT64 PcdPciIoBase; + UINT64 PcdPciIoSize; + + UINT64 PcdEmuVariableNvStoreReserved; + UINT32 PcdCpuBootLogicalProcessorNumber; + UINT32 PcdCpuMaxLogicalProcessorNumber; + UINT32 DefaultMaxCpuNumber; + + UINT32 S3AcpiReservedMemoryBase; + UINT32 S3AcpiReservedMemorySize; +} EFI_HOB_PLATFORM_INFO; +#pragma pack() + +/** + Reads 8-bits of CMOS data. + + Reads the 8-bits of CMOS data at the location specified by Index. + The 8-bit read value is returned. + + @param Index The CMOS location to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +PlatformCmosRead8 ( + IN UINTN Index + ); + +/** + Writes 8-bits of CMOS data. + + Writes 8-bits of CMOS data to the location specified by Index + with the value specified by Value and returns Value. + + @param Index The CMOS location to write. + @param Value The value to write to CMOS. + + @return The value written to CMOS. + +**/ +UINT8 +EFIAPI +PlatformCmosWrite8 ( + IN UINTN Index, + IN UINT8 Value + ); + +/** + Dump the CMOS content + */ +VOID +EFIAPI +PlatformDebugDumpCmos ( + VOID + ); + +#endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/PlatformPei/Cmos.c b/OvmfPkg/Library/PlatformInitLib/C= mos.c similarity index 61% rename from OvmfPkg/PlatformPei/Cmos.c rename to OvmfPkg/Library/PlatformInitLib/Cmos.c index a01b3866bee4..977aa97aea8c 100644 --- a/OvmfPkg/PlatformPei/Cmos.c +++ b/OvmfPkg/Library/PlatformInitLib/Cmos.c @@ -6,7 +6,8 @@ =20 **/ =20 -#include "Cmos.h" +#include +#include #include "Library/IoLib.h" =20 /** @@ -22,7 +23,7 @@ **/ UINT8 EFIAPI -CmosRead8 ( +PlatformCmosRead8 ( IN UINTN Index ) { @@ -44,7 +45,7 @@ CmosRead8 ( **/ UINT8 EFIAPI -CmosWrite8 ( +PlatformCmosWrite8 ( IN UINTN Index, IN UINT8 Value ) @@ -53,3 +54,28 @@ CmosWrite8 ( IoWrite8 (0x71, Value); return Value; } + +/** + Dump the CMOS content + */ +VOID +EFIAPI +PlatformDebugDumpCmos ( + VOID + ) +{ + UINT32 Loop; + + DEBUG ((DEBUG_INFO, "CMOS:\n")); + + for (Loop =3D 0; Loop < 0x80; Loop++) { + if ((Loop % 0x10) =3D=3D 0) { + DEBUG ((DEBUG_INFO, "%02x:", Loop)); + } + + DEBUG ((DEBUG_INFO, " %02x", PlatformCmosRead8 (Loop))); + if ((Loop % 0x10) =3D=3D 0xf) { + DEBUG ((DEBUG_INFO, "\n")); + } + } +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf new file mode 100644 index 000000000000..4ea2da86274f --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -0,0 +1,36 @@ +## @file +# Platform Initialization Lib +# +# This module provides platform specific function to detect boot mode. +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformInitLib + FILE_GUID =3D 89f886b0-7109-46e1-9d28-503ad4ab6ee0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformInitLib|PEIM + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[Sources] + Cmos.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 1ea43443ae97..27005eec89f2 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -300,6 +300,7 @@ QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf =20 MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLi= b.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 7aa94ca02863..6322d2e4de15 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -109,6 +109,10 @@ # XenPlatformLib|Include/Library/XenPlatformLib.h =20 + ## @libraryclass PlatformInitLib + # + PlatformInitLib|Include/Library/PlatformInitLib.h + [Guids] gUefiOvmfPkgTokenSpaceGuid =3D {0x93bb96af, 0xb9f2, 0x4eb8, {= 0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}} gEfiXenInfoGuid =3D {0xd3b46f3b, 0xd441, 0x1244, {= 0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}} diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 85abed24c1a7..8f02dca63869 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -300,6 +300,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a9c1daecc1a8..c58ef8494470 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -304,6 +304,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 718399299f57..227b9845619f 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -305,6 +305,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/PlatformPei/Cmos.h b/OvmfPkg/PlatformPei/Cmos.h deleted file mode 100644 index 2b3124d7ba36..000000000000 --- a/OvmfPkg/PlatformPei/Cmos.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - PC/AT CMOS access routines - - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __CMOS_H__ -#define __CMOS_H__ - -/** - Reads 8-bits of CMOS data. - - Reads the 8-bits of CMOS data at the location specified by Index. - The 8-bit read value is returned. - - @param Index The CMOS location to read. - - @return The value read. - -**/ -UINT8 -EFIAPI -CmosRead8 ( - IN UINTN Index - ); - -/** - Writes 8-bits of CMOS data. - - Writes 8-bits of CMOS data to the location specified by Index - with the value specified by Value and returns Value. - - @param Index The CMOS location to write. - @param Value The value to write to CMOS. - - @return The value written to CMOS. - -**/ -UINT8 -EFIAPI -CmosWrite8 ( - IN UINTN Index, - IN UINT8 Value - ); - -#endif diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 8ecc8257f9b9..9c5bf240e3ba 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -37,9 +37,9 @@ Module Name: #include #include #include +#include =20 #include "Platform.h" -#include "Cmos.h" =20 UINT8 mPhysMemAddressWidth; =20 @@ -412,8 +412,8 @@ GetSystemMemorySizeBelow4gb ( // into the calculation to get the total memory size. // =20 - Cmos0x34 =3D (UINT8)CmosRead8 (0x34); - Cmos0x35 =3D (UINT8)CmosRead8 (0x35); + Cmos0x34 =3D (UINT8)PlatformCmosRead8 (0x34); + Cmos0x35 =3D (UINT8)PlatformCmosRead8 (0x35); =20 return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); } @@ -436,7 +436,7 @@ GetSystemMemorySizeAbove4gb ( =20 Size =3D 0; for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) { - Size =3D (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex); + Size =3D (UINT32)(Size << 8) + (UINT32)PlatformCmosRead8 (CmosIndex); } =20 return LShiftU64 (Size, 16); diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index d0323c645162..594891786440 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -36,10 +36,10 @@ #include #include #include +#include #include =20 #include "Platform.h" -#include "Cmos.h" =20 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { { @@ -505,11 +505,11 @@ BootModeInitialization ( { EFI_STATUS Status; =20 - if (CmosRead8 (0xF) =3D=3D 0xFE) { + if (PlatformCmosRead8 (0xF) =3D=3D 0xFE) { mBootMode =3D BOOT_ON_S3_RESUME; } =20 - CmosWrite8 (0xF, 0x00); + PlatformCmosWrite8 (0xF, 0x00); =20 Status =3D PeiServicesSetBootMode (mBootMode); ASSERT_EFI_ERROR (Status); @@ -546,27 +546,6 @@ ReserveEmuVariableNvStore ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -VOID -DebugDumpCmos ( - VOID - ) -{ - UINT32 Loop; - - DEBUG ((DEBUG_INFO, "CMOS:\n")); - - for (Loop =3D 0; Loop < 0x80; Loop++) { - if ((Loop % 0x10) =3D=3D 0) { - DEBUG ((DEBUG_INFO, "%02x:", Loop)); - } - - DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop))); - if ((Loop % 0x10) =3D=3D 0xf) { - DEBUG ((DEBUG_INFO, "\n")); - } - } -} - VOID S3Verification ( VOID @@ -810,7 +789,7 @@ InitializePlatform ( =20 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); =20 - DebugDumpCmos (); + PlatformDebugDumpCmos (); =20 if (QemuFwCfgS3Enabled ()) { DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n")); diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 212aa7b04751..f6bfc09c2dd5 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -25,8 +25,6 @@ [Sources] AmdSev.c ClearCache.c - Cmos.c - Cmos.h FeatureControl.c Fv.c MemDetect.c @@ -64,6 +62,7 @@ MemEncryptSevLib PcdLib VmgExitLib + PlatformInitLib =20 [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87328): https://edk2.groups.io/g/devel/message/87328 Mute This Topic: https://groups.io/mt/89629672/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87329+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87329+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646706999; cv=none; d=zohomail.com; s=zohoarc; b=SObxDu0EoarIFzHzxyc99hch2Z+urHiIi6d0akvbY5APiCs2lFFfDPDU4SgojepyM+Q10AfFTJnRp0n7MrWxFJ8w8P5gSeg0uuXkpwcHXuTy7/2LfTXKprAtdH4bS0jr4OuHpwJms3wEyaKN4eztXnZwdee7VSgJ6tzyqEVDVYI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646706999; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=dWaUmaSJAdWRVWfNJRHrpcqINWvW6RQURZ7aMpnHKKI=; b=Js5nliD38W3Rbgnn+wWOz4R5sKWf9WZ+T1z9TfPN+F9rykazz1OmhVkW1KrmIs0daUbMLIU+i15fl9Hl1S+fS4Y3AL2fI8z392BS0o5uKi3hWaPnStS8EOfj3q2EGcZkBOh50g051BS6dffJmsolkBksD1prA/vSB9upJHCtMKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87329+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646706999056227.67769042254668; Mon, 7 Mar 2022 18:36:39 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id rOSMYY1788612xpHmEuP8okd; Mon, 07 Mar 2022 18:36:38 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:38 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317800942" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317800942" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:37 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432593" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:35 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH 02/14] OvmfPkg/PlatformInitLib: Add hob functions Date: Tue, 8 Mar 2022 10:36:03 +0800 Message-Id: <5ea5092ff00e7cb88dfdd3bf0279219f6d43f288.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: r2lV3SAxhsohWW2lEjYbSwvnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646706998; bh=LmIX19D37s2uPirPzVLhZkJA7Ow6us7YO4X11onqIqo=; h=Cc:Date:From:Reply-To:Subject:To; b=lkaFqsuarpjSw0/5XEfcUPBG6pFHG6rH0s4cOphddhuyoWflRekiCpis4CyP724wlLf pHhbzW0puUh4s05lSnzFxSF5KXrms4QV2cJNB1TuuWFfs5BhKz2060D+PpoE46bB+BESW h6JY8m/qVRop3XIPVT2Fh+P8i0WFkP+l+SU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707000291100007 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 In this patch of PlatformInitLib, below hob functions are introduced: - PlatformAddIoMemoryBaseSizeHob - PlatformAddIoMemoryRangeHob - PlatformAddMemoryBaseSizeHob - PlatformAddMemoryRangeHob - PlatformAddReservedMemoryBaseSizeHob They correspond the below functions in OvmfPkg/PlatformPei: - AddIoMemoryBaseSizeHob - AddIoMemoryRangeHob - AddMemoryBaseSizeHob - AddMemoryRangeHob - AddReservedMemoryBaseSizeHob After above hob functions are introduced in PlatformInitLib, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/Include/Library/PlatformInitLib.h | 36 ++++++ OvmfPkg/Library/PlatformInitLib/Platform.c | 106 ++++++++++++++++++ .../PlatformInitLib/PlatformInitLib.inf | 2 + OvmfPkg/PlatformPei/MemDetect.c | 20 ++-- OvmfPkg/PlatformPei/Platform.c | 101 ++--------------- OvmfPkg/PlatformPei/Platform.h | 31 ----- 6 files changed, 165 insertions(+), 131 deletions(-) create mode 100644 OvmfPkg/Library/PlatformInitLib/Platform.c diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index 2ebac5ccb013..9b99d4c1f514 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -96,4 +96,40 @@ PlatformDebugDumpCmos ( VOID ); =20 +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Platform.c new file mode 100644 index 000000000000..e41f230ff563 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -0,0 +1,106 @@ +/**@file + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include + +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + (Cacheable ? + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : + 0 + ) | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - Memor= yBase)); +} + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf index 4ea2da86274f..21813458cb59 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -24,6 +24,7 @@ =20 [Sources] Cmos.c + Platform.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec @@ -34,3 +35,4 @@ BaseLib DebugLib IoLib + HobLib diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 9c5bf240e3ba..e5e105f377dd 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -275,10 +275,10 @@ ScanOrAdd64BitE820Ram ( End =3D (E820Entry.BaseAddr + E820Entry.Length) & ~(UINT64)EFI_PAGE_MASK; if (Base < End) { - AddMemoryRangeHob (Base, End); + PlatformAddMemoryRangeHob (Base, End); DEBUG (( DEBUG_VERBOSE, - "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n", + "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", __FUNCTION__, Base, End @@ -816,8 +816,8 @@ QemuInitializeRamBelow1gb ( ) { if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { - AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); + PlatformAddReservedMemoryBaseSizeHob ( SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE, TRUE /* Cacheable */ @@ -826,12 +826,12 @@ QemuInitializeRamBelow1gb ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128= KB, "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" ); - AddMemoryRangeHob ( + PlatformAddMemoryRangeHob ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, BASE_512KB + BASE_128KB ); } else { - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); } } =20 @@ -889,14 +889,14 @@ QemuInitializeRam ( UINT32 TsegSize; =20 TsegSize =3D mQ35TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddReservedMemoryBaseSizeHob ( LowerMemorySize - TsegSize, TsegSize, TRUE ); } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); } =20 // @@ -908,7 +908,7 @@ QemuInitializeRam ( if (EFI_ERROR (Status)) { UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); if (UpperMemorySize !=3D 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 594891786440..62480c3c40e5 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -57,85 +57,6 @@ BOOLEAN mS3Supported =3D FALSE; =20 UINT32 mMaxCpuCount; =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_MAPPED_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - (Cacheable ? - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : - 0 - ) | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - VOID MemMapInitialization ( VOID @@ -155,12 +76,12 @@ MemMapInitialization ( // // Video memory + Legacy BIOS region // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); =20 if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { - AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ + PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ + PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } =20 @@ -194,20 +115,20 @@ MemMapInitialization ( // 0xFEE00000 LAPIC 1 MB // PciSize =3D 0xFC000000 - PciBase; - AddIoMemoryBaseSizeHob (PciBase, PciSize); + PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); =20 - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); // // Note: there should be an // - // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); + // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); // // call below, just like the one above for RCBA. However, Linux insists // that the MMCONFIG area be marked in the E820 or UEFI memory map as @@ -225,7 +146,7 @@ MemMapInitialization ( // is most definitely not RAM; so, as an exception, cover it with // uncacheable reserved memory right here. // - AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); + PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); BuildMemoryAllocationHob ( PciExBarBase, SIZE_256MB, @@ -233,7 +154,7 @@ MemMapInitialization ( ); } =20 - AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); + PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), S= IZE_1MB); =20 // // On Q35, the IO Port space is available for PCI resource allocations f= rom diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 24e4da4e1d93..f193ff736549 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,37 +11,6 @@ =20 #include =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ); - VOID AddressWidthInitialization ( VOID --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87329): https://edk2.groups.io/g/devel/message/87329 Mute This Topic: https://groups.io/mt/89629673/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87330+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87330+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707002; cv=none; d=zohomail.com; s=zohoarc; b=B3IgMzEweErJv8NAtu8GV9P+SYCRr41MrU+4pdoKVzRC0/Y55tLVGArmH5Ga//jd+2EZIpyUW8xJHM4CYCV5xK/TkvU/yrFVc5iv8f66lQZ6qBN1mEqLylVcmAFc2bt3o8yWNGZd8NRmu+l5bNow6A2KleC3qegZ0wN9XUPKYR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707002; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Q4C6js12C6SuKXEwWBX6tpXtnOQOx2lBdRfZJT9YPh0=; b=O4Gd/cG0iaSmR2yfrjqJrRi57mRjW0vQ1QT3BJq3S+KBykY/XynPsoy+Mo7gEMZW6Rkd6xQaVWCEdLv3dpGsPiUfMFNG7tVgcHL9AWG37VdreCGOAdSMTXJSzsGHUh5rRh5XtYLKcRPtkD387zO5qQpyzRKQWfLkEMVb69WO4vQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87330+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707002925761.0355649250301; Mon, 7 Mar 2022 18:36:42 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id kOk6YY1788612xOda8UhTEEj; Mon, 07 Mar 2022 18:36:42 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:41 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317800983" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317800983" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:40 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432610" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:37 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 03/14] OvmfPkg/PlatformPei: Move global variables to PlatformInfoHob Date: Tue, 8 Mar 2022 10:36:04 +0800 Message-Id: <446345b8c57f5e2a38937767fce1bbbe142a9179.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: PgGCaWNjHKo5DRc07R4KMRI8x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707002; bh=vMkae48YqPKxHZ0FCemzT1pcRFPDXR+vv9NvUDtdMAY=; h=Cc:Date:From:Reply-To:Subject:To; b=kWMsQdoFghlxDQobId2BX2kf9W8inrMd678pYWGA/CLotIl8QLtcdMn/k+zCGxQqZj9 9Pjmiy4vuZjzbtltybiDgE744hAYGxURZFYQJ4FGkmFZTvDkYnelDjWXB1gmrW5Zo39sa qRdeqi7F0eKjr24QOvKaC8W2y0KW/o+lyGE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707004140100002 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 The intention of PlatformInitLib is to extract the common function used in OvmfPkg/PlatformPei. This lib will be used not only in PEI phase but also in SEC phase. SEC phase cannot use global variables between different functions. So PlatformInfoHob is created to hold the informations shared between functions. For example, HostBridgeDevId corespond to mHostBridgeDevId in PlatformPei. In this patch we will first move below global variables to PlatformInfoHob. - mBootMode - mS3Supported - mPhysMemAddressWidth - mMaxCpuCount - mHostBridgeDevId - mQ35SmramAtDefaultSmbase - mQemuUc32Base - mS3AcpiReservedMemorySize - mS3AcpiReservedMemoryBase PlatformInfoHob also holds other information, for example, PciIoBase / PciIoSize. This is because in SEC phase, PcdSetxxx doesn't work. So we will restruct the functions which set PCDs into two, one for PlatformInfoLib, one for PlatformPei. So in this patch we first move global variables and PCDs to PlatformInfoHob. All the changes are in OvmfPkg/PlatformPei. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/AmdSev.c | 10 +- OvmfPkg/PlatformPei/Fv.c | 6 +- OvmfPkg/PlatformPei/MemDetect.c | 210 +++++++++++++++--------------- OvmfPkg/PlatformPei/MemTypeInfo.c | 4 +- OvmfPkg/PlatformPei/Platform.c | 109 ++++++++-------- OvmfPkg/PlatformPei/Platform.h | 43 +++--- 6 files changed, 201 insertions(+), 181 deletions(-) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index fb7e21ec140f..c180383b42b0 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -24,6 +24,8 @@ =20 #include "Platform.h" =20 +extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob; + STATIC UINT64 GetHypervisorFeature ( @@ -228,7 +230,7 @@ AmdSevEsInitialize ( // Since the pages must survive across the UEFI to OS transition // make them reserved. // - GhcbPageCount =3D mMaxCpuCount * 2; + GhcbPageCount =3D mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber * 2; GhcbBase =3D AllocateReservedPages (GhcbPageCount); ASSERT (GhcbBase !=3D NULL); =20 @@ -266,7 +268,7 @@ AmdSevEsInitialize ( // Allocate #VC recursion backup pages. The number of backup pages neede= d is // one less than the maximum VC count. // - GhcbBackupPageCount =3D mMaxCpuCount * (VMGEXIT_MAXIMUM_VC_COUNT - 1); + GhcbBackupPageCount =3D mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber= * (VMGEXIT_MAXIMUM_VC_COUNT - 1); GhcbBackupBase =3D AllocatePages (GhcbBackupPageCount); ASSERT (GhcbBackupBase !=3D NULL); =20 @@ -367,7 +369,7 @@ AmdSevInitialize ( // until after re-encryption, in order to prevent an information leak to= the // hypervisor. // - if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode !=3D BOOT_ON_S3_RES= UME)) { + if (mPlatformInfoHob.SmmSmramRequire && (mPlatformInfoHob.BootMode !=3D = BOOT_ON_S3_RESUME)) { RETURN_STATUS LocateMapStatus; UINTN MapPagesBase; UINTN MapPagesCount; @@ -378,7 +380,7 @@ AmdSevInitialize ( ); ASSERT_RETURN_ERROR (LocateMapStatus); =20 - if (mQ35SmramAtDefaultSmbase) { + if (mPlatformInfoHob.Q35SmramAtDefaultSmbase) { // // The initial SMRAM Save State Map has been covered as part of a la= rger // reserved memory allocation in InitializeRamRegions(). diff --git a/OvmfPkg/PlatformPei/Fv.c b/OvmfPkg/PlatformPei/Fv.c index 8cd8cacc5913..b9bf1a1d8b01 100644 --- a/OvmfPkg/PlatformPei/Fv.c +++ b/OvmfPkg/PlatformPei/Fv.c @@ -13,6 +13,8 @@ #include #include =20 +extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob; + /** Publish PEI & DXE (Decompressed) Memory based FVs to let PEI and DXE know about them. @@ -37,7 +39,7 @@ PeiFvInitialization ( BuildMemoryAllocationHob ( PcdGet32 (PcdOvmfPeiMemFvBase), PcdGet32 (PcdOvmfPeiMemFvSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData + mPlatformInfoHob.S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData ); =20 // @@ -45,7 +47,7 @@ PeiFvInitialization ( // BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSiz= e)); =20 - SecureS3Needed =3D mS3Supported && FeaturePcdGet (PcdSmmSmramRequire); + SecureS3Needed =3D mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmS= mramRequire; =20 // // Create a memory allocation HOB for the DXE FV. diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index e5e105f377dd..981a9ff28685 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -37,20 +37,10 @@ Module Name: #include #include #include -#include =20 #include "Platform.h" =20 -UINT8 mPhysMemAddressWidth; - -STATIC UINT32 mS3AcpiReservedMemoryBase; -STATIC UINT32 mS3AcpiReservedMemorySize; - -STATIC UINT16 mQ35TsegMbytes; - -BOOLEAN mQ35SmramAtDefaultSmbase; - -UINT32 mQemuUc32Base; +extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob; =20 VOID Q35TsegMbytesInitialization ( @@ -60,7 +50,7 @@ Q35TsegMbytesInitialization ( UINT16 ExtendedTsegMbytes; RETURN_STATUS PcdStatus; =20 - ASSERT (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID); + ASSERT (mPlatformInfoHob.HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID); =20 // // Check if QEMU offers an extended TSEG. @@ -81,7 +71,7 @@ Q35TsegMbytesInitialization ( PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY); ExtendedTsegMbytes =3D PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB)); if (ExtendedTsegMbytes =3D=3D MCH_EXT_TSEG_MB_QUERY) { - mQ35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes); + mPlatformInfoHob.Q35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes); return; } =20 @@ -93,7 +83,7 @@ Q35TsegMbytesInitialization ( )); PcdStatus =3D PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes); ASSERT_RETURN_ERROR (PcdStatus); - mQ35TsegMbytes =3D ExtendedTsegMbytes; + mPlatformInfoHob.Q35TsegMbytes =3D ExtendedTsegMbytes; } =20 VOID @@ -103,9 +93,9 @@ Q35SmramAtDefaultSmbaseInitialization ( { RETURN_STATUS PcdStatus; =20 - ASSERT (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID); + ASSERT (mPlatformInfoHob.HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID); =20 - mQ35SmramAtDefaultSmbase =3D FALSE; + mPlatformInfoHob.Q35SmramAtDefaultSmbase =3D FALSE; if (FeaturePcdGet (PcdCsmEnable)) { DEBUG (( DEBUG_INFO, @@ -118,37 +108,36 @@ Q35SmramAtDefaultSmbaseInitialization ( =20 CtlReg =3D DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL); PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY); - CtlRegVal =3D PciRead8 (CtlReg); - mQ35SmramAtDefaultSmbase =3D (BOOLEAN)(CtlRegVal =3D=3D - MCH_DEFAULT_SMBASE_IN_RAM); + CtlRegVal =3D PciRead8 (CtlReg); + mPlatformInfoHob.Q35SmramAtDefaultSmbase =3D (BOOLEAN)(CtlRegVal =3D= =3D + MCH_DEFAULT_SMBAS= E_IN_RAM); DEBUG (( DEBUG_INFO, "%a: SMRAM at default SMBASE %a\n", __FUNCTION__, - mQ35SmramAtDefaultSmbase ? "found" : "not found" + mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found" )); } =20 PcdStatus =3D PcdSetBoolS ( PcdQ35SmramAtDefaultSmbase, - mQ35SmramAtDefaultSmbase + mPlatformInfoHob.Q35SmramAtDefaultSmbase ); ASSERT_RETURN_ERROR (PcdStatus); } =20 VOID QemuUc32BaseInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINT32 LowerMemorySize; - UINT32 Uc32Size; =20 - if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { return; } =20 - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for @@ -157,40 +146,40 @@ QemuUc32BaseInitialization ( // variable MTRRs (preferably 1 or 2). // ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); - mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); + PlatformInfoHob->Uc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBase= Address); return; } =20 - if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { - Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; - mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + PlatformInfoHob->Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; + PlatformInfoHob->Uc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; return; } =20 - ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); + ASSERT (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); // // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one // variable MTRR suffices by truncating the size to a whole power of two, // while keeping the end affixed to 4GB. This will round the base up. // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); - Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize= )); - mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); + LowerMemorySize =3D GetSystemMemorySizeBelow4gb (PlatformInfoH= ob); + PlatformInfoHob->Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - Lower= MemorySize)); + PlatformInfoHob->Uc32Base =3D (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32S= ize); // // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. // Therefore mQemuUc32Base is at least 2GB. // - ASSERT (mQemuUc32Base >=3D BASE_2GB); + ASSERT (PlatformInfoHob->Uc32Base >=3D BASE_2GB); =20 - if (mQemuUc32Base !=3D LowerMemorySize) { + if (PlatformInfoHob->Uc32Base !=3D LowerMemorySize) { DEBUG (( DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for " "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, - mQemuUc32Base, - Uc32Size + PlatformInfoHob->Uc32Base, + PlatformInfoHob->Uc32Size )); } } @@ -385,7 +374,7 @@ GetHighestSystemMemoryAddressFromPvhMemmap ( =20 UINT32 GetSystemMemorySizeBelow4gb ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { EFI_STATUS Status; @@ -393,7 +382,7 @@ GetSystemMemorySizeBelow4gb ( UINT8 Cmos0x34; UINT8 Cmos0x35; =20 - if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { // Get the information from PVH memmap return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); } @@ -448,11 +437,10 @@ GetSystemMemorySizeAbove4gb ( STATIC UINT64 GetFirstNonAddress ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINT64 FirstNonAddress; - UINT64 Pci64Base, Pci64Size; UINT32 FwCfgPciMmio64Mb; EFI_STATUS Status; FIRMWARE_CONFIG_ITEM FwCfgItem; @@ -493,7 +481,7 @@ GetFirstNonAddress ( // Otherwise, in order to calculate the highest address plus one, we must // consider the 64-bit PCI host aperture too. Fetch the default size. // - Pci64Size =3D PcdGet64 (PcdPciMmio64Size); + PlatformInfoHob->PcdPciMmio64Size =3D PcdGet64 (PcdPciMmio64Size); =20 // // See if the user specified the number of megabytes for the 64-bit PCI = host @@ -513,7 +501,7 @@ GetFirstNonAddress ( break; case EFI_SUCCESS: if (FwCfgPciMmio64Mb <=3D 0x1000000) { - Pci64Size =3D LShiftU64 (FwCfgPciMmio64Mb, 20); + PlatformInfoHob->PcdPciMmio64Size =3D LShiftU64 (FwCfgPciMmio64Mb,= 20); break; } =20 @@ -529,8 +517,8 @@ GetFirstNonAddress ( break; } =20 - if (Pci64Size =3D=3D 0) { - if (mBootMode !=3D BOOT_ON_S3_RESUME) { + if (PlatformInfoHob->PcdPciMmio64Size =3D=3D 0) { + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { DEBUG (( DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n", @@ -577,8 +565,8 @@ GetFirstNonAddress ( // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so // that the host can map it with 1GB hugepages. Follow suit. // - Pci64Base =3D ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB); - Pci64Size =3D ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB); + PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (FirstNonAddress, (UIN= T64)SIZE_1GB); + PlatformInfoHob->PcdPciMmio64Size =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Size, (UINT64)SIZE_1GB); =20 // // The 64-bit PCI host aperture should also be "naturally" aligned. The @@ -586,32 +574,32 @@ GetFirstNonAddress ( // next smaller or equal power of two. That is, align the aperture by the // largest BAR size that can fit into it. // - Pci64Base =3D ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size)); + PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size)); =20 - if (mBootMode !=3D BOOT_ON_S3_RESUME) { + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { // // The core PciHostBridgeDxe driver will automatically add this range = to // the GCD memory space map through our PciHostBridgeLib instance; her= e we // only need to set the PCDs. // - PcdStatus =3D PcdSet64S (PcdPciMmio64Base, Pci64Base); + PcdStatus =3D PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio= 64Base); ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, Pci64Size); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio= 64Size); ASSERT_RETURN_ERROR (PcdStatus); =20 DEBUG (( DEBUG_INFO, "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", __FUNCTION__, - Pci64Base, - Pci64Size + PlatformInfoHob->PcdPciMmio64Base, + PlatformInfoHob->PcdPciMmio64Size )); } =20 // // The useful address space ends with the 64-bit PCI host aperture. // - FirstNonAddress =3D Pci64Base + Pci64Size; + FirstNonAddress =3D PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob-= >PcdPciMmio64Size; return FirstNonAddress; } =20 @@ -620,10 +608,11 @@ GetFirstNonAddress ( **/ VOID AddressWidthInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINT64 FirstNonAddress; + UINT8 PhysMemAddressWidth; =20 // // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts @@ -631,15 +620,15 @@ AddressWidthInitialization ( // The DXL IPL keys off of the physical address bits advertized in the C= PU // HOB. To conserve memory, we calculate the minimum address width here. // - FirstNonAddress =3D GetFirstNonAddress (); - mPhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); + FirstNonAddress =3D GetFirstNonAddress (PlatformInfoHob); + PhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); =20 // // If FirstNonAddress is not an integral power of two, then we need an // additional bit. // if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) { - ++mPhysMemAddressWidth; + ++PhysMemAddressWidth; } =20 // @@ -648,11 +637,14 @@ AddressWidthInitialization ( // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We // can simply assert that here, since 48 bits are good enough for 256 TB. // - if (mPhysMemAddressWidth <=3D 36) { - mPhysMemAddressWidth =3D 36; + if (PhysMemAddressWidth <=3D 36) { + PhysMemAddressWidth =3D 36; } =20 - ASSERT (mPhysMemAddressWidth <=3D 48); + ASSERT (PhysMemAddressWidth <=3D 48); + + PlatformInfoHob->FirstNonAddress =3D FirstNonAddress; + PlatformInfoHob->PhysMemAddressWidth =3D PhysMemAddressWidth; } =20 /** @@ -698,12 +690,12 @@ GetPeiMemoryCap ( } } =20 - if (mPhysMemAddressWidth <=3D 39) { + if (mPlatformInfoHob.PhysMemAddressWidth <=3D 39) { Pml4Entries =3D 1; - PdpEntries =3D 1 << (mPhysMemAddressWidth - 30); + PdpEntries =3D 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30); ASSERT (PdpEntries <=3D 0x200); } else { - Pml4Entries =3D 1 << (mPhysMemAddressWidth - 39); + Pml4Entries =3D 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39); ASSERT (Pml4Entries <=3D 0x200); PdpEntries =3D 512; } @@ -736,38 +728,46 @@ PublishPeiMemory ( UINT64 MemorySize; UINT32 LowerMemorySize; UINT32 PeiMemoryCap; + UINT32 S3AcpiReservedMemoryBase; + UINT32 S3AcpiReservedMemorySize; =20 - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); - if (FeaturePcdGet (PcdSmmSmramRequire)) { + LowerMemorySize =3D GetSystemMemorySizeBelow4gb (&mPlatformInfoHob); + if (mPlatformInfoHob.SmmSmramRequire) { // // TSEG is chipped from the end of low RAM // - LowerMemorySize -=3D mQ35TsegMbytes * SIZE_1MB; + LowerMemorySize -=3D mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB; } =20 + S3AcpiReservedMemoryBase =3D 0; + S3AcpiReservedMemorySize =3D 0; + // // If S3 is supported, then the S3 permanent PEI memory is placed next, // downwards. Its size is primarily dictated by CpuMpPei. The formula be= low // is an approximation. // - if (mS3Supported) { - mS3AcpiReservedMemorySize =3D SIZE_512KB + - mMaxCpuCount * - PcdGet32 (PcdCpuApStackSize); - mS3AcpiReservedMemoryBase =3D LowerMemorySize - mS3AcpiReservedMemoryS= ize; - LowerMemorySize =3D mS3AcpiReservedMemoryBase; + if (mPlatformInfoHob.S3Supported) { + S3AcpiReservedMemorySize =3D SIZE_512KB + + mPlatformInfoHob.PcdCpuMaxLogicalProcessorN= umber * + PcdGet32 (PcdCpuApStackSize); + S3AcpiReservedMemoryBase =3D LowerMemorySize - S3AcpiReservedMemorySiz= e; + LowerMemorySize =3D S3AcpiReservedMemoryBase; } =20 - if (mBootMode =3D=3D BOOT_ON_S3_RESUME) { - MemoryBase =3D mS3AcpiReservedMemoryBase; - MemorySize =3D mS3AcpiReservedMemorySize; + mPlatformInfoHob.S3AcpiReservedMemoryBase =3D S3AcpiReservedMemoryBase; + mPlatformInfoHob.S3AcpiReservedMemorySize =3D S3AcpiReservedMemorySize; + + if (mPlatformInfoHob.BootMode =3D=3D BOOT_ON_S3_RESUME) { + MemoryBase =3D S3AcpiReservedMemoryBase; + MemorySize =3D S3AcpiReservedMemorySize; } else { PeiMemoryCap =3D GetPeiMemoryCap (); DEBUG (( DEBUG_INFO, "%a: mPhysMemAddressWidth=3D%d PeiMemoryCap=3D%u KB\n", __FUNCTION__, - mPhysMemAddressWidth, + mPlatformInfoHob.PhysMemAddressWidth, PeiMemoryCap >> 10 )); =20 @@ -781,7 +781,7 @@ PublishPeiMemory ( // allocation HOB, and other allocations served from the permanent PEI= RAM // shouldn't overlap with that HOB. // - MemoryBase =3D mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ? + MemoryBase =3D mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmr= amRequire ? PcdGet32 (PcdOvmfDecompressionScratchEnd) : PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemF= vSize); MemorySize =3D LowerMemorySize - MemoryBase; @@ -796,7 +796,7 @@ PublishPeiMemory ( // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3 // permanent PEI RAM is located even higher. // - if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { + if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefau= ltSmbase) { ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <=3D MemoryBase); } =20 @@ -812,10 +812,10 @@ PublishPeiMemory ( STATIC VOID QemuInitializeRamBelow1gb ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { + if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefau= ltSmbase) { PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); PlatformAddReservedMemoryBaseSizeHob ( SMM_DEFAULT_SMBASE, @@ -842,7 +842,7 @@ QemuInitializeRamBelow1gb ( STATIC VOID QemuInitializeRam ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINT64 LowerMemorySize; @@ -855,9 +855,9 @@ QemuInitializeRam ( // // Determine total memory size available // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); + LowerMemorySize =3D GetSystemMemorySizeBelow4gb (PlatformInfoHob); =20 - if (mBootMode =3D=3D BOOT_ON_S3_RESUME) { + if (PlatformInfoHob->BootMode =3D=3D BOOT_ON_S3_RESUME) { // // Create the following memory HOB as an exception on the S3 boot path. // @@ -878,17 +878,17 @@ QemuInitializeRam ( // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en // looking for an area to borrow. // - QemuInitializeRamBelow1gb (); + QemuInitializeRamBelow1gb (PlatformInfoHob); } else { // // Create memory HOBs // - QemuInitializeRamBelow1gb (); + QemuInitializeRamBelow1gb (PlatformInfoHob); =20 - if (FeaturePcdGet (PcdSmmSmramRequire)) { + if (PlatformInfoHob->SmmSmramRequire) { UINT32 TsegSize; =20 - TsegSize =3D mQ35TsegMbytes * SIZE_1MB; + TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); PlatformAddReservedMemoryBaseSizeHob ( LowerMemorySize - TsegSize, @@ -924,7 +924,7 @@ QemuInitializeRam ( // practically any alignment, and we may not have enough variable MTRRs = to // cover it exactly. // - if (IsMtrrSupported () && (mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID)) { + if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId !=3D CLOUDHV= _DEVICE_ID)) { MtrrGetAllMtrrs (&MtrrSettings); =20 // @@ -957,8 +957,8 @@ QemuInitializeRam ( // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. // Status =3D MtrrSetMemoryAttribute ( - mQemuUc32Base, - SIZE_4GB - mQemuUc32Base, + PlatformInfoHob->Uc32Base, + SIZE_4GB - PlatformInfoHob->Uc32Base, CacheUncacheable ); ASSERT_EFI_ERROR (Status); @@ -971,20 +971,20 @@ QemuInitializeRam ( **/ VOID InitializeRamRegions ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - QemuInitializeRam (); + QemuInitializeRam (PlatformInfoHob); =20 SevInitializeRam (); =20 - if (mS3Supported && (mBootMode !=3D BOOT_ON_S3_RESUME)) { + if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode !=3D BOOT= _ON_S3_RESUME)) { // // This is the memory range that will be used for PEI on S3 resume // BuildMemoryAllocationHob ( - mS3AcpiReservedMemoryBase, - mS3AcpiReservedMemorySize, + PlatformInfoHob->S3AcpiReservedMemoryBase, + PlatformInfoHob->S3AcpiReservedMemorySize, EfiACPIMemoryNVS ); =20 @@ -1021,7 +1021,7 @@ InitializeRamRegions ( EfiACPIMemoryNVS ); =20 - if (MemEncryptSevEsIsEnabled ()) { + if (PlatformInfoHob->SevEsIsEnabled) { // // If SEV-ES is enabled, reserve the GHCB-related memory area. This // includes the extra page table used to break down the 2MB page @@ -1051,8 +1051,8 @@ InitializeRamRegions ( #endif } =20 - if (mBootMode !=3D BOOT_ON_S3_RESUME) { - if (!FeaturePcdGet (PcdSmmSmramRequire)) { + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + if (!PlatformInfoHob->SmmSmramRequire) { // // Reserve the lock box storage area // @@ -1070,20 +1070,20 @@ InitializeRamRegions ( BuildMemoryAllocationHob ( (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData + PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesD= ata ); } =20 - if (FeaturePcdGet (PcdSmmSmramRequire)) { + if (PlatformInfoHob->SmmSmramRequire) { UINT32 TsegSize; =20 // // Make sure the TSEG area that we reported as a reserved memory res= ource // cannot be used for reserved memory allocations. // - TsegSize =3D mQ35TsegMbytes * SIZE_1MB; + TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( - GetSystemMemorySizeBelow4gb () - TsegSize, + GetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, TsegSize, EfiReservedMemoryType ); @@ -1091,7 +1091,7 @@ InitializeRamRegions ( // Similarly, allocate away the (already reserved) SMRAM at the defa= ult // SMBASE, if it exists. // - if (mQ35SmramAtDefaultSmbase) { + if (PlatformInfoHob->Q35SmramAtDefaultSmbase) { BuildMemoryAllocationHob ( SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE, @@ -1115,7 +1115,7 @@ InitializeRamRegions ( BuildMemoryAllocationHob ( (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData + PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesD= ata ); } =20 diff --git a/OvmfPkg/PlatformPei/MemTypeInfo.c b/OvmfPkg/PlatformPei/MemTyp= eInfo.c index fc5ccfaf113d..6ee36ad1cc5c 100644 --- a/OvmfPkg/PlatformPei/MemTypeInfo.c +++ b/OvmfPkg/PlatformPei/MemTypeInfo.c @@ -17,6 +17,8 @@ =20 #include "Platform.h" =20 +extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob; + #define MEMORY_TYPE_INFO_DEFAULT(Type) \ { Type, FixedPcdGet32 (PcdMemoryType ## Type) } =20 @@ -208,7 +210,7 @@ MemTypeInfoInitialization ( { EFI_STATUS Status; =20 - if (!FeaturePcdGet (PcdSmmSmramRequire)) { + if (!mPlatformInfoHob.SmmSmramRequire) { // // EFI_PEI_READ_ONLY_VARIABLE2_PPI will never be available; install // the default memory type information HOB right away. diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 62480c3c40e5..80eb4cc9adcd 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -36,11 +36,13 @@ #include #include #include -#include +#include #include =20 #include "Platform.h" =20 +EFI_HOB_PLATFORM_INFO mPlatformInfoHob =3D { 0 }; + EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, @@ -49,17 +51,9 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { } }; =20 -UINT16 mHostBridgeDevId; - -EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION; - -BOOLEAN mS3Supported =3D FALSE; - -UINT32 mMaxCpuCount; - VOID MemMapInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINT64 PciIoBase; @@ -78,16 +72,16 @@ MemMapInitialization ( // PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); =20 - if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } =20 - TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); + TopOfLowRam =3D GetSystemMemorySizeBelow4gb (PlatformInfoHob); PciExBarBase =3D 0; - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // The MMCONFIG area is expected to fall between the top of low RAM and // the base of the 32-bit PCI host aperture. @@ -97,8 +91,8 @@ MemMapInitialization ( ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); } else { - ASSERT (TopOfLowRam <=3D mQemuUc32Base); - PciBase =3D mQemuUc32Base; + ASSERT (TopOfLowRam <=3D PlatformInfoHob->Uc32Base); + PciBase =3D PlatformInfoHob->Uc32Base; } =20 // @@ -121,9 +115,12 @@ MemMapInitialization ( PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); =20 + PlatformInfoHob->PcdPciMmio32Base =3D PciBase; + PlatformInfoHob->PcdPciMmio32Size =3D PciSize; + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); // // Note: there should be an @@ -160,7 +157,7 @@ MemMapInitialization ( // On Q35, the IO Port space is available for PCI resource allocations f= rom // 0x6000 up. // - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { PciIoBase =3D 0x6000; PciIoSize =3D 0xA000; ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase); @@ -180,6 +177,9 @@ MemMapInitialization ( ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciIoSize, PciIoSize); ASSERT_RETURN_ERROR (PcdStatus); + + PlatformInfoHob->PcdPciIoBase =3D PciIoBase; + PlatformInfoHob->PcdPciIoSize =3D PciIoSize; } =20 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \ @@ -306,7 +306,7 @@ MicrovmInitialization ( =20 VOID MiscInitialization ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINTN PmCmd; @@ -327,12 +327,12 @@ MiscInitialization ( // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing // S3 resume as well, so we build it unconditionally.) // - BuildCpuHob (mPhysMemAddressWidth, 16); + BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16); =20 // // Determine platform type and save Host Bridge DID to PCD // - switch (mHostBridgeDevId) { + switch (PlatformInfoHob->HostBridgeDevId) { case INTEL_82441_DEVICE_ID: PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); @@ -371,13 +371,13 @@ MiscInitialization ( DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, - mHostBridgeDevId + PlatformInfoHob->HostBridgeDevId )); ASSERT (FALSE); return; } =20 - PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId); + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->Hos= tBridgeDevId); ASSERT_RETURN_ERROR (PcdStatus); =20 // @@ -403,7 +403,7 @@ MiscInitialization ( PciOr8 (AcpiCtlReg, AcpiEnBit); } =20 - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // Set Root Complex Register Block BAR // @@ -421,18 +421,18 @@ MiscInitialization ( =20 VOID BootModeInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { EFI_STATUS Status; =20 if (PlatformCmosRead8 (0xF) =3D=3D 0xFE) { - mBootMode =3D BOOT_ON_S3_RESUME; + PlatformInfoHob->BootMode =3D BOOT_ON_S3_RESUME; } =20 PlatformCmosWrite8 (0xF, 0x00); =20 - Status =3D PeiServicesSetBootMode (mBootMode); + Status =3D PeiServicesSetBootMode (PlatformInfoHob->BootMode); ASSERT_EFI_ERROR (Status); =20 Status =3D PeiServicesInstallPpi (mPpiBootMode); @@ -473,7 +473,7 @@ S3Verification ( ) { #if defined (MDE_CPU_X64) - if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) { + if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) { DEBUG (( DEBUG_ERROR, "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", @@ -501,7 +501,7 @@ Q35BoardVerification ( VOID ) { - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + if (mPlatformInfoHob.HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { return; } =20 @@ -510,7 +510,7 @@ Q35BoardVerification ( "%a: no TSEG (SMRAM) on host bridge DID=3D0x%04x; " "only DID=3D0x%04x (Q35) is supported\n", __FUNCTION__, - mHostBridgeDevId, + mPlatformInfoHob.HostBridgeDevId, INTEL_Q35_MCH_DEVICE_ID )); ASSERT (FALSE); @@ -523,10 +523,11 @@ Q35BoardVerification ( **/ VOID MaxCpuCountInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { UINT16 BootCpuCount; + UINT32 MaxCpuCount; RETURN_STATUS PcdStatus; =20 // @@ -542,7 +543,7 @@ MaxCpuCountInitialization ( // first). // DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__)); - mMaxCpuCount =3D PcdGet32 (PcdCpuMaxLogicalProcessorNumber); + MaxCpuCount =3D PlatformInfoHob->DefaultMaxCpuNumber; } else { // // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs = up to @@ -553,7 +554,7 @@ MaxCpuCountInitialization ( UINTN CpuHpBase; UINT32 CmdData2; =20 - CpuHpBase =3D ((mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) ? + CpuHpBase =3D ((PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_= DEVICE_ID) ? ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE); =20 // @@ -605,7 +606,7 @@ MaxCpuCountInitialization ( "%a: modern CPU hotplug interface unavailable\n", __FUNCTION__ )); - mMaxCpuCount =3D BootCpuCount; + MaxCpuCount =3D BootCpuCount; } else { // // Grab the possible CPU count from the modern CPU hotplug interface. @@ -671,23 +672,26 @@ MaxCpuCountInitialization ( BootCpuCount =3D (UINT16)Present; } =20 - mMaxCpuCount =3D Possible; + MaxCpuCount =3D Possible; } } =20 DEBUG (( DEBUG_INFO, - "%a: BootCpuCount=3D%d mMaxCpuCount=3D%u\n", + "%a: BootCpuCount=3D%d MaxCpuCount=3D%u\n", __FUNCTION__, BootCpuCount, - mMaxCpuCount + MaxCpuCount )); - ASSERT (BootCpuCount <=3D mMaxCpuCount); + ASSERT (BootCpuCount <=3D MaxCpuCount); =20 PcdStatus =3D PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount); ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount); + PcdStatus =3D PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxCpuCount); ASSERT_RETURN_ERROR (PcdStatus); + + PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber =3D MaxCpuCount; + PlatformInfoHob->PcdCpuBootLogicalProcessorNumber =3D BootCpuCount; } =20 /** @@ -710,27 +714,30 @@ InitializePlatform ( =20 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); =20 + mPlatformInfoHob.SmmSmramRequire =3D FeaturePcdGet (PcdSmmSmramRequire); + mPlatformInfoHob.SevEsIsEnabled =3D MemEncryptSevEsIsEnabled (); + PlatformDebugDumpCmos (); =20 if (QemuFwCfgS3Enabled ()) { DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n")); - mS3Supported =3D TRUE; - Status =3D PcdSetBoolS (PcdAcpiS3Enable, TRUE); + mPlatformInfoHob.S3Supported =3D TRUE; + Status =3D PcdSetBoolS (PcdAcpiS3Enable, TRUE); ASSERT_EFI_ERROR (Status); } =20 S3Verification (); - BootModeInitialization (); - AddressWidthInitialization (); + BootModeInitialization (&mPlatformInfoHob); + AddressWidthInitialization (&mPlatformInfoHob); =20 // // Query Host Bridge DID // - mHostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID); + mPlatformInfoHob.HostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID); =20 - MaxCpuCountInitialization (); + MaxCpuCountInitialization (&mPlatformInfoHob); =20 - if (FeaturePcdGet (PcdSmmSmramRequire)) { + if (mPlatformInfoHob.SmmSmramRequire) { Q35BoardVerification (); Q35TsegMbytesInitialization (); Q35SmramAtDefaultSmbaseInitialization (); @@ -738,24 +745,24 @@ InitializePlatform ( =20 PublishPeiMemory (); =20 - QemuUc32BaseInitialization (); + QemuUc32BaseInitialization (&mPlatformInfoHob); =20 - InitializeRamRegions (); + InitializeRamRegions (&mPlatformInfoHob); =20 - if (mBootMode !=3D BOOT_ON_S3_RESUME) { - if (!FeaturePcdGet (PcdSmmSmramRequire)) { + if (mPlatformInfoHob.BootMode !=3D BOOT_ON_S3_RESUME) { + if (!mPlatformInfoHob.SmmSmramRequire) { ReserveEmuVariableNvStore (); } =20 PeiFvInitialization (); MemTypeInfoInitialization (); - MemMapInitialization (); + MemMapInitialization (&mPlatformInfoHob); NoexecDxeInitialization (); } =20 InstallClearCacheCallback (); AmdSevInitialize (); - MiscInitialization (); + MiscInitialization (&mPlatformInfoHob); InstallFeatureControlCallback (); =20 return EFI_SUCCESS; diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index f193ff736549..a5fa27c3794f 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -10,10 +10,11 @@ #define _PLATFORM_PEI_H_INCLUDED_ =20 #include +#include =20 VOID AddressWidthInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 VOID @@ -33,17 +34,37 @@ PublishPeiMemory ( =20 UINT32 GetSystemMemorySizeBelow4gb ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 VOID QemuUc32BaseInitialization ( - VOID + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 VOID InitializeRamRegions ( - VOID + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +VOID +MemMapInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +VOID +MiscInitialization ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +VOID +BootModeInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +VOID +MaxCpuCountInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 EFI_STATUS @@ -71,23 +92,9 @@ AmdSevInitialize ( VOID ); =20 -extern EFI_BOOT_MODE mBootMode; - VOID SevInitializeRam ( VOID ); =20 -extern BOOLEAN mS3Supported; - -extern UINT8 mPhysMemAddressWidth; - -extern UINT32 mMaxCpuCount; - -extern UINT16 mHostBridgeDevId; - -extern BOOLEAN mQ35SmramAtDefaultSmbase; - -extern UINT32 mQemuUc32Base; - #endif // _PLATFORM_PEI_H_INCLUDED_ --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87330): https://edk2.groups.io/g/devel/message/87330 Mute This Topic: https://groups.io/mt/89629675/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87331+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87331+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707005; cv=none; d=zohomail.com; s=zohoarc; b=UHTG+n8oe3pih7GCE/szd9nJbJUcDb82taKuW+BUB0ox+0Wx5vsph4d9TTd14gYkvI3N+LgTcxzcEMpOq6TuvG2aeyuRN1w7KxxZI8OIjbWbCbKzP/Q8iwzNytOdeYGL4Xft8lLt30GhzQr8L7fXgplYRl6JYLCSs8S4SGTJI/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707005; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=fZEv2BEjrgNs1MTVpKRZQQ7DBMjGjLAeJ+Qqsigrb14=; b=VQJMdjVDNPByp0Ws/tTphFGVZ10OkZUqzRg3frB1cqJ4A5r74UBG1CzewjR4UsoTalklCdxdcFif48zArY+pA1jNIdLLOwwIuauwUiq3miw9bvyF1YHtXl3WOrC3jJosEz1HEtwRBacD0d/wpHgkzsR5JWUJQ5NrGyf8qu4mEr4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87331+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707005886754.8432999968517; Mon, 7 Mar 2022 18:36:45 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id jiwfYY1788612xYWHEooMIbB; Mon, 07 Mar 2022 18:36:45 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:45 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801022" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801022" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:44 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432649" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:40 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 04/14] OvmfPkg/PlatformPei: Refactor MiscInitialization Date: Tue, 8 Mar 2022 10:36:05 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: Qw2d377pw2iWPKNuRjlXjLWAx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707005; bh=mJBZRB4kH7FVrkP+ubt0kmwp3lr4NmxbBX3pv1lKTvY=; h=Cc:Date:From:Reply-To:Subject:To; b=c2Su84/ol7nWCfSP/Ag0EUfEL111idckPckYsFCCDegC3JK9Hcy9qcew/6rTDd4suxo F3BTkS5ymNDpfs0gdWeIDilDkPWzeJMqJfwBPv82xROQmJGAN331GaOINctFjerRd3y/I SvTg10iCJA+8tHaAFf13Ko7mgtpgusGytzY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707008108100007 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 In MiscInitialization Microvm looks a little weird. Other platforms call PcdSet16S to set the PcdOvmfHostBridgePciDevId with the value same as PlatformInfoHob->HostBridgeDevId. But Microvm doesn't follow this way. In switch-case 0xffff is Microvm, but set with MICROVM_PSEUDO_DEVICE_ID. So we have to add a new function ( MiscInitializationForMicrovm ) for Microvm and delete the code in MiscInitialization. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/Platform.c | 46 ++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 80eb4cc9adcd..af9e72cd7a98 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -304,6 +304,36 @@ MicrovmInitialization ( *FdtHobData =3D (UINTN)NewBase; } =20 +VOID +MiscInitializationForMicrovm ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + ASSERT (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff); + + DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); + // + // Disable A20 Mask + // + IoOr8 (0x92, BIT1); + + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16); + + MicrovmInitialization (); + PcdStatus =3D PcdSet16S ( + PcdOvmfHostBridgePciDevId, + MICROVM_PSEUDO_DEVICE_ID + ); + ASSERT_RETURN_ERROR (PcdStatus); +} + VOID MiscInitialization ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob @@ -349,15 +379,6 @@ MiscInitialization ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; - case 0xffff: /* microvm */ - DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); - MicrovmInitialization (); - PcdStatus =3D PcdSet16S ( - PcdOvmfHostBridgePciDevId, - MICROVM_PSEUDO_DEVICE_ID - ); - ASSERT_RETURN_ERROR (PcdStatus); - return; case CLOUDHV_DEVICE_ID: DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION= __)); PcdStatus =3D PcdSet16S ( @@ -762,7 +783,12 @@ InitializePlatform ( =20 InstallClearCacheCallback (); AmdSevInitialize (); - MiscInitialization (&mPlatformInfoHob); + if (mPlatformInfoHob.HostBridgeDevId =3D=3D 0xffff) { + MiscInitializationForMicrovm (&mPlatformInfoHob); + } else { + MiscInitialization (&mPlatformInfoHob); + } + InstallFeatureControlCallback (); =20 return EFI_SUCCESS; --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87331): https://edk2.groups.io/g/devel/message/87331 Mute This Topic: https://groups.io/mt/89629676/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87332+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87332+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707009; cv=none; d=zohomail.com; s=zohoarc; b=Y/lmb4SWvVI9DvBUSdhNB4sItPkIKc4n07CpSpP8ihM7rT2Qz6ASZg/5Wl8hUV7zbS2cly61wEm4asruBiOumD/9b7XQ+hZ9rQHOTMST6Amuj7ss2Tc2QdkUWWVv+QLK7RZZRZRG1B4lttnXtqOaR6InDMXuKFc10WIRWp/RQkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707009; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=che4v50+oF7sCKkUhRlsxdm1fbrCHidjv7kWyl7J6R8=; b=hPawh8Q/d2jBUawvGXNP1evgZONzrvN4OHDLxfIRhvH+BgltltH+zbXjgsgB9DD0iMYm+eJNjJ9gJhBFYj/LBRst2m7ogZQ17/MAXyG5rhvuvNR9G1Vwr6uuMKerihFb3wCetNXNatXX9CFu5WbsIjXPtfjjM8+9QKCbdjD46mc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87332+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707009648829.7966742898172; Mon, 7 Mar 2022 18:36:49 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id tiO7YY1788612xOBxR2VwJ3s; Mon, 07 Mar 2022 18:36:49 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:48 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801056" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801056" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:47 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432710" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:44 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 05/14] OvmfPkg/PlatformPei: Refactor MiscInitialization for CloudHV Date: Tue, 8 Mar 2022 10:36:06 +0800 Message-Id: <3e9adaab701ee84a311d8ac712e96702212add48.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: i3hgvVW88oh1vwWyiqT4hCIqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707009; bh=Yju7scdwPUfHj5rpoSb7zcqh2A0EezHwWrCSPIAiidg=; h=Cc:Date:From:Reply-To:Subject:To; b=N1s5mRQ8SPLzsEfkA70jDdUfbdS4HQgd5+8/jPAunoCIiczZMkADSd3BzjvcKtExT5E vhVuVnAUvB69Z2oL8c0sIyBFj6DTTUxFUdBnaKStiL/QWm7T2EZdN4oR2siBLGB3Qn1h7 1ktIdLKridoKxac2aBBAWbEh20/ooTQLrFg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707012187100011 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 Refactor MiscInitialization for CloudHV to set PCD as other platforms do. Because in the following patch we will split the functions which set PCDs into two, one for PlatformInitLib, one for PlatformPei. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/Platform.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index af9e72cd7a98..3e0c56db57ed 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -380,13 +380,7 @@ MiscInitialization ( AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; case CLOUDHV_DEVICE_ID: - DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION= __)); - PcdStatus =3D PcdSet16S ( - PcdOvmfHostBridgePciDevId, - CLOUDHV_DEVICE_ID - ); - ASSERT_RETURN_ERROR (PcdStatus); - return; + break; default: DEBUG (( DEBUG_ERROR, @@ -401,6 +395,11 @@ MiscInitialization ( PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->Hos= tBridgeDevId); ASSERT_RETURN_ERROR (PcdStatus); =20 + if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__)); + return; + } + // // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has // been configured and skip the setup here. This matches the logic in --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87332): https://edk2.groups.io/g/devel/message/87332 Mute This Topic: https://groups.io/mt/89629677/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87333+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87333+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707012; cv=none; d=zohomail.com; s=zohoarc; b=MyxAoDnhbpemMp9dymU9Jlx6caavoW7fYqpF2g0hTDVzdy5ZuHo8AwLFk/2GEzJjfZNcEr0hMso3JH5d3MOD2Dn2w6CAqQF2uu/vkXffKffl7KVdtUXVBgPbGqcc6KKpYawT47kdV1HCTNNAPzoof5ml3eNFwcx71P/1v2Z5YQ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=nuztoX8rrn2Lht1KF4AZPXldjfLKzXVugUoWgcMzvjE=; b=IK7B/JNYWcFn0Tflzm1BZMax9hUfAhTYUzBL+5hWr5TZB+KKmi/gtlEfxN+lPp6LMM9At2U0SatfC0mHRD+Ma3daa0uySVHbRMoS2ylVyeoRA2f76zTtE+fZSZUQpA0ez6CEUmjwTuFoj3Yh8GsQezfePvfT3oteRX0ik4JaXnk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87333+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707012638890.8877939754888; Mon, 7 Mar 2022 18:36:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id mocbYY1788612xjHKowCJKMH; Mon, 07 Mar 2022 18:36:52 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:51 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801098" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801098" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:51 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432754" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:48 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 06/14] OvmfPkg/PlatformPei: Refactor AddressWidthInitialization Date: Tue, 8 Mar 2022 10:36:07 +0800 Message-Id: <9a4eb7161f638c320b4945909385844ce9dc50f7.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: IGpzc2oDH9pXGEqYq1ugHGLEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707012; bh=6vrlbwjssa1912unS+pDwyy/ytLfGpF7ZZRJAPyM8cg=; h=Cc:Date:From:Reply-To:Subject:To; b=pCKU1GtJIsup1kurh9vpRwHaLeB8GIAq2OgVlk8NFMYqHxhOj1+FT7oROvRRkfywAWl D0kBl/VXUJH/DQeoNff7KL1L4y6r3yMDrtcejn8l+n/zBKLnI4cV9JznvtOLII8pv7Ocy S636UrY8EXIkZboqGFrswsZ1bV8ZYQ2EPIM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707014308100001 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 From this patch we start to restruct the functions which set PCDs into two, one for PlatformInitLib, one for PlatformPei. AddressWidthInitialization is the first one. It is splitted into two: - PlatformAddressWidthInitialization is for PlatformInitLib - AddressWidthInitialization is for PlatformPei. It calls PlatformAddressWidthInitialization then set PCDs. Below functions are also refined for PlatformInitLib: - PlatformScanOrAdd64BitE820Ram - PlatformGetSystemMemorySizeAbove4gb - PlatformGetFirstNonAddress All the SetPcd codes are removed from above functions. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/MemDetect.c | 111 ++++++++++++++++++++------------ OvmfPkg/PlatformPei/Platform.c | 6 +- 2 files changed, 75 insertions(+), 42 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 981a9ff28685..56011143759c 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -191,7 +191,7 @@ QemuUc32BaseInitialization ( Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce descriptor HOBs for RAM entries that start at or above 4GB. =20 - @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ra= m() + @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64B= itE820Ram() produces memory resource descriptor HOBs for RAM entries that start at or above 4GB. =20 @@ -212,7 +212,7 @@ QemuUc32BaseInitialization ( **/ STATIC EFI_STATUS -ScanOrAdd64BitE820Ram ( +PlatformScanOrAdd64BitE820Ram ( IN BOOLEAN AddHighHob, OUT UINT64 *LowMemory OPTIONAL, OUT UINT64 *MaxAddress OPTIONAL @@ -387,7 +387,7 @@ GetSystemMemorySizeBelow4gb ( return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); } =20 - Status =3D ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); + Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { return (UINT32)LowerMemorySize; } @@ -409,7 +409,7 @@ GetSystemMemorySizeBelow4gb ( =20 STATIC UINT64 -GetSystemMemorySizeAbove4gb ( +PlatformGetSystemMemorySizeAbove4gb ( ) { UINT32 Size; @@ -436,7 +436,7 @@ GetSystemMemorySizeAbove4gb ( **/ STATIC UINT64 -GetFirstNonAddress ( +PlatformGetFirstNonAddress ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -446,7 +446,6 @@ GetFirstNonAddress ( FIRMWARE_CONFIG_ITEM FwCfgItem; UINTN FwCfgSize; UINT64 HotPlugMemoryEnd; - RETURN_STATUS PcdStatus; =20 // // set FirstNonAddress to suppress incorrect compiler/analyzer warnings @@ -460,9 +459,9 @@ GetFirstNonAddress ( // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich // can only express a size smaller than 1TB), and add it to 4GB. // - Status =3D ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); + Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); if (EFI_ERROR (Status)) { - FirstNonAddress =3D BASE_4GB + GetSystemMemorySizeAbove4gb (); + FirstNonAddress =3D BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); } =20 // @@ -477,12 +476,6 @@ GetFirstNonAddress ( =20 #endif =20 - // - // Otherwise, in order to calculate the highest address plus one, we must - // consider the 64-bit PCI host aperture too. Fetch the default size. - // - PlatformInfoHob->PcdPciMmio64Size =3D PcdGet64 (PcdPciMmio64Size); - // // See if the user specified the number of megabytes for the 64-bit PCI = host // aperture. Accept an aperture size up to 16TB. @@ -524,8 +517,6 @@ GetFirstNonAddress ( "%a: disabling 64-bit PCI host aperture\n", __FUNCTION__ )); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0); - ASSERT_RETURN_ERROR (PcdStatus); } =20 // @@ -576,26 +567,6 @@ GetFirstNonAddress ( // PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size)); =20 - if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { - // - // The core PciHostBridgeDxe driver will automatically add this range = to - // the GCD memory space map through our PciHostBridgeLib instance; her= e we - // only need to set the PCDs. - // - PcdStatus =3D PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio= 64Base); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio= 64Size); - ASSERT_RETURN_ERROR (PcdStatus); - - DEBUG (( - DEBUG_INFO, - "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", - __FUNCTION__, - PlatformInfoHob->PcdPciMmio64Base, - PlatformInfoHob->PcdPciMmio64Size - )); - } - // // The useful address space ends with the 64-bit PCI host aperture. // @@ -607,7 +578,8 @@ GetFirstNonAddress ( Initialize the mPhysMemAddressWidth variable, based on guest RAM size. **/ VOID -AddressWidthInitialization ( +EFIAPI +PlatformAddressWidthInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -620,7 +592,7 @@ AddressWidthInitialization ( // The DXL IPL keys off of the physical address bits advertized in the C= PU // HOB. To conserve memory, we calculate the minimum address width here. // - FirstNonAddress =3D GetFirstNonAddress (PlatformInfoHob); + FirstNonAddress =3D PlatformGetFirstNonAddress (PlatformInfoHob); PhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); =20 // @@ -647,6 +619,65 @@ AddressWidthInitialization ( PlatformInfoHob->PhysMemAddressWidth =3D PhysMemAddressWidth; } =20 +/** + Initialize the mPhysMemAddressWidth variable, based on guest RAM size. +**/ +VOID +AddressWidthInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PlatformAddressWidthInitialization (PlatformInfoHob); + + // + // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO + // resources to 32-bit anyway. See DegradeResource() in + // "PciResourceSupport.c". + // + #ifdef MDE_CPU_IA32 + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { + return; + } + + #endif + + if (PlatformInfoHob->PcdPciMmio64Size =3D=3D 0) { + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + DEBUG (( + DEBUG_INFO, + "%a: disabling 64-bit PCI host aperture\n", + __FUNCTION__ + )); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0); + ASSERT_RETURN_ERROR (PcdStatus); + } + + return; + } + + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + // + // The core PciHostBridgeDxe driver will automatically add this range = to + // the GCD memory space map through our PciHostBridgeLib instance; her= e we + // only need to set the PCDs. + // + PcdStatus =3D PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio= 64Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio= 64Size); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG (( + DEBUG_INFO, + "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", + __FUNCTION__, + PlatformInfoHob->PcdPciMmio64Base, + PlatformInfoHob->PcdPciMmio64Size + )); + } +} + /** Calculate the cap for the permanent PEI memory. **/ @@ -904,9 +935,9 @@ QemuInitializeRam ( // entries. Otherwise, create a single memory HOB with the flat >=3D4GB // memory size read from the CMOS. // - Status =3D ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); + Status =3D PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL); if (EFI_ERROR (Status)) { - UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); + UpperMemorySize =3D PlatformGetSystemMemorySizeAbove4gb (); if (UpperMemorySize !=3D 0) { PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3e0c56db57ed..7d370c9b8fa8 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -734,8 +734,10 @@ InitializePlatform ( =20 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); =20 - mPlatformInfoHob.SmmSmramRequire =3D FeaturePcdGet (PcdSmmSmramRequire); - mPlatformInfoHob.SevEsIsEnabled =3D MemEncryptSevEsIsEnabled (); + mPlatformInfoHob.SmmSmramRequire =3D FeaturePcdGet (PcdSmmSmramRequi= re); + mPlatformInfoHob.SevEsIsEnabled =3D MemEncryptSevEsIsEnabled (); + mPlatformInfoHob.PcdPciMmio64Size =3D PcdGet64 (PcdPciMmio64Size); + mPlatformInfoHob.DefaultMaxCpuNumber =3D PcdGet32 (PcdCpuMaxLogicalProce= ssorNumber); =20 PlatformDebugDumpCmos (); =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87333): https://edk2.groups.io/g/devel/message/87333 Mute This Topic: https://groups.io/mt/89629679/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87334+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87334+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707015986523.356375330539; Mon, 7 Mar 2022 18:36:55 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id xYuzYY1788612xNCOM3CDoSx; Mon, 07 Mar 2022 18:36:56 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:56 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801138" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801138" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:55 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432791" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:51 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 07/14] OvmfPkg/PlatformPei: Refactor MaxCpuCountInitialization Date: Tue, 8 Mar 2022 10:36:08 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: WQrtY6zmsGWB3wmOo7F7ZO7hx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707016; bh=9BHv3A9kTvQds/F0fh6ANPjXk9lOhxIiPhjgGu/5log=; h=Cc:Date:From:Reply-To:Subject:To; b=HjWjDeTeYs163AG46bZUqMr6afyx+aIHqB18667Vta1dJ7GPMtNYHWO4i8sFYojj8LG iodNV/w/XJ5DL/zZ8LQ3ph47iS4aUJRoCRe9sgHX5lKXOY5oVSPDmKmPBOmT8ItMnDHMO s74O+rl9Ys08PQWWZpx4oeq8RZKtn8ZI6Vc= X-ZohoMail-DKIM: fail (Signature date is -1 seconds in the future.) X-ZM-MESSAGEID: 1646707018181100001 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 MaxCpuCountInitialization is splitted into two: - PlatformMaxCpuCountInitialization is for PlatformInitLib - MaxCpuCountInitialization is for PlatformPei. It calls PlatformMaxCpuCountInitialization then sets PCDs. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/Platform.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 7d370c9b8fa8..c184fdb57ee0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -542,13 +542,12 @@ Q35BoardVerification ( them to UefiCpuPkg modules. Set the mMaxCpuCount variable. **/ VOID -MaxCpuCountInitialization ( +PlatformMaxCpuCountInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT16 BootCpuCount; - UINT32 MaxCpuCount; - RETURN_STATUS PcdStatus; + UINT16 BootCpuCount; + UINT32 MaxCpuCount; =20 // // Try to fetch the boot CPU count. @@ -705,15 +704,29 @@ MaxCpuCountInitialization ( )); ASSERT (BootCpuCount <=3D MaxCpuCount); =20 - PcdStatus =3D PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxCpuCount); - ASSERT_RETURN_ERROR (PcdStatus); - PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber =3D MaxCpuCount; PlatformInfoHob->PcdCpuBootLogicalProcessorNumber =3D BootCpuCount; } =20 +/** + Fetch the boot CPU count and the possible CPU count from QEMU, and expose + them to UefiCpuPkg modules. Set the mMaxCpuCount variable. +**/ +VOID +MaxCpuCountInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PlatformMaxCpuCountInitialization (PlatformInfoHob); + + PcdStatus =3D PcdSet32S (PcdCpuBootLogicalProcessorNumber, PlatformInfoH= ob->PcdCpuBootLogicalProcessorNumber); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet32S (PcdCpuMaxLogicalProcessorNumber, PlatformInfoHo= b->PcdCpuMaxLogicalProcessorNumber); + ASSERT_RETURN_ERROR (PcdStatus); +} + /** Perform Platform PEI initialization. =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87334): https://edk2.groups.io/g/devel/message/87334 Mute This Topic: https://groups.io/mt/89629681/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87335+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87335+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707020; cv=none; d=zohomail.com; s=zohoarc; b=DG25WNvr6SULdpHKhFKaMT+Llrr0R88/Ej12fzF6ZAim4nTj6tkdw6QaGsaW2VawGUF9fIPDTl1roaVnDMDnKWFpOoKghal/ueiL4Gdklu20Zl9w5Jz0GylsRP951hEinEpc842PFaXtAfzwmQIHvUwOvfbVBg8kHVMP7xeRgkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707020; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8wAWkyXxgjRfKjrJKmvnCwTWpNba79dVciM4x7k7zYE=; b=Yp7wehDEl/MZNiMsbD6MzTMsFxFind+CyWAVbqyH19nqj0U/G+qyBr64eJhvkPcz8hTN5Lq3amn9Q/vJtckSm7RrTGJXXWgcugC+y25mVCaicBQkurv1FDES5ajwzdjR/aDvAqzuuqJpQXji0zv87cSxhMui6xgbjsOyeEZ3hAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87335+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707020469125.8115907381333; Mon, 7 Mar 2022 18:37:00 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zbsRYY1788612xT2X1oPwXvQ; Mon, 07 Mar 2022 18:36:59 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:36:59 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801170" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801170" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:58 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432809" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:55 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 08/14] OvmfPkg/PlatformPei: Refactor QemuUc32BaseInitialization Date: Tue, 8 Mar 2022 10:36:09 +0800 Message-Id: <6c882ad3669689b4638624a3254eeaf922b22f57.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: v63yMb09j5MOKC7mT2GQfuemx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707019; bh=k1h8tcSce4WnysqyY2KkDSuQktvtpAkav3YwVA1jEtc=; h=Cc:Date:From:Reply-To:Subject:To; b=dhvf75vJBaDDlrqoraiS9wankJWayqDCcOF6SobPJCkJ8WtYszaYS62pWcNOk8Z7ONm OE0g29CeHo1me3a0DfacvRQhuT/4eIoJ2acGF/p1O/mv5zv7zmD7xXuC4biUo/p4arae+ zUPEdeSvFKePI0VoQPx0JhsZqHJbS0AxS1U= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707022212100001 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 Rename QemuUc32BaseInitialization to PlatformQemuUc32BaseInitialization. This function is for PlatformInitLib. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/MemDetect.c | 3 ++- OvmfPkg/PlatformPei/Platform.c | 2 +- OvmfPkg/PlatformPei/Platform.h | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 56011143759c..33c39228e448 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -127,7 +127,8 @@ Q35SmramAtDefaultSmbaseInitialization ( } =20 VOID -QemuUc32BaseInitialization ( +EFIAPI +PlatformQemuUc32BaseInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index c184fdb57ee0..0bf92e117bee 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -780,7 +780,7 @@ InitializePlatform ( =20 PublishPeiMemory (); =20 - QemuUc32BaseInitialization (&mPlatformInfoHob); + PlatformQemuUc32BaseInitialization (&mPlatformInfoHob); =20 InitializeRamRegions (&mPlatformInfoHob); =20 diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index a5fa27c3794f..b5e831aa68e2 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -38,7 +38,8 @@ GetSystemMemorySizeBelow4gb ( ); =20 VOID -QemuUc32BaseInitialization ( +EFIAPI +PlatformQemuUc32BaseInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87335): https://edk2.groups.io/g/devel/message/87335 Mute This Topic: https://groups.io/mt/89629682/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87336+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87336+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707023; cv=none; d=zohomail.com; s=zohoarc; b=aB+NirrqkMJi2wwpSiuOk6s/7ohkgluVKeLNnmb2EyZsY4qIRGPJjYNqjJY3cXqB9faQARa/BA7ZLMWbl9AD27cneF8M6hMaRm9wnzli/4u5o2//0c9Hgk2FeKacVFsJ1rHMxRVXkCgOjcvrp+LlWehN8ixpzFwyPfmv2prQngg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707023; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pOBv5c2igX7ZXcAzR/RGiJ6EU7AggVYQjl0dbJa3pSw=; b=XD5CPWUhW18ftzsNCNOlRY9XIIjh5QkIlQc+ZWoMYntT8pCCAsPn+IKGYalvvo3Es66uX30vSAJPLuY8JcQ/PA8F00gzpr53FKhnIXCsdIexBzFtm6UY7RFKjWs+m6Pv0GWKWaLDZz1e3yEez577cR19alDDew5gQbygrXWh9JY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87336+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707023271354.9306998571267; Mon, 7 Mar 2022 18:37:03 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id H2PBYY1788612x9LixmjsMfg; Mon, 07 Mar 2022 18:37:03 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:37:02 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801201" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801201" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:02 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432831" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:36:59 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 09/14] OvmfPkg/PlatformPei: Refactor InitializeRamRegions Date: Tue, 8 Mar 2022 10:36:10 +0800 Message-Id: <69b1b726e06bb8104a8c69ae2f0b73e6c3c4589a.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: k7UQwzmCBK3QfDST1hfq1ubOx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707023; bh=6NdO4VYavQNTJYagHlufPDt2v64vywYxOxi3RvZbBEw=; h=Cc:Date:From:Reply-To:Subject:To; b=pSDWAqisGDRKHos+IHPu0D3LdWj8Il5J62WtIr1M1yxoZRnXjPn9NIgSf/l17Vi8xGV 49FQsAS3CfMfGc/pn4suu7rsxzElB3mgTQNHFIY1qoP4HbaxqjnF+eYAw0eN3HpIieubw r7VJGt54vKprToXBYDCvG5N0HHSPaiJ0oc8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707024231100007 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 InitializeRamRegions is refactored into 3 calls: - PlatformQemuInitializeRam - SevInitializeRam - PlatformQemuInitializeRamForS3 SevInitializeRam is not in PlatformInitLib. Because in the first stage PlatformInitLib only support the basic platform featues. PlatformQemuInitializeRamForS3 wraps the code which was previously in InitializeRamRegions (many code in 2 if-checks). Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/MemDetect.c | 40 ++++++++++++++++++++------------- OvmfPkg/PlatformPei/Platform.c | 2 +- OvmfPkg/PlatformPei/Platform.h | 3 ++- 3 files changed, 28 insertions(+), 17 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 33c39228e448..5709766f86f3 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -163,7 +163,7 @@ PlatformQemuUc32BaseInitialization ( // variable MTRR suffices by truncating the size to a whole power of two, // while keeping the end affixed to 4GB. This will round the base up. // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (PlatformInfoH= ob); + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (Platf= ormInfoHob); PlatformInfoHob->Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - Lower= MemorySize)); PlatformInfoHob->Uc32Base =3D (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32S= ize); // @@ -374,7 +374,8 @@ GetHighestSystemMemoryAddressFromPvhMemmap ( } =20 UINT32 -GetSystemMemorySizeBelow4gb ( +EFIAPI +PlatformGetSystemMemorySizeBelow4gb ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -763,7 +764,7 @@ PublishPeiMemory ( UINT32 S3AcpiReservedMemoryBase; UINT32 S3AcpiReservedMemorySize; =20 - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (&mPlatformInfoHob); + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (&mPlatformInfoH= ob); if (mPlatformInfoHob.SmmSmramRequire) { // // TSEG is chipped from the end of low RAM @@ -873,7 +874,7 @@ QemuInitializeRamBelow1gb ( **/ STATIC VOID -QemuInitializeRam ( +PlatformQemuInitializeRam ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -887,7 +888,7 @@ QemuInitializeRam ( // // Determine total memory size available // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (PlatformInfoHob); + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob= ); =20 if (PlatformInfoHob->BootMode =3D=3D BOOT_ON_S3_RESUME) { // @@ -997,19 +998,12 @@ QemuInitializeRam ( } } =20 -/** - Publish system RAM and reserve memory regions - -**/ +STATIC VOID -InitializeRamRegions ( +PlatformQemuInitializeRamForS3 ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - QemuInitializeRam (PlatformInfoHob); - - SevInitializeRam (); - if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode !=3D BOOT= _ON_S3_RESUME)) { // // This is the memory range that will be used for PEI on S3 resume @@ -1115,7 +1109,7 @@ InitializeRamRegions ( // TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( - GetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, TsegSize, EfiReservedMemoryType ); @@ -1154,3 +1148,19 @@ InitializeRamRegions ( #endif } } + +/** + Publish system RAM and reserve memory regions + +**/ +VOID +InitializeRamRegions ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + PlatformQemuInitializeRam (PlatformInfoHob); + + SevInitializeRam (); + + PlatformQemuInitializeRamForS3 (PlatformInfoHob); +} diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 0bf92e117bee..3e02ba2c9fc4 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -79,7 +79,7 @@ MemMapInitialization ( return; } =20 - TopOfLowRam =3D GetSystemMemorySizeBelow4gb (PlatformInfoHob); + TopOfLowRam =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); PciExBarBase =3D 0; if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index b5e831aa68e2..494836c3efe4 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -33,7 +33,8 @@ PublishPeiMemory ( ); =20 UINT32 -GetSystemMemorySizeBelow4gb ( +EFIAPI +PlatformGetSystemMemorySizeBelow4gb ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87336): https://edk2.groups.io/g/devel/message/87336 Mute This Topic: https://groups.io/mt/89629685/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87337+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87337+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707026; cv=none; d=zohomail.com; s=zohoarc; b=ced7TjiTlOhwGX2pRiuSj5t1vH/YRRrWnbNba7VpY5YeSObZOqO+nYcDdDxpDTobapP5QhRM9wRk7Bnfp08KctkK5wh7vNQXtsqnCxC2PrkPxAS2Ys1Uc04W9aQTAafIEY/NLGcTI1assyrj+tfGsOWiIQvC1t+B/+peVllBx6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707026; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7dM1NaVuRQWoTJ696MaKM7YCEOK9cii3pyZRQvyTofE=; b=N2CEgpuV+K50r4fVA3GLo6wr5DEXqtZc9ArUbSRb/3DI8zbi1k/yXdbNjt9vKeh9iAwZql9QjUHyfNZiYW+g8BI/1a1L2CVoE6JZN1QIccop/Hlnc6hXiS8ZgJ97FyJ8+QsSyqvn0E9aKgWqeXmJy9gehpT9gZtZbVuyJ7xbt0k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87337+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707026282406.1326151032072; Mon, 7 Mar 2022 18:37:06 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ePavYY1788612xN0A7xDvK9D; Mon, 07 Mar 2022 18:37:06 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:37:05 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801228" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801228" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:05 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432875" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:02 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 10/14] OvmfPkg/PlatformPei: Refactor MemMapInitialization Date: Tue, 8 Mar 2022 10:36:11 +0800 Message-Id: <44b3cb73e66e502186ffb6df9b7a0018d7f6c6d8.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: MNSLjWglFAoOHYUTE7TkPrX1x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707026; bh=I+3QTXLHAtqxsMP9lnCJ0WzvkhItmGQZnE3NNeyi/ug=; h=Cc:Date:From:Reply-To:Subject:To; b=GHYjRZKtgVtnSLdQUo8/2gc4hmD2/x7JspvbC9Twrb44WKcs/DTYossGZw3wcCebV+2 8WCk0VNtr5+6CTZ7fdYSUygXoEELxgK6iYncZW0cADfVKqRS0TXrXcMJ0vjMuIUPEqmma 4qJ2swPZJBVUWQBdUC0F488KO+3GX64z56Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707028462100002 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 MemMapInitialization is split into 2 functions: - PlatformMemMapInitialization is for PlatformInfoLib - MemMapInitialization calls PlatformMemMapInitialization and then sets PCDs. It is for PlatformPei. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/Platform.c | 35 +++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3e02ba2c9fc4..01fca33e7119 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -52,7 +52,8 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { }; =20 VOID -MemMapInitialization ( +EFIAPI +PlatformMemMapInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -110,10 +111,6 @@ MemMapInitialization ( // PciSize =3D 0xFC000000 - PciBase; PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); - PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize); - ASSERT_RETURN_ERROR (PcdStatus); =20 PlatformInfoHob->PcdPciMmio32Base =3D PciBase; PlatformInfoHob->PcdPciMmio32Size =3D PciSize; @@ -173,15 +170,35 @@ MemMapInitialization ( PciIoBase, PciIoSize ); - PcdStatus =3D PcdSet64S (PcdPciIoBase, PciIoBase); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciIoSize, PciIoSize); - ASSERT_RETURN_ERROR (PcdStatus); =20 PlatformInfoHob->PcdPciIoBase =3D PciIoBase; PlatformInfoHob->PcdPciIoSize =3D PciIoSize; } =20 +VOID +MemMapInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PlatformMemMapInitialization (PlatformInfoHob); + + if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { + return; + } + + PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PlatformInfoHob->PcdPciMmio32= Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PlatformInfoHob->PcdPciMmio32= Size); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus =3D PcdSet64S (PcdPciIoBase, PlatformInfoHob->PcdPciIoBase); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdPciIoSize, PlatformInfoHob->PcdPciIoSize); + ASSERT_RETURN_ERROR (PcdStatus); +} + #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \ do { \ BOOLEAN Setting; \ --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87337): https://edk2.groups.io/g/devel/message/87337 Mute This Topic: https://groups.io/mt/89629686/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87338+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87338+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707029; cv=none; d=zohomail.com; s=zohoarc; b=Wo6lFXm5RTbFAsCiMoDDx9As+GX6WUbeYWFvLVQqN+3Q/Rs3EbGOQQ4qg7atvhdI9tyGesOj+ZLRHZQU3T126x94MnZTNGyyFSHMHg69mUetZuXD5z9Ay2lolIIdh+FG0wJ0YXSxzPO5OK+tttAV+maC2NNhk96ySCFqs3usBII= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707029; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cp51H2VgxkwCPY9DxNfAd00djb+R1/cn3LVCJx5QGSM=; b=DHPyS497CW4x8ZSc7K0QH5g4Va8C3mw8CIvAeQ5iaUb93mWNud2/KOkZYjVdAcOiBKTDIm9NPObHn746SPuL0nBPesdInpBAHLbdGnIgkjyplLc28scYEziT98cY4d1w06wY5zLDbkWyrT3oaaoo7bBryOQ0ukd+F5zgDqQT6CY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87338+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707029737157.6982475154498; Mon, 7 Mar 2022 18:37:09 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id CEuuYY1788612x23WM0Dg6Ox; Mon, 07 Mar 2022 18:37:09 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:37:08 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801247" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801247" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:08 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432891" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:05 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 11/14] OvmfPkg/PlatformPei: Refactor NoexecDxeInitialization Date: Tue, 8 Mar 2022 10:36:12 +0800 Message-Id: <1e10fcce6003b5e83563d7aacc8da987aceff1e8.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: NBDr08xW98qHm4xg5h96UFlTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707029; bh=5XatQ6L6L2mI+F3FFqDZXYPf5UsVTfyMz2qany12IFk=; h=Cc:Date:From:Reply-To:Subject:To; b=VSppwh4N1Fedt5YU3S/zRvp2fuV2GgOahpba5fqwVK9SHIAQooPR2Xk6jkLY4Uc18cj +89+Xg1DmPPcpE1F4tW8iR+3GhfifdKnNu4rmC5wIAyi+ztgksZXzqR47PRFXGJMWWGBs S3YAoqT4w9TgYvMa+fTCepTxgBsCF10T3Rk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707030276100006 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 NoexecDxeInitialization is split into 2 functions: - PlatformNoexecDxeInitialization is for PlatformInitLib - NoexecDxeInitialization calls PlatformNoexecDxeInitialization and then sets PCD. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/Platform.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 01fca33e7119..2d652b0dc127 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -59,7 +59,6 @@ PlatformMemMapInitialization ( { UINT64 PciIoBase; UINT64 PciIoSize; - RETURN_STATUS PcdStatus; UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; @@ -199,24 +198,33 @@ MemMapInitialization ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \ - do { \ - BOOLEAN Setting; \ - RETURN_STATUS PcdStatus; \ - \ - if (!RETURN_ERROR (QemuFwCfgParseBool ( \ - "opt/ovmf/" #TokenName, &Setting))) { \ - PcdStatus =3D PcdSetBoolS (TokenName, Setting); \ - ASSERT_RETURN_ERROR (PcdStatus); \ - } \ - } while (0) +/** + * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU + * + * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxFor= Stack". + * @return EFI_SUCCESS Successfully fetch the settings. + */ +EFI_STATUS +EFIAPI +PlatformNoexecDxeInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob= ->PcdSetNxForStack); +} =20 VOID NoexecDxeInitialization ( VOID ) { - UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack); + RETURN_STATUS Status; + + Status =3D PlatformNoexecDxeInitialization (&mPlatformInfoHob); + if (!RETURN_ERROR (Status)) { + Status =3D PcdSetBoolS (PcdSetNxForStack, mPlatformInfoHob.PcdSetNxFor= Stack); + ASSERT_RETURN_ERROR (Status); + } } =20 VOID --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87338): https://edk2.groups.io/g/devel/message/87338 Mute This Topic: https://groups.io/mt/89629688/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87339+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87339+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707038; cv=none; d=zohomail.com; s=zohoarc; b=f0E2GHlrFakefRDXQJQMHg5zoW4qyQhu2vU2ZZcpVV6hwP9edsqWsKtJmRnKy/K341/aXvNrN1/XvyQ7vyCi2k6L/4kGYE+BOs+ZuZ9w1IJG7XAC6Iqj0CKyhLe68qD3lxoTUEFSJ1Y6LkPXnB27hzVB6jszX+daXAC604lmNek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707038; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xG8H8lC+0ndN0CnCDDJqDWxWODrpsP+88Yr1wRGgCzA=; b=ROK2ZLyhY49XcBKfcNk84Esv2k4VuyHuDDXHhyUM0em7sT6s8v9P7BXYKOS+q+1G3xO8YuPjaCi6mWa8h4OZN4PCb+u2KXK+7mQLtJojSt6NgwY25vNsZnnBB99G63yrYCPnOeacV1B4MOeUhXM4F+PTRx31hZwhBH4wPjGvmwg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87339+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707038769287.3073455433273; Mon, 7 Mar 2022 18:37:18 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id xZDmYY1788612xAJd3l58g1y; Mon, 07 Mar 2022 18:37:18 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:37:13 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801254" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801254" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:11 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432913" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:08 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 12/14] OvmfPkg/PlatformPei: Refactor MiscInitialization Date: Tue, 8 Mar 2022 10:36:13 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: liX5s7xBZgSQOUoshjyLzxeGx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707038; bh=DWQGvzpwMLLBZzoAVc2grEYilbaFPJmq+A1Z4OE7ULk=; h=Cc:Date:From:Reply-To:Subject:To; b=olB21G8XvHlptVhdoLhKORb3eHiYuxNRLX4nsk6Tl8hepKqyKwmhJPFgklegWcaq+Nv JfcQ5xIrMKwZ5k8zga5sbJI9b98e4/iaKaupSHe0thGwmAzSwwYg/0S6rFwTpaMTT60Y2 f0EoHunhYdO2Ph0WymVwQEyRIdZI6GHcZNc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707040326100005 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 MiscInitialization is split into 2 functions: - PlatformMiscInitialization is for PlatformInitLib. - MiscInitialization calls PlatformMiscInitialization and then sets PCD. It is for PlatformPei. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/PlatformPei/Platform.c | 43 ++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 2d652b0dc127..a5ed2c0bcc99 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -57,12 +57,12 @@ PlatformMemMapInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINT64 PciIoBase; - UINT64 PciIoSize; - UINT32 TopOfLowRam; - UINT64 PciExBarBase; - UINT32 PciBase; - UINT32 PciSize; + UINT64 PciIoBase; + UINT64 PciIoSize; + UINT32 TopOfLowRam; + UINT64 PciExBarBase; + UINT32 PciBase; + UINT32 PciSize; =20 PciIoBase =3D 0xC000; PciIoSize =3D 0x4000; @@ -360,17 +360,16 @@ MiscInitializationForMicrovm ( } =20 VOID -MiscInitialization ( +PlatformMiscInitialization ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { - UINTN PmCmd; - UINTN Pmba; - UINT32 PmbaAndVal; - UINT32 PmbaOrVal; - UINTN AcpiCtlReg; - UINT8 AcpiEnBit; - RETURN_STATUS PcdStatus; + UINTN PmCmd; + UINTN Pmba; + UINT32 PmbaAndVal; + UINT32 PmbaOrVal; + UINTN AcpiCtlReg; + UINT8 AcpiEnBit; =20 // // Disable A20 Mask @@ -417,9 +416,6 @@ MiscInitialization ( return; } =20 - PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->Hos= tBridgeDevId); - ASSERT_RETURN_ERROR (PcdStatus); - if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__)); return; @@ -464,6 +460,19 @@ MiscInitialization ( } } =20 +VOID +MiscInitialization ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PlatformMiscInitialization (PlatformInfoHob); + + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, PlatformInfoHob->Hos= tBridgeDevId); + ASSERT_RETURN_ERROR (PcdStatus); +} + VOID BootModeInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87339): https://edk2.groups.io/g/devel/message/87339 Mute This Topic: https://groups.io/mt/89629689/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87340+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87340+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707036; cv=none; d=zohomail.com; s=zohoarc; b=DL4S8jAB+BeSm+Yw+hi22x4z66F5V29hitqXEWAa1kCzxQSBbPvqq7qE8b30+kGZ2ON/uGm+zpCDbF/Lp+mq/5KDOqyUjap/6/9uDifPxqQGLI+46He3fILNryfTsF/tE5jpEsZzQnGsoVIB6qGwP3EelW0hIVw8g7etPnm6U/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707036; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/iqxlUXF/bq+L3vMyDhxluBRYBmHMlYi9o07Ysw7WY0=; b=Mf0zSs2oy1J3pU5dh4oBNnL7vfv87weyE6YVhMWSsso/ycH6DQ7H8dg2QKBVh/C5mMZVrOpeKQl98VNJKfIuMc6mJKQDXFORSHB5E63wjS1UPT/bJJobHi+tRTOpX9hZEk26mUfHqTFxrQNBCJh1xhKZpFGB1Xoh+a+hLsR0AYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87340+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1646707036465392.21065224704057; Mon, 7 Mar 2022 18:37:16 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id UM1eYY1788612xNTYMCUJ5xi; Mon, 07 Mar 2022 18:37:16 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:37:15 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801290" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801290" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:14 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432944" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:11 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 13/14] OvmfPkg/PlatformInitLib: Create MemDetect.c Date: Tue, 8 Mar 2022 10:36:14 +0800 Message-Id: <0a299b38433c91b1ad9c156fcdac7776344ac5d6.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 0YVCYU9HFg7hw2IAX1a0tt9px1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707036; bh=HXjbqc2ZaOQrovr+R6ASZuCWGhCyR5+4/IvTrm0jcnk=; h=Cc:Date:From:Reply-To:Subject:To; b=fk3mEqTr7Bq2uBPdU200BNlHh3D6PL9DNoRNzRsH+j4VOzUNbrHi2p1e+vf5EPzWZv3 qOAjtOfLkAfVvLZyXKRnJ6rePiBdODDFF8PcUZaoxwzJkkHAoy2suFy+ojZRqKiDoOQLn LCJ7jv8OHnBqnpwV5agwVLvNiLp9MTlI1WM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707038473100002 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 Move functions in PlatformPei\MemDetect.c to PlatformInitLib\MemDetect.c. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/Include/Library/PlatformInitLib.h | 37 + OvmfPkg/Library/PlatformInitLib/MemDetect.c | 842 ++++++++++++++++++ .../PlatformInitLib/PlatformInitLib.inf | 49 + OvmfPkg/PlatformPei/MemDetect.c | 804 +---------------- OvmfPkg/PlatformPei/Platform.h | 12 - 5 files changed, 929 insertions(+), 815 deletions(-) create mode 100644 OvmfPkg/Library/PlatformInitLib/MemDetect.c diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index 9b99d4c1f514..2e4bb8140368 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -132,4 +132,41 @@ PlatformAddReservedMemoryBaseSizeHob ( IN BOOLEAN Cacheable ); =20 +VOID +EFIAPI +PlatformQemuUc32BaseInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +UINT32 +EFIAPI +PlatformGetSystemMemorySizeBelow4gb ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +/** + Initialize the mPhysMemAddressWidth variable, based on guest RAM size. +**/ +VOID +EFIAPI +PlatformAddressWidthInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +/** + Peform Memory Detection for QEMU / KVM + +**/ +VOID +EFIAPI +PlatformQemuInitializeRam ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +VOID +EFIAPI +PlatformQemuInitializeRamForS3 ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/= PlatformInitLib/MemDetect.c new file mode 100644 index 000000000000..fbd3073bd3d1 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -0,0 +1,842 @@ +/**@file + Memory Detection for Virtual Machines. + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include +#include +#include +#include +#include +#include +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +EFIAPI +PlatformQemuUc32BaseInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT32 LowerMemorySize; + + if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { + return; + } + + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, + // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for + // setting PcdPciExpressBaseAddress such that describing the + // [PcdPciExpressBaseAddress, 4GB) range require a very small number of + // variable MTRRs (preferably 1 or 2). + // + ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); + PlatformInfoHob->Uc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBase= Address); + return; + } + + if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + PlatformInfoHob->Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; + PlatformInfoHob->Uc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + return; + } + + ASSERT (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); + // + // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one + // variable MTRR suffices by truncating the size to a whole power of two, + // while keeping the end affixed to 4GB. This will round the base up. + // + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (Platf= ormInfoHob); + PlatformInfoHob->Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - Lower= MemorySize)); + PlatformInfoHob->Uc32Base =3D (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32S= ize); + // + // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. + // Therefore mQemuUc32Base is at least 2GB. + // + ASSERT (PlatformInfoHob->Uc32Base >=3D BASE_2GB); + + if (PlatformInfoHob->Uc32Base !=3D LowerMemorySize) { + DEBUG (( + DEBUG_VERBOSE, + "%a: rounded UC32 base from 0x%x up to 0x%x, for " + "an UC32 size of 0x%x\n", + __FUNCTION__, + LowerMemorySize, + PlatformInfoHob->Uc32Base, + PlatformInfoHob->Uc32Size + )); + } +} + +/** + Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start ou= tside + of the 32-bit address range. + + Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce + descriptor HOBs for RAM entries that start at or above 4GB. + + @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64B= itE820Ram() + produces memory resource descriptor HOBs for RAM + entries that start at or above 4GB. + + Otherwise, MaxAddress holds the highest exclusive + >=3D4GB RAM address on output. If QEMU's fw_cfg = E820 + RAM map contains no RAM entry that starts outsid= e of + the 32-bit address range, then MaxAddress is exa= ctly + 4GB on output. + + @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and proces= sed. + + @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a + whole multiple of sizeof(EFI_E820_ENTRY64). = No + RAM entry was processed. + + @return Error codes from QemuFwCfgFindFile(). No RAM + entry was processed. +**/ +STATIC +EFI_STATUS +PlatformScanOrAdd64BitE820Ram ( + IN BOOLEAN AddHighHob, + OUT UINT64 *LowMemory OPTIONAL, + OUT UINT64 *MaxAddress OPTIONAL + ) +{ + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + EFI_E820_ENTRY64 E820Entry; + UINTN Processed; + + Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); + if (EFI_ERROR (Status)) { + return Status; + } + + if (FwCfgSize % sizeof E820Entry !=3D 0) { + return EFI_PROTOCOL_ERROR; + } + + if (LowMemory !=3D NULL) { + *LowMemory =3D 0; + } + + if (MaxAddress !=3D NULL) { + *MaxAddress =3D BASE_4GB; + } + + QemuFwCfgSelectItem (FwCfgItem); + for (Processed =3D 0; Processed < FwCfgSize; Processed +=3D sizeof E820E= ntry) { + QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry); + DEBUG (( + DEBUG_VERBOSE, + "%a: Base=3D0x%Lx Length=3D0x%Lx Type=3D%u\n", + __FUNCTION__, + E820Entry.BaseAddr, + E820Entry.Length, + E820Entry.Type + )); + if (E820Entry.Type =3D=3D EfiAcpiAddressRangeMemory) { + if (AddHighHob && (E820Entry.BaseAddr >=3D BASE_4GB)) { + UINT64 Base; + UINT64 End; + + // + // Round up the start address, and round down the end address. + // + Base =3D ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE); + End =3D (E820Entry.BaseAddr + E820Entry.Length) & + ~(UINT64)EFI_PAGE_MASK; + if (Base < End) { + PlatformAddMemoryRangeHob (Base, End); + DEBUG (( + DEBUG_VERBOSE, + "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", + __FUNCTION__, + Base, + End + )); + } + } + + if (MaxAddress || LowMemory) { + UINT64 Candidate; + + Candidate =3D E820Entry.BaseAddr + E820Entry.Length; + if (MaxAddress && (Candidate > *MaxAddress)) { + *MaxAddress =3D Candidate; + DEBUG (( + DEBUG_VERBOSE, + "%a: MaxAddress=3D0x%Lx\n", + __FUNCTION__, + *MaxAddress + )); + } + + if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB= )) { + *LowMemory =3D Candidate; + DEBUG (( + DEBUG_VERBOSE, + "%a: LowMemory=3D0x%Lx\n", + __FUNCTION__, + *LowMemory + )); + } + } + } + } + + return EFI_SUCCESS; +} + +/** + Returns PVH memmap + + @param Entries Pointer to PVH memmap + @param Count Number of entries + + @return EFI_STATUS +**/ +EFI_STATUS +GetPvhMemmapEntries ( + struct hvm_memmap_table_entry **Entries, + UINT32 *Count + ) +{ + UINT32 *PVHResetVectorData; + struct hvm_start_info *pvh_start_info; + + PVHResetVectorData =3D (VOID *)(UINTN)PcdGet32 (PcdXenPvhStartOfDayStruc= tPtr); + if (PVHResetVectorData =3D=3D 0) { + return EFI_NOT_FOUND; + } + + pvh_start_info =3D (struct hvm_start_info *)(UINTN)PVHResetVectorData[0]; + + *Entries =3D (struct hvm_memmap_table_entry *)(UINTN)pvh_start_info->mem= map_paddr; + *Count =3D pvh_start_info->memmap_entries; + + return EFI_SUCCESS; +} + +STATIC +UINT64 +GetHighestSystemMemoryAddressFromPvhMemmap ( + BOOLEAN Below4gb + ) +{ + struct hvm_memmap_table_entry *Memmap; + UINT32 MemmapEntriesCount; + struct hvm_memmap_table_entry *Entry; + EFI_STATUS Status; + UINT32 Loop; + UINT64 HighestAddress; + UINT64 EntryEnd; + + HighestAddress =3D 0; + + Status =3D GetPvhMemmapEntries (&Memmap, &MemmapEntriesCount); + ASSERT_EFI_ERROR (Status); + + for (Loop =3D 0; Loop < MemmapEntriesCount; Loop++) { + Entry =3D Memmap + Loop; + EntryEnd =3D Entry->addr + Entry->size; + + if ((Entry->type =3D=3D XEN_HVM_MEMMAP_TYPE_RAM) && + (EntryEnd > HighestAddress)) + { + if (Below4gb && (EntryEnd <=3D BASE_4GB)) { + HighestAddress =3D EntryEnd; + } else if (!Below4gb && (EntryEnd >=3D BASE_4GB)) { + HighestAddress =3D EntryEnd; + } + } + } + + return HighestAddress; +} + +UINT32 +EFIAPI +PlatformGetSystemMemorySizeBelow4gb ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + EFI_STATUS Status; + UINT64 LowerMemorySize =3D 0; + UINT8 Cmos0x34; + UINT8 Cmos0x35; + + if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + // Get the information from PVH memmap + return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); + } + + Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); + if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { + return (UINT32)LowerMemorySize; + } + + // + // CMOS 0x34/0x35 specifies the system memory above 16 MB. + // * CMOS(0x35) is the high byte + // * CMOS(0x34) is the low byte + // * The size is specified in 64kb chunks + // * Since this is memory above 16MB, the 16MB must be added + // into the calculation to get the total memory size. + // + + Cmos0x34 =3D (UINT8)PlatformCmosRead8 (0x34); + Cmos0x35 =3D (UINT8)PlatformCmosRead8 (0x35); + + return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); +} + +STATIC +UINT64 +PlatformGetSystemMemorySizeAbove4gb ( + ) +{ + UINT32 Size; + UINTN CmosIndex; + + // + // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. + // * CMOS(0x5d) is the most significant size byte + // * CMOS(0x5c) is the middle size byte + // * CMOS(0x5b) is the least significant size byte + // * The size is specified in 64kb chunks + // + + Size =3D 0; + for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) { + Size =3D (UINT32)(Size << 8) + (UINT32)PlatformCmosRead8 (CmosIndex); + } + + return LShiftU64 (Size, 16); +} + +/** + Return the highest address that DXE could possibly use, plus one. +**/ +STATIC +UINT64 +PlatformGetFirstNonAddress ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 FirstNonAddress; + UINT32 FwCfgPciMmio64Mb; + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + UINT64 HotPlugMemoryEnd; + + // + // set FirstNonAddress to suppress incorrect compiler/analyzer warnings + // + FirstNonAddress =3D 0; + + // + // If QEMU presents an E820 map, then get the highest exclusive >=3D4GB = RAM + // address from it. This can express an address >=3D 4GB+1TB. + // + // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich + // can only express a size smaller than 1TB), and add it to 4GB. + // + Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); + if (EFI_ERROR (Status)) { + FirstNonAddress =3D BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); + } + + // + // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO + // resources to 32-bit anyway. See DegradeResource() in + // "PciResourceSupport.c". + // + #ifdef MDE_CPU_IA32 + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { + return FirstNonAddress; + } + + #endif + + // + // See if the user specified the number of megabytes for the 64-bit PCI = host + // aperture. Accept an aperture size up to 16TB. + // + // As signaled by the "X-" prefix, this knob is experimental, and might = go + // away at any time. + // + Status =3D QemuFwCfgParseUint32 ( + "opt/ovmf/X-PciMmio64Mb", + FALSE, + &FwCfgPciMmio64Mb + ); + switch (Status) { + case EFI_UNSUPPORTED: + case EFI_NOT_FOUND: + break; + case EFI_SUCCESS: + if (FwCfgPciMmio64Mb <=3D 0x1000000) { + PlatformInfoHob->PcdPciMmio64Size =3D LShiftU64 (FwCfgPciMmio64Mb,= 20); + break; + } + + // + // fall through + // + default: + DEBUG (( + DEBUG_WARN, + "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\= n", + __FUNCTION__ + )); + break; + } + + if (PlatformInfoHob->PcdPciMmio64Size =3D=3D 0) { + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + DEBUG (( + DEBUG_INFO, + "%a: disabling 64-bit PCI host aperture\n", + __FUNCTION__ + )); + } + + // + // There's nothing more to do; the amount of memory above 4GB fully + // determines the highest address plus one. The memory hotplug area (s= ee + // below) plays no role for the firmware in this case. + // + return FirstNonAddress; + } + + // + // The "etc/reserved-memory-end" fw_cfg file, when present, contains an + // absolute, exclusive end address for the memory hotplug area. This area + // starts right at the end of the memory above 4GB. The 64-bit PCI host + // aperture must be placed above it. + // + Status =3D QemuFwCfgFindFile ( + "etc/reserved-memory-end", + &FwCfgItem, + &FwCfgSize + ); + if (!EFI_ERROR (Status) && (FwCfgSize =3D=3D sizeof HotPlugMemoryEnd)) { + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd); + DEBUG (( + DEBUG_VERBOSE, + "%a: HotPlugMemoryEnd=3D0x%Lx\n", + __FUNCTION__, + HotPlugMemoryEnd + )); + + ASSERT (HotPlugMemoryEnd >=3D FirstNonAddress); + FirstNonAddress =3D HotPlugMemoryEnd; + } + + // + // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so + // that the host can map it with 1GB hugepages. Follow suit. + // + PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (FirstNonAddress, (UIN= T64)SIZE_1GB); + PlatformInfoHob->PcdPciMmio64Size =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Size, (UINT64)SIZE_1GB); + + // + // The 64-bit PCI host aperture should also be "naturally" aligned. The + // alignment is determined by rounding the size of the aperture down to = the + // next smaller or equal power of two. That is, align the aperture by the + // largest BAR size that can fit into it. + // + PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size)); + + // + // The useful address space ends with the 64-bit PCI host aperture. + // + FirstNonAddress =3D PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob-= >PcdPciMmio64Size; + return FirstNonAddress; +} + +/** + Initialize the mPhysMemAddressWidth variable, based on guest RAM size. +**/ +VOID +EFIAPI +PlatformAddressWidthInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 FirstNonAddress; + UINT8 PhysMemAddressWidth; + + // + // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts + // are dominated by the identity-mapping page tables built by the DXE IP= L. + // The DXL IPL keys off of the physical address bits advertized in the C= PU + // HOB. To conserve memory, we calculate the minimum address width here. + // + FirstNonAddress =3D PlatformGetFirstNonAddress (PlatformInfoHob); + PhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); + + // + // If FirstNonAddress is not an integral power of two, then we need an + // additional bit. + // + if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) { + ++PhysMemAddressWidth; + } + + // + // The minimum address width is 36 (covers up to and excluding 64 GB, wh= ich + // is the maximum for Ia32 + PAE). The theoretical architecture maximum = for + // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We + // can simply assert that here, since 48 bits are good enough for 256 TB. + // + if (PhysMemAddressWidth <=3D 36) { + PhysMemAddressWidth =3D 36; + } + + ASSERT (PhysMemAddressWidth <=3D 48); + + PlatformInfoHob->FirstNonAddress =3D FirstNonAddress; + PlatformInfoHob->PhysMemAddressWidth =3D PhysMemAddressWidth; +} + +STATIC +VOID +QemuInitializeRamBelow1gb ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefau= ltSmbase) { + PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); + PlatformAddReservedMemoryBaseSizeHob ( + SMM_DEFAULT_SMBASE, + MCH_DEFAULT_SMBASE_SIZE, + TRUE /* Cacheable */ + ); + STATIC_ASSERT ( + SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128= KB, + "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" + ); + PlatformAddMemoryRangeHob ( + SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, + BASE_512KB + BASE_128KB + ); + } else { + PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + } +} + +/** + Peform Memory Detection for QEMU / KVM + +**/ +VOID +EFIAPI +PlatformQemuInitializeRam ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 LowerMemorySize; + UINT64 UpperMemorySize; + MTRR_SETTINGS MtrrSettings; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__)); + + // + // Determine total memory size available + // + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob= ); + + if (PlatformInfoHob->BootMode =3D=3D BOOT_ON_S3_RESUME) { + // + // Create the following memory HOB as an exception on the S3 boot path. + // + // Normally we'd create memory HOBs only on the normal boot path. Howe= ver, + // CpuMpPei specifically needs such a low-memory HOB on the S3 path as + // well, for "borrowing" a subset of it temporarily, for the AP startup + // vector. + // + // CpuMpPei saves the original contents of the borrowed area in perman= ent + // PEI RAM, in a backup buffer allocated with the normal PEI services. + // CpuMpPei restores the original contents ("returns" the borrowed are= a) at + // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before + // transferring control to the OS's wakeup vector in the FACS. + // + // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to + // restore the original contents. Furthermore, we expect all such PEIMs + // (CpuMpPei included) to claim the borrowed areas by producing memory + // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en + // looking for an area to borrow. + // + QemuInitializeRamBelow1gb (PlatformInfoHob); + } else { + // + // Create memory HOBs + // + QemuInitializeRamBelow1gb (PlatformInfoHob); + + if (PlatformInfoHob->SmmSmramRequire) { + UINT32 TsegSize; + + TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddReservedMemoryBaseSizeHob ( + LowerMemorySize - TsegSize, + TsegSize, + TRUE + ); + } else { + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); + } + + // + // If QEMU presents an E820 map, then create memory HOBs for the >=3D4= GB RAM + // entries. Otherwise, create a single memory HOB with the flat >=3D4GB + // memory size read from the CMOS. + // + Status =3D PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL); + if (EFI_ERROR (Status)) { + UpperMemorySize =3D PlatformGetSystemMemorySizeAbove4gb (); + if (UpperMemorySize !=3D 0) { + PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + } + } + } + + // + // We'd like to keep the following ranges uncached: + // - [640 KB, 1 MB) + // - [LowerMemorySize, 4 GB) + // + // Everything else should be WB. Unfortunately, programming the inverse = (ie. + // keeping the default UC, and configuring the complement set of the abo= ve as + // WB) is not reliable in general, because the end of the upper RAM can = have + // practically any alignment, and we may not have enough variable MTRRs = to + // cover it exactly. + // + if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId !=3D CLOUDHV= _DEVICE_ID)) { + MtrrGetAllMtrrs (&MtrrSettings); + + // + // MTRRs disabled, fixed MTRRs disabled, default type is uncached + // + ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); + + // + // flip default type to writeback + // + SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); + ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); + MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; + MtrrSetAllMtrrs (&MtrrSettings); + + // + // Set memory range from 640KB to 1MB to uncacheable + // + Status =3D MtrrSetMemoryAttribute ( + BASE_512KB + BASE_128KB, + BASE_1MB - (BASE_512KB + BASE_128KB), + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + // + // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI + // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. + // + Status =3D MtrrSetMemoryAttribute ( + PlatformInfoHob->Uc32Base, + SIZE_4GB - PlatformInfoHob->Uc32Base, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } +} + +VOID +EFIAPI +PlatformQemuInitializeRamForS3 ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode !=3D BOOT= _ON_S3_RESUME)) { + // + // This is the memory range that will be used for PEI on S3 resume + // + BuildMemoryAllocationHob ( + PlatformInfoHob->S3AcpiReservedMemoryBase, + PlatformInfoHob->S3AcpiReservedMemorySize, + EfiACPIMemoryNVS + ); + + // + // Cover the initial RAM area used as stack and temporary PEI heap. + // + // This is reserved as ACPI NVS so it can be used on S3 resume. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdOvmfSecPeiTempRamBase), + PcdGet32 (PcdOvmfSecPeiTempRamSize), + EfiACPIMemoryNVS + ); + + // + // SEC stores its table of GUIDed section handlers here. + // + BuildMemoryAllocationHob ( + PcdGet64 (PcdGuidedExtractHandlerTableAddress), + PcdGet32 (PcdGuidedExtractHandlerTableSize), + EfiACPIMemoryNVS + ); + + #ifdef MDE_CPU_X64 + // + // Reserve the initial page tables built by the reset vector code. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase), + (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize), + EfiACPIMemoryNVS + ); + + if (PlatformInfoHob->SevEsIsEnabled) { + // + // If SEV-ES is enabled, reserve the GHCB-related memory area. This + // includes the extra page table used to break down the 2MB page + // mapping into 4KB page entries where the GHCB resides and the + // GHCB area itself. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase= ), + (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize), + EfiACPIMemoryNVS + ); + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase), + (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize), + EfiACPIMemoryNVS + ); + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase), + (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize), + EfiACPIMemoryNVS + ); + } + + #endif + } + + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + if (!PlatformInfoHob->SmmSmramRequire) { + // + // Reserve the lock box storage area + // + // Since this memory range will be used on S3 resume, it must be + // reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to t= he + // LockBox area. We ought to prevent DXE from serving allocation req= uests + // such that they would overlap the LockBox storage. + // + ZeroMem ( + (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), + (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize) + ); + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), + (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize), + PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesD= ata + ); + } + + if (PlatformInfoHob->SmmSmramRequire) { + UINT32 TsegSize; + + // + // Make sure the TSEG area that we reported as a reserved memory res= ource + // cannot be used for reserved memory allocations. + // + TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; + BuildMemoryAllocationHob ( + PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, + TsegSize, + EfiReservedMemoryType + ); + // + // Similarly, allocate away the (already reserved) SMRAM at the defa= ult + // SMBASE, if it exists. + // + if (PlatformInfoHob->Q35SmramAtDefaultSmbase) { + BuildMemoryAllocationHob ( + SMM_DEFAULT_SMBASE, + MCH_DEFAULT_SMBASE_SIZE, + EfiReservedMemoryType + ); + } + } + + #ifdef MDE_CPU_X64 + if (FixedPcdGet32 (PcdOvmfWorkAreaSize) !=3D 0) { + // + // Reserve the work area. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to t= he + // work area. We ought to prevent DXE from serving allocation reques= ts + // such that they would overlap the work area. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), + (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), + PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesD= ata + ); + } + + #endif + } +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf index 21813458cb59..19a88d363819 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -24,15 +24,64 @@ =20 [Sources] Cmos.c + MemDetect.c Platform.c =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec + UefiCpuPkg/UefiCpuPkg.dec =20 [LibraryClasses] BaseLib DebugLib IoLib HobLib + QemuFwCfgLib + QemuFwCfgSimpleParserLib + MtrrLib + PcdLib + PciLib + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSnpSecretsSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize + + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress + gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr + gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress + gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize + +[FeaturePcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 5709766f86f3..3907de1545de 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -34,7 +34,7 @@ Module Name: #include #include #include -#include + #include #include =20 @@ -126,501 +126,6 @@ Q35SmramAtDefaultSmbaseInitialization ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -VOID -EFIAPI -PlatformQemuUc32BaseInitialization ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINT32 LowerMemorySize; - - if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { - return; - } - - if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for - // setting PcdPciExpressBaseAddress such that describing the - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of - // variable MTRRs (preferably 1 or 2). - // - ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); - PlatformInfoHob->Uc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBase= Address); - return; - } - - if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { - PlatformInfoHob->Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; - PlatformInfoHob->Uc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; - return; - } - - ASSERT (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); - // - // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one - // variable MTRR suffices by truncating the size to a whole power of two, - // while keeping the end affixed to 4GB. This will round the base up. - // - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (Platf= ormInfoHob); - PlatformInfoHob->Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - Lower= MemorySize)); - PlatformInfoHob->Uc32Base =3D (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32S= ize); - // - // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. - // Therefore mQemuUc32Base is at least 2GB. - // - ASSERT (PlatformInfoHob->Uc32Base >=3D BASE_2GB); - - if (PlatformInfoHob->Uc32Base !=3D LowerMemorySize) { - DEBUG (( - DEBUG_VERBOSE, - "%a: rounded UC32 base from 0x%x up to 0x%x, for " - "an UC32 size of 0x%x\n", - __FUNCTION__, - LowerMemorySize, - PlatformInfoHob->Uc32Base, - PlatformInfoHob->Uc32Size - )); - } -} - -/** - Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start ou= tside - of the 32-bit address range. - - Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce - descriptor HOBs for RAM entries that start at or above 4GB. - - @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64B= itE820Ram() - produces memory resource descriptor HOBs for RAM - entries that start at or above 4GB. - - Otherwise, MaxAddress holds the highest exclusive - >=3D4GB RAM address on output. If QEMU's fw_cfg = E820 - RAM map contains no RAM entry that starts outsid= e of - the 32-bit address range, then MaxAddress is exa= ctly - 4GB on output. - - @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and proces= sed. - - @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a - whole multiple of sizeof(EFI_E820_ENTRY64). = No - RAM entry was processed. - - @return Error codes from QemuFwCfgFindFile(). No RAM - entry was processed. -**/ -STATIC -EFI_STATUS -PlatformScanOrAdd64BitE820Ram ( - IN BOOLEAN AddHighHob, - OUT UINT64 *LowMemory OPTIONAL, - OUT UINT64 *MaxAddress OPTIONAL - ) -{ - EFI_STATUS Status; - FIRMWARE_CONFIG_ITEM FwCfgItem; - UINTN FwCfgSize; - EFI_E820_ENTRY64 E820Entry; - UINTN Processed; - - Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); - if (EFI_ERROR (Status)) { - return Status; - } - - if (FwCfgSize % sizeof E820Entry !=3D 0) { - return EFI_PROTOCOL_ERROR; - } - - if (LowMemory !=3D NULL) { - *LowMemory =3D 0; - } - - if (MaxAddress !=3D NULL) { - *MaxAddress =3D BASE_4GB; - } - - QemuFwCfgSelectItem (FwCfgItem); - for (Processed =3D 0; Processed < FwCfgSize; Processed +=3D sizeof E820E= ntry) { - QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry); - DEBUG (( - DEBUG_VERBOSE, - "%a: Base=3D0x%Lx Length=3D0x%Lx Type=3D%u\n", - __FUNCTION__, - E820Entry.BaseAddr, - E820Entry.Length, - E820Entry.Type - )); - if (E820Entry.Type =3D=3D EfiAcpiAddressRangeMemory) { - if (AddHighHob && (E820Entry.BaseAddr >=3D BASE_4GB)) { - UINT64 Base; - UINT64 End; - - // - // Round up the start address, and round down the end address. - // - Base =3D ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE); - End =3D (E820Entry.BaseAddr + E820Entry.Length) & - ~(UINT64)EFI_PAGE_MASK; - if (Base < End) { - PlatformAddMemoryRangeHob (Base, End); - DEBUG (( - DEBUG_VERBOSE, - "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", - __FUNCTION__, - Base, - End - )); - } - } - - if (MaxAddress || LowMemory) { - UINT64 Candidate; - - Candidate =3D E820Entry.BaseAddr + E820Entry.Length; - if (MaxAddress && (Candidate > *MaxAddress)) { - *MaxAddress =3D Candidate; - DEBUG (( - DEBUG_VERBOSE, - "%a: MaxAddress=3D0x%Lx\n", - __FUNCTION__, - *MaxAddress - )); - } - - if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB= )) { - *LowMemory =3D Candidate; - DEBUG (( - DEBUG_VERBOSE, - "%a: LowMemory=3D0x%Lx\n", - __FUNCTION__, - *LowMemory - )); - } - } - } - } - - return EFI_SUCCESS; -} - -/** - Returns PVH memmap - - @param Entries Pointer to PVH memmap - @param Count Number of entries - - @return EFI_STATUS -**/ -EFI_STATUS -GetPvhMemmapEntries ( - struct hvm_memmap_table_entry **Entries, - UINT32 *Count - ) -{ - UINT32 *PVHResetVectorData; - struct hvm_start_info *pvh_start_info; - - PVHResetVectorData =3D (VOID *)(UINTN)PcdGet32 (PcdXenPvhStartOfDayStruc= tPtr); - if (PVHResetVectorData =3D=3D 0) { - return EFI_NOT_FOUND; - } - - pvh_start_info =3D (struct hvm_start_info *)(UINTN)PVHResetVectorData[0]; - - *Entries =3D (struct hvm_memmap_table_entry *)(UINTN)pvh_start_info->mem= map_paddr; - *Count =3D pvh_start_info->memmap_entries; - - return EFI_SUCCESS; -} - -STATIC -UINT64 -GetHighestSystemMemoryAddressFromPvhMemmap ( - BOOLEAN Below4gb - ) -{ - struct hvm_memmap_table_entry *Memmap; - UINT32 MemmapEntriesCount; - struct hvm_memmap_table_entry *Entry; - EFI_STATUS Status; - UINT32 Loop; - UINT64 HighestAddress; - UINT64 EntryEnd; - - HighestAddress =3D 0; - - Status =3D GetPvhMemmapEntries (&Memmap, &MemmapEntriesCount); - ASSERT_EFI_ERROR (Status); - - for (Loop =3D 0; Loop < MemmapEntriesCount; Loop++) { - Entry =3D Memmap + Loop; - EntryEnd =3D Entry->addr + Entry->size; - - if ((Entry->type =3D=3D XEN_HVM_MEMMAP_TYPE_RAM) && - (EntryEnd > HighestAddress)) - { - if (Below4gb && (EntryEnd <=3D BASE_4GB)) { - HighestAddress =3D EntryEnd; - } else if (!Below4gb && (EntryEnd >=3D BASE_4GB)) { - HighestAddress =3D EntryEnd; - } - } - } - - return HighestAddress; -} - -UINT32 -EFIAPI -PlatformGetSystemMemorySizeBelow4gb ( - IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - EFI_STATUS Status; - UINT64 LowerMemorySize =3D 0; - UINT8 Cmos0x34; - UINT8 Cmos0x35; - - if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { - // Get the information from PVH memmap - return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); - } - - Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); - if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { - return (UINT32)LowerMemorySize; - } - - // - // CMOS 0x34/0x35 specifies the system memory above 16 MB. - // * CMOS(0x35) is the high byte - // * CMOS(0x34) is the low byte - // * The size is specified in 64kb chunks - // * Since this is memory above 16MB, the 16MB must be added - // into the calculation to get the total memory size. - // - - Cmos0x34 =3D (UINT8)PlatformCmosRead8 (0x34); - Cmos0x35 =3D (UINT8)PlatformCmosRead8 (0x35); - - return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); -} - -STATIC -UINT64 -PlatformGetSystemMemorySizeAbove4gb ( - ) -{ - UINT32 Size; - UINTN CmosIndex; - - // - // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. - // * CMOS(0x5d) is the most significant size byte - // * CMOS(0x5c) is the middle size byte - // * CMOS(0x5b) is the least significant size byte - // * The size is specified in 64kb chunks - // - - Size =3D 0; - for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) { - Size =3D (UINT32)(Size << 8) + (UINT32)PlatformCmosRead8 (CmosIndex); - } - - return LShiftU64 (Size, 16); -} - -/** - Return the highest address that DXE could possibly use, plus one. -**/ -STATIC -UINT64 -PlatformGetFirstNonAddress ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINT64 FirstNonAddress; - UINT32 FwCfgPciMmio64Mb; - EFI_STATUS Status; - FIRMWARE_CONFIG_ITEM FwCfgItem; - UINTN FwCfgSize; - UINT64 HotPlugMemoryEnd; - - // - // set FirstNonAddress to suppress incorrect compiler/analyzer warnings - // - FirstNonAddress =3D 0; - - // - // If QEMU presents an E820 map, then get the highest exclusive >=3D4GB = RAM - // address from it. This can express an address >=3D 4GB+1TB. - // - // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich - // can only express a size smaller than 1TB), and add it to 4GB. - // - Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); - if (EFI_ERROR (Status)) { - FirstNonAddress =3D BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); - } - - // - // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO - // resources to 32-bit anyway. See DegradeResource() in - // "PciResourceSupport.c". - // - #ifdef MDE_CPU_IA32 - if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { - return FirstNonAddress; - } - - #endif - - // - // See if the user specified the number of megabytes for the 64-bit PCI = host - // aperture. Accept an aperture size up to 16TB. - // - // As signaled by the "X-" prefix, this knob is experimental, and might = go - // away at any time. - // - Status =3D QemuFwCfgParseUint32 ( - "opt/ovmf/X-PciMmio64Mb", - FALSE, - &FwCfgPciMmio64Mb - ); - switch (Status) { - case EFI_UNSUPPORTED: - case EFI_NOT_FOUND: - break; - case EFI_SUCCESS: - if (FwCfgPciMmio64Mb <=3D 0x1000000) { - PlatformInfoHob->PcdPciMmio64Size =3D LShiftU64 (FwCfgPciMmio64Mb,= 20); - break; - } - - // - // fall through - // - default: - DEBUG (( - DEBUG_WARN, - "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\= n", - __FUNCTION__ - )); - break; - } - - if (PlatformInfoHob->PcdPciMmio64Size =3D=3D 0) { - if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { - DEBUG (( - DEBUG_INFO, - "%a: disabling 64-bit PCI host aperture\n", - __FUNCTION__ - )); - } - - // - // There's nothing more to do; the amount of memory above 4GB fully - // determines the highest address plus one. The memory hotplug area (s= ee - // below) plays no role for the firmware in this case. - // - return FirstNonAddress; - } - - // - // The "etc/reserved-memory-end" fw_cfg file, when present, contains an - // absolute, exclusive end address for the memory hotplug area. This area - // starts right at the end of the memory above 4GB. The 64-bit PCI host - // aperture must be placed above it. - // - Status =3D QemuFwCfgFindFile ( - "etc/reserved-memory-end", - &FwCfgItem, - &FwCfgSize - ); - if (!EFI_ERROR (Status) && (FwCfgSize =3D=3D sizeof HotPlugMemoryEnd)) { - QemuFwCfgSelectItem (FwCfgItem); - QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd); - DEBUG (( - DEBUG_VERBOSE, - "%a: HotPlugMemoryEnd=3D0x%Lx\n", - __FUNCTION__, - HotPlugMemoryEnd - )); - - ASSERT (HotPlugMemoryEnd >=3D FirstNonAddress); - FirstNonAddress =3D HotPlugMemoryEnd; - } - - // - // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so - // that the host can map it with 1GB hugepages. Follow suit. - // - PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (FirstNonAddress, (UIN= T64)SIZE_1GB); - PlatformInfoHob->PcdPciMmio64Size =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Size, (UINT64)SIZE_1GB); - - // - // The 64-bit PCI host aperture should also be "naturally" aligned. The - // alignment is determined by rounding the size of the aperture down to = the - // next smaller or equal power of two. That is, align the aperture by the - // largest BAR size that can fit into it. - // - PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size)); - - // - // The useful address space ends with the 64-bit PCI host aperture. - // - FirstNonAddress =3D PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob-= >PcdPciMmio64Size; - return FirstNonAddress; -} - -/** - Initialize the mPhysMemAddressWidth variable, based on guest RAM size. -**/ -VOID -EFIAPI -PlatformAddressWidthInitialization ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINT64 FirstNonAddress; - UINT8 PhysMemAddressWidth; - - // - // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts - // are dominated by the identity-mapping page tables built by the DXE IP= L. - // The DXL IPL keys off of the physical address bits advertized in the C= PU - // HOB. To conserve memory, we calculate the minimum address width here. - // - FirstNonAddress =3D PlatformGetFirstNonAddress (PlatformInfoHob); - PhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); - - // - // If FirstNonAddress is not an integral power of two, then we need an - // additional bit. - // - if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) { - ++PhysMemAddressWidth; - } - - // - // The minimum address width is 36 (covers up to and excluding 64 GB, wh= ich - // is the maximum for Ia32 + PAE). The theoretical architecture maximum = for - // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We - // can simply assert that here, since 48 bits are good enough for 256 TB. - // - if (PhysMemAddressWidth <=3D 36) { - PhysMemAddressWidth =3D 36; - } - - ASSERT (PhysMemAddressWidth <=3D 48); - - PlatformInfoHob->FirstNonAddress =3D FirstNonAddress; - PlatformInfoHob->PhysMemAddressWidth =3D PhysMemAddressWidth; -} - /** Initialize the mPhysMemAddressWidth variable, based on guest RAM size. **/ @@ -842,313 +347,6 @@ PublishPeiMemory ( return Status; } =20 -STATIC -VOID -QemuInitializeRamBelow1gb ( - IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefau= ltSmbase) { - PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - PlatformAddReservedMemoryBaseSizeHob ( - SMM_DEFAULT_SMBASE, - MCH_DEFAULT_SMBASE_SIZE, - TRUE /* Cacheable */ - ); - STATIC_ASSERT ( - SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128= KB, - "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" - ); - PlatformAddMemoryRangeHob ( - SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, - BASE_512KB + BASE_128KB - ); - } else { - PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); - } -} - -/** - Peform Memory Detection for QEMU / KVM - -**/ -STATIC -VOID -PlatformQemuInitializeRam ( - IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINT64 LowerMemorySize; - UINT64 UpperMemorySize; - MTRR_SETTINGS MtrrSettings; - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__)); - - // - // Determine total memory size available - // - LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob= ); - - if (PlatformInfoHob->BootMode =3D=3D BOOT_ON_S3_RESUME) { - // - // Create the following memory HOB as an exception on the S3 boot path. - // - // Normally we'd create memory HOBs only on the normal boot path. Howe= ver, - // CpuMpPei specifically needs such a low-memory HOB on the S3 path as - // well, for "borrowing" a subset of it temporarily, for the AP startup - // vector. - // - // CpuMpPei saves the original contents of the borrowed area in perman= ent - // PEI RAM, in a backup buffer allocated with the normal PEI services. - // CpuMpPei restores the original contents ("returns" the borrowed are= a) at - // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before - // transferring control to the OS's wakeup vector in the FACS. - // - // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to - // restore the original contents. Furthermore, we expect all such PEIMs - // (CpuMpPei included) to claim the borrowed areas by producing memory - // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en - // looking for an area to borrow. - // - QemuInitializeRamBelow1gb (PlatformInfoHob); - } else { - // - // Create memory HOBs - // - QemuInitializeRamBelow1gb (PlatformInfoHob); - - if (PlatformInfoHob->SmmSmramRequire) { - UINT32 TsegSize; - - TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; - PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - PlatformAddReservedMemoryBaseSizeHob ( - LowerMemorySize - TsegSize, - TsegSize, - TRUE - ); - } else { - PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); - } - - // - // If QEMU presents an E820 map, then create memory HOBs for the >=3D4= GB RAM - // entries. Otherwise, create a single memory HOB with the flat >=3D4GB - // memory size read from the CMOS. - // - Status =3D PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL); - if (EFI_ERROR (Status)) { - UpperMemorySize =3D PlatformGetSystemMemorySizeAbove4gb (); - if (UpperMemorySize !=3D 0) { - PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); - } - } - } - - // - // We'd like to keep the following ranges uncached: - // - [640 KB, 1 MB) - // - [LowerMemorySize, 4 GB) - // - // Everything else should be WB. Unfortunately, programming the inverse = (ie. - // keeping the default UC, and configuring the complement set of the abo= ve as - // WB) is not reliable in general, because the end of the upper RAM can = have - // practically any alignment, and we may not have enough variable MTRRs = to - // cover it exactly. - // - if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId !=3D CLOUDHV= _DEVICE_ID)) { - MtrrGetAllMtrrs (&MtrrSettings); - - // - // MTRRs disabled, fixed MTRRs disabled, default type is uncached - // - ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); - - // - // flip default type to writeback - // - SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); - ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); - MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; - MtrrSetAllMtrrs (&MtrrSettings); - - // - // Set memory range from 640KB to 1MB to uncacheable - // - Status =3D MtrrSetMemoryAttribute ( - BASE_512KB + BASE_128KB, - BASE_1MB - (BASE_512KB + BASE_128KB), - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - // - // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI - // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. - // - Status =3D MtrrSetMemoryAttribute ( - PlatformInfoHob->Uc32Base, - SIZE_4GB - PlatformInfoHob->Uc32Base, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } -} - -STATIC -VOID -PlatformQemuInitializeRamForS3 ( - IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode !=3D BOOT= _ON_S3_RESUME)) { - // - // This is the memory range that will be used for PEI on S3 resume - // - BuildMemoryAllocationHob ( - PlatformInfoHob->S3AcpiReservedMemoryBase, - PlatformInfoHob->S3AcpiReservedMemorySize, - EfiACPIMemoryNVS - ); - - // - // Cover the initial RAM area used as stack and temporary PEI heap. - // - // This is reserved as ACPI NVS so it can be used on S3 resume. - // - BuildMemoryAllocationHob ( - PcdGet32 (PcdOvmfSecPeiTempRamBase), - PcdGet32 (PcdOvmfSecPeiTempRamSize), - EfiACPIMemoryNVS - ); - - // - // SEC stores its table of GUIDed section handlers here. - // - BuildMemoryAllocationHob ( - PcdGet64 (PcdGuidedExtractHandlerTableAddress), - PcdGet32 (PcdGuidedExtractHandlerTableSize), - EfiACPIMemoryNVS - ); - - #ifdef MDE_CPU_X64 - // - // Reserve the initial page tables built by the reset vector code. - // - // Since this memory range will be used by the Reset Vector on S3 - // resume, it must be reserved as ACPI NVS. - // - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase), - (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize), - EfiACPIMemoryNVS - ); - - if (PlatformInfoHob->SevEsIsEnabled) { - // - // If SEV-ES is enabled, reserve the GHCB-related memory area. This - // includes the extra page table used to break down the 2MB page - // mapping into 4KB page entries where the GHCB resides and the - // GHCB area itself. - // - // Since this memory range will be used by the Reset Vector on S3 - // resume, it must be reserved as ACPI NVS. - // - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase= ), - (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize), - EfiACPIMemoryNVS - ); - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase), - (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize), - EfiACPIMemoryNVS - ); - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase), - (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize), - EfiACPIMemoryNVS - ); - } - - #endif - } - - if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { - if (!PlatformInfoHob->SmmSmramRequire) { - // - // Reserve the lock box storage area - // - // Since this memory range will be used on S3 resume, it must be - // reserved as ACPI NVS. - // - // If S3 is unsupported, then various drivers might still write to t= he - // LockBox area. We ought to prevent DXE from serving allocation req= uests - // such that they would overlap the LockBox storage. - // - ZeroMem ( - (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), - (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize) - ); - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), - (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize), - PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesD= ata - ); - } - - if (PlatformInfoHob->SmmSmramRequire) { - UINT32 TsegSize; - - // - // Make sure the TSEG area that we reported as a reserved memory res= ource - // cannot be used for reserved memory allocations. - // - TsegSize =3D PlatformInfoHob->Q35TsegMbytes * SIZE_1MB; - BuildMemoryAllocationHob ( - PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize, - TsegSize, - EfiReservedMemoryType - ); - // - // Similarly, allocate away the (already reserved) SMRAM at the defa= ult - // SMBASE, if it exists. - // - if (PlatformInfoHob->Q35SmramAtDefaultSmbase) { - BuildMemoryAllocationHob ( - SMM_DEFAULT_SMBASE, - MCH_DEFAULT_SMBASE_SIZE, - EfiReservedMemoryType - ); - } - } - - #ifdef MDE_CPU_X64 - if (FixedPcdGet32 (PcdOvmfWorkAreaSize) !=3D 0) { - // - // Reserve the work area. - // - // Since this memory range will be used by the Reset Vector on S3 - // resume, it must be reserved as ACPI NVS. - // - // If S3 is unsupported, then various drivers might still write to t= he - // work area. We ought to prevent DXE from serving allocation reques= ts - // such that they would overlap the work area. - // - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), - (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), - PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesD= ata - ); - } - - #endif - } -} - /** Publish system RAM and reserve memory regions =20 diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 494836c3efe4..31670747d8b0 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -32,18 +32,6 @@ PublishPeiMemory ( VOID ); =20 -UINT32 -EFIAPI -PlatformGetSystemMemorySizeBelow4gb ( - IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ); - -VOID -EFIAPI -PlatformQemuUc32BaseInitialization ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ); - VOID InitializeRamRegions ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87340): https://edk2.groups.io/g/devel/message/87340 Mute This Topic: https://groups.io/mt/89629691/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 05:50:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+87341+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87341+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1646707040; cv=none; d=zohomail.com; s=zohoarc; b=IQAmI9Fl0EpS3QgusQ1mepjQFDGlFM/L469mJHoklREvJrwdZf9X/+eKXgnCkP4Bzk3HP6lbcBcc/5P2WIlXIHlVtv8CUf0wBv6zO+9CurusmastL0tBsylwXGcq28bdkIJlLaTI1m4XbaerCZyTJ3/Jkg1djQP5GMD8jZpFozM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646707040; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YJ7Zo34LlUehXug12I45/6Dwop+voX4J4J+SxyeqILE=; b=mDCqVzqEmqif4NcfcB2DdFO1SIsZ5CrTPv88hk6LgBm9gmoUDisPW9k3p6sz9DHObpLY84lyd+ORpELmA75mD8SxFNHY41jvbgEJGQlYfN918GqkfIrd/Ys5TbWyfxBrIgv+tPOhIRopQ6W2ihXzJ/s3ol+nVLPkUbswWX8t9Xk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+87341+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164670704088499.55916860859156; Mon, 7 Mar 2022 18:37:20 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id N48rYY1788612xWtwNN8IGTL; Mon, 07 Mar 2022 18:37:20 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.4209.1646706992182166839 for ; Mon, 07 Mar 2022 18:37:20 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10279"; a="317801307" X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="317801307" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:18 -0800 X-IronPort-AV: E=Sophos;i="5.90,163,1643702400"; d="scan'208";a="553432982" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 18:37:14 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH 14/14] OvmfPkg/PlatformInitLib: Move functions to Platform.c Date: Tue, 8 Mar 2022 10:36:15 +0800 Message-Id: <44e6ea925fcd45f6a085c956ad7939e42334e009.1646706302.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: FCdfEVmIiA21BmIM3uKFK1Sex1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1646707040; bh=ghSPikDjGr+zD0J6IkiQNCSRxFOvunKktCp2hm7sy+o=; h=Cc:Date:From:Reply-To:Subject:To; b=UE/LA+2+GklNe8H6sa4rbA7Z/pxernsq4rb5N7ta6fVktTMTpAjX0rM2CJmKH+n7Qrr niaFENfBnUhfQE9Q2VBl5hrcO89hMIpI4PjMxsDpdD/Y6cYClp7qcdRZmD7LIy0AKjH0F tnzlszAAUZNZFW02tdMZUQSr020Rf1J4G4Q= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1646707042508100008 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 Move functions in PlatformPei/Platform.c to PlatformInitLib/Platform.c. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Signed-off-by: Min Xu Acked-by: Gerd Hoffmann Acked-by: Sebastien Boeuf --- OvmfPkg/Include/Library/PlatformInitLib.h | 34 ++ OvmfPkg/Library/PlatformInitLib/Platform.c | 465 +++++++++++++++++++++ OvmfPkg/PlatformPei/Platform.c | 451 -------------------- 3 files changed, 499 insertions(+), 451 deletions(-) diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index 2e4bb8140368..21fc385e35eb 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -169,4 +169,38 @@ PlatformQemuInitializeRamForS3 ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ); =20 +VOID +EFIAPI +PlatformMemMapInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +/** + * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU + * + * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxFor= Stack". + * @return EFI_SUCCESS Successfully fetch the settings. + */ +EFI_STATUS +EFIAPI +PlatformNoexecDxeInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +VOID +EFIAPI +PlatformMiscInitialization ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + +/** + Fetch the boot CPU count and the possible CPU count from QEMU, and expose + them to UefiCpuPkg modules. Set the mMaxCpuCount variable. +**/ +VOID +EFIAPI +PlatformMaxCpuCountInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Platform.c index e41f230ff563..96bc41b1098c 100644 --- a/OvmfPkg/Library/PlatformInitLib/Platform.c +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -19,6 +19,18 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + #include =20 VOID @@ -104,3 +116,456 @@ PlatformAddMemoryRangeHob ( { PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); } + +VOID +EFIAPI +PlatformMemMapInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT64 PciIoBase; + UINT64 PciIoSize; + UINT32 TopOfLowRam; + UINT64 PciExBarBase; + UINT32 PciBase; + UINT32 PciSize; + + PciIoBase =3D 0xC000; + PciIoSize =3D 0x4000; + + // + // Video memory + Legacy BIOS region + // + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); + + if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { + PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ + PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ + return; + } + + TopOfLowRam =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); + PciExBarBase =3D 0; + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // The MMCONFIG area is expected to fall between the top of low RAM and + // the base of the 32-bit PCI host aperture. + // + PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); + ASSERT (TopOfLowRam <=3D PciExBarBase); + ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); + PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + } else { + ASSERT (TopOfLowRam <=3D PlatformInfoHob->Uc32Base); + PciBase =3D PlatformInfoHob->Uc32Base; + } + + // + // address purpose size + // ------------ -------- ------------------------- + // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) + // 0xFC000000 gap 44 MB + // 0xFEC00000 IO-APIC 4 KB + // 0xFEC01000 gap 1020 KB + // 0xFED00000 HPET 1 KB + // 0xFED00400 gap 111 KB + // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB + // 0xFED20000 gap 896 KB + // 0xFEE00000 LAPIC 1 MB + // + PciSize =3D 0xFC000000 - PciBase; + PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); + + PlatformInfoHob->PcdPciMmio32Base =3D PciBase; + PlatformInfoHob->PcdPciMmio32Size =3D PciSize; + + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + // + // Note: there should be an + // + // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); + // + // call below, just like the one above for RCBA. However, Linux insists + // that the MMCONFIG area be marked in the E820 or UEFI memory map as + // "reserved memory" -- Linux does not content itself with a simple gap + // in the memory map wherever the MCFG ACPI table points to. + // + // This appears to be a safety measure. The PCI Firmware Specification + // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources c= an + // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory + // [...]". (Emphasis added here.) + // + // Normally we add memory resource descriptor HOBs in + // QemuInitializeRam(), and pre-allocate from those with memory + // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG ar= ea + // is most definitely not RAM; so, as an exception, cover it with + // uncacheable reserved memory right here. + // + PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); + BuildMemoryAllocationHob ( + PciExBarBase, + SIZE_256MB, + EfiReservedMemoryType + ); + } + + PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), S= IZE_1MB); + + // + // On Q35, the IO Port space is available for PCI resource allocations f= rom + // 0x6000 up. + // + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + PciIoBase =3D 0x6000; + PciIoSize =3D 0xA000; + ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase); + } + + // + // Add PCI IO Port space available for PCI resource allocations. + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED, + PciIoBase, + PciIoSize + ); + + PlatformInfoHob->PcdPciIoBase =3D PciIoBase; + PlatformInfoHob->PcdPciIoSize =3D PciIoSize; +} + +/** + * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU + * + * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxFor= Stack". + * @return EFI_SUCCESS Successfully fetch the settings. + */ +EFI_STATUS +EFIAPI +PlatformNoexecDxeInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob= ->PcdSetNxForStack); +} + +VOID +PciExBarInitialization ( + VOID + ) +{ + union { + UINT64 Uint64; + UINT32 Uint32[2]; + } PciExBarBase; + + // + // We only support the 256MB size for the MMCONFIG area: + // 256 buses * 32 devices * 8 functions * 4096 bytes config space. + // + // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea + // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B. + // + // Note that (b) also ensures that the minimum address width we have + // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce + // for DXE's page tables to cover the MMCONFIG area. + // + PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); + ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); + ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); + + // + // Clear the PCIEXBAREN bit first, before programming the high register. + // + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); + + // + // Program the high register. Then program the low register, setting the + // MMCONFIG area size and enabling decoding at once. + // + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); + PciWrite32 ( + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), + PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN + ); +} + +VOID +EFIAPI +PlatformMiscInitialization ( + IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINTN PmCmd; + UINTN Pmba; + UINT32 PmbaAndVal; + UINT32 PmbaOrVal; + UINTN AcpiCtlReg; + UINT8 AcpiEnBit; + + // + // Disable A20 Mask + // + IoOr8 (0x92, BIT1); + + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16); + + // + // Determine platform type and save Host Bridge DID to PCD + // + switch (PlatformInfoHob->HostBridgeDevId) { + case INTEL_82441_DEVICE_ID: + PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); + Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); + PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK; + PmbaOrVal =3D PIIX4_PMBA_VALUE; + AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); + AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE; + break; + case INTEL_Q35_MCH_DEVICE_ID: + PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); + Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); + PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK; + PmbaOrVal =3D ICH9_PMBASE_VALUE; + AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); + AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; + break; + case CLOUDHV_DEVICE_ID: + break; + default: + DEBUG (( + DEBUG_ERROR, + "%a: Unknown Host Bridge Device ID: 0x%04x\n", + __FUNCTION__, + PlatformInfoHob->HostBridgeDevId + )); + ASSERT (FALSE); + return; + } + + if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__)); + return; + } + + // + // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has + // been configured and skip the setup here. This matches the logic in + // AcpiTimerLibConstructor (). + // + if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) { + // + // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e: + // 1. set PMBA + // + PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal); + + // + // 2. set PCICMD/IOSE + // + PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); + + // + // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) + // + PciOr8 (AcpiCtlReg, AcpiEnBit); + } + + if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // Set Root Complex Register Block BAR + // + PciWrite32 ( + POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), + ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN + ); + + // + // Set PCI Express Register Range Base Address + // + PciExBarInitialization (); + } +} + +/** + Fetch the boot CPU count and the possible CPU count from QEMU, and expose + them to UefiCpuPkg modules. Set the mMaxCpuCount variable. +**/ +VOID +EFIAPI +PlatformMaxCpuCountInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + UINT16 BootCpuCount; + UINT32 MaxCpuCount; + + // + // Try to fetch the boot CPU count. + // + QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount); + BootCpuCount =3D QemuFwCfgRead16 (); + if (BootCpuCount =3D=3D 0) { + // + // QEMU doesn't report the boot CPU count. (BootCpuCount =3D=3D 0) wil= l let + // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or + // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reach= ed + // first). + // + DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__)); + MaxCpuCount =3D PlatformInfoHob->DefaultMaxCpuNumber; + } else { + // + // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs = up to + // (BootCpuCount - 1) precisely, regardless of timeout. + // + // Now try to fetch the possible CPU count. + // + UINTN CpuHpBase; + UINT32 CmdData2; + + CpuHpBase =3D ((PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_= DEVICE_ID) ? + ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE); + + // + // If only legacy mode is available in the CPU hotplug register block,= or + // the register block is completely missing, then the writes below are + // no-ops. + // + // 1. Switch the hotplug register block to modern mode. + // + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); + // + // 2. Select a valid CPU for deterministic reading of + // QEMU_CPUHP_R_CMD_DATA2. + // + // CPU#0 is always valid; it is the always present and non-removable + // BSP. + // + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); + // + // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to + // read as zero, and which does not invalidate the selector. (The + // selector may change, but it must not become invalid.) + // + // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later. + // + IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING); + // + // 4. Read QEMU_CPUHP_R_CMD_DATA2. + // + // If the register block is entirely missing, then this is an unass= igned + // IO read, returning all-bits-one. + // + // If only legacy mode is available, then bit#0 stands for CPU#0 in= the + // "CPU present bitmap". CPU#0 is always present. + // + // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (retu= rning + // all-bits-zero), or it is specified to read as zero after the abo= ve + // steps. Both cases confirm modern mode. + // + CmdData2 =3D IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2); + DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=3D0x%x\n", __FUNCTION__, CmdData2= )); + if (CmdData2 !=3D 0) { + // + // QEMU doesn't support the modern CPU hotplug interface. Assume tha= t the + // possible CPU count equals the boot CPU count (precluding hotplug). + // + DEBUG (( + DEBUG_WARN, + "%a: modern CPU hotplug interface unavailable\n", + __FUNCTION__ + )); + MaxCpuCount =3D BootCpuCount; + } else { + // + // Grab the possible CPU count from the modern CPU hotplug interface. + // + UINT32 Present, Possible, Selected; + + Present =3D 0; + Possible =3D 0; + + // + // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures + // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However, + // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pe= nding + // hotplug events; therefore, select CPU#0 forcibly. + // + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); + + do { + UINT8 CpuStatus; + + // + // Read the status of the currently selected CPU. This will help w= ith a + // sanity check against "BootCpuCount". + // + CpuStatus =3D IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT); + if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) !=3D 0) { + ++Present; + } + + // + // Attempt to select the next CPU. + // + ++Possible; + IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); + // + // If the selection is successful, then the following read will re= turn + // the selector (which we know is positive at this point). Otherwi= se, + // the read will return 0. + // + Selected =3D IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA); + ASSERT (Selected =3D=3D Possible || Selected =3D=3D 0); + } while (Selected > 0); + + // + // Sanity check: fw_cfg and the modern CPU hotplug interface should + // return the same boot CPU count. + // + if (BootCpuCount !=3D Present) { + DEBUG (( + DEBUG_WARN, + "%a: QEMU v2.7 reset bug: BootCpuCount=3D%d " + "Present=3D%u\n", + __FUNCTION__, + BootCpuCount, + Present + )); + // + // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug pl= us + // platform reset (including S3), was corrected in QEMU commit + // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device ad= ded + // CPUs", 2016-11-16), part of release v2.8.0. + // + BootCpuCount =3D (UINT16)Present; + } + + MaxCpuCount =3D Possible; + } + } + + DEBUG (( + DEBUG_INFO, + "%a: BootCpuCount=3D%d MaxCpuCount=3D%u\n", + __FUNCTION__, + BootCpuCount, + MaxCpuCount + )); + ASSERT (BootCpuCount <=3D MaxCpuCount); + + PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber =3D MaxCpuCount; + PlatformInfoHob->PcdCpuBootLogicalProcessorNumber =3D BootCpuCount; +} diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index a5ed2c0bcc99..0f81c6193e12 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -51,129 +51,6 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { } }; =20 -VOID -EFIAPI -PlatformMemMapInitialization ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINT64 PciIoBase; - UINT64 PciIoSize; - UINT32 TopOfLowRam; - UINT64 PciExBarBase; - UINT32 PciBase; - UINT32 PciSize; - - PciIoBase =3D 0xC000; - PciIoSize =3D 0x4000; - - // - // Video memory + Legacy BIOS region - // - PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); - - if (PlatformInfoHob->HostBridgeDevId =3D=3D 0xffff /* microvm */) { - PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ - return; - } - - TopOfLowRam =3D PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob); - PciExBarBase =3D 0; - if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // The MMCONFIG area is expected to fall between the top of low RAM and - // the base of the 32-bit PCI host aperture. - // - PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <=3D PciExBarBase); - ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); - } else { - ASSERT (TopOfLowRam <=3D PlatformInfoHob->Uc32Base); - PciBase =3D PlatformInfoHob->Uc32Base; - } - - // - // address purpose size - // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) - // 0xFC000000 gap 44 MB - // 0xFEC00000 IO-APIC 4 KB - // 0xFEC01000 gap 1020 KB - // 0xFED00000 HPET 1 KB - // 0xFED00400 gap 111 KB - // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB - // 0xFED20000 gap 896 KB - // 0xFEE00000 LAPIC 1 MB - // - PciSize =3D 0xFC000000 - PciBase; - PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); - - PlatformInfoHob->PcdPciMmio32Base =3D PciBase; - PlatformInfoHob->PcdPciMmio32Size =3D PciSize; - - PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); - if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); - // - // Note: there should be an - // - // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); - // - // call below, just like the one above for RCBA. However, Linux insists - // that the MMCONFIG area be marked in the E820 or UEFI memory map as - // "reserved memory" -- Linux does not content itself with a simple gap - // in the memory map wherever the MCFG ACPI table points to. - // - // This appears to be a safety measure. The PCI Firmware Specification - // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources c= an - // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory - // [...]". (Emphasis added here.) - // - // Normally we add memory resource descriptor HOBs in - // QemuInitializeRam(), and pre-allocate from those with memory - // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG ar= ea - // is most definitely not RAM; so, as an exception, cover it with - // uncacheable reserved memory right here. - // - PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); - BuildMemoryAllocationHob ( - PciExBarBase, - SIZE_256MB, - EfiReservedMemoryType - ); - } - - PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), S= IZE_1MB); - - // - // On Q35, the IO Port space is available for PCI resource allocations f= rom - // 0x6000 up. - // - if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - PciIoBase =3D 0x6000; - PciIoSize =3D 0xA000; - ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase); - } - - // - // Add PCI IO Port space available for PCI resource allocations. - // - BuildResourceDescriptorHob ( - EFI_RESOURCE_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED, - PciIoBase, - PciIoSize - ); - - PlatformInfoHob->PcdPciIoBase =3D PciIoBase; - PlatformInfoHob->PcdPciIoSize =3D PciIoSize; -} - VOID MemMapInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob @@ -198,21 +75,6 @@ MemMapInitialization ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -/** - * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU - * - * @param Setting The pointer to the setting of "/opt/ovmf/PcdSetNxFor= Stack". - * @return EFI_SUCCESS Successfully fetch the settings. - */ -EFI_STATUS -EFIAPI -PlatformNoexecDxeInitialization ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob= ->PcdSetNxForStack); -} - VOID NoexecDxeInitialization ( VOID @@ -227,47 +89,6 @@ NoexecDxeInitialization ( } } =20 -VOID -PciExBarInitialization ( - VOID - ) -{ - union { - UINT64 Uint64; - UINT32 Uint32[2]; - } PciExBarBase; - - // - // We only support the 256MB size for the MMCONFIG area: - // 256 buses * 32 devices * 8 functions * 4096 bytes config space. - // - // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea - // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B. - // - // Note that (b) also ensures that the minimum address width we have - // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce - // for DXE's page tables to cover the MMCONFIG area. - // - PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); - ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); - - // - // Clear the PCIEXBAREN bit first, before programming the high register. - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); - - // - // Program the high register. Then program the low register, setting the - // MMCONFIG area size and enabling decoding at once. - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); - PciWrite32 ( - DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), - PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN - ); -} - static const UINT8 EmptyFdt[] =3D { 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48, @@ -359,107 +180,6 @@ MiscInitializationForMicrovm ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -VOID -PlatformMiscInitialization ( - IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINTN PmCmd; - UINTN Pmba; - UINT32 PmbaAndVal; - UINT32 PmbaOrVal; - UINTN AcpiCtlReg; - UINT8 AcpiEnBit; - - // - // Disable A20 Mask - // - IoOr8 (0x92, BIT1); - - // - // Build the CPU HOB with guest RAM size dependent address width and 16-= bits - // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing - // S3 resume as well, so we build it unconditionally.) - // - BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16); - - // - // Determine platform type and save Host Bridge DID to PCD - // - switch (PlatformInfoHob->HostBridgeDevId) { - case INTEL_82441_DEVICE_ID: - PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); - Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); - PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK; - PmbaOrVal =3D PIIX4_PMBA_VALUE; - AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); - AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE; - break; - case INTEL_Q35_MCH_DEVICE_ID: - PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); - Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); - PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK; - PmbaOrVal =3D ICH9_PMBASE_VALUE; - AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); - AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; - break; - case CLOUDHV_DEVICE_ID: - break; - default: - DEBUG (( - DEBUG_ERROR, - "%a: Unknown Host Bridge Device ID: 0x%04x\n", - __FUNCTION__, - PlatformInfoHob->HostBridgeDevId - )); - ASSERT (FALSE); - return; - } - - if (PlatformInfoHob->HostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { - DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__)); - return; - } - - // - // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has - // been configured and skip the setup here. This matches the logic in - // AcpiTimerLibConstructor (). - // - if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) { - // - // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e: - // 1. set PMBA - // - PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal); - - // - // 2. set PCICMD/IOSE - // - PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); - - // - // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) - // - PciOr8 (AcpiCtlReg, AcpiEnBit); - } - - if (PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // Set Root Complex Register Block BAR - // - PciWrite32 ( - POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), - ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN - ); - - // - // Set PCI Express Register Range Base Address - // - PciExBarInitialization (); - } -} - VOID MiscInitialization ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob @@ -571,177 +291,6 @@ Q35BoardVerification ( CpuDeadLoop (); } =20 -/** - Fetch the boot CPU count and the possible CPU count from QEMU, and expose - them to UefiCpuPkg modules. Set the mMaxCpuCount variable. -**/ -VOID -PlatformMaxCpuCountInitialization ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob - ) -{ - UINT16 BootCpuCount; - UINT32 MaxCpuCount; - - // - // Try to fetch the boot CPU count. - // - QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount); - BootCpuCount =3D QemuFwCfgRead16 (); - if (BootCpuCount =3D=3D 0) { - // - // QEMU doesn't report the boot CPU count. (BootCpuCount =3D=3D 0) wil= l let - // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or - // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reach= ed - // first). - // - DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__)); - MaxCpuCount =3D PlatformInfoHob->DefaultMaxCpuNumber; - } else { - // - // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs = up to - // (BootCpuCount - 1) precisely, regardless of timeout. - // - // Now try to fetch the possible CPU count. - // - UINTN CpuHpBase; - UINT32 CmdData2; - - CpuHpBase =3D ((PlatformInfoHob->HostBridgeDevId =3D=3D INTEL_Q35_MCH_= DEVICE_ID) ? - ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE); - - // - // If only legacy mode is available in the CPU hotplug register block,= or - // the register block is completely missing, then the writes below are - // no-ops. - // - // 1. Switch the hotplug register block to modern mode. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); - // - // 2. Select a valid CPU for deterministic reading of - // QEMU_CPUHP_R_CMD_DATA2. - // - // CPU#0 is always valid; it is the always present and non-removable - // BSP. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); - // - // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to - // read as zero, and which does not invalidate the selector. (The - // selector may change, but it must not become invalid.) - // - // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later. - // - IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING); - // - // 4. Read QEMU_CPUHP_R_CMD_DATA2. - // - // If the register block is entirely missing, then this is an unass= igned - // IO read, returning all-bits-one. - // - // If only legacy mode is available, then bit#0 stands for CPU#0 in= the - // "CPU present bitmap". CPU#0 is always present. - // - // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (retu= rning - // all-bits-zero), or it is specified to read as zero after the abo= ve - // steps. Both cases confirm modern mode. - // - CmdData2 =3D IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2); - DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=3D0x%x\n", __FUNCTION__, CmdData2= )); - if (CmdData2 !=3D 0) { - // - // QEMU doesn't support the modern CPU hotplug interface. Assume tha= t the - // possible CPU count equals the boot CPU count (precluding hotplug). - // - DEBUG (( - DEBUG_WARN, - "%a: modern CPU hotplug interface unavailable\n", - __FUNCTION__ - )); - MaxCpuCount =3D BootCpuCount; - } else { - // - // Grab the possible CPU count from the modern CPU hotplug interface. - // - UINT32 Present, Possible, Selected; - - Present =3D 0; - Possible =3D 0; - - // - // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures - // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However, - // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pe= nding - // hotplug events; therefore, select CPU#0 forcibly. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); - - do { - UINT8 CpuStatus; - - // - // Read the status of the currently selected CPU. This will help w= ith a - // sanity check against "BootCpuCount". - // - CpuStatus =3D IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT); - if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) !=3D 0) { - ++Present; - } - - // - // Attempt to select the next CPU. - // - ++Possible; - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); - // - // If the selection is successful, then the following read will re= turn - // the selector (which we know is positive at this point). Otherwi= se, - // the read will return 0. - // - Selected =3D IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA); - ASSERT (Selected =3D=3D Possible || Selected =3D=3D 0); - } while (Selected > 0); - - // - // Sanity check: fw_cfg and the modern CPU hotplug interface should - // return the same boot CPU count. - // - if (BootCpuCount !=3D Present) { - DEBUG (( - DEBUG_WARN, - "%a: QEMU v2.7 reset bug: BootCpuCount=3D%d " - "Present=3D%u\n", - __FUNCTION__, - BootCpuCount, - Present - )); - // - // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug pl= us - // platform reset (including S3), was corrected in QEMU commit - // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device ad= ded - // CPUs", 2016-11-16), part of release v2.8.0. - // - BootCpuCount =3D (UINT16)Present; - } - - MaxCpuCount =3D Possible; - } - } - - DEBUG (( - DEBUG_INFO, - "%a: BootCpuCount=3D%d MaxCpuCount=3D%u\n", - __FUNCTION__, - BootCpuCount, - MaxCpuCount - )); - ASSERT (BootCpuCount <=3D MaxCpuCount); - - PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber =3D MaxCpuCount; - PlatformInfoHob->PcdCpuBootLogicalProcessorNumber =3D BootCpuCount; -} - /** Fetch the boot CPU count and the possible CPU count from QEMU, and expose them to UefiCpuPkg modules. Set the mMaxCpuCount variable. --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87341): https://edk2.groups.io/g/devel/message/87341 Mute This Topic: https://groups.io/mt/89629699/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-