.../MinnowBoard3Module/BoardInitDxe/BoardInitDxe.c | 14 +- .../MinnowBoard3Module/BoardInitDxe/BoardInitDxe.h | 8 +- .../BoardInitDxe/BoardInitDxe.inf | 6 +- .../BoardInitPostMem/BoardGpios.c | 175 +++++-------- .../BoardInitPostMem/BoardGpios.h | 24 +- .../BoardInitPostMem/BoardInit.c | 26 +- .../BoardInitPostMem/BoardInit.h | 8 +- .../BoardInitPostMem/BoardInitMiscs.c | 27 +- .../BoardInitPostMem/BoardInitMiscs.h | 73 +++--- .../BoardInitPostMem/BoardInitPostMem.inf | 12 +- .../BoardInitPostMem/PlatformInfoHob.c | 4 +- .../MinnowBoard3Module/BoardInitPostMem/TypeC.c | 290 +++++++++++++++++++++ .../MinnowBoard3Module/BoardInitPostMem/TypeC.h | 88 +++++++ .../MinnowBoard3Module/BoardInitPreMem/BoardInit.c | 42 +-- .../BoardInitPreMem/BoardInitMiscs.c | 138 +++++----- .../BoardInitPreMem/BoardInitMiscs.h | 20 +- .../BoardInitPreMem/BoardInitPreMem.inf | 6 +- .../BoardInitPreMem/PlatformId.c | 230 +++++++++------- .../BoardInitPreMem/PlatformId.h | 29 ++- .../Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin | Bin 5632 -> 5632 bytes 20 files changed, 833 insertions(+), 387 deletions(-) create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
1. Renamed from MinnowBoard3Next to MinnowBoard3Module (MB3N to MB3M).
2. Add Minnow3Module board specific code
Cc: David Wei <david.wei@intel.com>
Cc: Mike Wu <mike.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Kelly Steele <kelly.steele@intel.com>
Signed-off-by: Guo Mang <mang.guo@intel.com>
---
.../MinnowBoard3Module/BoardInitDxe/BoardInitDxe.c | 14 +-
.../MinnowBoard3Module/BoardInitDxe/BoardInitDxe.h | 8 +-
.../BoardInitDxe/BoardInitDxe.inf | 6 +-
.../BoardInitPostMem/BoardGpios.c | 175 +++++--------
.../BoardInitPostMem/BoardGpios.h | 24 +-
.../BoardInitPostMem/BoardInit.c | 26 +-
.../BoardInitPostMem/BoardInit.h | 8 +-
.../BoardInitPostMem/BoardInitMiscs.c | 27 +-
.../BoardInitPostMem/BoardInitMiscs.h | 73 +++---
.../BoardInitPostMem/BoardInitPostMem.inf | 12 +-
.../BoardInitPostMem/PlatformInfoHob.c | 4 +-
.../MinnowBoard3Module/BoardInitPostMem/TypeC.c | 290 +++++++++++++++++++++
.../MinnowBoard3Module/BoardInitPostMem/TypeC.h | 88 +++++++
.../MinnowBoard3Module/BoardInitPreMem/BoardInit.c | 42 +--
.../BoardInitPreMem/BoardInitMiscs.c | 138 +++++-----
.../BoardInitPreMem/BoardInitMiscs.h | 20 +-
.../BoardInitPreMem/BoardInitPreMem.inf | 6 +-
.../BoardInitPreMem/PlatformId.c | 230 +++++++++-------
.../BoardInitPreMem/PlatformId.h | 29 ++-
.../Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin | Bin 5632 -> 5632 bytes
20 files changed, 833 insertions(+), 387 deletions(-)
create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.c
index 71deb43..c1c1cf8 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.c
@@ -2,7 +2,7 @@
Board specific functions in DXE phase to be set as dynamic PCD and consumed by
commmon platform code.
- Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -16,11 +16,11 @@
#include "BoardInitDxe.h"
-GET_BOARD_NAME mMb3NGetBoardNamePtr = Mb3NGetBoardName;
+GET_BOARD_NAME mMb3MGetBoardNamePtr = Mb3MGetBoardName;
CHAR16*
EFIAPI
-Mb3NGetBoardName (
+Mb3MGetBoardName (
IN UINT8 BoardId
)
{
@@ -30,7 +30,7 @@ Mb3NGetBoardName (
UnicodeSPrint (BoardName, sizeof (BoardName), L"MinnowBoard 3 Module ");
- if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+ if (BoardId != (UINT8) BOARD_ID_MINNOW_MODULE) {
return NULL;
} else {
return BoardName;
@@ -49,7 +49,7 @@ Mb3NGetBoardName (
**/
EFI_STATUS
EFIAPI
-Mb3NBoardInitDxeConstructor (
+Mb3MBoardInitDxeConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
@@ -57,11 +57,11 @@ Mb3NBoardInitDxeConstructor (
UINT8 BoardId;
BoardId = PcdGet8 (PcdBoardId);
- if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+ if (BoardId != (UINT8) BOARD_ID_MINNOW_MODULE) {
return EFI_SUCCESS;
}
- PcdSet64 (PcdGetBoardNameFunc, (UINT64) mMb3NGetBoardNamePtr);
+ PcdSet64 (PcdGetBoardNameFunc, (UINT64) mMb3MGetBoardNamePtr);
return EFI_SUCCESS;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.h
index 74407ac..b8d8c60 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.h
@@ -2,7 +2,7 @@
The internal header file includes the common header files, defines
internal structure and functions used by ImageVerificationLib.
- Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -14,8 +14,8 @@
**/
-#ifndef __MINNOW3_NEXT_BOARD_INIT_DXE_H__
-#define __MINNOW3_NEXT_BOARD_INIT_DXE_H__
+#ifndef __MINNOW3_MODULE_BOARD_INIT_DXE_H__
+#define __MINNOW3_MODULE_BOARD_INIT_DXE_H__
#include <BoardFunctionsDxe.h>
#include <Library/UefiDriverEntryPoint.h>
@@ -30,7 +30,7 @@
CHAR16*
EFIAPI
-Mb3NGetBoardName (
+Mb3MGetBoardName (
IN UINT8 BoardId
);
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.inf
index 0b385e9..df6b6f0 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.inf
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitDxe/BoardInitDxe.inf
@@ -2,7 +2,7 @@
# Board specific functions in DXE phase to be set as dynamic PCD and consumed by
# commmon platform code.
#
-# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -16,12 +16,12 @@
[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = Mb3NBoardInitDxe
+ BASE_NAME = Mb3MBoardInitDxe
FILE_GUID = 82919D30-DA6E-4177-8358-D490B45EFF3B
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = NULL|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
- CONSTRUCTOR = Mb3NBoardInitDxeConstructor
+ CONSTRUCTOR = Mb3MBoardInitDxeConstructor
[Sources]
BoardInitDxe.c
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.c
index d89ee67..569f566 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.c
@@ -1,7 +1,7 @@
/** @file
Gpio setting for multiplatform.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -14,10 +14,7 @@
**/
#include "BoardGpios.h"
-#include <Library/GpioLib.h>
-#include <Library/SteppingLib.h>
-#include <Library/TimerLib.h>
-
+#include <Library/EepromPlatformLib.h>
/**
Returns the Correct GPIO table for Mobile/Desktop respectively.
@@ -31,12 +28,12 @@
**/
EFI_STATUS
-Minnow3NextMultiPlatformGpioTableInit (
+Minnow3ModuleMultiPlatformGpioTableInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
- DEBUG ((DEBUG_INFO, "Minnow3NextMultiPlatformGpioTableInit()...\n"));
+ DEBUG ((DEBUG_INFO, "%a()...\n", __FUNCTION__));
DEBUG ((DEBUG_INFO, "PlatformInfoHob->BoardId: 0x%02X\n", PlatformInfoHob->BoardId));
//
@@ -45,18 +42,18 @@ Minnow3NextMultiPlatformGpioTableInit (
switch (PlatformInfoHob->BoardId) {
case BOARD_ID_LFH_CRB:
case BOARD_ID_MINNOW:
- case BOARD_ID_MINNOW_NEXT:
+ case BOARD_ID_MINNOW_MODULE:
case BOARD_ID_BENSON:
- PlatformInfoHob->PlatformGpioSetting_SW = &mMinnow3Next_GpioInitData_SW[0];
- PlatformInfoHob->PlatformGpioSetting_W = &mMinnow3Next_GpioInitData_W[0];
- PlatformInfoHob->PlatformGpioSetting_NW = &mMinnow3Next_GpioInitData_NW[0];
- PlatformInfoHob->PlatformGpioSetting_N = &mMinnow3Next_GpioInitData_N[0];
+ PlatformInfoHob->PlatformGpioSetting_SW = &mMinnow3Module_GpioInitData_SW[0];
+ PlatformInfoHob->PlatformGpioSetting_W = &mMinnow3Module_GpioInitData_W[0];
+ PlatformInfoHob->PlatformGpioSetting_NW = &mMinnow3Module_GpioInitData_NW[0];
+ PlatformInfoHob->PlatformGpioSetting_N = &mMinnow3Module_GpioInitData_N[0];
break;
default:
- PlatformInfoHob->PlatformGpioSetting_SW = &mMinnow3Next_GpioInitData_SW[0];
- PlatformInfoHob->PlatformGpioSetting_W = &mMinnow3Next_GpioInitData_W[0];
- PlatformInfoHob->PlatformGpioSetting_NW = &mMinnow3Next_GpioInitData_NW[0];
- PlatformInfoHob->PlatformGpioSetting_N = &mMinnow3Next_GpioInitData_N[0];
+ PlatformInfoHob->PlatformGpioSetting_SW = &mMinnow3Module_GpioInitData_SW[0];
+ PlatformInfoHob->PlatformGpioSetting_W = &mMinnow3Module_GpioInitData_W[0];
+ PlatformInfoHob->PlatformGpioSetting_NW = &mMinnow3Module_GpioInitData_NW[0];
+ PlatformInfoHob->PlatformGpioSetting_N = &mMinnow3Module_GpioInitData_N[0];
break;
}
@@ -69,11 +66,11 @@ Minnow3NextMultiPlatformGpioTableInit (
**/
VOID
-Minnow3NextSetGpioPadCfgLock (
+Minnow3ModuleSetGpioPadCfgLock (
VOID
)
{
- UINT32 Data32;
+ UINT32 Data32;
Data32 = 0;
@@ -118,15 +115,15 @@ Minnow3NextSetGpioPadCfgLock (
// SMBus
// Set SMBus GPIO PAD_CFG.PADRSTCFG to Powergood
//
- Data32 = GpioPadRead (SW_SMB_ALERTB);
+ Data32 = GpioPadRead (SW_SMB_ALERTB);
Data32 &= ~(BIT31 | BIT30);
GpioPadWrite (SW_SMB_ALERTB, Data32);
- Data32 = GpioPadRead (SW_SMB_CLK);
+ Data32 = GpioPadRead (SW_SMB_CLK);
Data32 &= ~(BIT31 | BIT30);
GpioPadWrite (SW_SMB_CLK, Data32);
- Data32 = GpioPadRead (SW_SMB_DATA);
+ Data32 = GpioPadRead (SW_SMB_DATA);
Data32 &= ~(BIT31 | BIT30);
GpioPadWrite (SW_SMB_DATA, Data32);
@@ -135,9 +132,8 @@ Minnow3NextSetGpioPadCfgLock (
GpioLockPadCfg (SW_SMB_DATA);
}
-
/**
- Returns the Correct GPIO table for Mobile/Desktop respectively.
+ Programs the GPIOs according to the platform.
Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.
@param[in] PeiServices General purpose services available to every PEIM.
@@ -148,7 +144,7 @@ Minnow3NextSetGpioPadCfgLock (
**/
EFI_STATUS
-Minnow3NextMultiPlatformGpioProgram (
+Minnow3ModuleMultiPlatformGpioProgram (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
@@ -157,93 +153,62 @@ Minnow3NextMultiPlatformGpioProgram (
EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
SYSTEM_CONFIGURATION SystemConfiguration;
- VariableSize = sizeof (SYSTEM_CONFIGURATION);
- ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
-
- (*PeiServices)->LocatePpi (
- PeiServices,
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- (VOID **) &VariableServices
- );
-
- VariableServices->GetVariable (
- VariableServices,
- PLATFORM_SETUP_VARIABLE_NAME,
- &gEfiSetupVariableGuid,
- NULL,
- &VariableSize,
- &SystemConfiguration
- );
-
- DEBUG ((DEBUG_INFO, "MultiPlatformGpioProgram()...\n"));
-
- switch (PlatformInfoHob->BoardId) {
- case BOARD_ID_LFH_CRB:
- case BOARD_ID_MINNOW:
- case BOARD_ID_MINNOW_NEXT:
- case BOARD_ID_BENSON:
- //
- // PAD programming
- //
- DEBUG ((DEBUG_INFO, "PAD programming, Board ID: 0x%X\n", PlatformInfoHob->BoardId));
-
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_N) / sizeof (mMinnow3Next_GpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
-
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_NW) / sizeof (mMinnow3Next_GpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
-
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_W) / sizeof (mMinnow3Next_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
-
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_SW) / sizeof (mMinnow3Next_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUNCTION__, __LINE__));
- break;
- default:
- //
- // PAD programming
- //
- DEBUG ((DEBUG_INFO, "No board ID available for this board ....\n"));
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_N) / sizeof (mMinnow3Next_GpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_NW) / sizeof (mMinnow3Next_GpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_W) / sizeof (mMinnow3Next_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
- GpioPadConfigTable (sizeof (mMinnow3Next_GpioInitData_SW) / sizeof (mMinnow3Next_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
- break;
- }
-
- DEBUG ((DEBUG_INFO, "PAD programming done\n"));
+ if (PlatformInfoHob->BoardId != BOARD_ID_MINNOW_MODULE) {
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - This is not a Minnow Board 3 Module\n", __FUNCTION__, __LINE__));
+ } else {
+ //
+ // Get setup data
+ //
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
+ (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+ VariableServices->GetVariable (
+ VariableServices,
+ PLATFORM_SETUP_VARIABLE_NAME,
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ &SystemConfiguration
+ );
+ //
+ // PAD programming
+ //
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - PAD programming, Board ID: 0x%X\n", __FUNCTION__, __LINE__, PlatformInfoHob->BoardId));
+ GpioPadConfigTable (sizeof (mMinnow3Module_GpioInitData_N) / sizeof (mMinnow3Module_GpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
+ GpioPadConfigTable (sizeof (mMinnow3Module_GpioInitData_NW) / sizeof (mMinnow3Module_GpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
+ GpioPadConfigTable (sizeof (mMinnow3Module_GpioInitData_W) / sizeof (mMinnow3Module_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
+ GpioPadConfigTable (sizeof (mMinnow3Module_GpioInitData_SW) / sizeof (mMinnow3Module_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - PAD programming done\n", __FUNCTION__, __LINE__));
- //
- // Dump Community registers
- //
- DumpGpioCommunityRegisters (NORTH);
- DumpGpioCommunityRegisters (NORTHWEST);
- DumpGpioCommunityRegisters (WEST);
- DumpGpioCommunityRegisters (SOUTHWEST);
+ //
+ // Dump Community registers
+ //
+ DumpGpioCommunityRegisters (NORTH);
+ DumpGpioCommunityRegisters (NORTHWEST);
+ DumpGpioCommunityRegisters (WEST);
+ DumpGpioCommunityRegisters (SOUTHWEST);
- switch (PlatformInfoHob->BoardId) {
- case BOARD_ID_LFH_CRB:
- case BOARD_ID_MINNOW:
- case BOARD_ID_MINNOW_NEXT:
- case BOARD_ID_BENSON:
- //
- // PAD programming
- //
- DEBUG ((DEBUG_INFO, "Dump Community pad registers, Board ID: 0x%X\n", PlatformInfoHob->BoardId));
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_N) / sizeof (mMinnow3Next_GpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_NW) / sizeof (mMinnow3Next_GpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_W) / sizeof (mMinnow3Next_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_SW) / sizeof (mMinnow3Next_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
- break;
- default:
//
- // Dump Community pad registers
+ // Dump GPIO tables
//
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_N) / sizeof (mMinnow3Next_GpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_NW) / sizeof (mMinnow3Next_GpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_W) / sizeof (mMinnow3Next_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
- DumpGpioPadTable (sizeof (mMinnow3Next_GpioInitData_SW) / sizeof (mMinnow3Next_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - Dump Community pad registers, Board ID: 0x%X\n", __FUNCTION__, __LINE__, PlatformInfoHob->BoardId));
+ DumpGpioPadTable (sizeof (mMinnow3Module_GpioInitData_N) / sizeof (mMinnow3Module_GpioInitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N);
+ DumpGpioPadTable (sizeof (mMinnow3Module_GpioInitData_NW) / sizeof (mMinnow3Module_GpioInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW);
+ DumpGpioPadTable (sizeof (mMinnow3Module_GpioInitData_W) / sizeof (mMinnow3Module_GpioInitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W);
+ DumpGpioPadTable (sizeof (mMinnow3Module_GpioInitData_SW) / sizeof (mMinnow3Module_GpioInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW);
- break;
+ //
+ // Now program any EEPROM defined GPIOs
+ //
+ EepromProgramGpioPads ();
}
return EFI_SUCCESS;
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.h
index 818001a..754b3c5 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardGpios.h
@@ -1,7 +1,7 @@
/** @file
GPIO setting for Broxton.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -13,17 +13,17 @@
**/
-#ifndef _MINNOW3_NEXT_BOARDGPIOS_H_
-#define _MINNOW3_NEXT_BOARDGPIOS_H_
+#ifndef _MINNOW3_MODULE_BOARDGPIOS_H_
+#define _MINNOW3_MODULE_BOARDGPIOS_H_
#include <PiPei.h>
-#include"ChipsetAccess.h"
-#include"PlatformBaseAddresses.h"
+#include "ChipsetAccess.h"
+#include "PlatformBaseAddresses.h"
#include "BoardInitMiscs.h"
-#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
#include <Library/HobLib.h>
+#include <Library/IoLib.h>
#include <Guid/PlatformInfo_Aplk.h>
-#include <Library/GpioLib.h>
/**
GPIO input pin interrupt type configuration:
@@ -58,7 +58,7 @@ Wake_Enabled:
//
// North Community
//
-BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_N[] =
+BXT_GPIO_PAD_INIT mMinnow3Module_GpioInitData_N[] =
{
//
// Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm, MMIO_Offset , Community
@@ -146,7 +146,7 @@ BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_N[] =
//
// North West Community
//
-BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_NW [] =
+BXT_GPIO_PAD_INIT mMinnow3Module_GpioInitData_NW [] =
{
//
// Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger, Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset , Community
@@ -233,7 +233,7 @@ BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_NW [] =
//
// West Community
//
-BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_W [] =
+BXT_GPIO_PAD_INIT mMinnow3Module_GpioInitData_W [] =
{
//
// Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset , Community
@@ -290,7 +290,7 @@ BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_W [] =
//
// South West Community
//
-BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_SW[]=
+BXT_GPIO_PAD_INIT mMinnow3Module_GpioInitData_SW[]=
{
//
// Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IOSTerm, MMIO_Offset , Community
@@ -338,7 +338,7 @@ BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_SW[]=
BXT_GPIO_PAD_CONF(L"LPC_FRAMEB", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,DisPuPd, GPIO_PADBAR+0x0150, SOUTHWEST), // LPC_FRAME#
};
-BXT_GPIO_PAD_INIT mMinnow3Next_GpioInitData_FAB2[] =
+BXT_GPIO_PAD_INIT mMinnow3Module_GpioInitData_FAB2[] =
{
//
// Group Pin#: pad_name, PMode,GPIO_Config,HostSw,GPO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, IOSTerm, MMIO_Offset ,Community
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c
index cafc777..e075486 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c
@@ -1,7 +1,7 @@
/** @file
Board Init driver.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -25,20 +25,20 @@
EFI_STATUS
EFIAPI
-MinnowBoard3NextPostMemInitCallback (
+MinnowBoard3ModulePostMemInitCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
);
-static EFI_PEI_NOTIFY_DESCRIPTOR mMinnowBoard3NextPostMemNotifyList = {
+static EFI_PEI_NOTIFY_DESCRIPTOR mMinnowBoard3ModulePostMemNotifyList = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gBoardPostMemInitStartGuid,
- MinnowBoard3NextPostMemInitCallback
+ MinnowBoard3ModulePostMemInitCallback
};
-static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPostMemDonePpi = {
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3ModulePostMemDonePpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gBoardPostMemInitDoneGuid,
NULL
@@ -46,7 +46,7 @@ static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPostMemDonePpi = {
EFI_STATUS
EFIAPI
-MinnowBoard3NextPostMemInitCallback (
+MinnowBoard3ModulePostMemInitCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
@@ -97,7 +97,7 @@ MinnowBoard3NextPostMemInitCallback (
BoardId = (UINT8) PcdGet8 (PcdBoardId);
FabId = (UINT8) PcdGet8 (PcdFabId);
DEBUG ((EFI_D_INFO, "PostMemInit: BoardId == 0x%X, FabId == 0x%X\n", BoardId, FabId));
- if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+ if (BoardId != (UINT8) BOARD_ID_MINNOW_MODULE) {
DEBUG ((EFI_D_INFO, "Minnow Board 3 Next Post Mem Init callback: Skip\n"));
return EFI_SUCCESS;
}
@@ -107,7 +107,7 @@ MinnowBoard3NextPostMemInitCallback (
//
// Set init function PCD
//
- PcdSet64 (PcdBoardPostMemInitFunc, (UINT64) (UINTN) Minnow3NextMultiPlatformInfoInit);
+ PcdSet64 (PcdBoardPostMemInitFunc, (UINT64) (UINTN) Minnow3ModuleMultiPlatformInfoInit);
//
// Set Reset Type according to different Board
@@ -119,7 +119,7 @@ MinnowBoard3NextPostMemInitCallback (
// Board specific VBT table.
//
BufferSize = sizeof (EFI_GUID);
- PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiMinnow3NextVbtGuid);
+ PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiMinnow3ModuleVbtGuid);
//
// Set PcdeMMCHostMaxSpeed
@@ -138,7 +138,7 @@ MinnowBoard3NextPostMemInitCallback (
//
// Install a flag signalling a board's post mem init is done
//
- Status = PeiServicesInstallPpi (&mMinnowBoard3NextPostMemDonePpi);
+ Status = PeiServicesInstallPpi (&mMinnowBoard3ModulePostMemDonePpi);
return EFI_SUCCESS;
}
@@ -154,17 +154,17 @@ MinnowBoard3NextPostMemInitCallback (
**/
EFI_STATUS
EFIAPI
-MinnowBoard3NextInitConstructor (
+MinnowBoard3ModuleInitConstructor (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
- DEBUG ((EFI_D_INFO, "MinnowBoard3Next Post Mem Init Constructor \n"));
+ DEBUG ((EFI_D_INFO, "MinnowBoard3Module Post Mem Init Constructor \n"));
DEBUG ((EFI_D_INFO, "Notify on Post Mem Init Start PPI \n"));
- Status = PeiServicesNotifyPpi (&mMinnowBoard3NextPostMemNotifyList);
+ Status = PeiServicesNotifyPpi (&mMinnowBoard3ModulePostMemNotifyList);
return Status;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.h
index ddae082..053423d 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.h
@@ -2,7 +2,7 @@
GPIO setting for CherryView.
This file includes package header files, library classes.
- Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -14,8 +14,8 @@
**/
-#ifndef _MINNOW3_NEXT_BOARDINIT_H_
-#define _MINNOW3_NEXT_BOARDINIT_H_
+#ifndef _MINNOW3_MODULE_BOARDINIT_H_
+#define _MINNOW3_MODULE_BOARDINIT_H_
#include <PiPei.h>
#include <Library/IoLib.h>
@@ -24,7 +24,7 @@
#include <Guid/PlatformInfo_Aplk.h>
#include <ScRegs/RegsPcu.h>
-VOID Minnow3NextGpioTest (VOID);
+VOID Minnow3ModuleGpioTest (VOID);
#endif
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
index a370291..99e643f 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
@@ -1,7 +1,7 @@
/** @file
This file does Multiplatform initialization.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -25,11 +25,11 @@
**/
VOID
-Minnow3NextGpioGroupTierInit (
+Minnow3ModuleGpioGroupTierInit (
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
{
- DEBUG ((DEBUG_INFO, "Minnow3NextGpioGroupTierInit Start\n"));
+ DEBUG ((DEBUG_INFO, "Minnow3ModuleGpioGroupTierInit Start\n"));
switch (PlatformInfoHob->BoardId) {
default:
GpioSetGroupToGpeDwX (GPIO_BXTP_GROUP_7, // map group 7 to GPE 0 ~ 31
@@ -44,7 +44,7 @@ Minnow3NextGpioGroupTierInit (
EFI_STATUS
EFIAPI
-Minnow3NextMultiPlatformInfoInit (
+Minnow3ModuleMultiPlatformInfoInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
@@ -110,30 +110,35 @@ Minnow3NextMultiPlatformInfoInit (
//
// Get GPIO table
//
- Status = Minnow3NextMultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
+ Status = Minnow3ModuleMultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
ASSERT_EFI_ERROR (Status);
//
// Program GPIO
//
- Status = Minnow3NextMultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
+ Status = Minnow3ModuleMultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
if (GetBxtSeries () == BxtP) {
- Minnow3NextGpioGroupTierInit (PlatformInfoHob);
+ Minnow3ModuleGpioGroupTierInit (PlatformInfoHob);
}
//
// Update OemId
//
- Status = Minnow3NextInitializeBoardOemId (PeiServices, PlatformInfoHob);
- Status = Minnow3NextInitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
+ Status = Minnow3ModuleInitializeBoardOemId (PeiServices, PlatformInfoHob);
+ Status = Minnow3ModuleInitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
+
+ //
+ // TypeC MUX AUX mode
+ //
+ MB3SetupTypecMuxAux ();
return EFI_SUCCESS;
}
EFI_STATUS
-Minnow3NextInitializeBoardOemId (
+Minnow3ModuleInitializeBoardOemId (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
@@ -158,7 +163,7 @@ Minnow3NextInitializeBoardOemId (
}
EFI_STATUS
-Minnow3NextInitializeBoardSsidSvid (
+Minnow3ModuleInitializeBoardSsidSvid (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
)
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.h
index c1ced34..2afeee5 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.h
@@ -2,7 +2,7 @@
Multiplatform initialization header file.
This file includes package header files, library classes.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -14,8 +14,8 @@
**/
-#ifndef _MINNOW_NEXT_MULTIPLATFORM_LIB_H_
-#define _MINNOW_NEXT_MULTIPLATFORM_LIB_H_
+#ifndef _MINNOW_MODULE_MULTIPLATFORM_LIB_H_
+#define _MINNOW_MODULE_MULTIPLATFORM_LIB_H_
#define LEN_64M 0x4000000
//
@@ -27,42 +27,47 @@
#define RES_IO_LIMIT 0xFFFF
#include <PiDxe.h>
-#include <Library/BaseLib.h>
#include <FrameworkPei.h>
+
+#include "CMOSMap.h"
+#include "CpuRegs.h"
+#include "Platform.h"
#include "PlatformBaseAddresses.h"
+#include "PlatformBootMode.h"
#include "ScAccess.h"
#include "SetupMode.h"
-#include "PlatformBootMode.h"
-#include "CpuRegs.h"
-#include "Platform.h"
-#include "CMOSMap.h"
-#include <Ppi/Stall.h>
-#include <Guid/SetupVariable.h>
-#include <Ppi/AtaController.h>
-#include <Ppi/BootInRecoveryMode.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Ppi/Capsule.h>
+#include "TypeC.h"
+
+#include <Guid/Capsule.h>
#include <Guid/EfiVpdData.h>
-#include <Library/DebugLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/FirmwareFileSystem.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/PlatformInfo_Aplk.h>
+#include <Guid/RecoveryDevice.h>
+#include <Guid/SetupVariable.h>
+
+#include <IndustryStandard/Pci22.h>
+
+#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
#include <Library/HobLib.h>
-#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
#include <Library/SteppingLib.h>
-#include <IndustryStandard/Pci22.h>
-#include <Guid/FirmwareFileSystem.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Ppi/Reset.h>
+
+#include <Ppi/AtaController.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Ppi/Capsule.h>
+#include <Ppi/DeviceRecoveryModule.h>
#include <Ppi/EndOfPeiPhase.h>
+#include <Ppi/MasterBootMode.h>
#include <Ppi/MemoryDiscovered.h>
-#include <Guid/GlobalVariable.h>
+#include <Ppi/ReadOnlyVariable2.h>
#include <Ppi/RecoveryModule.h>
-#include <Ppi/DeviceRecoveryModule.h>
-#include <Guid/Capsule.h>
-#include <Guid/RecoveryDevice.h>
-#include <Ppi/MasterBootMode.h>
-#include <Guid/PlatformInfo_Aplk.h>
+#include <Ppi/Reset.h>
+#include <Ppi/Stall.h>
#define EFI_ACPI_OEM_ID_DEFAULT SIGNATURE_64('I', 'N', 'T', 'E', 'L', ' ', ' ', ' ') // max 6 chars
#define EFI_ACPI_OEM_ID1 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '1', ' ', ' ') // max 6 chars
@@ -95,37 +100,37 @@
#define EMMC_DDR50_MODE 0x02
EFI_STATUS
-Minnow3NextGetPlatformInfoHob (
+Minnow3ModuleGetPlatformInfoHob (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
);
EFI_STATUS
-Minnow3NextMultiPlatformGpioTableInit (
+Minnow3ModuleMultiPlatformGpioTableInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
);
EFI_STATUS
-Minnow3NextMultiPlatformGpioProgram (
+Minnow3ModuleMultiPlatformGpioProgram (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
);
EFI_STATUS
-Minnow3NextMultiPlatformInfoInit (
+Minnow3ModuleMultiPlatformInfoInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
);
EFI_STATUS
-Minnow3NextInitializeBoardOemId (
+Minnow3ModuleInitializeBoardOemId (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
);
EFI_STATUS
-Minnow3NextInitializeBoardSsidSvid (
+Minnow3ModuleInitializeBoardSsidSvid (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob
);
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf
index 1a4cc28..9610ce4 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf
@@ -2,7 +2,7 @@
# Board detected module for Intel(R) Atom(TM) x5 Processor Series.
# It will detect the board ID.
#
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -16,11 +16,11 @@
[Defines]
INF_VERSION = 0x00010017
- BASE_NAME = MinnowBoard3NextInitPostMem
+ BASE_NAME = MinnowBoard3ModuleInitPostMem
FILE_GUID = 39D9CFF9-6187-4984-903F-34FF2840EB91
VERSION_STRING = 1.0
MODULE_TYPE = PEIM
- CONSTRUCTOR = MinnowBoard3NextInitConstructor
+ CONSTRUCTOR = MinnowBoard3ModuleInitConstructor
[Sources]
BoardInit.c
@@ -30,11 +30,14 @@
PlatformInfoHob.c
BoardGpios.c
BoardGpios.h
+ TypeC.c
+ TypeC.h
[LibraryClasses]
PeiServicesLib
PcdLib
DebugLib
+ EepromPlatformLib
HeciMsgLib
HobLib
IoLib
@@ -72,11 +75,10 @@
gEfiTpmDeviceInstanceTpm12Guid
gEfiTpmDeviceInstanceTpm20DtpmGuid
gTpmDeviceInstanceTpm20PttPtpGuid
- gPeiMinnow3NextVbtGuid
+ gPeiMinnow3ModuleVbtGuid
[Ppis]
gBoardPostMemInitStartGuid
gBoardPostMemInitDoneGuid
gEfiPeiReadOnlyVariable2PpiGuid
gSeCfTPMPolicyPpiGuid
-
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/PlatformInfoHob.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/PlatformInfoHob.c
index 9b65526..9f0dfc1 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/PlatformInfoHob.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/PlatformInfoHob.c
@@ -1,7 +1,7 @@
/** @file
This file does Multiplatform initialization.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -26,7 +26,7 @@
**/
EFI_STATUS
-Minnow3NextGetPlatformInfoHob (
+Minnow3ModuleGetPlatformInfoHob (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
)
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
new file mode 100644
index 0000000..7b8d56a
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
@@ -0,0 +1,290 @@
+/** @file
+ This file does TypeC initialization.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "TypeC.h"
+
+static MUX_PROGRAMMING_TABLE mMB3MuxTable[] = {
+ // Address Register Data String
+ //====================================================================================
+ {A_GENERAL, R_FIRMWARE_VERSION, MUX_TABLE_NULL, "Firmware Version Number"},
+ {A_STATUS, R_CC_STATUS_1, MUX_TABLE_NULL, "CC_Status_1"},
+ {A_STATUS, R_CC_STATUS_2, MUX_TABLE_NULL, "CC_Status_2"},
+ {A_STATUS, R_CC_STATUS_3, MUX_TABLE_NULL, "CC_Status_3"},
+ {A_STATUS, R_MUX_HPD_ASSERT, MUX_TABLE_NULL, "MUX_In_HPD_Assertion"},
+ {A_STATUS, R_MUX_STATUS, MUX_TABLE_NULL, "MUX Status"},
+ {A_STATUS, R_MUX_DP_TRAINING, MUX_TABLE_NULL, "MUX_DP_Training_Disable"},
+ {A_STATUS, R_MUX_DP_AUX_INTERCEPT, MUX_TABLE_NULL, "MUX_DP_AUX_Interception_Disable"},
+ {A_STATUS, R_MUX_DP_EQ_CONFIG, MUX_TABLE_NULL, "MUX_DP_EQ_Configuration"},
+ {A_STATUS, R_MUX_DP_OUTPUT_CONFIG, MUX_TABLE_NULL, "MUX_DP_Output_Configuration"}
+};
+
+VOID
+MB3PrintChar (
+ IN UINTN DebugMask,
+ IN UINTN Count,
+ IN CHAR16 *Char
+)
+{
+ UINTN Index;
+
+ for (Index = 0; Index < Count; Index++) {
+ DEBUG ((DebugMask, "%s", Char));
+ }
+}
+
+#define DIVIDING_LINE "+----------------------------------------------------+------------------+\n"
+
+VOID
+MB3DumpParagraph (
+ IN UINTN DebugMask,
+ IN VOID *Ptr,
+ IN UINTN Count
+ )
+{
+ CHAR8 AsciiBuffer[17];
+ UINT8 *Data;
+ UINTN Index;
+ UINTN Paragraphs;
+ UINTN PlaceHolder;
+ UINTN PlaceHolders;
+
+ //
+ // Use a different pointer so that the one passed in doesn't change
+ //
+ Data = (UINT8 *) Ptr;
+ //
+ // Calcualte the number of paragraphs
+ //
+ Paragraphs = Count / 16;
+ if ((Paragraphs * 16) < Count) {
+ Paragraphs++;
+ }
+ //
+ // Calculate the number of columns
+ //
+ PlaceHolder = Paragraphs;
+ PlaceHolders = 0;
+ while (PlaceHolder > 0) {
+ PlaceHolders++;
+ PlaceHolder >>= 4;
+ }
+
+ //
+ // Dump the buffer
+ //
+ if (Count > 0 ) {
+ //
+ // Print header
+ //
+ MB3PrintChar (DebugMask, PlaceHolders + 5, L" ");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ MB3PrintChar (DebugMask, PlaceHolders + 5, L" ");
+ DEBUG ((DebugMask, "| x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF | String |\n"));
+ DEBUG ((DebugMask, " +"));
+ MB3PrintChar (DebugMask, PlaceHolders + 3, L"-");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ //
+ // Print data
+ //
+ for (Index = 0; Index < (Paragraphs * 16); Index++) {
+ //
+ // Print divider
+ //
+ if (Index % 0x10 == 0x00) {
+ if ((Index > 0) && ((Index / 0x10) % 0x04 == 0x00) && (Paragraphs > 6)) {
+ DEBUG ((DebugMask, " +"));
+ MB3PrintChar (DebugMask, PlaceHolders + 3, L"-");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ }
+ DEBUG ((DebugMask, " | %0*xx | ", PlaceHolders, (Index / 0x10)));
+ }
+ //
+ // Print the data or a filler
+ //
+ if (Index < Count) {
+ DEBUG ((DebugMask, "%02x ", Data[Index]));
+ if ((Data[Index] < 32) || (Data[Index] > 126)) {
+ //
+ // Not printable
+ //
+ AsciiBuffer[(Index % 0x10)] = '.';
+ } else {
+ //
+ // Printable
+ //
+ AsciiBuffer[(Index % 0x10)] = Data[Index];
+ }
+ } else {
+ DEBUG ((DebugMask, " "));
+ AsciiBuffer[(Index % 0x10)] = ' ';
+ }
+ //
+ // Print break or line end if needed
+ //
+ if (Index % 0x10 == 0x0F) {
+ AsciiBuffer[16] = 0x00;
+ DEBUG ((DebugMask, "| %a |\n", AsciiBuffer));
+ } else if (Index % 0x04 == 0x03) {
+ DEBUG ((DebugMask, " "));
+ }
+ }
+ //
+ // Print footer
+ //
+ DEBUG ((DebugMask, " +"));
+ MB3PrintChar (DebugMask, PlaceHolders + 3, L"-");
+ DEBUG ((DebugMask, DIVIDING_LINE));
+ }
+}
+
+EFI_STATUS
+EFIAPI
+MB3ReadMux (
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ OUT UINT8 *Data
+ )
+{
+ UINT8 RetryCount;
+ EFI_STATUS Status;
+
+ RetryCount = MUX_RETRY_COUNT;
+ do {
+ *Data = 0x00;
+ Status = ByteReadI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
+ } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+MB3WriteMux (
+ IN UINT8 SlaveAddress,
+ IN UINT8 Offset,
+ OUT UINT8 *Data
+ )
+{
+ UINT8 RetryCount;
+ EFI_STATUS Status;
+
+ RetryCount = MUX_RETRY_COUNT;
+ do {
+ Status = ByteWriteI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
+ } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
+
+ return Status;
+}
+
+VOID
+MB3DumpMux (
+ VOID
+ )
+{
+ UINT8 Data[256];
+ UINT16 Offset;
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT8 SlaveAddress;
+ EFI_STATUS Status;
+
+ //
+ // Loop thru device and dump it all
+ //
+ DEBUG ((DEBUG_INFO, "\n%a(#%4d) - Dump the PS8750 I2C data\n", __FUNCTION__, __LINE__));
+ for (SlaveAddress = 0x08; SlaveAddress <= 0x0E; SlaveAddress++) {
+ for (Offset = 0x00; Offset <= 0xFF; Offset++) {
+ Status = MB3ReadMux (SlaveAddress, (UINT8) Offset, &Data[Offset]);
+ if (EFI_ERROR (Status)) Data[Offset] = 0xFF;
+ }
+ DEBUG ((DEBUG_INFO, "\nSlaveAddress = 0x%02x\n", (SlaveAddress << 1)));
+ MB3DumpParagraph (DEBUG_INFO, Data, 256);
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+ padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d RxInv = %d\n\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
+}
+
+EFI_STATUS
+EFIAPI
+MB3SetupTypecMuxAux (
+ VOID
+ )
+{
+ UINT8 Data8;
+ UINTN index;
+ MUX_DATA_TABLE MuxData;
+ BXT_CONF_PAD0 padConfg0;
+ BXT_CONF_PAD1 padConfg1;
+ UINT8 *Ptr;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...[0x%02x]\n", __FUNCTION__, __LINE__, PARADE_MUX_ADDRESS));
+
+ //
+ // Read/write MUX info
+ //
+ Ptr = (UINT8 *) &MuxData;
+ for (index = 0; index < (sizeof (mMB3MuxTable) / sizeof (mMB3MuxTable[0])); index++) {
+ Status = MB3ReadMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mMB3MuxTable[index].String, (mMB3MuxTable[index].Address << 1), mMB3MuxTable[index].Register, Data8, Status));
+ Ptr[index] = Data8;
+ if ((mMB3MuxTable[index].Data != MUX_TABLE_NULL) && (!EFI_ERROR (Status))) {
+ Data8 = (UINT8) (mMB3MuxTable[index].Data & 0x00FF);
+ Status = MB3WriteMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a(#%4d) - ERROR: ByteWriteI2C returned %r for %a = 0x%02x\n", __FUNCTION__, __LINE__, Status, mMB3MuxTable[index].String, Data8));
+ } else {
+ Status = MB3ReadMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mMB3MuxTable[index].String, (mMB3MuxTable[index].Address << 1), mMB3MuxTable[index].Register, Data8, Status));
+ Ptr[index] = Data8;
+ }
+ }
+ }
+
+ //
+ // Display HPD
+ //
+ padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
+
+ //
+ // See if we need to assert the HPD on the MUX
+ //
+ if ((MuxData.MuxStatus & BIT7) == BIT7) {
+ //
+ // We are in DP mode
+ //
+ if ((MuxData.HpdAssert & BIT7) != BIT7) {
+ //
+ // We need to assert the MUX HPD
+ //
+ Data8 = MuxData.HpdAssert | BIT7;
+ Status = MB3WriteMux (A_STATUS, R_MUX_HPD_ASSERT, &Data8);
+
+ //
+ // Display HPD
+ //
+ padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
+ padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
+ DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
new file mode 100644
index 0000000..0664158
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
@@ -0,0 +1,88 @@
+/** @file
+ Multiplatform initialization header file.
+ This file includes package header files, library classes.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MB3M_TYPEC_LIB_H_
+#define _MB3M_TYPEC_LIB_H_
+
+#include <PiDxe.h>
+#include <FrameworkPei.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Library/I2cLib.h>
+
+//
+// Parade Tech PS8750 TypeC MUX
+//
+#define PARADE_MUX_I2C_BUS 0x07
+#define PARADE_MUX_ADDRESS 0x50 // 0x10, 0x30, 0x50, 0x90
+#define A_GENERAL (PARADE_MUX_ADDRESS >> 1)
+#define R_FIRMWARE_VERSION 0x90
+#define A_STATUS (A_GENERAL + 0x01)
+#define R_DP_AUX_SNOOP_BW 0x10
+#define R_DP_AUX_SNOOP_LC 0x11
+#define R_DP_AUX_SNOOP_L0 0x12
+#define R_DP_AUX_SNOOP_L1 0x13
+#define R_DP_AUX_SNOOP_L2 0x14
+#define R_DP_AUX_SNOOP_L3 0x15
+#define R_DP_AUX_SNOOP_D3 0x1E
+#define R_MUX_STATUS 0x80
+#define R_MUX_DP_TRAINING 0x83
+#define R_MUX_DP_AUX_INTERCEPT 0x85
+#define R_MUX_DP_EQ_CONFIG 0x86
+#define R_MUX_DP_OUTPUT_CONFIG 0x87
+#define R_MUX_HPD_ASSERT 0xBC
+#define R_CC_STATUS_1 0xEC
+#define R_CC_STATUS_2 0xED
+#define R_CC_STATUS_3 0xEE
+#define MUX_TABLE_NULL 0xFFFF
+#define MUX_RETRY_COUNT 0x03
+#define MUX_TABLE_STRING_LENGTH 32
+
+#define MUX_HPD_GPIO NW_GPIO_200
+
+typedef struct {
+ UINT8 Address;
+ UINT8 Register;
+ UINT16 Data;
+ CHAR8 String[MUX_TABLE_STRING_LENGTH];
+} MUX_PROGRAMMING_TABLE;
+
+typedef struct {
+ //
+ // These UINT8 elements need to match the MUX_PROGRAMMING_TABLE list so we can use the Index to reference them
+ //
+ UINT8 FirmwareVersion; // Offset 0
+ UINT8 CcStatus1; // Offset 1
+ UINT8 CcStatus2; // Offset 2
+ UINT8 CcStatus3; // Offset 3
+ UINT8 MuxStatus; // Offset 4
+ UINT8 HpdAssert; // Offset 5
+ UINT8 DpTraining; // Offset 6
+ UINT8 DpAuxIntercept; // Offset 7
+ UINT8 DpEqConfig; // Offset 8
+ UINT8 DpOutputConfig; // Offset 9
+} MUX_DATA_TABLE;
+
+EFI_STATUS
+EFIAPI
+MB3SetupTypecMuxAux (
+ VOID
+ );
+
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInit.c
index a3a0cd8..649e69d 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInit.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInit.c
@@ -1,7 +1,7 @@
/** @file
Board Init driver.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -26,22 +26,22 @@
EFI_STATUS
EFIAPI
-MinnowBoard3NextPreMemInit (
+MinnowBoard3ModulePreMemInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN PEI_BOARD_PRE_MEM_INIT_PPI *This
);
-static PEI_BOARD_PRE_MEM_INIT_PPI mMinnow3NextPreMemInitPpiInstance = {
- MinnowBoard3NextPreMemInit
+static PEI_BOARD_PRE_MEM_INIT_PPI mMinnow3ModulePreMemInitPpiInstance = {
+ MinnowBoard3ModulePreMemInit
};
-static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitPpi = {
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3ModulePreMemInitPpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gBoardPreMemInitPpiGuid,
- &mMinnow3NextPreMemInitPpiInstance
+ &mMinnow3ModulePreMemInitPpiInstance
};
-static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitDonePpi = {
+static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3ModulePreMemInitDonePpi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gBoardPreMemInitDoneGuid,
NULL
@@ -49,7 +49,7 @@ static EFI_PEI_PPI_DESCRIPTOR mMinnowBoard3NextPreMemInitDonePpi = {
EFI_STATUS
EFIAPI
-MinnowBoard3NextPreMemInit (
+MinnowBoard3ModulePreMemInit (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN PEI_BOARD_PRE_MEM_INIT_PPI *This
)
@@ -76,9 +76,9 @@ MinnowBoard3NextPreMemInit (
//
// Pre Mem Board Init
//
- Status = Minnow3NextGetEmbeddedBoardIdFabId (PeiServices, &BoardId, &FabId);
+ Status = Minnow3ModuleGetEmbeddedBoardIdFabId (PeiServices, &BoardId, &FabId);
- if (BoardId != (UINT8) BOARD_ID_MINNOW_NEXT) {
+ if (BoardId != (UINT8) BOARD_ID_MINNOW_MODULE) {
return EFI_SUCCESS;
}
@@ -86,22 +86,22 @@ MinnowBoard3NextPreMemInit (
PcdSet8 (PcdBoardId, BoardId);
PcdSet8 (PcdFabId, FabId);
-
+
//
//PcdSet8 (PcdSerialIoUartNumber, 0);
//
-
+
//
// Set board specific function as dynamic PCD to be called by common platform code
//
- PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mMb3NUpdateFspmUpdPtr);
- PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mMb3NDramCreatePolicyDefaultsPtr);
- PcdSet64 (PcdUpdatePcieConfigFunc, (UINT64) (UINTN) mMb3NUpdatePcieConfigPtr);
+ PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mMb3MUpdateFspmUpdPtr);
+ PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mMb3MDramCreatePolicyDefaultsPtr);
+ PcdSet64 (PcdUpdatePcieConfigFunc, (UINT64) (UINTN) mMb3MUpdatePcieConfigPtr);
//
// Install a flag signalling a board is detected and pre-mem init is done
//
- Status = PeiServicesInstallPpi (&mMinnowBoard3NextPreMemInitDonePpi);
+ Status = PeiServicesInstallPpi (&mMinnowBoard3ModulePreMemInitDonePpi);
return EFI_SUCCESS;
}
@@ -117,7 +117,7 @@ MinnowBoard3NextPreMemInit (
**/
EFI_STATUS
EFIAPI
-MinnowBoard3NextInitConstructor (
+MinnowBoard3ModuleInitConstructor (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
@@ -127,7 +127,7 @@ MinnowBoard3NextInitConstructor (
EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor;
UINTN Instance;
- DEBUG ((EFI_D_INFO, "MinnowBoard3Next Pre Mem Init Constructor \n"));
+ DEBUG ((EFI_D_INFO, "MinnowBoard3Module Pre Mem Init Constructor \n"));
Status = PeiServicesLocatePpi (
&gBoardPreMemInitDoneGuid,
@@ -146,7 +146,7 @@ MinnowBoard3NextInitConstructor (
DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init Done PPI\n"));
Status = PeiServicesReInstallPpi (
PeiPpiDescriptor,
- &mMinnowBoard3NextPreMemInitDonePpi
+ &mMinnowBoard3ModulePreMemInitDonePpi
);
ASSERT_EFI_ERROR (Status);
@@ -173,7 +173,7 @@ MinnowBoard3NextInitConstructor (
DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init PPI\n"));
Status = PeiServicesReInstallPpi (
PeiPpiDescriptor,
- &mMinnowBoard3NextPreMemInitPpi
+ &mMinnowBoard3ModulePreMemInitPpi
);
ASSERT_EFI_ERROR (Status);
@@ -183,7 +183,7 @@ MinnowBoard3NextInitConstructor (
}
DEBUG ((EFI_D_INFO, "Install Pre Mem Init PPI \n"));
- Status = PeiServicesInstallPpi (&mMinnowBoard3NextPreMemInitPpi);
+ Status = PeiServicesInstallPpi (&mMinnowBoard3ModulePreMemInitPpi);
return Status;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.c
index 888b316..8d8db81 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.c
@@ -1,7 +1,7 @@
/** @file
This file does Multiplatform initialization.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,32 +15,42 @@
#include "BoardInitMiscs.h"
-UPDATE_FSPM_UPD_FUNC mMb3NUpdateFspmUpdPtr = Mb3NUpdateFspmUpd;
-DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3NDramCreatePolicyDefaultsPtr = Mb3NDramCreatePolicyDefaults;
-UPDATE_PCIE_CONFIG_FUNC mMb3NUpdatePcieConfigPtr = Mb3NUpdatePcieConfig;
+UPDATE_FSPM_UPD_FUNC mMb3MUpdateFspmUpdPtr = Mb3MUpdateFspmUpd;
+DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3MDramCreatePolicyDefaultsPtr = Mb3MDramCreatePolicyDefaults;
+UPDATE_PCIE_CONFIG_FUNC mMb3MUpdatePcieConfigPtr = Mb3MUpdatePcieConfig;
//
-// Minnow Board Next swizzling
+// Minnow Board Module, Fab A swizzling
//
-UINT8 ChSwizzle_MB3N[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = {
+UINT8 ChSwizzle_MB3Ma[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = {
{0x00,0x06,0x04,0x05,0x01,0x03,0x02,0x07,0x08,0x09,0x0B,0x0F,0x0A,0x0D,0x0C,0x0E,0x1C,0x18,0x1A,0x1B,0x1D,0x1E,0x1F,0x19,0x12,0x13,0x14,0x11,0x10,0x16,0x17,0x15}, // Channel 0
{0x0E,0x0F,0x0A,0x0B,0x08,0x0D,0x0C,0x09,0x07,0x04,0x05,0x00,0x01,0x03,0x02,0x06,0x12,0x15,0x14,0x17,0x10,0x13,0x11,0x16,0x1D,0x1C,0x1F,0x1B,0x1A,0x19,0x18,0x1E}, // Channel 1
{0x0B,0x0D,0x0C,0x0F,0x09,0x08,0x0A,0x0E,0x05,0x06,0x03,0x07,0x00,0x01,0x02,0x04,0x17,0x11,0x10,0x13,0x14,0x16,0x15,0x12,0x19,0x1B,0x1A,0x18,0x1C,0x1D,0x1E,0x1F}, // Channel 2
{0x07,0x01,0x02,0x03,0x04,0x05,0x06,0x00,0x0E,0x0D,0x0B,0x0C,0x0A,0x08,0x0F,0x09,0x1E,0x18,0x1C,0x1D,0x1A,0x19,0x1B,0x1F,0x14,0x11,0x12,0x16,0x13,0x15,0x17,0x10} // Channel 3
};
-BOARD_CHANNEL_INFO gMb3nChannelInfo[] = {
+//
+// Minnow Board Module, Fab C swizzling
+//
+UINT8 ChSwizzle_MB3Mc[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = {
+ {0x0F,0x0A,0x09,0x08,0x0E,0x0C,0x0D,0x0B,0x01,0x05,0x06,0x04,0x02,0x03,0x00,0x07,0x1C,0x18,0x1A,0x1B,0x1D,0x1E,0x1F,0x19,0x12,0x13,0x14,0x11,0x10,0x16,0x17,0x15}, // Channel 0
+ {0x0E,0x0F,0x0A,0x0B,0x08,0x0D,0x0C,0x09,0x07,0x04,0x05,0x00,0x01,0x03,0x02,0x06,0x1C,0x18,0x1B,0x1A,0x1F,0x1E,0x1D,0x19,0x15,0x16,0x14,0x17,0x10,0x12,0x11,0x13}, // Channel 1
+ {0x07,0x00,0x02,0x03,0x06,0x05,0x04,0x01,0x0C,0x0B,0x0F,0x09,0x0A,0x0D,0x0E,0x08,0x17,0x11,0x10,0x13,0x14,0x16,0x15,0x12,0x19,0x1B,0x1A,0x18,0x1C,0x1D,0x1E,0x1F}, // Channel 2
+ {0x07,0x01,0x02,0x03,0x04,0x05,0x06,0x00,0x0E,0x0D,0x0B,0x0C,0x0A,0x08,0x0F,0x09,0x10,0x15,0x13,0x11,0x14,0x16,0x17,0x12,0x1A,0x1F,0x1C,0x1B,0x1D,0x19,0x18,0x1E} // Channel 3
+};
+
+BOARD_CHANNEL_INFO gMB3MChannelInfo[] = {
// DeviceWidth DramDensity Option RankEnable DescString
// Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3
- {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x01, 0x01, 0x00, 0x00}, "LPDDR4 8Gbit 2 channels"}, // #1 - LPDDR4 8Gbit 2 channels
- {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x01, 0x01, 0x01, 0x01}, "LPDDR4 8Gbit 4 channels"}, // #2 - LPDDR4 8Gbit 4 channels
- {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x03, 0x03, 0x00, 0x00}, "LPDDR4 16Gbit 2 channels"}, // #3 - LPDDR4 16Gbit 2 channels
- {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x03, 0x03, 0x03, 0x03}, "LPDDR4 16Gbit 4 channels"}, // #4 - LPDDR4 16Gbit 4 channels
+ {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x01, 0x01, 0x00, 0x00}, "LPDDR4 8Gbit 2 channels"}, // #1 - MT53B256M32D1 8Gbit 2 channels
+ {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x01, 0x01, 0x01, 0x01}, "LPDDR4 8Gbit 4 channels"}, // #2 - MT53B256M32D1 8Gbit 4 channels
+ {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x03, 0x03, 0x00, 0x00}, "LPDDR4 16Gbit 2 channels"}, // #3 - MT53B512M32D2 16Gbit 2 channels
+ {{0x01, 0x01, 0x01, 0x01}, {0x02, 0x02, 0x02, 0x02}, {0x03, 0x03, 0x03, 0x03}, {0x03, 0x03, 0x03, 0x03}, "LPDDR4 16Gbit 4 channels"}, // #4 - MT53B512M32D2 16Gbit 4 channels
};
EFI_STATUS
EFIAPI
-Mb3NUpdateFspmUpd (
+Mb3MUpdateFspmUpd (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN FSPM_UPD *FspUpdRgn
)
@@ -68,7 +78,9 @@ Mb3NUpdateFspmUpd (
(VOID **) &DramPolicy
);
- if (!EFI_ERROR (Status)) {
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "%a() - LocatePpi(gDramPolicyPpiGuid) returned %r\n", __FUNCTION__, Status));
+ } else {
FspUpdRgn->FspmConfig.Package = DramPolicy->Package;
FspUpdRgn->FspmConfig.Profile = DramPolicy->Profile;
FspUpdRgn->FspmConfig.MemoryDown = DramPolicy->MemoryDown;
@@ -100,7 +112,7 @@ Mb3NUpdateFspmUpd (
if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
- DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n"));
+ DEBUG ((DEBUG_INFO, "%a() - NvsBufferPtr\n", __FUNCTION__));
MrcNvData = (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool (sizeof (MRC_PARAMS_SAVE_RESTORE));
BootVariableNvData = (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (sizeof (BOOT_VARIABLE_NV_DATA));
@@ -112,11 +124,9 @@ Mb3NUpdateFspmUpd (
FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
FspUpdRgn->FspmConfig.VariableNvsBufferPtr = (VOID *)(UINT32)BootVariableNvData;
}
- } else {
- DEBUG ((DEBUG_INFO, "UpdateFspmUpd - LocatePpi(gDramPolicyPpiGuid) returned %r\n", Status));
}
- DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
+ DEBUG ((DEBUG_INFO, "%a() - gEfiPlatformInfoGuid\n", __FUNCTION__));
Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
ASSERT (Hob.Raw != NULL);
PlatformInfo = GET_GUID_HOB_DATA (Hob.Raw);
@@ -129,16 +139,16 @@ Mb3NUpdateFspmUpd (
//
// E3950 path
//
- DEBUG ((DEBUG_INFO, "**** MB3N - E3950 detected!\n"));
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - E3950 detected!\n"));
} else if (VidDid == 0x5A858086) {
//
// E3930 path
//
- DEBUG ((DEBUG_INFO, "**** MB3N - E3930 detected!\n"));
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - E3930 detected!\n"));
}
//
- // Overrides for MinnowBoard3Next from Platfrom4 profile
+ // Overrides for MinnowBoard3Module from Platfrom4 profile
//
// Description | DualRank | RankEnable | DeviceWidth | DramDenisty | SoC | Channel
// ================|==========|============|=============|=============|=======|=========
@@ -150,16 +160,20 @@ Mb3NUpdateFspmUpd (
//
// Get HWCONF straps
//
- HwconfStraps = Minnow3NextGetHwconfStraps ();
- DEBUG ((DEBUG_INFO, "**** MB3N - HWCONF straps = 0x%08X\n", HwconfStraps));
+ HwconfStraps = Minnow3ModuleGetHwconfStraps ();
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - HWCONF straps = 0x%08X\n", HwconfStraps));
//
// Translate into Memory Type
//
- MemoryType = (UINT8) ((HwconfStraps >> 6) & 0x07);
+ MemoryType = (UINT8) ((HwconfStraps & HWCONF_MEMORY_MASK) >> HWCONF_MEMORY);
if (MemoryType == 0) {
- DEBUG ((DEBUG_INFO, "**** MB3N - SPD based memory init requested, but converted into Memory Profile type #4!\n"));
- MemoryType = 4;
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - SPD based memory init requested, but converted into Memory Profile type #4!\n"));
+ MemoryType = 4; // LPDDR4 16Gbit 4 channels
+ }
+ if (MemoryType == 5) {
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - EEPROM based memory init requested, but converted into Memory Profile type #4!\n"));
+ MemoryType = 4; // LPDDR4 16Gbit 4 channels
}
MemoryType--; // Zero base it for use as index into array
@@ -167,51 +181,58 @@ Mb3NUpdateFspmUpd (
// Common items
//
FspUpdRgn->FspmConfig.Package = 0x01;
- FspUpdRgn->FspmConfig.Profile = 0x09; // 0x0B; // LPDDR4_2400_24_22_22
+ FspUpdRgn->FspmConfig.Profile = 0x09; // LPDDR4_1600_14_15_15
+// FspUpdRgn->FspmConfig.Profile = 0x0B; // LPDDR4_2400_24_22_22
FspUpdRgn->FspmConfig.MemoryDown = 0x01;
FspUpdRgn->FspmConfig.DualRankSupportEnable = 0x01;
//
// Memory Type specific items
//
- if (MemoryType < (sizeof (gMb3nChannelInfo) / sizeof (gMb3nChannelInfo[0]))) {
- DEBUG ((DEBUG_INFO, "**** MB3N - %a detected!\n", gMb3nChannelInfo[MemoryType].DescString));
+ if (MemoryType < (sizeof (gMB3MChannelInfo) / sizeof (gMB3MChannelInfo[0]))) {
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - %a detected!\n", gMB3MChannelInfo[MemoryType].DescString));
// DDR0CH0
- FspUpdRgn->FspmConfig.Ch0_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[0];
- FspUpdRgn->FspmConfig.Ch0_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[0];
- FspUpdRgn->FspmConfig.Ch0_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[0];
- FspUpdRgn->FspmConfig.Ch0_Option = gMb3nChannelInfo[MemoryType].Option[0];
+ FspUpdRgn->FspmConfig.Ch0_RankEnable = gMB3MChannelInfo[MemoryType].RankEnable[0];
+ FspUpdRgn->FspmConfig.Ch0_DeviceWidth = gMB3MChannelInfo[MemoryType].DeviceWidth[0];
+ FspUpdRgn->FspmConfig.Ch0_DramDensity = gMB3MChannelInfo[MemoryType].DramDensity[0];
+ FspUpdRgn->FspmConfig.Ch0_Option = gMB3MChannelInfo[MemoryType].Option[0];
// DDR0CH1
- FspUpdRgn->FspmConfig.Ch1_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[1];
- FspUpdRgn->FspmConfig.Ch1_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[1];
- FspUpdRgn->FspmConfig.Ch1_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[1];
- FspUpdRgn->FspmConfig.Ch1_Option = gMb3nChannelInfo[MemoryType].Option[1];
+ FspUpdRgn->FspmConfig.Ch1_RankEnable = gMB3MChannelInfo[MemoryType].RankEnable[1];
+ FspUpdRgn->FspmConfig.Ch1_DeviceWidth = gMB3MChannelInfo[MemoryType].DeviceWidth[1];
+ FspUpdRgn->FspmConfig.Ch1_DramDensity = gMB3MChannelInfo[MemoryType].DramDensity[1];
+ FspUpdRgn->FspmConfig.Ch1_Option = gMB3MChannelInfo[MemoryType].Option[1];
// DDR1CH0
- FspUpdRgn->FspmConfig.Ch2_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[2];
- FspUpdRgn->FspmConfig.Ch2_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[2];
- FspUpdRgn->FspmConfig.Ch2_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[2];
- FspUpdRgn->FspmConfig.Ch2_Option = gMb3nChannelInfo[MemoryType].Option[2];
+ FspUpdRgn->FspmConfig.Ch2_RankEnable = gMB3MChannelInfo[MemoryType].RankEnable[2];
+ FspUpdRgn->FspmConfig.Ch2_DeviceWidth = gMB3MChannelInfo[MemoryType].DeviceWidth[2];
+ FspUpdRgn->FspmConfig.Ch2_DramDensity = gMB3MChannelInfo[MemoryType].DramDensity[2];
+ FspUpdRgn->FspmConfig.Ch2_Option = gMB3MChannelInfo[MemoryType].Option[2];
// DDR1CH1
- FspUpdRgn->FspmConfig.Ch3_RankEnable = gMb3nChannelInfo[MemoryType].RankEnable[3];
- FspUpdRgn->FspmConfig.Ch3_DeviceWidth = gMb3nChannelInfo[MemoryType].DeviceWidth[3];
- FspUpdRgn->FspmConfig.Ch3_DramDensity = gMb3nChannelInfo[MemoryType].DramDensity[3];
- FspUpdRgn->FspmConfig.Ch3_Option = gMb3nChannelInfo[MemoryType].Option[3];
+ FspUpdRgn->FspmConfig.Ch3_RankEnable = gMB3MChannelInfo[MemoryType].RankEnable[3];
+ FspUpdRgn->FspmConfig.Ch3_DeviceWidth = gMB3MChannelInfo[MemoryType].DeviceWidth[3];
+ FspUpdRgn->FspmConfig.Ch3_DramDensity = gMB3MChannelInfo[MemoryType].DramDensity[3];
+ FspUpdRgn->FspmConfig.Ch3_Option = gMB3MChannelInfo[MemoryType].Option[3];
} else {
- DEBUG ((DEBUG_INFO, "**** MB3N - Memory Type 0x%02X is out of range!\n", MemoryType));
+ DEBUG ((DEBUG_INFO, "**** MB3 Module - Memory Type 0x%02X is out of range!\n", MemoryType));
}
//
// Swizzling
//
- if (ChSwizzle_MB3N != NULL) {
- CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzle_MB3N[0], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
- CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzle_MB3N[1], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
- CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzle_MB3N[2], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
- CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_MB3N[3], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
+ if ((PcdGet8 (PcdFabId) == FAB_ID_A) && (ChSwizzle_MB3Ma != NULL)) {
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzle_MB3Ma[0], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzle_MB3Ma[1], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzle_MB3Ma[2], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_MB3Ma[3], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ }
+ if ((PcdGet8 (PcdFabId) == FAB_ID_C) && (ChSwizzle_MB3Mc != NULL)) {
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzle_MB3Mc[0], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzle_MB3Mc[1], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzle_MB3Mc[2], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
+ CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_MB3Mc[3], DRAM_POLICY_NUMBER_BITS * sizeof (UINT8));
}
//
@@ -230,11 +251,11 @@ Mb3NUpdateFspmUpd (
);
if (!EFI_ERROR (Status)) {
if (SystemConfiguration.DciEn == 0) {
- FspUpdRgn->FspmConfig.NpkEn = 0;
+ FspUpdRgn->FspmConfig.NpkEn = 0; // Disable
} else if (SystemConfiguration.DciAutoDetect == 1) {
- FspUpdRgn->FspmConfig.NpkEn = 3;
+ FspUpdRgn->FspmConfig.NpkEn = 3; // Auto
} else {
- FspUpdRgn->FspmConfig.NpkEn = 1;
+ FspUpdRgn->FspmConfig.NpkEn = 1; // Enable
}
}
}
@@ -242,7 +263,6 @@ Mb3NUpdateFspmUpd (
return EFI_SUCCESS;
}
-
/**
DramCreatePolicyDefaults creates the default setting of Dram Policy.
@@ -254,7 +274,7 @@ Mb3NUpdateFspmUpd (
**/
EFI_STATUS
EFIAPI
-Mb3NDramCreatePolicyDefaults (
+Mb3MDramCreatePolicyDefaults (
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
OUT DRAM_POLICY_PPI **DramPolicyPpi,
IN IAFWDramConfig *DramConfigData,
@@ -272,7 +292,7 @@ Mb3NDramCreatePolicyDefaults (
PlatfromDramConf *DramConfig;
BOOLEAN ReadSetupVars;
- DEBUG ((EFI_D_INFO, "*** Minnow Board 3 Next DramCreatePolicyDefaults\n"));
+ DEBUG ((EFI_D_INFO, "*** Minnow Board 3 Module DramCreatePolicyDefaults\n"));
DramPolicy = (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY_PPI));
if (DramPolicy == NULL) {
ASSERT (FALSE);
@@ -398,7 +418,7 @@ Mb3NDramCreatePolicyDefaults (
}
/**
- BgUpdatePcieConfig updates the PCIe config block for platform specific items.
+ MB3MUpdatePcieConfig updates the PCIe config block for platform specific items.
@param[in] PciePreMemConfig The pointer to the PCIe premem config instance
@@ -408,12 +428,12 @@ Mb3NDramCreatePolicyDefaults (
**/
EFI_STATUS
EFIAPI
-Mb3NUpdatePcieConfig (
+Mb3MUpdatePcieConfig (
IN SC_PCIE_PREMEM_CONFIG *PciePreMemConfig
)
{
//
- // Minnow Board v3 Next
+ // Minnow Board v3 Module
//
PciePreMemConfig->RootPort[0].Perst = W_PMU_PLTRST_B; // D20:F0 - PCIe-A
PciePreMemConfig->RootPort[1].Perst = W_PMU_PLTRST_B; // D20:F1 - PCIe-B
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.h
index 663ab6f..011e4a3 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitMiscs.h
@@ -2,7 +2,7 @@
Multiplatform initialization header file.
This file includes package header files, library classes.
- Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -14,22 +14,22 @@
**/
-#ifndef _MINNOW_NEXT_MULTIPLATFORM_LIB_H_
-#define _MINNOW_NEXT_MULTIPLATFORM_LIB_H_
+#ifndef _MINNOW_MODULE_MULTIPLATFORM_LIB_H_
+#define _MINNOW_MODULE_MULTIPLATFORM_LIB_H_
+#include "PlatformId.h"
#include <BoardFunctionsPei.h>
#include <Guid/SetupVariable.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiDxeSmmMmPciLib.h>
#include <SaRegs.h>
-#include "PlatformId.h"
#include "MmrcData.h"
-extern UPDATE_FSPM_UPD_FUNC mMb3NUpdateFspmUpdPtr;
-extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3NDramCreatePolicyDefaultsPtr;
-extern UPDATE_PCIE_CONFIG_FUNC mMb3NUpdatePcieConfigPtr;
+extern UPDATE_FSPM_UPD_FUNC mMb3MUpdateFspmUpdPtr;
+extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3MDramCreatePolicyDefaultsPtr;
+extern UPDATE_PCIE_CONFIG_FUNC mMb3MUpdatePcieConfigPtr;
typedef struct {
UINT8 DeviceWidth[DRAM_POLICY_NUMBER_CHANNELS];
@@ -41,14 +41,14 @@ typedef struct {
EFI_STATUS
EFIAPI
-Mb3NUpdateFspmUpd (
+Mb3MUpdateFspmUpd (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN FSPM_UPD *FspUpdRgn
);
EFI_STATUS
EFIAPI
-Mb3NDramCreatePolicyDefaults (
+Mb3MDramCreatePolicyDefaults (
IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi,
OUT DRAM_POLICY_PPI **DramPolicyPpi,
IN IAFWDramConfig *DramConfigData,
@@ -59,7 +59,7 @@ Mb3NDramCreatePolicyDefaults (
EFI_STATUS
EFIAPI
-Mb3NUpdatePcieConfig (
+Mb3MUpdatePcieConfig (
IN SC_PCIE_PREMEM_CONFIG *PciePreMemConfig
);
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitPreMem.inf
index 6cb3dcf..5c83c12 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitPreMem.inf
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/BoardInitPreMem.inf
@@ -2,7 +2,7 @@
# Board detected module for Intel(R) Atom(TM) x5 Processor Series.
# It will detect the board ID.
#
-# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -16,11 +16,11 @@
[Defines]
INF_VERSION = 0x00010017
- BASE_NAME = MinnowBoard3NextInitPreMem
+ BASE_NAME = MinnowBoard3ModuleInitPreMem
FILE_GUID = A40B6929-FF79-4CF4-8B4E-40554390EC71
VERSION_STRING = 1.0
MODULE_TYPE = PEIM
- CONSTRUCTOR = MinnowBoard3NextInitConstructor
+ CONSTRUCTOR = MinnowBoard3ModuleInitConstructor
[Sources]
BoardInit.c
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.c
index c1ed7fc..f81a1bf 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.c
@@ -1,7 +1,7 @@
/** @file
Implement Platform ID code.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -15,93 +15,124 @@
#include <Uefi.h>
#include <Library/BaseMemoryLib.h>
-#include <Library/I2CLib.h>
+#include <Library/I2cLib.h>
#include <Library/GpioLib.h>
-#include <Guid/PlatformInfo.h>
#include "PlatformId.h"
PAD_ID_INFO gRawBoardIdPadInfo[] = {
- {NW_PMIC_STDBY, EnPd, P_20K_L},
- {NW_GPIO_213, EnPd, P_20K_L},
- {NW_PMIC_RESET_B, EnPd, P_20K_L},
- {NW_PMIC_PWRGOOD, EnPd, P_20K_L},
- {N_GPIO_27, EnPd, P_20K_L},
- {N_GPIO_72, EnPd, P_20K_L},
- {N_GPIO_64, EnPd, P_20K_L}
+ {NW_PMIC_STDBY, EnPd, P_20K_L}, // bit 0
+ {NW_GPIO_213, EnPd, P_20K_L}, // bit 1
+ {NW_PMIC_RESET_B, EnPd, P_20K_L}, // bit 2
+ {NW_PMIC_PWRGOOD, EnPd, P_20K_L}, // bit 3
+ {N_GPIO_27, EnPd, P_20K_L}, // bit 4
+ {N_GPIO_72, EnPd, P_20K_L}, // bit 5
+ {N_GPIO_64, EnPd, P_20K_L} // bit 6
};
//
-// MinnowBoardv3 = 0x00000017
-//===========================================
-// NW_PMIC_STDBY - BOARD_ID0 - 10k PU -> 1
-// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1
-// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1
-// NW_PMIC_PWRGOOD - - 10k PD -> 0
-// N_GPIO_27 - BOARD_ID3 - 10k PU -> 1
-// N_GPIO_72 - - Float -> 0
-// N_GPIO_64 - - Float -> 0
+// MinnowBoard v3 = 0x00000017
//===========================================
+// NW_PMIC_STDBY - BOARD_ID0 - 10k PU -> 1 xxxxxxx1
+// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1 xxxxxx1x
+// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 xxxxx1xx
+// NW_PMIC_PWRGOOD - - 10k PD -> 0 xxxx0xxx
+// N_GPIO_27 - BOARD_ID3 - 10k PU -> 1 xxx1xxxx
+// N_GPIO_72 - - Float -> 0 xx0xxxxx
+// N_GPIO_64 - - Float -> 0 x0xxxxxx
+//=========================================== 00010111b
// Benson Glacier = 0x00000024
//===========================================
-// NW_PMIC_STDBY - BOARD_ID0 - 10k PD -> 0
-// NW_GPIO_213 - BOARD_ID1 - 10k PD -> 0
-// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1
-// NW_PMIC_PWRGOOD - - Float -> 0
-// N_GPIO_27 - - Float -> 0
-// N_GPIO_72 - BOARD_ID3 - 10k PU -> 1
-// N_GPIO_64 - - Float -> 0
-//===========================================
+// NW_PMIC_STDBY - BOARD_ID0 - 10k PD -> 0 xxxxxxx0
+// NW_GPIO_213 - BOARD_ID1 - 10k PD -> 0 xxxxxx0x
+// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 xxxxx1xx
+// NW_PMIC_PWRGOOD - - Float -> 0 xxxx0xxx
+// N_GPIO_27 - - Float -> 0 xxx0xxxx
+// N_GPIO_72 - BOARD_ID3 - 10k PU -> 1 xx1xxxxx
+// N_GPIO_64 - - Float -> 0 x0xxxxxx
+//=========================================== 00100100b
-// MinnowBoardv3Next = 0x00000040
+// Aurora Glacier = 0x00000026
//===========================================
-// NW_PMIC_STDBY - - Float -> 0
-// NW_GPIO_213 - - Float -> 0
-// NW_PMIC_RESET_B - - Float -> 0
-// NW_PMIC_PWRGOOD - - Float -> 0
-// N_GPIO_27 - - Float -> 0
-// N_GPIO_72 - - Float -> 0
-// N_GPIO_64 - - 10k PU -> 1
+// NW_PMIC_STDBY - BOARD_ID0 - 10k PD -> 0 xxxxxxx0
+// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1 xxxxxx1x
+// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 xxxxx1xx
+// NW_PMIC_PWRGOOD - - Float -> 0 xxxx0xxx
+// N_GPIO_27 - - Float -> 0 xxx0xxxx
+// N_GPIO_72 - BOARD_ID3 - 10k PU -> 1 xx1xxxxx
+// N_GPIO_64 - - Float -> 0 x0xxxxxx
+//=========================================== 00100110b
+
+// MinnowBoard v3 Module = 0x00000040
//===========================================
+// NW_PMIC_STDBY - - Float -> 0 xxxxxxx0
+// NW_GPIO_213 - - Float -> 0 xxxxxx0x
+// NW_PMIC_RESET_B - - Float -> 0 xxxxx0xx
+// NW_PMIC_PWRGOOD - - Float -> 0 xxxx0xxx
+// N_GPIO_27 - - Float -> 0 xxx0xxxx
+// N_GPIO_72 - - Float -> 0 xx0xxxxx
+// N_GPIO_64 - - 10k PU -> 1 x1xxxxxx
+//=========================================== 01000000b
// LeafHill = 0x00000047
//===========================================
-// NW_PMIC_STDBY - BOARD_ID0 - 10k PU -> 1
-// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1
-// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1
-// NW_PMIC_PWRGOOD - BOARD_ID3 - 10k PD -> 0
-// N_GPIO_27 - - Float -> 0
-// N_GPIO_72 - - Float -> 0
-// N_GPIO_64 - - 0k PU -> 1
+// NW_PMIC_STDBY - BOARD_ID0 - 10k PU -> 1 xxxxxxx1
+// NW_GPIO_213 - BOARD_ID1 - 10k PU -> 1 xxxxxx1x
+// NW_PMIC_RESET_B - BOARD_ID2 - 10k PU -> 1 xxxxx1xx
+// NW_PMIC_PWRGOOD - BOARD_ID3 - 10k PD -> 0 xxxx0xxx
+// N_GPIO_27 - - Float -> 0 xxx0xxxx
+// N_GPIO_72 - - Float -> 0 xx0xxxxx
+// N_GPIO_64 - - 0k PU -> 1 x1xxxxxx
+//=========================================== 01000111b
+
+TRANSLATE_ID_INFO gBoardIdInfo[] = {
+ {0x00000017, BOARD_ID_MINNOW, "Minnow Board v3"},
+ {0x00000024, BOARD_ID_BENSON, "Benson Glacier"},
+ {0x00000026, BOARD_ID_AURORA, "Aurora Glacier"},
+ {0x00000040, BOARD_ID_MINNOW_MODULE, "Minnow Board v3 Module"},
+ {0x00000047, BOARD_ID_LFH_CRB, "Leafhill"},
+ {0xFFFFFFFF, BOARD_ID_APL_UNKNOWN, "Unknown Board ID"}
+};
+
+PAD_ID_INFO gRawFabIdPadInfo[] = {
+ {SW_GPIO_207, EnPd, P_20K_L} // bit 0 - GPIO 207
+};
+
+// MinnowBoard v3 Module, Fab A = 0x00000000
+//===========================================
+// SW_GPIO_207 - Float -> 0 xxxxxxx0
+//=========================================== 00000000b
+
+// MinnowBoard v3 Module, Fab C = 0x00000001
//===========================================
+// SW_GPIO_207 - 10k PU -> 1 xxxxxxx1
+//=========================================== 00000001b
-BOARD_ID_INFO gBoardIdInfo[] = {
- {0x00000017, BOARD_ID_MINNOW}, // MinnowBoardv3
- {0x00000024, BOARD_ID_BENSON}, // Benson Glacier
- {0x00000040, BOARD_ID_MINNOW_NEXT}, // MinnowBoardv3Next
- {0x00000047, BOARD_ID_LFH_CRB} // LeafHill
+TRANSLATE_ID_INFO gFabIdInfo[] = {
+ {0x00000000, FAB_ID_A, "Fab ID A"},
+ {0x00000001, FAB_ID_C, "Fab ID C"},
+ {0xFFFFFFFF, UNKNOWN_FAB, "Unknown Fab ID"}
};
-PAD_ID_INFO gMb3nHwconfPadInfo[] = {
- {W_GPIO_128, DisPuPd, P_NONE}, // HWCONF0
- {W_GPIO_131, DisPuPd, P_NONE}, // HWCONF1
- {W_GPIO_130, DisPuPd, P_NONE}, // HWCONF2
- {W_GPIO_129, DisPuPd, P_NONE}, // HWCONF3
- {W_GPIO_139, DisPuPd, P_NONE}, // HWCONF4
- {W_GPIO_138, DisPuPd, P_NONE}, // HWCONF5
- {NW_GPIO_80, DisPuPd, P_NONE}, // HWCONF6
- {NW_GPIO_81, DisPuPd, P_NONE}, // HWCONF7
- {NW_GPIO_83, DisPuPd, P_NONE} // HWCONF8
+PAD_ID_INFO gMB3MHwconfPadInfo[] = {
+ {W_GPIO_128, DisPuPd, P_NONE}, // bit 0 - HWCONF0
+ {W_GPIO_131, DisPuPd, P_NONE}, // bit 1 - HWCONF1
+ {W_GPIO_130, DisPuPd, P_NONE}, // bit 2 - HWCONF2
+ {W_GPIO_129, DisPuPd, P_NONE}, // bit 3 - HWCONF3
+ {W_GPIO_139, DisPuPd, P_NONE}, // bit 4 - HWCONF4
+ {W_GPIO_138, DisPuPd, P_NONE}, // bit 5 - HWCONF5
+ {NW_GPIO_80, DisPuPd, P_NONE}, // bit 6 - HWCONF6
+ {NW_GPIO_81, DisPuPd, P_NONE}, // bit 7 - HWCONF7
+ {NW_GPIO_83, DisPuPd, P_NONE} // bit 8 - HWCONF8
};
UINT32
EFIAPI
-GetId (
+Minnow3ModuleGetId (
IN PAD_ID_INFO *PadInfoPtr,
IN UINT8 NumberOfEntries
)
{
- UINT8 bit;
UINT32 CommAndOffset;
UINT8 index;
BXT_CONF_PAD0 padConfg0;
@@ -117,15 +148,18 @@ GetId (
//
// Nothing in structure. Skip.
//
- ReturnId = 0xFF;
+ ReturnId = 0xFFFFFFFF;
} else {
ReturnId = 0;
for (index = 0; index < NumberOfEntries; index++) {
+ //
+ // Read original pad programming
+ //
CommAndOffset = PadInfoPtr[index].CommAndOffset;
padConfg0Org.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
padConfg1Org.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
//
- // Set pad to be able to read the bit
+ // Set pad to be able to read the GPI level
//
padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
padConfg1.padCnf1 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET);
@@ -136,10 +170,10 @@ GetId (
GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
//
- // Read the bit
+ // Read the pad GPI level and OR into ID
//
- bit = (UINT8) (((GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << index);
- ReturnId |= bit;
+ padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+ ReturnId |= padConfg0.r.GPIORxState << index;
//
// Restore orginal pad programming.
//
@@ -152,41 +186,69 @@ GetId (
UINT8
EFIAPI
-GetCommonBoardId (
+Minnow3ModuleGetCommonBoardId (
VOID
)
{
UINT8 BoardId;
UINT8 index;
UINT32 RawBoardId;
-
+
DEBUG ((DEBUG_INFO, "%a(#%3d) - Starting...\n", __FUNCTION__, __LINE__));
//
// Get BoardId
//
- RawBoardId = GetId (gRawBoardIdPadInfo, sizeof (gRawBoardIdPadInfo) / sizeof (gRawBoardIdPadInfo[0]));
+ RawBoardId = Minnow3ModuleGetId (gRawBoardIdPadInfo, sizeof (gRawBoardIdPadInfo) / sizeof (gRawBoardIdPadInfo[0]));
+ DEBUG ((DEBUG_INFO, "%a(#%3d) - Raw BoardId: %02X\n", __FUNCTION__, __LINE__, RawBoardId));
//
// Convert from a 32-bit raw BoardId to an 8-bit one.
//
- BoardId = BOARD_ID_APL_UNKNOWN;
for (index = 0; index < sizeof (gBoardIdInfo) / sizeof (gBoardIdInfo[0]); index++) {
- if (gBoardIdInfo[index].RawId == RawBoardId) {
- BoardId = gBoardIdInfo[index].BoardId;
+ if ((gBoardIdInfo[index].RawId == RawBoardId) || (gBoardIdInfo[index].RawId == 0xFFFFFFFF)) {
+ BoardId = gBoardIdInfo[index].TranslatedId;
+ DEBUG ((DEBUG_INFO, "%a(#%3d) - BoardId: %02X = %a\n", __FUNCTION__, __LINE__, BoardId, gBoardIdInfo[index].Description));
break;
}
}
-
- DEBUG ((DEBUG_INFO, "%a(#%3d) - BoardId: %02X\n", __FUNCTION__, __LINE__, BoardId));
return BoardId;
}
+UINT8
+EFIAPI
+Minnow3ModuleGetCommonFabId (
+ VOID
+ )
+{
+ UINT8 FabId;
+ UINT8 index;
+ UINT32 RawFabId;
+ DEBUG ((DEBUG_INFO, "%a(#%3d) - Starting...\n", __FUNCTION__, __LINE__));
+
+ //
+ // Get FabId
+ //
+ RawFabId = Minnow3ModuleGetId (gRawFabIdPadInfo, sizeof (gRawFabIdPadInfo) / sizeof (gRawFabIdPadInfo[0]));
+ DEBUG ((DEBUG_INFO, "%a(#%3d) - Raw FabId: %02X\n", __FUNCTION__, __LINE__, RawFabId));
+
+ //
+ // Convert from a 32-bit raw FabId to an 8-bit one.
+ //
+ for (index = 0; index < sizeof (gFabIdInfo) / sizeof (gFabIdInfo[0]); index++) {
+ if ((gFabIdInfo[index].RawId == RawFabId) || (gFabIdInfo[index].RawId == 0xFFFFFFFF)) {
+ FabId = gFabIdInfo[index].TranslatedId;
+ DEBUG ((DEBUG_INFO, "%a(#%3d) - FabId: %02X = %a\n", __FUNCTION__, __LINE__, FabId, gFabIdInfo[index].Description));
+ break;
+ }
+ }
+ return FabId;
+}
EFI_STATUS
EFIAPI
-Minnow3NextGetEmbeddedBoardIdFabId (
+Minnow3ModuleGetEmbeddedBoardIdFabId (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT UINT8 *BoardId,
OUT UINT8 *FabId
@@ -194,20 +256,13 @@ Minnow3NextGetEmbeddedBoardIdFabId (
{
DEBUG ((DEBUG_INFO, "%a(#%3d) - Starting...\n", __FUNCTION__, __LINE__));
- //
- // Get BoardId
- //
- *BoardId = GetCommonBoardId ();
+ *BoardId = Minnow3ModuleGetCommonBoardId ();
+ *FabId = Minnow3ModuleGetCommonFabId ();
+ Minnow3ModuleGetHwconfStraps ();
- if (*BoardId != BOARD_ID_MINNOW_NEXT) {
+ if (*BoardId != BOARD_ID_MINNOW_MODULE) {
*BoardId = BOARD_ID_APL_UNKNOWN;
*FabId = UNKNOWN_FAB;
- } else {
- //
- // Get FabId
- //
- *FabId = FAB_ID_A; // MBv3N FabID is behind the EC. Just say Fab A for now.
- DEBUG ((DEBUG_INFO, "%a(#%3d) - FabId : %02X\n", __FUNCTION__, __LINE__, *FabId));
}
return EFI_SUCCESS;
@@ -215,16 +270,17 @@ Minnow3NextGetEmbeddedBoardIdFabId (
UINT32
EFIAPI
-Minnow3NextGetHwconfStraps (
+Minnow3ModuleGetHwconfStraps (
VOID
)
{
UINT32 HwconfStraps;
-
+
//
// Get HWCONF straps
//
- HwconfStraps = GetId (gMb3nHwconfPadInfo, sizeof (gMb3nHwconfPadInfo) / sizeof (gMb3nHwconfPadInfo[0]));
+ HwconfStraps = Minnow3ModuleGetId (gMB3MHwconfPadInfo, sizeof (gMB3MHwconfPadInfo) / sizeof (gMB3MHwconfPadInfo[0]));
+ DEBUG ((DEBUG_INFO, "%a(#%3d) - HWCONF : %08X\n", __FUNCTION__, __LINE__, HwconfStraps));
return HwconfStraps;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.h
index 7ee6777..fbaac35 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPreMem/PlatformId.h
@@ -1,7 +1,7 @@
/** @file
Header file for the Platform ID code.
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -13,8 +13,22 @@
**/
-#ifndef __MINNOWBOARD_NEXT_PLATFORM_ID_H__
-#define __MINNOWBOARD_NEXT_PLATFORM_ID_H__
+#ifndef __MINNOWBOARD_MODULE_PLATFORM_ID_H__
+#define __MINNOWBOARD_MODULE_PLATFORM_ID_H__
+
+#include <Guid/PlatformInfo.h>
+
+//
+// HWCONF defines. Low = off & high = on
+//
+#define HWCONF_COMx BIT0
+#define HWCONF_ECC BIT1
+//#define HWCONF_COMx BIT2
+//#define HWCONF_COMx BIT3
+#define HWCONF_USB3 BIT4
+#define HWCONF_CAMERA BIT5
+#define HWCONF_MEMORY 6
+#define HWCONF_MEMORY_MASK (BIT6 | BIT7 | BIT8)
typedef struct {
UINT32 CommAndOffset;
@@ -24,12 +38,13 @@ typedef struct {
typedef struct {
UINT32 RawId;
- UINT8 BoardId;
-} BOARD_ID_INFO;
+ UINT8 TranslatedId;
+ CHAR8 Description[32];
+} TRANSLATE_ID_INFO;
EFI_STATUS
EFIAPI
-Minnow3NextGetEmbeddedBoardIdFabId (
+Minnow3ModuleGetEmbeddedBoardIdFabId (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT UINT8 *BoardId,
OUT UINT8 *FabId
@@ -37,7 +52,7 @@ Minnow3NextGetEmbeddedBoardIdFabId (
UINT32
EFIAPI
-Minnow3NextGetHwconfStraps (
+Minnow3ModuleGetHwconfStraps (
VOID
);
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin
index 5907374b5ebdc09b27125d28a2f15036252d0ad8..8a432de2d9717d1916e552bd20e7dfc627861bca 100644
GIT binary patch
delta 25
gcmZqBY0#M<#XOn8U~(X%@J54vMn=ZX2N)eh0ACRX`~Uy|
delta 25
gcmZqBY0#M<#XN<<U~(X%@J54vMn;Cs2N)eh0AC#j`~Uy|
--
2.10.1.windows.1
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