From nobody Mon Apr 29 16:02:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150759826671176.61272192056731; Mon, 9 Oct 2017 18:17:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 87DA220945BD7; Mon, 9 Oct 2017 18:14:17 -0700 (PDT) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2EDB521F3C185 for ; Mon, 9 Oct 2017 18:14:16 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2017 18:17:43 -0700 Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 09 Oct 2017 18:17:42 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 9 Oct 2017 18:17:42 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 9 Oct 2017 18:17:42 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Tue, 10 Oct 2017 09:17:39 +0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=mang.guo@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,502,1500966000"; d="dat'59?scan'59,208,59";a="1204055912" From: "Guo, Mang" To: "edk2-devel@lists.01.org" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Enable SueCreek Thread-Index: AdNBZZAMjJLjkhU4R9iYln3Nne5Hfg== Date: Tue, 10 Oct 2017 01:17:39 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D152570C87@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D152570C87@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Enable SueCreek X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Rytkonen, Teemu S" , "Jones, Mark L" , "Yoon, Yeon Sil" , "Loeppert, Anthony" , "Wei, David" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Change SPI mode and speed for SueCreek 2. Update SueCreek HOST_IRQ and HOST_RST GPIO configuration 3. Add a PCD to make sure that SueCreek only reported to OS when it is actu= ally present on the board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yeon Sil Yoon Signed-off-by: Guo Mang Reviewed-by: zwei4 --- .../Board/BensonGlacier/BoardInitPostMem/BoardGpios.h | 4 ++-- .../Board/BensonGlacier/BoardInitPostMem/BoardInit.c | 5 +++++ .../BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/LeafHill/BoardInitPostMem/BoardInit.c | 5 +++++ .../Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/MinnowBoard3/BoardInitPostMem/BoardInit.c | 5 +++++ .../Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c | 2 ++ .../Common/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf | 1 + .../Common/Acpi/AcpiTablesPCAT/GloblNvs.asl | 8 +++++++- .../Acpi/AcpiTablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl | 12 +++++++-= ---- Platform/BroxtonPlatformPkg/PlatformPkg.dec | 2 ++ .../NorthCluster/Include/Protocol/GlobalNvsArea.h | 3 ++- 13 files changed, 41 insertions(+), 9 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInit= PostMem/BoardGpios.h index e0bdde8..d72cd80 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dGpios.h +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dGpios.h @@ -80,13 +80,13 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_N[] =3D BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,D= isPuPd, GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in= Sch: SIM_CON_CD1, falling edge trigger - BXT_GPIO_PAD_CONF(L"GPIO_17", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0088, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D,= NA , Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,D= isPuPd, GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00B0, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPIO ,GPIO_D ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00B8, NORTH),//Feature: LB USB Power in LFH + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, = LO , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = EnPu, GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0 BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D ,= NA , Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , = NA, GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in= Sch: SATA_ODD_DA_IN BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitP= ostMem/BoardInit.c index 8b21b50..536c390 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.c @@ -88,6 +88,11 @@ BensonGlacierPostMemInitCallback ( // BufferSize =3D sizeof (EFI_GUID); PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiBensonGlacierV= btGuid); + =20 + // + // Set PcdSueCreek + // + PcdSetBool (PcdSueCreek, TRUE); =20 // // Add init steps here diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/B= oardInitPostMem/BoardInitPostMem.inf index c22bfad..5989d30 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -63,6 +63,7 @@ gPlatformModuleTokenSpaceGuid.PcdFabId gPlatformModuleTokenSpaceGuid.PcdResetType gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid + gPlatformModuleTokenSpaceGuid.PcdSueCreek =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Bo= ardInit.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Boa= rdInit.c index 60fe1a3..af53b8c 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= .c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= .c @@ -96,6 +96,11 @@ LeafHillPostMemInitCallback ( // BufferSize =3D sizeof (EFI_GUID); PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiLeafHillVbtGui= d); + =20 + // + // Set PcdSueCreek + // + PcdSetBool (PcdSueCreek, FALSE); =20 // // Add init steps here diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Bo= ardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPo= stMem/BoardInitPostMem.inf index 0717bc3..a794d6b 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= PostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= PostMem.inf @@ -61,6 +61,7 @@ gPlatformModuleTokenSpaceGuid.PcdFabId gPlatformModuleTokenSpaceGuid.PcdResetType gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid + gPlatformModuleTokenSpaceGuid.PcdSueCreek =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPos= tMem/BoardInit.c index ca79940..0aa9246 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Init.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Init.c @@ -96,6 +96,11 @@ MinnowBoard3PostMemInitCallback ( // BufferSize =3D sizeof (EFI_GUID); PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiMinnowBoard3Vb= tGuid); + =20 + // + // Set PcdSueCreek + // + PcdSetBool (PcdSueCreek, FALSE); =20 // // Add init steps here diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Boa= rdInitPostMem/BoardInitPostMem.inf index 90494ba..8fa5ffa 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= InitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= InitPostMem.inf @@ -59,6 +59,7 @@ gPlatformModuleTokenSpaceGuid.PcdFabId gPlatformModuleTokenSpaceGuid.PcdResetType gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid + gPlatformModuleTokenSpaceGuid.PcdSueCreek =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPl= atform.c b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlat= form.c index d3c10b1..f0a77d1 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatform.c @@ -1439,6 +1439,8 @@ AcpiPlatformEntryPoint ( mGlobalNvsArea.Area->BatteryCapacity0 =3D 100; mGlobalNvsArea.Area->Mmio32Base =3D (MmioRead32 ((UINT= N) PcdGet64 (PcdPciExpressBaseAddress) + 0xBC) & 0xFFF00000);; mGlobalNvsArea.Area->Mmio32Length =3D ACPI_MMIO_BASE_ADD= RESS - mGlobalNvsArea.Area->Mmio32Base; + mGlobalNvsArea.Area->SueCreekEnable =3D PcdGetBool(PcdSu= eCreek); + // // Initialize IGD state by checking if IGD Device 2 Function 0 is enab= led in the chipset // diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPl= atformDxe.inf b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/Acp= iPlatformDxe.inf index 5e876dc..be047c1 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformD= xe.inf +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiPlatformDxe/AcpiPlatformD= xe.inf @@ -86,6 +86,7 @@ gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gPlatformModuleTokenSpaceGuid.PcdResetType + gPlatformModuleTokenSpaceGuid.PcdSueCreek =20 [Depex] gEfiAcpiSupportProtocolGuid AND diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNv= s.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl index b2f6f56..78416f6 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl @@ -1,7 +1,7 @@ /** @file ACPI GNVS =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -474,5 +474,11 @@ IC5S, 32, // (906) I2C5 Speed - Standard mode/Fast mode/FastPl= us mode/HighSpeed mode IC6S, 32, // (910) I2C6 Speed - Standard mode/Fast mode/FastPl= us mode/HighSpeed mode IC7S, 32, // (914) I2C7 Speed - Standard mode/Fast mode/FastPl= us mode/HighSpeed mode + SEN2, 8, // (918) EnableSen2Participant + PTTP, 8, // (919) PassiveThermalTripPointSen2 + CTTP, 8, // (920) CriticalThermalTripPointSen2S3 + HTTP, 8, // (921) HotThermalTripPointSen2 + CRTP, 8, // (922) CriticalThermalTripPointSen2 + SUCE, 8, // (923) SueCreekEnable: 0: disabled; 1: enabled } =20 diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platfor= mSsdt/SueCreek/SueCreek.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiT= ablesPCAT/PlatformSsdt/SueCreek/SueCreek.asl index d67b3c4..3baa88c 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/S= ueCreek/SueCreek.asl +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/S= ueCreek/SueCreek.asl @@ -14,7 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 Scope (\_SB.PCI0.SPI1) { Device (TP0) { - Name (_HID, "SPT0001") + Name (_HID, "SUE1000") Name (_DDN, "SueCreek - SPI0, CS0") Name (_CRS, ResourceTemplate () { SpiSerialBus ( @@ -23,15 +23,17 @@ Scope (\_SB.PCI0.SPI1) { FourWireMode, // Full duplex 8, // Bits per word is 8 (byte) ControllerInitiated, // Don't care - 1000000, // 1 MHz - ClockPolarityLow, // SPI mode 0 - ClockPhaseFirst, // SPI mode 0 + 9600000, // 9.6 MHz + ClockPolarityHigh, // SPI mode 3 + ClockPhaseSecond, // SPI mode 3 "\\_SB.PCI0.SPI1", // SPI host controller 0 // Must be 0 ) }) + + External(\SUCE, IntObj) Method (_STA, 0x0, NotSerialized) { - If (LEqual (OSYS, 2015)) { + If (LEqual (SUCE, 0)) { Return (0x0) } else { Return (0xF) diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.dec b/Platform/Broxton= PlatformPkg/PlatformPkg.dec index 4813145..f37ceaf 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.dec +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.dec @@ -182,6 +182,8 @@ gPlatformModuleTokenSpaceGuid.PcdGetBoardNameFunc|0|UINT64|0x80000012 gPlatformModuleTokenSpaceGuid.PcdResetType|0x0E|UINT8|0x80000013 gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid|{ 0x00, 0x00, 0x00, 0x= 00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 = }|VOID*|0x80000014 + ## This PCD used to enable or disable SueCreek + gPlatformModuleTokenSpaceGuid.PcdSueCreek|FALSE|BOOLEAN|0x80000015 =20 ## MemoryCheck value for checking memory before boot OS. ## To save the boot performance, the default MemoryCheck is set to 0. diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/= GlobalNvsArea.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Prot= ocol/GlobalNvsArea.h index b32f334..e8319ce 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalN= vsArea.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalN= vsArea.h @@ -1,7 +1,7 @@ /** @file Header file for Global NVS Area definition. =20 - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -506,6 +506,7 @@ typedef struct { UINT8 CriticalThermalTripPointSen2S3; ///< (920) Critica= lThermalTripPointSen2S3 UINT8 HotThermalTripPointSen2; ///< (921) HotTher= malTripPointSen2 UINT8 CriticalThermalTripPointSen2; ///< (922) Critica= lThermalTripPointSen2 + UINT8 SueCreekEnable; ///< (923) SueCree= kEnable: 0: disabled; 1: enabled =20 } EFI_GLOBAL_NVS_AREA; #pragma pack () =20 --=20 2.10.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel