From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113972+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113972+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540710; cv=none; d=zohomail.com; s=zohoarc; b=Ugg7ddv5iCr4Wpg8DptTx0NmxdWweZAaE6+fIsK3MaLUsFltrVUZTL1ZPM1V6HkwxezbLpI1tMb35hL2xkZlLP1Gf37QsvcCXu9y/oiuTsF/VT8VCiOq790VdKmD9mxqpJ/j6Jun2kjcz6dpNWwdkngxxtsylGTX4C3uXvxoiN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540710; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YW5U+8tQ4VfUNb2TumE9ZtSSJVGDbQiir2/Xp8yL2jw=; b=kHN0wcTNSR7LNsQKsAvT03dBVtcbxgVVBeLE9BzUKSrnpOb/atR6N+tgdzZRYjnQoTvl9aBhQkwNj//XqkMWzIbZP6qj+qzSm66Tjv1aphbKfqldz8qs3HnXqCl+BY7SwhS1//EvCmFYEDkJ2Akt5CZHIGqh3/wwg2HxcUaFuHM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113972+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540710709931.5520259406343; Wed, 17 Jan 2024 17:18:30 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=5/SHgoeryQ5P7sdM76NfmWhz3XYEfT1fxndAnqmv5X8=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540710; v=1; b=CY8lx5a7kqO2NAYb8L+HkxwrdiFBbQ8VTSNx2H+LGfg5atHEkekAchFJ5Itv1WYDtYqHA17Q zDnMufItF+hHcL0be2ni0i9M46ccXNwY54fjB5DIXWeOqiiBcdAcRuACFx0msTByLaYrtCE+RgO K7VbZ1xSSJblxAFrP9zAs99E= X-Received: by 127.0.0.2 with SMTP id hF3wYY1788612xV5wjNzg7An; Wed, 17 Jan 2024 17:18:30 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.926.1705540709507118852 for ; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHSY3c029567; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4ru-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:28 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id 12E093F7081; Wed, 17 Jan 2024 17:18:27 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 1/7] Silicon/Marvell: New Marvell Odyssey processor Date: Wed, 17 Jan 2024 17:18:11 -0800 Message-ID: <20240118011817.4348-2-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: -WwX9O7afffreQqqqgIoL7sDjxc-j7Fh X-Proofpoint-GUID: -WwX9O7afffreQqqqgIoL7sDjxc-j7Fh Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: oms24M8taEAlSvoUL0xaW1jvx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540712782100016 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds helper library to initialize Odyssey SoC. Signed-off-by: Narinder Dhillon --- .../OdysseyLib/AArch64/ArmPlatformHelper.S | 97 ++++++++++++ .../Library/OdysseyLib/OdysseyLib.c | 79 ++++++++++ .../Library/OdysseyLib/OdysseyLib.inf | 60 ++++++++ .../Library/OdysseyLib/OdysseyLibMem.c | 142 ++++++++++++++++++ 4 files changed, 378 insertions(+) create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/A= rmPlatformHelper.S create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLi= b.c create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLi= b.inf create mode 100644 Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLi= bMem.c diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatf= ormHelper.S b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlat= formHelper.S new file mode 100644 index 0000000000..e816e6bd5a --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/AArch64/ArmPlatformHelp= er.S @@ -0,0 +1,97 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include +#include +#include +#include +#include +#include + +/* x1 - node number + */ + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmGetCpuCountPerCluster) + +GCC_ASM_IMPORT(mDeviceTreeBaseAddress) +GCC_ASM_IMPORT(mSystemMemoryEnd) + +ASM_FUNC(ArmPlatformPeiBootAction) + // Save the boot parameter to a global variable + adr x10, mDeviceTreeBaseAddress + str x1, [x10] + + adr x1, PrimaryCoreMpid + str w0, [x1] + ldr x0, =3DMV_SMC_ID_DRAM_SIZE + mov x1, xzr + smc #0 + sub x0, x0, #1 // Last valid address + // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs + cmp x0, #0xffffffffffffffff + bne done + // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs + MOV64 (x0, FixedPcdGet64(PcdSystemMemoryBase) + FixedPcdGet64(PcdSystemM= emorySize) - 1) +done: + adr x1, mSystemMemoryEnd + str x0, [x1] // Set mSystemMemoryEnd + + ret + + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32(w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) +/* + Affinity Level 0: single thread 0 + Affinity Level 1: clustering 0( + Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 16 = (Iliad) + Affinity Level 3: number of chip 0 + LinearId =3D Aff2 +*/ + and x0, x0, #ARM_CORE_AFF2 + lsr x0, x0, #16 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED + +PrimaryCoreMpid: .word 0x0 diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c b/S= ilicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c new file mode 100644 index 0000000000..ed48a00950 --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.c @@ -0,0 +1,79 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include +#include // EFI_BOOT_MODE +#include // EFI_PEI_PPI_DESCRIPTOR +#include // ASSERT +#include // ArmPlatformIsPrimaryCore +#include // ARM_MP_CORE_INFO_PPI + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePei or ArmPlatformPkg/P= ei/PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + ASSERT(ArmPlatformIsPrimaryCore (MpId)); + + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + return EFI_UNSUPPORTED; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf b= /Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf new file mode 100644 index 0000000000..c47a19767b --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLib.inf @@ -0,0 +1,60 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2022 Marvell +# +# Marvell ARM Platform library +# Based on ArmPlatformPkg/Library/ArmPlatformLibNull +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D OdysseyLib + FILE_GUID =3D 7ea0f45b-0e06-4e45-8353-9c28b091a11c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OdysseyLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec # Include ArmPlatformLib.h + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + +[LibraryClasses] + ArmLib + HobLib + DebugLib + MemoryAllocationLib + SmcLib + FdtLib + +[Sources] + OdysseyLib.c + OdysseyLibMem.c + +[Sources.AARCH64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase + gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdIoSize + +[Ppis] + gArmMpCoreInfoPpiGuid + +[Guids] + gFdtHobGuid diff --git a/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c = b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c new file mode 100644 index 0000000000..bfec57952a --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/OdysseyLibMem.c @@ -0,0 +1,142 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include // Basic UEFI types +#include // DEBUG +#include // EFI_BOOT_MODE required by PiH= ob.h +#include // EFI_RESOURCE_ATTRIBUTE_TYPE +#include // BuildResourceDescriptorHob +#include // PcdGet64 +#include // ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK +#include // SmcGetRamSize +#include // AllocatePages +#include // fdt_totalsize // + +// Number of Virtual Memory Map Descriptors +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 129 +#define MAX_NODES 1 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED + +UINT64 mDeviceTreeBaseAddress =3D 0; + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINT64 VirtualMemoryTableSize; + UINT64 MemoryBase; + UINT64 MemorySize; + UINTN Index =3D 0; + UINTN Node; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTableSize =3D sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VI= RTUAL_MEMORY_MAP_DESCRIPTORS; + VirtualMemoryTable =3D AllocatePages (EFI_SIZE_TO_PAGES (VirtualMemoryTa= bleSize)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + CacheAttributes =3D DDR_ATTRIBUTES_CACHED; + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdFdSize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + Index++; + + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + PcdGet64 (PcdFdBaseAddress), + PcdGet32 (PcdFdSize)); + + for (Node =3D 0; Node < MAX_NODES; Node++) { + MemoryBase =3D Node * FixedPcdGet64(PcdNodeDramBase); + MemorySize =3D SmcGetRamSize(Node); + + MemoryBase +=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : 0; + MemorySize -=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : 0; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemoryBase, + MemorySize); + + DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory %lx @ %lx\n", MemorySize, = MemoryBase)); + VirtualMemoryTable[Index].PhysicalBase =3D MemoryBase; + VirtualMemoryTable[Index].VirtualBase =3D MemoryBase; + VirtualMemoryTable[Index].Length =3D MemorySize; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + Index++; + } + + for (Node =3D 0; Node < MAX_NODES; Node++) { + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64(PcdIoBaseAdd= ress) + + Node * FixedPcdGet64(PcdNo= deIoBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64(PcdIoBaseAdd= ress) + + Node * FixedPcdGet64(PcdNo= deIoBaseAddress); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64(PcdIoSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + DEBUG ((DEBUG_LOAD | DEBUG_INFO, + "IO %lx @ %lx\n", + VirtualMemoryTable[Index].Length, + VirtualMemoryTable[Index].PhysicalBase)); + + Index++; + } + + // End of Table + VirtualMemoryTable[Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + *VirtualMemoryMap =3D VirtualMemoryTable; + + // Build the FDT HOB + ASSERT(fdt_check_header ((VOID *)mDeviceTreeBaseAddress) =3D=3D 0); + DEBUG((DEBUG_INFO, "FDT address: %lx, size: %d\n", + mDeviceTreeBaseAddress, + fdt_totalsize((VOID *)mDeviceTreeBaseAddress))); + + BuildGuidDataHob (&gFdtHobGuid, &mDeviceTreeBaseAddress, sizeof(mDeviceT= reeBaseAddress)); +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113972): https://edk2.groups.io/g/devel/message/113972 Mute This Topic: https://groups.io/mt/103800150/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113973+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113973+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540711; cv=none; d=zohomail.com; s=zohoarc; b=ShjOZFU0QxeMGTgorJfSue0hkFhzuzkJ5D8njO0tw1Y1PiB1++ACgjXpcBE6B2FrCXMu7xAJxUjxBnUozDXnfZFEsSSC3vKoH4nd/EqBZo9IMjTx+Pv/sLQFUAQpd5J3HcnN5ebzsGAOV5jEaI/Vckcu0jBS4jV+82uJP/wBu20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540711; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0J+PdT3Y6T7Cl+X1tzyFpirzszw/M8a+rikmbV6dqAY=; b=Pv53Afc2NbTQqSNvbHp9eW9SFBXPLpg47nzfjyTgMA/vfg84eBWC5rObn57Kw2fdhnFeDhlu1sobIw3LKNYm9g63IhV59vT7Xsou2vXUIVK70iZB34WVYJkY4nkCbWnu274UKbZZFHfidfoUr3zmE4guLTtglQh7KuxmemIiUu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113973+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540711142899.1011876931535; Wed, 17 Jan 2024 17:18:31 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=PTJtSnOlVNVD8sF2d4YDyIA7jEHiDrzG6MTSdi3FwZ0=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540710; v=1; b=uUcfw99ALBp1BUS8ZSjkkgRa2PaANmglqFB+BHn+QokgdWegSAjQkLmN0c4GwiInI7emfzmz d/9NAj8ikqT2XqqDIbfQATTc6SUrhUUF9Se3OLXVyY/km1eyrrENS3aRRQU+JFWyxhL4dZYdE3F RbIs0bmqEqjZiTRyxRfpuWdQ= X-Received: by 127.0.0.2 with SMTP id dfMFYY1788612xm7zhUPhQgr; Wed, 17 Jan 2024 17:18:30 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.927.1705540709673689451 for ; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHSY3d029567; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4ru-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:29 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id 4D75D3F7084; Wed, 17 Jan 2024 17:18:27 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 2/7] Silicon/Marvell: Odyssey SmcLib Date: Wed, 17 Jan 2024 17:18:12 -0800 Message-ID: <20240118011817.4348-3-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 3X_ztjtuIgX1LIEoTKrST4pw2l4oku8y X-Proofpoint-GUID: 3X_ztjtuIgX1LIEoTKrST4pw2l4oku8y Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: bpfhPcYgGJvjq2IUcHEQjmThx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540712725100011 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch provides SMC call needed by Odyssey to determine size of available memory. Signed-off-by: Narinder Dhillon --- Silicon/Marvell/Library/SmcLib/SmcLib.c | 24 +++++++++++++++ Silicon/Marvell/Library/SmcLib/SmcLib.inf | 29 +++++++++++++++++++ .../Include/IndustryStandard/SmcLib.h | 28 ++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 Silicon/Marvell/Library/SmcLib/SmcLib.c create mode 100644 Silicon/Marvell/Library/SmcLib/SmcLib.inf create mode 100644 Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStand= ard/SmcLib.h diff --git a/Silicon/Marvell/Library/SmcLib/SmcLib.c b/Silicon/Marvell/Libr= ary/SmcLib/SmcLib.c new file mode 100644 index 0000000000..0280983dd0 --- /dev/null +++ b/Silicon/Marvell/Library/SmcLib/SmcLib.c @@ -0,0 +1,24 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Source file for Marvell SMC Interface +* +**/ + +#include +#include // ArmCallSmc + +UINTN SmcGetRamSize ( IN UINTN Node ) +{ + ARM_SMC_ARGS ArmSmcArgs; + + ArmSmcArgs.Arg0 =3D MV_SMC_ID_DRAM_SIZE; + ArmSmcArgs.Arg1 =3D Node; + ArmCallSmc (&ArmSmcArgs); + + return ArmSmcArgs.Arg0; +} diff --git a/Silicon/Marvell/Library/SmcLib/SmcLib.inf b/Silicon/Marvell/Li= brary/SmcLib/SmcLib.inf new file mode 100644 index 0000000000..7fc1085b85 --- /dev/null +++ b/Silicon/Marvell/Library/SmcLib/SmcLib.inf @@ -0,0 +1,29 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# Marvell SMC Interface library +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmcLib + FILE_GUID =3D fee427a7-816a-4636-bb81-a640c8288f28 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SmcLib + +[Sources] + SmcLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + +[LibraryClasses] + ArmSmcLib diff --git a/Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStandard/Smc= Lib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStandard/SmcLib.h new file mode 100644 index 0000000000..f2d0bed356 --- /dev/null +++ b/Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStandard/SmcLib.h @@ -0,0 +1,28 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Header file for for Marvell SMC Interface +* +**/ + +#ifndef __SMCLIB_H__ +#define __SMCLIB_H__ + +/* SMC function IDs for Marvell Service queries */ + +#define MV_SMC_ID_CALL_COUNT 0xc200ff00 +#define MV_SMC_ID_UID 0xc200ff01 + +#define MV_SMC_ID_VERSION 0xc200ff03 + +/* x1 - node number */ +#define MV_SMC_ID_DRAM_SIZE 0xc2000301 + + +UINTN SmcGetRamSize (IN UINTN Node); + +#endif --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113973): https://edk2.groups.io/g/devel/message/113973 Mute This Topic: https://groups.io/mt/103800151/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113974+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113974+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540711; cv=none; d=zohomail.com; s=zohoarc; b=e3r2nSs9zog/r5dK6uXXq1vd/VD8Rx/Y2ozdV/7vhk7oJz+RyyQsBuiOfjL1jSYYj9Ucg3KjF/LfT9aYwyXu9I37TT5XT/FtJ49Fi2Q3W21UI59i/KW7ZsIoo0qDU5he1Fx8aLWghC177hLVN13s6iLwrGuo8oU362O6uL6oaNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540711; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=jC36Rz8IkXRI5cibuJpLQ/yigC88Zap0D00sFBRlOrY=; b=eJ8pMuVq18Pcf0R0ot4B/kMk5ZNF1/oGn24gzIsf10FVqDTgXzzflV2yPUezDLLVP7h4EtynfkolHwZDe0DhMaW3NiwzKFknc6pY1mJG6QK5dyNiSkL+t3Ovg/xnAmvGIQPW0NZ29Xy2/8Tlv94PAbpznMBHh55PZXYwOo68KTg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113974+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540711534427.45549166765386; Wed, 17 Jan 2024 17:18:31 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=vYxtCQSgVQNu2ZTq8ZmPijTu0Cg9yKFlaawVFaP+ppw=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540711; v=1; b=i4s895sT1yM4qPmQCJF+nnJUTjysvYrdn7Mwh8a/1zkSNOOQrQ6NgQt19jd6L2zfVcCT/aWe sPI+Jy2qDcOr04PbMvhdlYGI2Fb3wUIoYxFTlvszvOcX/iUKuwy5ivZldmlEwZX9KgN3bl6nAFi VsIH3aTNc7tIhelkTmr8dddI= X-Received: by 127.0.0.2 with SMTP id zCZRYY1788612xrV8ViA30jX; Wed, 17 Jan 2024 17:18:31 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.928.1705540710162662732 for ; Wed, 17 Jan 2024 17:18:30 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHSY3e029567; Wed, 17 Jan 2024 17:18:30 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4ru-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:29 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:27 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id A07713F7087; Wed, 17 Jan 2024 17:18:27 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 3/7] Silicon/Marvell: Odyssey watchdog driver Date: Wed, 17 Jan 2024 17:18:13 -0800 Message-ID: <20240118011817.4348-4-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Dsyt8c4qWrjUEI1C9xkEB_SgWKcOW5cg X-Proofpoint-GUID: Dsyt8c4qWrjUEI1C9xkEB_SgWKcOW5cg Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: u4QeFwoGQMkQWnTIhP34Y7D1x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540712770100015 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds watchdog driver for Odyssey SoC. Signed-off-by: Narinder Dhillon --- .../Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c | 408 ++++++++++++++++++ .../Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf | 45 ++ 2 files changed, 453 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c create mode 100644 Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogD= xe.inf diff --git a/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c b/Sil= icon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c new file mode 100644 index 0000000000..c8f2888423 --- /dev/null +++ b/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c @@ -0,0 +1,408 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell Watchdog driver +* +**/ + + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define GTI_CWD_WDOG(Core) (FixedPcdGet64(PcdGtiWatchdogBase64) + 0x400= 00 + Core * 0x8) +#define GTI_CWD_POKE(Core) (FixedPcdGet64(PcdGtiWatchdogBase64) + 0x500= 00 + Core * 0x8) + +typedef union _GTI_CWD_WDOG_UNION { + UINT64 U64; + struct { + UINTN Mode : 2; + UINTN State : 2; + UINTN Len : 16; + UINTN Cnt : 24; + UINTN DStop : 1; + UINTN GStop : 1; + UINTN Rsvd : 18; + } PACKED S; +} GTI_CWD_WDOG_UNION; + +#define CWD_WDOG_MODE_RST (BIT1 | BIT0) + +#define RST_BOOT_PNR_MUL(Val) ((Val >> 33) & 0x1F) + +EFI_EVENT mGtiExitBootServicesEvent =3D (EFI_EVENT)NULL; +UINT32 mSclk =3D 0; +BOOLEAN mHardwarePlatform =3D TRUE; + +/** + Stop the GTI watchdog timer from counting down by disabling interrupts. +**/ +STATIC +VOID +GtiWdtStop ( + VOID + ) +{ + GTI_CWD_WDOG_UNION Wdog; + + MmioWrite64(GTI_CWD_POKE(0), 0); + + Wdog.U64 =3D MmioRead64(GTI_CWD_WDOG(0)); + + // Disable WDT + if (Wdog.S.Mode !=3D 0) { + Wdog.S.Len =3D 1; + Wdog.S.Mode =3D 0; + MmioWrite64 (GTI_CWD_WDOG(0), Wdog.U64); + } +} + +/** + Starts the GTI WDT countdown by enabling interrupts. + The count down will start from the value stored in the Load register, + not from the value where it was previously stopped. +**/ +STATIC +VOID +GtiWdtStart ( + VOID + ) +{ + GTI_CWD_WDOG_UNION Wdog; + + // Reset the WDT + MmioWrite64 (GTI_CWD_POKE(0), 0); + + Wdog.U64 =3D MmioRead64 (GTI_CWD_WDOG(0)); + + // Enable countdown + if (Wdog.S.Mode =3D=3D 0) { + Wdog.S.Mode =3D CWD_WDOG_MODE_RST; + MmioWrite64 (GTI_CWD_WDOG(0), Wdog.U64); + } +} + +/** + On exiting boot services we must make sure the SP805 Watchdog Timer + is stopped. +**/ +VOID +EFIAPI +GtiExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + MmioWrite64 (GTI_CWD_POKE(0), 0); + GtiWdtStop (); +} + +/** + This function registers the handler NotifyFunction so it is called every= time + the watchdog timer expires. It also passes the amount of time since the= last + handler call to the NotifyFunction. + If NotifyFunction is not NULL and a handler is not already registered, + then the new handler is registered and EFI_SUCCESS is returned. + If NotifyFunction is NULL, and a handler is already registered, + then that handler is unregistered. + If an attempt is made to register a handler when a handler is already re= gistered, + then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fir= es. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so = it can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The watchdog timer handler was registered. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler = is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was = not + previously registered. + @retval EFI_UNSUPPORTED HW does not support this functionality. + +**/ +EFI_STATUS +EFIAPI +GtiWdtRegisterHandler ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction + ) +{ + // UNSUPPORTED - The hardware watchdog will reset the board + return EFI_UNSUPPORTED; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 = nS units. If + the timer hardware is not programmable, then EF= I_UNSUPPORTED is + returned. If the timer is programmable, then th= e timer period + will be rounded up to the nearest timer period = that is supported + by the timer hardware. If TimerPeriod is set to= 0, then the + timer interrupts will be disabled. + + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of t= he timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due = to a device error. + +**/ +EFI_STATUS +EFIAPI +GtiWdtSetTimerPeriod ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod // In 100ns un= its + ) +{ + UINT32 Clock; + UINT64 CountDown; + GTI_CWD_WDOG_UNION Wdog; + + if (TimerPeriod =3D=3D 0) { + + // This is a watchdog stop request + GtiWdtStop(); + + return EFI_SUCCESS; + } else { + // + // The system is reset only after the WDT expires for the 3rd time + // + + Clock =3D mSclk / 1000000; //MHz + CountDown =3D DivU64x32 (MultU64x32 (TimerPeriod, Clock), 30); + + // WDT counts in 1024 cycle steps + // Only upper 16 bits can be used + + Wdog.U64 =3D 0; + Wdog.S.Len =3D (CountDown + (0xFF << 10)) >> 18; + MmioWrite64 (GTI_CWD_WDOG(0), Wdog.U64); + + // Start the watchdog + if (mHardwarePlatform =3D=3D TRUE) { + GtiWdtStart(); + } + } + + return EFI_SUCCESS; +} + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 10= 0 ns units. If + 0 is returned, then the timer is currently disa= bled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeri= od. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +GtiWdtGetTimerPeriod ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + UINT32 Clock; + UINT64 CountDown; + UINT64 ReturnValue; + GTI_CWD_WDOG_UNION Wdog; + + if (TimerPeriod =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Wdog.U64 =3D MmioRead64 (GTI_CWD_WDOG(0)); + + // Check if the watchdog is stopped + if (Wdog.S.Mode =3D=3D 0) { + // It is stopped, so return zero. + ReturnValue =3D 0; + } else { + // Convert the Watchdog ticks into TimerPeriod + Clock =3D mSclk / 1000000; //MHz + CountDown =3D Wdog.S.Len << 18; + + ReturnValue =3D MultU64x32(DivU64x32(3 * CountDown, Clock), 10); // us= ecs * 10 + } + + *TimerPeriod =3D ReturnValue; + + return EFI_SUCCESS; +} + +/** + Interface structure for the Watchdog Architectural Protocol. + + @par Protocol Description: + This protocol provides a service to set the amount of time to wait + before firing the watchdog timer, and it also provides a service to + register a handler that is invoked when the watchdog timer fires. + + @par When the watchdog timer fires, control will be passed to a handler + if one has been registered. If no handler has been registered, + or the registered handler returns, then the system will be + reset by calling the Runtime Service ResetSystem(). + + @param RegisterHandler + Registers a handler that will be called each time the + watchdogtimer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + NOTE: If the watchdog resets the system in hardware, then + this function will not have any chance of executing. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + +**/ +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer =3D { + (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) GtiWdtRegisterHandler, + (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) GtiWdtSetTimerPeriod, + (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) GtiWdtGetTimerPeriod +}; + +/** + Initialize the state information for the Watchdog Timer Architectural Pr= otocol. + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +GtiWdtInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle =3D NULL; + FDT_HANDLE SclkHandle =3D 0; + FDT_HANDLE RootHandle =3D 0; + CONST UINT32 *SclkFreq =3D NULL; + MRVL_FDT_CLIENT_PROTOCOL *FdtClient =3D NULL; + CONST CHAR8 *Platform; + + DEBUG ((DEBUG_INFO, "GtiWdtInitialize: Start\n")); + // Stop the watchdog from triggering unexpectedly + GtiWdtStop (); + + // + // Make sure the Watchdog Timer Architectural Protocol has not been inst= alled in the system yet. + // This will avoid conflicts with the universal watchdog + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolG= uid); + + Status =3D gBS->LocateProtocol (&gMrvlFdtClientProtocolGuid, + NULL, + (VOID **)&FdtClient); + + if (EFI_ERROR (Status) || (FdtClient =3D=3D NULL)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: cannot locate: gMrvlFdtClientProtocol= Guid\n", __func__)); + return EFI_ABORTED; + } + + Status =3D FdtClient->GetNode (FdtClient, "/soc@0/sclk", &SclkHandle); + if (EFI_ERROR (Status) || !SclkHandle) { + DEBUG ((DEBUG_ERROR, "%a: %s node not found!\n", __func__, L"/soc@0/sc= lk")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, "%a: Found: %s\n", __func__, L"/soc@0/sclk")); + Status =3D FdtClient->GetNodeProperty (FdtClient, + SclkHandle, + "clock-frequency", + (CONST VOID **)&SclkFreq, + NULL); + if (EFI_ERROR (Status) || NULL =3D=3D SclkFreq) { + DEBUG ((DEBUG_ERROR, "%a: %s property not found!\n", __func__, L"\"clo= ck-frequency\"")); + return EFI_NO_MAPPING; + } + + mSclk =3D FdtToCpu32(*SclkFreq); + DEBUG ((DEBUG_INFO, "%a: DT sclk =3D %d Mhz (0x%x)\n", __func__, mSclk/1= 000000, mSclk)); + + Status =3D FdtClient->GetNode (FdtClient, "/soc@0", &RootHandle); + if (!EFI_ERROR (Status) && RootHandle) { + Status =3D FdtClient->GetNodeProperty (FdtClient, + RootHandle, + "runplatform", + (CONST VOID **)&Platform, + NULL); + if (!EFI_ERROR (Status)) { + if (AsciiStrCmp (Platform, "HW_PLATFORM")) { + mHardwarePlatform =3D FALSE; + DEBUG ((DEBUG_INFO, "%a: Not a hardware platform\n", __func__)); + } + } + } + + // Register for an ExitBootServicesEvent + Status =3D gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + GtiExitBootServices, + NULL, + &mGtiExitBootServicesEvent); + ASSERT_EFI_ERROR(Status); + + // Install the Timer Architectural Protocol onto a new handle + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "GtiWdtInitialize: Exit\n")); + + return EFI_SUCCESS; +} diff --git a/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf = b/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf new file mode 100644 index 0000000000..e3470f831c --- /dev/null +++ b/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf @@ -0,0 +1,45 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2022 Marvell +# +# Module definition file for Marvell Watchdog driver. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D GtiWatchdogDxe + FILE_GUID =3D 789F5711-6FD3-4170-BE11-EE4000037EA8 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D GtiWdtInitialize + +[Sources.common] + GtiWatchdog.c + +[Packages] + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gMarvellSiliconTokenSpaceGuid.PcdGtiWatchdogBase64 + +[Protocols] + gEfiWatchdogTimerArchProtocolGuid #PRODUCES + gMrvlFdtClientProtocolGuid #CONSUMED + +[Depex] + gMrvlFdtClientProtocolGuid --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113974): https://edk2.groups.io/g/devel/message/113974 Mute This Topic: https://groups.io/mt/103800152/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113976+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113976+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540712; cv=none; d=zohomail.com; s=zohoarc; b=ZD7aaYvsr2X8MaNGsbF/CCHejxplSWOMHwKUeqtCfHlRwAHG13ZpvrQ9iHoAsnYPgNY4c320h57vaGN8MIRkHI7Sy1FqcuF47QkeAeEvRGiP481yPG1dZOCKqk8djuy3dkeJ0n0to4v5oHd5cpZg7HpTEWIQtmhMtVJn5iJJLnc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540712; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=v7p3khNN2rh5Zb5NRgVTct/AwuFG+znUmGWF2hjYrHg=; b=lD/qMeHdckvY6QbMprWxfCOqum3hK1YN6RvtIQjZ41ZkeWoxHV80ke1LVasSrV6tvP87aM9lOirxeKoGzq05oBI0GsZPlnWREDsZiNFr3pjjADTE0Mk8eCmxwGhqq1XQVi7tvmxF77IiVPcf3LQ/w3GoaNAPdlGFy1deRgS3d9A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113976+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 17055407124901000.7572908064353; Wed, 17 Jan 2024 17:18:32 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=1w/NSW0ECbT0eBexYzN0RtuTebNB08BIYjZOuTiJ1Sk=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540712; v=1; b=TeA0xYmL7tw1+83//EEUYj8yA9JHPl6pBHnxGahIDM859iKUAR7ez5dxD3I0Rs5fMhR82MoC 71jGvl3F7XlK6Sh7lkvSLcIf1wzTJpN33MJqj6rlxXVkdYMAuXIDGmDP3h2eg0o46z0MjDmP0+N InjgU5pzvF2s3GxjA/zF44UE= X-Received: by 127.0.0.2 with SMTP id 2vr5YY1788612xEps8JqaOsi; Wed, 17 Jan 2024 17:18:32 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mx.groups.io with SMTP id smtpd.web10.930.1705540711230935546 for ; Wed, 17 Jan 2024 17:18:31 -0800 X-Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HI2Q1I003958; Wed, 17 Jan 2024 17:18:30 -0800 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3vp0ge68ey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:30 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:28 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:28 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id DB17C3F707D; Wed, 17 Jan 2024 17:18:27 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 4/7] Silicon/Marvell: Device tree driver Date: Wed, 17 Jan 2024 17:18:14 -0800 Message-ID: <20240118011817.4348-5-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: zHi_jn6HEZJFIDXZCDjyk7w8bKgI6TTh X-Proofpoint-ORIG-GUID: zHi_jn6HEZJFIDXZCDjyk7w8bKgI6TTh Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: BtYN9gK3bpG0Sp5XySh5Nq0Ax1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540714660100022 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds a device tree driver that is used to read board configuration information from a device tree. Signed-off-by: Narinder Dhillon --- .../Drivers/Fdt/FdtClientDxe/FdtClientDxe.c | 382 ++++++++++++++++++ .../Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf | 43 ++ .../Include/Protocol/FdtClient.h | 180 +++++++++ 3 files changed, 605 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.i= nf create mode 100644 Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtC= lient.h diff --git a/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c b/Sili= con/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c new file mode 100644 index 0000000000..8741a41e46 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c @@ -0,0 +1,382 @@ +/** @file +* FDT client driver +* +* Copyright (c) 2016, Cavium Inc. All rights reserved.
+* Copyright (c) 2016, Linaro Ltd. All rights reserved.
+* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +STATIC VOID *mDeviceTreeBase; + +STATIC +EFI_STATUS +GetNodeProperty ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + OUT CONST VOID **Prop, + OUT UINT32 *PropSize OPTIONAL + ) +{ + INT32 Len; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Prop !=3D NULL); + + *Prop =3D fdt_getprop (mDeviceTreeBase, Node, PropertyName, &Len); + if (*Prop =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + if (PropSize !=3D NULL) { + *PropSize =3D Len; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SetNodeProperty ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + IN CONST VOID *Prop, + IN UINT32 PropSize + ) +{ + INT32 Ret; + + ASSERT (mDeviceTreeBase !=3D NULL); + + Ret =3D fdt_setprop (mDeviceTreeBase, Node, PropertyName, Prop, PropSize= ); + if (Ret !=3D 0) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +FindCompatibleNode ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *CompatibleString, + IN FDT_HANDLE PrevNode, + OUT FDT_HANDLE *Node + ) +{ + FDT_HANDLE Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_node_offset_by_compatible (mDeviceTreeBase, PrevNode, Com= patibleString); + + if (Offset < 0) { + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetOrInsertChosenNode ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + OUT INT32 *Node + ) +{ + INT32 NewNode; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + NewNode =3D fdt_path_offset (mDeviceTreeBase, "/chosen"); + + if (NewNode < 0) { + NewNode =3D fdt_add_subnode (mDeviceTreeBase, 0, "/chosen"); + } + + if (NewNode < 0) { + return EFI_OUT_OF_RESOURCES; + } + + *Node =3D NewNode; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNodeDepth ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT INT32 *Depth +) +{ + *Depth =3D fdt_node_depth (mDeviceTreeBase, Node); + + if (*Depth < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetParentNode ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT FDT_HANDLE *Parent +) +{ + *Parent =3D fdt_parent_offset (mDeviceTreeBase, Node); + + if (*Parent < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNode ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *Path, + OUT FDT_HANDLE *Node +) +{ + *Node =3D fdt_path_offset (mDeviceTreeBase, Path); + + if (*Node < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNodePath ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Node, + OUT CHAR8 *Path, + IN INT32 Size +) +{ + INT32 Result; + + Result =3D fdt_get_path (mDeviceTreeBase, Node, Path, Size); + + if (Result < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNodeByPropertyValue ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE StartNode, + IN CHAR8 *Property, + IN VOID *Value, + IN INT32 Size, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_node_offset_by_prop_value (mDeviceTreeBase, StartNode, + Property, Value, + Size); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetSubnodeByPropertyValue( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + IN CHAR8 *PropertyName, + IN VOID *PropertyValue, + IN INT32 PropertyLength, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + CONST VOID *Property; + INT32 Length; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_first_subnode (mDeviceTreeBase, Parent); + + while (Offset > 0) { + Property =3D fdt_getprop (mDeviceTreeBase, Offset, PropertyName, &Leng= th); + + if ((Property !=3D NULL) && + (PropertyLength =3D=3D Length) && + (CompareMem (Property, PropertyValue, Length) =3D=3D 0)) { + *Node =3D Offset; + return EFI_SUCCESS; + } + + Offset =3D fdt_next_subnode(mDeviceTreeBase, Offset); + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +GetNodeByPHandle ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE PHandle, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_node_offset_by_phandle (mDeviceTreeBase, PHandle); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetFirstSubnode ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_first_subnode (mDeviceTreeBase, Parent); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNextSubnode ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Subnode, + OUT FDT_HANDLE *Next +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Next !=3D NULL); + + Offset =3D fdt_next_subnode (mDeviceTreeBase, Subnode); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Next =3D Offset; + + return EFI_SUCCESS; +} + +STATIC MRVL_FDT_CLIENT_PROTOCOL mFdtClientProtocol =3D { + GetNodeProperty, + SetNodeProperty, + FindCompatibleNode, + GetOrInsertChosenNode, + GetNodeDepth, + GetParentNode, + GetNode, + GetNodePath, + GetNodeByPropertyValue, + GetSubnodeByPropertyValue, + GetNodeByPHandle, + GetFirstSubnode, + GetNextSubnode +}; + +EFI_STATUS +EFIAPI +InitializeFdtClientDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + VOID *Hob; + VOID *DeviceTreeBase; + + Hob =3D GetFirstGuidHob (&gFdtHobGuid); + + if (Hob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + DeviceTreeBase =3D GET_GUID_HOB_DATA (Hob); + mDeviceTreeBase =3D (VOID *)*(UINT64 *)DeviceTreeBase; + if (fdt_check_header (mDeviceTreeBase)) { + DEBUG ((DEBUG_ERROR, "No DTB found @ 0x%p\n", DeviceTreeBase)); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, "DTB @ 0x%p\n", mDeviceTreeBase)); + + return gBS->InstallMultipleProtocolInterfaces (&ImageHandle, + &gMrvlFdtClientProtocolGuid, &mFdt= ClientProtocol, + NULL); +} diff --git a/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf b/Si= licon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf new file mode 100644 index 0000000000..26362344f7 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf @@ -0,0 +1,43 @@ +## @file +# FDT client driver +# +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FdtClientDxe + FILE_GUID =3D 9A871B00-1C16-4F61-8D2C-93B6654B5AD6 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeFdtClientDxe + +[Sources] + FdtClientDxe.c + +[Packages] + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + FdtLib + HobLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gMrvlFdtClientProtocolGuid ## PRODUCES + +[Guids] + gFdtHobGuid + gFdtTableGuid + +[Depex] + TRUE diff --git a/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtClient.h= b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtClient.h new file mode 100644 index 0000000000..38480c8831 --- /dev/null +++ b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtClient.h @@ -0,0 +1,180 @@ +/** @file + + DISCLAIMER: the FDT_CLIENT_PROTOCOL introduced here is a work in progres= s, + and should not be used outside of the EDK II tree. + + Copyright (C) 2023 Marvell + Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FDT_CLIENT_H__ +#define __FDT_CLIENT_H__ + +#define FDT_CLIENT_PROTOCOL_GUID { \ + 0xE11FACA0, 0x4710, 0x4C8E, {0xA7, 0xA2, 0x01, 0xBA, 0xA2, 0x59, 0x1B, 0= x4C} \ + } + +#define FdtToCpu32(Value) SwapBytes32(Value) +#define CpuToFdt32(Value) SwapBytes32(Value) + +#define FdtToCpu64(Value) SwapBytes64(Value) +#define CpuToFdt64(Value) SwapBytes64(Value) + +// +// Protocol interface structure +// +typedef int FDT_HANDLE; +#define FDT_START_HANDLE -1 +typedef struct _MRVL_FDT_CLIENT_PROTOCOL MRVL_FDT_CLIENT_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NODE_PROPERTY) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + OUT CONST VOID **Prop, + OUT UINT32 *PropSize OPTIONAL + ); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_SET_NODE_PROPERTY) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + IN CONST VOID *Prop, + IN UINT32 PropSize + ); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_FIND_COMPATIBLE_NODE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *CompatibleString, + IN FDT_HANDLE PrevNode, + OUT FDT_HANDLE *Node + ); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_FIND_COMPATIBLE_NODE_PROPERTY) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *CompatibleString, + IN CONST CHAR8 *PropertyName, + OUT CONST VOID **Prop, + OUT UINT32 *PropSize OPTIONAL + ); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_OR_INSERT_CHOSEN_NODE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + OUT FDT_HANDLE *Node + ); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NODE_DEPTH) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT FDT_HANDLE *Depth +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_PARENT_NODE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT FDT_HANDLE *Parent +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NODE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *Path, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NODE_PATH) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Node, + OUT CHAR8 *Path, + IN INT32 Size +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NODE_BY_PROPERTY_VALUE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE StartNode, + IN CHAR8 *Property, + IN VOID *Value, + IN INT32 Size, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_SUBNODE_BY_PROPERTY_VALUE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + IN CHAR8 *PropertyName, + IN VOID *PropertyValue, + IN INT32 PropertyLength, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NODE_BY_PHANDLE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE PHandle, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_FIRST_SUBNODE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + OUT FDT_HANDLE *Node + ); + +typedef +EFI_STATUS +(EFIAPI *MRVL_FDT_CLIENT_GET_NEXT_SUBNODE) ( + IN MRVL_FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Subnode, + OUT FDT_HANDLE *Next + ); + +struct _MRVL_FDT_CLIENT_PROTOCOL { + MRVL_FDT_CLIENT_GET_NODE_PROPERTY GetNodeProperty; + MRVL_FDT_CLIENT_SET_NODE_PROPERTY SetNodeProperty; + + MRVL_FDT_CLIENT_FIND_COMPATIBLE_NODE FindCompatibleNode; + + MRVL_FDT_CLIENT_GET_OR_INSERT_CHOSEN_NODE GetOrInsertChosenNode; + + MRVL_FDT_CLIENT_GET_NODE_DEPTH GetNodeDepth; + MRVL_FDT_CLIENT_GET_PARENT_NODE GetParentNode; + MRVL_FDT_CLIENT_GET_NODE GetNode; + MRVL_FDT_CLIENT_GET_NODE_PATH GetNodePath; + MRVL_FDT_CLIENT_GET_NODE_BY_PROPERTY_VALUE GetNodeByPropertyValue; + MRVL_FDT_CLIENT_GET_SUBNODE_BY_PROPERTY_VALUE GetSubnodeByPropertyValue; + MRVL_FDT_CLIENT_GET_NODE_BY_PHANDLE GetNodeByPHandle; + MRVL_FDT_CLIENT_GET_FIRST_SUBNODE GetFirstSubnode; + MRVL_FDT_CLIENT_GET_NEXT_SUBNODE GetNextSubnode; + +}; + +extern EFI_GUID gMrvlFdtClientProtocolGuid; + +#endif --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113976): https://edk2.groups.io/g/devel/message/113976 Mute This Topic: https://groups.io/mt/103800155/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113978+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113978+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540733; cv=none; d=zohomail.com; s=zohoarc; b=UMrWINSbh0QUQDFe749wLhCj64q1uqJDEzIhzCpoqSKsw4NDUVzTFIuYdHkVJjjuu0IDRBVY4r7aR6SQwnk6MFm3ZKPKWXmbgMdfyWQE6c00fpz0vWGueqZf/jtXaGx8ZKCtyL2WX5Zol7yFXbEFK0hJFfJjjzmp7aOrYiEgOq4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540733; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=zHBBkcTd4F5eVz5ZYv9iQDS9tJiQQkZWrl7v/V7Rzio=; b=ExkO8O6/68VXp2lSoFO2PxosDL9B70s/fEoQKKmrHVMv1f7xfdBLugNXnS28vbP8q5V0aol2L3gN9PHMzR7BE2Ccbt9Z+GHK43SUi0WtXhnJ8S+SmUJCcsldpJ4PHUIKJtpBsiAqPtc+Pz0DJ7JTiPY32hqy/pljQbDYXvEjckQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113978+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540733131220.18549634751548; Wed, 17 Jan 2024 17:18:53 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=5ylUcbcXb1Fji5T/btcYs/AlcUCuP1RWxyb0ls1lEHs=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540732; v=1; b=IuImDJEKdNKIBHNzj9P0BDQSJMFKcMge3oPe/ZA0Lsr7Ti91kyPl3B3LGLN8+j7Loi0f+07b Gg0hTxyemtA5zyjR8Ih72ZJynLmagrU7fkeb7xS9FX+6I80gwQ9zsXaIGCUPMAgxiuyJJw5Znig SNiWKSerJUfHHQl7VrjD6Y7w= X-Received: by 127.0.0.2 with SMTP id deoZYY1788612xBZS0LjgcOe; Wed, 17 Jan 2024 17:18:52 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.936.1705540731926646491 for ; Wed, 17 Jan 2024 17:18:51 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHGq0R008637; Wed, 17 Jan 2024 17:18:51 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4st-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:51 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:49 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:28 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id 377E43F7081; Wed, 17 Jan 2024 17:18:28 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 5/7] Silicon/Marvell: Driver to publish device tree Date: Wed, 17 Jan 2024 17:18:15 -0800 Message-ID: <20240118011817.4348-6-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 6etvcSQPhq5U763oIdd0TDNhl3TMjX7W X-Proofpoint-GUID: 6etvcSQPhq5U763oIdd0TDNhl3TMjX7W Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 85i8CX2EeIBTQ8r9n7wwQymLx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540734866100002 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds driver that can provide device tree to OS if user so wishes. PCD's are used to enable this, default is not to take this action. Signed-off-by: Narinder Dhillon --- .../Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c | 259 ++++++++++++++++++ .../Fdt/FdtPlatformDxe/FdtPlatformDxe.inf | 49 ++++ .../MarvellSiliconPkg/MarvellSiliconPkg.dec | 20 ++ 3 files changed, 328 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformD= xe.inf diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c b/Sil= icon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c new file mode 100644 index 0000000000..cc3b853dff --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c @@ -0,0 +1,259 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + https://spdx.org/licenses + + Copyright (C) 2023 Marvell + + Copyright (c) 2015, ARM Ltd. All rights reserved.
+ +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +// +// Internal variables +// + +VOID *mFdtBlobBase; + +EFI_STATUS +DeleteFdtNode ( + IN VOID *FdtAddr, + CONST CHAR8 *NodePath, + CONST CHAR8 *Compatible +) +{ + INTN Offset =3D -1; + INTN Return; + + if ((NodePath !=3D NULL) && (Compatible !=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (NodePath !=3D NULL) { + Offset =3D fdt_path_offset (FdtAddr, NodePath); + + DEBUG ((DEBUG_INFO, "Offset: %d\n", Offset)); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Error getting the device node %a offset: %a\n", + NodePath, fdt_strerror (Offset))); + return EFI_NOT_FOUND; + } + } + + if (Compatible !=3D NULL) { + Offset =3D fdt_node_offset_by_compatible (FdtAddr, -1, Compatible); + + DEBUG ((DEBUG_INFO, "Offset: %d\n", Offset)); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Error getting the device node for %a offset: %= a\n", + Compatible, fdt_strerror (Offset))); + return EFI_NOT_FOUND; + } + } + + if (Offset >=3D 0) { + Return =3D fdt_del_node (FdtAddr, Offset); + + DEBUG ((DEBUG_INFO, "Return: %d\n", Return)); + + if (Return < 0) { + DEBUG ((DEBUG_ERROR, "Error deleting the device node %a: %a\n", + NodePath, fdt_strerror (Return))); + return EFI_NOT_FOUND; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +DeleteRtcNode ( + IN VOID *FdtAddr + ) +{ + INT32 Offset, NameLen, Return; + BOOLEAN Found; + CONST CHAR8 *Name; + + Found =3D FALSE; + for (Offset =3D fdt_next_node(FdtAddr, 0, NULL); + Offset >=3D 0; + Offset =3D fdt_next_node(FdtAddr, Offset, NULL)) { + + Name =3D fdt_get_name(FdtAddr, Offset, &NameLen); + if (!Name) { + continue; + } + + if ((Name[0] =3D=3D 'r') && (Name[1] =3D=3D 't') && (Name[2] =3D=3D 'c= ')) { + Found =3D TRUE; + break; + } + } + + if (Found =3D=3D TRUE) { + Return =3D fdt_del_node (FdtAddr, Offset); + + if (Return < 0) { + DEBUG ((DEBUG_ERROR, "Error deleting the device node %a\n", Name)); + return EFI_NOT_FOUND; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FdtFixup( + IN VOID *FdtAddr + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + if (FeaturePcdGet(PcdFixupFdt)) { + Status |=3D DeleteFdtNode (FdtAddr, (CHAR8*)PcdGetPtr (PcdFdtConfigRoo= tNode), NULL); + + // Hide the RTC + Status |=3D DeleteRtcNode (FdtAddr); + } + + if (!EFI_ERROR(Status)) { + fdt_pack(FdtAddr); + } + + return EFI_SUCCESS; +} + + +/** + Install the FDT specified by its device path in text form. + + @retval EFI_SUCCESS The FDT was installed. + @retval EFI_NOT_FOUND Failed to locate a protocol or a file. + @retval EFI_INVALID_PARAMETER Invalid device path. + @retval EFI_UNSUPPORTED Device path not supported. + @retval EFI_OUT_OF_RESOURCES An allocation failed. +**/ +STATIC +EFI_STATUS +InstallFdt ( + VOID +) +{ + EFI_STATUS Status; + UINTN FdtBlobSize; + VOID *FdtConfigurationTableBase; + VOID *HobList; + EFI_HOB_GUID_TYPE *GuidHob; + + // + // Get the HOB list. If it is not present, then ASSERT. + // + HobList =3D GetHobList (); + ASSERT (HobList !=3D NULL); + + // + // Search for FDT GUID HOB. If it is not present, then + // there's nothing we can do. It may not exist on the update path. + // + GuidHob =3D GetNextGuidHob (&gFdtHobGuid, HobList); + if (GuidHob !=3D NULL) { + mFdtBlobBase =3D (VOID *)*(UINT64 *)(GET_GUID_HOB_DATA (GuidHob)); + FdtBlobSize =3D fdt_totalsize((VOID *)mFdtBlobBase); + + // + // Ensure that the FDT header is valid and that the Size of the Device= Tree + // is smaller than the size of the read file + // + if (fdt_check_header (mFdtBlobBase)) { + DEBUG ((DEBUG_ERROR, "InstallFdt() - FDT blob seems to be corrupt\= n")); + mFdtBlobBase =3D NULL; + Status =3D EFI_LOAD_ERROR; + goto Error; + } + } else { + Status =3D EFI_NOT_FOUND; + goto Error; + } + + Status =3D EFI_SUCCESS; + + if (FeaturePcdGet(PcdPublishFdt)) { + FdtConfigurationTableBase =3D AllocateRuntimeCopyPool (FdtBlobSize, mF= dtBlobBase); + + if (FdtConfigurationTableBase =3D=3D NULL) { + goto Error; + } + + Status =3D FdtFixup((VOID*)FdtConfigurationTableBase); + + if (EFI_ERROR (Status)) { + FreePool (FdtConfigurationTableBase); + goto Error; + } + + // + // Install the FDT into the Configuration Table + // + Status =3D gBS->InstallConfigurationTable ( + &gFdtTableGuid, + FdtConfigurationTableBase + ); + + if (EFI_ERROR (Status)) { + FreePool (FdtConfigurationTableBase); + } + } + +Error: + return Status; +} + +/** + Main entry point of the FDT platform driver. + + @param[in] ImageHandle The firmware allocated handle for the present = driver + UEFI image. + @param[in] *SystemTable A pointer to the EFI System table. + + @retval EFI_SUCCESS The driver was initialized. + @retval EFI_OUT_OF_RESOURCES The "End of DXE" event could not be alloc= ated or + there was not enough memory in pool to in= stall + the Shell Dynamic Command protocol. + @retval EFI_LOAD_ERROR Unable to add the HII package. + +**/ +EFI_STATUS +FdtPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Install the Device Tree from its expected location + // + Status =3D InstallFdt (); + + ASSERT_EFI_ERROR(Status); + + return Status; +} diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf = b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf new file mode 100644 index 0000000000..4e254f17cb --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf @@ -0,0 +1,49 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# Copyright (c) 2015, ARM Ltd. All rights reserved.
+# +#**/ + +[Defines] + INF_VERSION =3D 0x00010006 + BASE_NAME =3D FdtPlatformDxe + FILE_GUID =3D 6e9a4c69-57c6-4fcd-b083-4f2c3bdb6051 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 0.1 + ENTRY_POINT =3D FdtPlatformEntryPoint + +[Sources.common] + FdtPlatform.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/ARM/ARM.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + FdtLib + HobLib + +[Guids] + gFdtHobGuid + gFdtTableGuid + +[FeaturePcd] + gMarvellSiliconTokenSpaceGuid.PcdPublishFdt + gMarvellSiliconTokenSpaceGuid.PcdFixupFdt + +[FixedPcd] + gMarvellSiliconTokenSpaceGuid.PcdFdtConfigRootNode + +[Depex] + TRUE diff --git a/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec b/Sili= con/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec index 1e17152f13..d3106f0c5d 100644 --- a/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec +++ b/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec @@ -28,6 +28,7 @@ gShellEepromHiiGuid =3D { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce= , 0x7b, 0x91, 0x7f, 0x5f, 0x2f } } gShellFUpdateHiiGuid =3D { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4= a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } } gShellSfHiiGuid =3D { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x= 0f, 0x6d, 0x58, 0x81, 0x39 } } + gShellDumpFdtHiiGuid =3D { 0x8afa7610, 0x62b1, 0x46aa, { 0xb5, 0x34, 0xc= 3, 0xde, 0xff, 0x39, 0x77, 0x8c } } =20 [LibraryClasses] ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h @@ -42,6 +43,8 @@ # that depend on the lowlevel platform initialization having been comple= ted gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } =20 + gMrvlFdtClientProtocolGuid =3D { 0xE11FACA0, 0x4710, 0x4C8E, { 0xA7, 0xA= 2, 0x01, 0xBA, 0xA2, 0x59, 0x1B, 0x4C } } + [PcdsFixedAtBuild.common] #Board description gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 @@ -198,6 +201,23 @@ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004 gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005 =20 +# FDT + # FDT configuration node to be stripped before passing to OS + gMarvellSiliconTokenSpaceGuid.PcdFdtConfigRootNode|"/marvell,ebf"|VOID*|= 0x50000090 + + gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase|0x10000000000|UINT64|0x000= 00004 + gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress|0x800000000000|UINT64|0x0= 0000005 + gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress|0x100000000000|UINT64= |0x00000006 + gMarvellSiliconTokenSpaceGuid.PcdIoSize|0xF0000000000|UINT64|0x00000007 + + gMarvellSiliconTokenSpaceGuid.PcdGtiWatchdogBase64|0x802000000000|UINT64= |0x00000008 + +[PcdsFeatureFlag.common] + # Publish FDT to the OS as Configuration Table with gFdtTableGuid + gMarvellSiliconTokenSpaceGuid.PcdPublishFdt|FALSE|BOOLEAN|0x50000091 + # Fixup the FDT or not (taken into consideration only when PcdPublishFdt= =3D TRUE) + gMarvellSiliconTokenSpaceGuid.PcdFixupFdt|TRUE|BOOLEAN|0x50000092 + [Protocols] gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113978): https://edk2.groups.io/g/devel/message/113978 Mute This Topic: https://groups.io/mt/103800162/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113975+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113975+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540716; cv=none; d=zohomail.com; s=zohoarc; b=KHsWG38Ecndl59OPvaFFFnaAi0o7x0G0lJf47g5qR47Cv44cB3fkEcaoE0+v1uXl1EL13EZF+92e7BFnMqeWFGW0pdcn7IO8f4KMJnd4Hr1T/nA9UnikGVw5YIvyiJZSZ1RrbR9HCLRXh6U9iPw2TdTQ+5jLUwbKgeIne2GtXfY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540716; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=e46W8SeSlZ4d4A1R3QMl+oatQQUb7bK7lr7D+5rSSCs=; b=JEbDB0ocN89Bdz0iELEt7jXsGgn5KOG9I3zpDSJaMOa1pSzC8hFuGHYaQ6i9elNnCUhdV7vYt2Lg5X/6p1sT3DYX0paRYsmeiIOmJCx8eYTfYeXka+B1YmOn2HShc7tdC+a6i2y9Q7ou5YDO4dDu86SF5Ahv1wqtdL0VSIpoPK0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113975+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540716964719.3377282550099; Wed, 17 Jan 2024 17:18:36 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=9K37FlL2rCdUgHVeiLKGuf6SvEkH/9BYz9EKIEIy2Cg=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540716; v=1; b=QVB7FI0RsZT46BtfOhjcBxWZeClFW/9h8Jo+2i8qlF8rU5ioneGpVyXVPcxZ9LhIF7Fd4tpx vdlylBqE22cpkulXpkjR1rYmmMHco7Ywnqpz2QjUyACjaoSh9X/sfmID5BSnC24Ed5w9KIa8ihH O2TMGsUtSW/0zak9Ar9qaZtM= X-Received: by 127.0.0.2 with SMTP id HwRhYY1788612xEAD8lYQBzl; Wed, 17 Jan 2024 17:18:36 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.918.1705540711124260531 for ; Wed, 17 Jan 2024 17:18:31 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHSY3f029567; Wed, 17 Jan 2024 17:18:31 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4ru-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:30 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:28 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:28 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id 8F5CE3F7084; Wed, 17 Jan 2024 17:18:28 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 6/7] Silicon/Marvell: Command to dump device tree Date: Wed, 17 Jan 2024 17:18:16 -0800 Message-ID: <20240118011817.4348-7-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: sMGP6mDoMmppvASD0u3uPxjBEOrzcrR- X-Proofpoint-GUID: sMGP6mDoMmppvASD0u3uPxjBEOrzcrR- Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: hUhCKVmKrHw0MJWJuVylVAbDx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540718753100001 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds an EDK2 shell command to dump configuration device tree. Signed-off-by: Narinder Dhillon --- .../Marvell/Applications/DumpFdt/DumpFdt.c | 344 ++++++++++++++++++ .../Marvell/Applications/DumpFdt/DumpFdt.inf | 52 +++ .../Marvell/Applications/DumpFdt/DumpFdt.uni | 35 ++ 3 files changed, 431 insertions(+) create mode 100644 Silicon/Marvell/Applications/DumpFdt/DumpFdt.c create mode 100644 Silicon/Marvell/Applications/DumpFdt/DumpFdt.inf create mode 100644 Silicon/Marvell/Applications/DumpFdt/DumpFdt.uni diff --git a/Silicon/Marvell/Applications/DumpFdt/DumpFdt.c b/Silicon/Marve= ll/Applications/DumpFdt/DumpFdt.c new file mode 100644 index 0000000000..7abfb62a2c --- /dev/null +++ b/Silicon/Marvell/Applications/DumpFdt/DumpFdt.c @@ -0,0 +1,344 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + https://spdx.org/licenses + + Copyright (C) 2023 Marvell + + Copyright (c) 2015, ARM Ltd. All rights reserved.
+ +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMD_NAME_STRING L"dumpfdt" + +STATIC EFI_HII_HANDLE gShellDumpFdtHiiHandle =3D NULL; +STATIC VOID *mFdtBlobBase =3D NULL; +STATIC CONST CHAR16 gShellDumpFdtFileName[] =3D L"ShellCommands"; + +#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) +#define PALIGN(p, a) ((void *)(ALIGN ((unsigned long)(p), (a)))) +#define GET_CELL(p) (p +=3D 4, *((const uint32_t *)(p-4))) + +STATIC +UINTN +IsPrintableString ( + IN CONST VOID* data, + IN UINTN len + ) +{ + CONST CHAR8 *s =3D data; + CONST CHAR8 *ss; + + // Zero length is not + if (len =3D=3D 0) { + return 0; + } + + // Must terminate with zero + if (s[len - 1] !=3D '\0') { + return 0; + } + + ss =3D s; + while (*s/* && isprint (*s)*/) { + s++; + } + + // Not zero, or not done yet + if (*s !=3D '\0' || (s + 1 - ss) < len) { + return 0; + } + + return 1; +} + +STATIC +VOID +PrintData ( + IN CONST CHAR8* data, + IN UINTN len + ) +{ + UINTN i; + CONST CHAR8 *p =3D data; + + // No data, don't print + if (len =3D=3D 0) + return; + + if (IsPrintableString (data, len)) { + Print (L" =3D \"%a\"", (const char *)data); + } else if ((len % 4) =3D=3D 0) { + Print (L" =3D <"); + for (i =3D 0; i < len; i +=3D 4) { + Print (L"0x%08x%a", fdt32_to_cpu (GET_CELL (p)), i < (len - 4) ? " "= : ""); + } + Print (L">"); + } else { + Print (L" =3D ["); + for (i =3D 0; i < len; i++) + Print (L"%02x%a", *p++, i < len - 1 ? " " : ""); + Print (L"]"); + } +} + +STATIC +VOID +DumpFdt ( + IN VOID* FdtBlob + ) +{ + struct fdt_header *bph; + UINT32 off_dt; + UINT32 off_str; + CONST CHAR8* p_struct; + CONST CHAR8* p_strings; + CONST CHAR8* p; + CONST CHAR8* s; + CONST CHAR8* t; + UINT32 tag; + UINTN sz; + UINTN depth; + UINTN shift; + UINT32 version; + + { + // Can 'memreserve' be printed by below code? + INTN num =3D fdt_num_mem_rsv (FdtBlob); + INTN i, err; + UINT64 addr =3D 0, size =3D 0; + + for (i =3D 0; i < num; i++) { + err =3D fdt_get_mem_rsv (FdtBlob, i, &addr, &size); + if (err) { + DEBUG ((DEBUG_ERROR, "Error (%d) : Cannot get memreserve section (= %d)\n", err, i)); + } + else { + Print (L"/memreserve/ \t0x%lx \t0x%lx;\n", addr, size); + } + } + } + + depth =3D 0; + shift =3D 4; + + bph =3D FdtBlob; + off_dt =3D fdt32_to_cpu (bph->off_dt_struct); + off_str =3D fdt32_to_cpu (bph->off_dt_strings); + p_struct =3D (CONST CHAR8*)FdtBlob + off_dt; + p_strings =3D (CONST CHAR8*)FdtBlob + off_str; + version =3D fdt32_to_cpu (bph->version); + + p =3D p_struct; + while ((tag =3D fdt32_to_cpu (GET_CELL (p))) !=3D FDT_END) { + if (tag =3D=3D FDT_BEGIN_NODE) { + s =3D p; + p =3D PALIGN (p + AsciiStrLen (s) + 1, 4); + + if (*s =3D=3D '\0') + s =3D "/"; + + Print (L"%*s%a {\n", depth * shift, L" ", s); + + depth++; + continue; + } + + if (tag =3D=3D FDT_END_NODE) { + depth--; + + Print (L"%*s};\n", depth * shift, L" "); + continue; + } + + if (tag =3D=3D FDT_NOP) { + /* Print (L"%*s// [NOP]\n", depth * shift, L" "); */ + continue; + } + + if (tag !=3D FDT_PROP) { + Print (L"%*s ** Unknown tag 0x%08x\n", depth * shift, L" ", tag); + break; + } + sz =3D fdt32_to_cpu (GET_CELL (p)); + s =3D p_strings + fdt32_to_cpu (GET_CELL (p)); + if (version < 16 && sz >=3D 8) + p =3D PALIGN (p, 8); + t =3D p; + + p =3D PALIGN (p + sz, 4); + + Print (L"%*s%a", depth * shift, L" ", s); + PrintData (t, sz); + Print (L";\n"); + } +} + +STATIC +SHELL_STATUS +EFIAPI +ShellCommandRunDumpFdt ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + SHELL_STATUS ShellStatus; + EFI_STATUS Status; + + ShellStatus =3D SHELL_SUCCESS; + + Status =3D ShellInitialize (); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return SHELL_ABORTED; + } + + DumpFdt (mFdtBlobBase); + + return ShellStatus; +} + +/** + Return the file name of the help text file if not using HII. + + @return The string pointer to the file name. +**/ +STATIC +CONST CHAR16* +EFIAPI +ShellCommandGetManFileNameDumpFdt ( + VOID + ) +{ + return gShellDumpFdtFileName; +} + +/** + Install the FDT specified by its device path in text form. + + @retval EFI_SUCCESS The FDT was installed. + @retval EFI_NOT_FOUND Failed to locate a protocol or a file. + @retval EFI_INVALID_PARAMETER Invalid device path. + @retval EFI_UNSUPPORTED Device path not supported. + @retval EFI_OUT_OF_RESOURCES An allocation failed. +**/ +STATIC +EFI_STATUS +InstallFdt ( + VOID +) +{ + EFI_STATUS Status; + VOID *HobList; + EFI_HOB_GUID_TYPE *GuidHob; + + // + // Get the HOB list. If it is not present, then ASSERT. + // + HobList =3D GetHobList (); + ASSERT (HobList !=3D NULL); + + // + // Search for FDT GUID HOB. If it is not present, then + // there's nothing we can do. It may not exist on the update path. + // + GuidHob =3D GetNextGuidHob (&gFdtHobGuid, HobList); + if (GuidHob !=3D NULL) { + mFdtBlobBase =3D (VOID *)*(UINT64 *)(GET_GUID_HOB_DATA (GuidHob)); + + // + // Ensure that the FDT header is valid and that the Size of the Device= Tree + // is smaller than the size of the read file + // + if (fdt_check_header (mFdtBlobBase)) { + DEBUG ((DEBUG_ERROR, "InstallFdt() - FDT blob seems to be corrupt\= n")); + mFdtBlobBase =3D NULL; + Status =3D EFI_LOAD_ERROR; + goto Error; + } + } else { + Status =3D EFI_NOT_FOUND; + goto Error; + } + + Status =3D EFI_SUCCESS; + +Error: + return Status; +} + +EFI_STATUS +EFIAPI +ShellDumpFdtCommandConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D InstallFdt(); + if (EFI_ERROR(Status)) { + Print (L"%s: Error while installing FDT\n", CMD_NAME_STRING); + return Status; + } + + gShellDumpFdtHiiHandle =3D NULL; + + gShellDumpFdtHiiHandle =3D HiiAddPackages ( + &gShellDumpFdtHiiGuid, + gImageHandle, + UefiShellDumpFdtLibStrings, + NULL + ); + + if (gShellDumpFdtHiiHandle =3D=3D NULL) { + Print (L"%s: Cannot add Hii package\n", CMD_NAME_STRING); + return EFI_DEVICE_ERROR; + } + + Status =3D ShellCommandRegisterCommandName ( + CMD_NAME_STRING, + ShellCommandRunDumpFdt, + ShellCommandGetManFileNameDumpFdt, + 0, + CMD_NAME_STRING, + TRUE, + gShellDumpFdtHiiHandle, + STRING_TOKEN (STR_GET_HELP_DUMPFDT) + ); + + if (EFI_ERROR(Status)) { + Print (L"%s: Error while registering command\n", CMD_NAME_STRING); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +ShellDumpFdtCommandDestructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + if (gShellDumpFdtHiiHandle !=3D NULL) { + HiiRemovePackages (gShellDumpFdtHiiHandle); + } + + return EFI_SUCCESS; +} diff --git a/Silicon/Marvell/Applications/DumpFdt/DumpFdt.inf b/Silicon/Mar= vell/Applications/DumpFdt/DumpFdt.inf new file mode 100644 index 0000000000..d24adaaae8 --- /dev/null +++ b/Silicon/Marvell/Applications/DumpFdt/DumpFdt.inf @@ -0,0 +1,52 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# Copyright (c) 2015, ARM Ltd. All rights reserved.
+# +#**/ + +[Defines] + INF_VERSION =3D 0x00010006 + BASE_NAME =3D UefiShellDumpFdtLib + FILE_GUID =3D 6e9a4c69-57c6-4fcd-b083-4f2c3bdb6051 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 0.1 + LIBRARY_CLASS =3D NULL|UEFI_APPLICATION UEFI_DRIVER + CONSTRUCTOR =3D ShellDumpFdtCommandConstructor + DESTRUCTOR =3D ShellDumpFdtCommandDestructor + +[Sources.common] + DumpFdt.c + DumpFdt.uni + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/ARM/ARM.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + ShellPkg/ShellPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + UefiLib + FdtLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + HiiLib + ShellCommandLib + ShellLib + HobLib + +[Guids] + gFdtHobGuid + gFdtTableGuid + gShellDumpFdtHiiGuid + +[FixedPcd] + gMarvellSiliconTokenSpaceGuid.PcdFdtConfigRootNode diff --git a/Silicon/Marvell/Applications/DumpFdt/DumpFdt.uni b/Silicon/Mar= vell/Applications/DumpFdt/DumpFdt.uni new file mode 100644 index 0000000000..bbfd44f2e0 --- /dev/null +++ b/Silicon/Marvell/Applications/DumpFdt/DumpFdt.uni @@ -0,0 +1,35 @@ +// *++ +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// https://spdx.org/licenses +// +// Copyright (C) 2023 Marvell +// +// Copyright (c) 2014, ARM Ltd. All rights reserved.
+// +// +// Module Name: +// +// DumpFdt +// +// Abstract: +// +// String definitions for the EFI Shell 'dumpfdt' command +// +// Revision History: +// +// --*/ + +/=3D# + +#langdef en-US "English" + +#string STR_GET_HELP_DUMPFDT #language en-US "" +".TH dumpfdt 0 "Dump installed Flat Device Tree (FDT) of the platform."\r\= n" +".SH NAME\r\n" +"Dump current Flat Device Tree (FDT)\r\n" +".SH SYNOPSIS\r\n" +"dumpfdt\r\n" +"\r\n" +".SH DESCRIPTION\r\n" +"\r\n" --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113975): https://edk2.groups.io/g/devel/message/113975 Mute This Topic: https://groups.io/mt/103800154/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 13:16:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+113977+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113977+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1705540712; cv=none; d=zohomail.com; s=zohoarc; b=m28YJttI5DAsKxE1gksoUPkJwdnugE15yj1Etbq5XAvXcvvVRbA+a0ZC7CDkwifM0nTUnDyVKYKJAFfNCjPyfX5AmmKrg5TWuMr+49Ge4hueiSDqxLQWguCdbtzOoSmeqrdOfXj1oxXMnXjbcVpt/vsADUIbDQvvWpkuQcCcPYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705540712; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=HeWuowh+St6sWAm4JgYrIZbSXM6GKDGuJxsW69xpkus=; b=XZGZvrIX9/8Rfk0xq+oVq3p6DaS6JXSoFIN2QqDujfPT4hhhTlwp7EbgwXMjmHBxyUU24aVdXg7qyeLLlPy53xzsRPDW06JUZE6k3+I2wYRl3QcaLLYew11C2wUIyDO7rPG6w1b3ccbfMm/uVsTkGA0/+yK2IPetldeD/tu1H60= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+113977+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1705540712742530.5086881908492; Wed, 17 Jan 2024 17:18:32 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=pXNtZ+V9ZHSK3y2ag42vJptR51ra7AiSde4p2MudQKA=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1705540712; v=1; b=aFDUyFI+O0266ZhEuEaWalm5pd6yVYAs9GQxykIa9ME2r7IhmP8Fko6qE4qfqGxVXzHJM1Ba +PUPzoMcxCmJxSYdfsOgoEbDrZOnLnQbuXc4T2J/1D85+QEH4eIYEJUb9pUc3yAEAJjPmhSGrrk AIVH6A52tpPYwpzqZUWOPg30= X-Received: by 127.0.0.2 with SMTP id zPcnYY1788612xowoDc9igO3; Wed, 17 Jan 2024 17:18:32 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.920.1705540711769391977 for ; Wed, 17 Jan 2024 17:18:31 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40HHSY3g029567; Wed, 17 Jan 2024 17:18:31 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpaskb4ru-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 17 Jan 2024 17:18:31 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 17:18:29 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.85.176.100]) by maili.marvell.com (Postfix) with ESMTP id CC6C63F7087; Wed, 17 Jan 2024 17:18:28 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v3 7/7] Silicon/Marvell: Odyssey project description files Date: Wed, 17 Jan 2024 17:18:17 -0800 Message-ID: <20240118011817.4348-8-ndhillon@marvell.com> In-Reply-To: <20240118011817.4348-1-ndhillon@marvell.com> References: <20240118011817.4348-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: TlmeX41Y0VumJcTlB4ELxQLAVV3FGWWG X-Proofpoint-GUID: TlmeX41Y0VumJcTlB4ELxQLAVV3FGWWG Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: fcjNtKkg2gLOY5FkS5JAEE9Lx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1705540714735100024 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds Odyssey SoC project description and flash description files. Signed-off-by: Narinder Dhillon --- Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc | 219 ++++++++++ Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf | 304 +++++++++++++ Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc | 399 ++++++++++++++++++ 3 files changed, 922 insertions(+) create mode 100644 Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc create mode 100644 Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf create mode 100644 Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc diff --git a/Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc b/Platform/Marvell/= OdysseyPkg/OdysseyPkg.dsc new file mode 100644 index 0000000000..a9dad7b029 --- /dev/null +++ b/Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc @@ -0,0 +1,219 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# The main build description file for OdysseyPkg. +#**/ + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D OdysseyPkg # PLAT=3Dody + PLATFORM_GUID =3D 7E7000DE-F50F-46AE-9B2C-903225F72B13 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 +!ifdef $(EDK2_OUT_DIR) # Custom output directory, e.g. -D EDK2_OUT_DIR=3DB= uild/XYZ + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/Marvell/$(PLATFORM_NAME)/$(P= LATFORM_NAME).fdf + +# dsc.inc file can be used in case there are different variants/boards of = Odyssey family. +# Per-board additional components shall be defined in exclusive dsc.inc fi= les. +!include Silicon/Marvell/$(PLATFORM_NAME)/$(PLATFORM_NAME).dsc.inc + +[LibraryClasses] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf # used by PlatformSmbiosDxe + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf # used by SmcLib + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf # used by Sp= iNorDxe + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf # used by UsbKbDxe + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLib= Null.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf # used by Ba= seBmpSupportLib +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf +!endif +# ShellPkg/Application/Shell/Shell.inf -> UefiShellCommandLib -> OrderedCo= llectionLib + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf # used by CapsuleApp + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + +[BuildOptions] +# GCC will generate code that runs on processors as idicated by -march +# Single =3D (append) allows flags appendixes coming from [BuildOptions] d= efined in specific INFs. + GCC:*_*_AARCH64_PLATFORM_FLAGS =3D -DPLAT=3D0xBF -march=3Darmv8.2-a -fdi= agnostics-color -fno-diagnostics-show-caret +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFixedAtBuild.common] + + # Generic Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x8020000A0000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x8020000B0000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|0x1A + + # BIT0 - Initialization message.
+ # BIT1 - Warning message.
+ # BIT2 - Load Event message.
+ # BIT3 - File System message.
+ # BIT6 - Information message.
+ # DEBUG_ERROR 0x80000000 // Error + # NOTE: Adjust according to needs. See MdePkg.dec for bits definition. + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F + + # The size of volatile buffer. This buffer is used to store VOLATILE att= ribute variables. + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x00040000 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Set ARM PCD: Odyssey: up to 80 Neoverse V2 cores (code named Demeter) + # Used to setup secondary cores stacks and ACPI PPTT. + gArmPlatformTokenSpaceGuid.PcdCoreCount|80 + + # Stacks for MPCores in Normal World, Non-Trusted DRAM + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # System Memory (40 - 1TB of DRAM) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00004000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000000 + + # Size of the region used by UEFI in permanent memory (Reserved 128MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000 + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x87e028000000 + + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x801000000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x801000080000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x801000020000 + + # Hardcoded terminal: TTYTERM, NOT defined in UEFI SPEC + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # UART port Divisor setting based on clock 16.66Mhz and baud 115200 + gArmPlatformTokenSpaceGuid.PL011UartInteger|9 + gArmPlatformTokenSpaceGuid.PL011UartFractional|2 + +[PcdsDynamicDefault.common] + + # Indicates if Variable driver will enable emulated variable NV mode. + # Reset by SpiNorDxe driver when SPI is in place and can handle storing = EFI Variables. + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + + # UEFI is placed in RAM by bootloader + ArmPlatformPkg/PrePi/PeiMPCore.inf { + + # SoC specific implementation of ArmPlatformLib + ArmPlatformLib|Silicon/Marvell/OdysseyPkg/Library/OdysseyLib/Odyssey= Lib.inf + } + + # + # PEI Phase modules + # + # PEI phase is skipped. SEC jumps directly to DXE. + + # + # Core DXE modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # DXE Status codes + # +!if $(DEBUG) =3D=3D 1 + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf +!endif + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePol= icyLibRuntimeDxe.inf + } + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + # Produces gEfiFaultTolerantWriteProtocolGuid needed for non-volatile UE= FI variable storage. + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # RTC Support + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/Virtual= RealTimeClockLib.inf + } + + # + # ARM Support + # + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Multiple Console IO support + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf diff --git a/Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf b/Platform/Marvell/= OdysseyPkg/OdysseyPkg.fdf new file mode 100644 index 0000000000..d017965475 --- /dev/null +++ b/Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf @@ -0,0 +1,304 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# The main Flash Description File for OdysseyPkg. +#**/ + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.ODYSSEY_AARCH64_EFI] # Name must match with FV_PREFIX from bootloader= /uefi/Makefile +BaseAddress =3D 0x04000000|gArmTokenSpaceGuid.PcdFdBaseAddress # UEFI i= n DRAM + 64MB. +Size =3D 0x01000000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the device (16MiB). +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x1000 + +# 2.5 M should be enough for all modules +0x00000000|0x00820000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 16 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D d248e9b7-9ce3-43a7-868e-70c17c4b3819 + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf # gEfi= PcdProtocolGuid + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf # gHar= dwareInterruptProtocolGuid + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf # gEfi= CpuArchProtocolGuid + } + + # + # Core DXE modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf # (in OdysseyPkg.dsc.inc) + + # + # DXE Status codes + # +!if $(DEBUG) =3D=3D 1 + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatu= sCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandle= rRuntimeDxe.inf +!endif + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConf= igDxe.inf +!endif + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + # Produces gEfiFaultTolerantWriteProtocolGuid needed for non-volatile UE= FI variable storage. + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf + + # RTC Support + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # ARM Support + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe= .inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + # FV Filesystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.i= nf + + # SectionExtraction + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + + # + # FDT support + # + # The UEFI driver is at the end of the list of the driver to be dispatch= ed + # after the device drivers (eg: Ethernet) to ensure we have support for = them. + INF Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf + INF Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + # + # SEC Phase modules + # + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + + # + # PEI Phase modules + # + # PEI phase is skipped. SEC jumps directly to DXE. + + # + # DXE Phase modules stored in separate LZMA compressed FV. + # + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc b/Silicon/Marvel= l/OdysseyPkg/OdysseyPkg.dsc.inc new file mode 100644 index 0000000000..899bd3516f --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc @@ -0,0 +1,399 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# DSC include file for OdysseyPkg. +# +# This file can be included to platform DSC file +# by using "!include OdysseyPkg.dsc.inc" // path relative to platform DSC= file. +# +#**/ + +[Defines] + SECURE_BOOT_ENABLE =3D FALSE + MIN_IMAGE =3D FALSE + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +[LibraryClasses.common] +!if $(TARGET) =3D=3D RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + + # + # Assume everything is fixed at build + # + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf +#!if $(MIN_IMAGE) =3D=3D FALSE + # Networking Requirements + DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf + UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf +#!endif + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + + # Boot manager + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + + # Silicon Specific Libraries + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + # ARM PL011 UART Library + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc= kLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The S= tandard IO window + # in the debugger will show load and unload commands for symbols. You ca= n cut and paste this + # into the command window to load symbols. We should be able to use a sc= ript to do this, but + # the version of RVD I have does not support scripts accessing system me= mory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffEx= traActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePe= CoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # RunAxf support via Dynamic Shell Command protocol + # It uses the Shell libraries. + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + + # Platform Support Libraries + SmcLib|Silicon/Marvell/Library/SmcLib/SmcLib.inf + +[LibraryClasses.common.SEC] + + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + # ARM PL011 UART Runtime Library + #SerialPortLib|Silicon/Marvell/Library/PL011SerialPortRuntimeLib/PL011Se= rialPortRuntimeLib.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf +!endif + +[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER] + # + # PSCI support in EL3 may not be available if we are not running under a= PSCI + # compliant secure firmware, but since the default VExpress EfiResetSyst= emLib + # cannot be supported at runtime (due to the fact that the syscfg MMIO r= egisters + # cannot be runtime remapped), it is our best bet to get ResetSystem fun= ctionality + # on these platforms. + # + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSyste= mLib.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. + # This library provides the instrinsic functions generate by a given com= piler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM imag= es. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + +[BuildOptions] + RVCT:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + # Need to set this to TRUE to stop secondary cores from booting in UEFI + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE + +[PcdsFixedAtBuild.common] +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER= )" +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL UEFI 5= .0.0" +!endif + +!ifdef $(RELEASE_DATE) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"$(RELEASE_= DATE)" +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"2022" +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 # BIT0 - = Enable Performance Measurement. + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Verbose + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80304FCF + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # RunAxf support via Dynamic Shell Command protocol + # We want to use the Shell Libraries but do not want it to initialise + # automatically. We initialise the libraries when the command is called = by the + # Shell. + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + # Define PcdBootManagerMenuFile as FILE_GUID of bootloader/uefi/MdeModul= ePkg/Application/UiApp/UiApp.inf + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # Max capsule size + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1400000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizePopulateCapsule|0x1400000 + + # Use MPIDR Affinity Level 2 to identify the PrimaryCore + # Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 1= 6 (Iliad) + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xFF0000 + +[PcdsDynamicHii.common.DEFAULT] +!if $(MIN_IMAGE) =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 +!endif + +[Components.common] + + # FV Filesystem + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # SectionExtraction + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf { + + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/Dx= eExtractGuidedSectionLib.inf + } + + # + # FDT support + # + Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf + Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf + + # No EMMC/SD Interface + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf + NULL|Silicon/Marvell/Applications/DumpFdt/DumpFdt.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + } + + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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