[v2] RISC-V: Add support for Sstc extension

[edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension

Posted by Sunil V L 3 months, 3 weeks ago

This series adds the support for RISC-V Sstc extension in EDK2 timer
implementation. Sstc extension allows S-mode software to program the
timer directly without using SBI calls.

Currently, PCD variable is used to detect whether feature is enabled. By
default the feature is enabled and platforms need to set the PCD to
disable the feature if Sstc is not supported.

For RiscVVirtQemu, it is disabled by default (until extension discovery
feature is enabled).

Changes since v1:
	1) Updated "PATCH 3" to address Laszlo's comments.
	2) Updated RB tag for PATCH 4.

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Sunil V L (4):
  MdePkg.dec: RISC-V: Define override bit for Sstc extension
  MdePkg/BaseLib: RISC-V: Add function to update stimecmp register
  UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc
  OvmfPkg/RiscVVirt: Override Sstc extension

 MdePkg/MdePkg.dec                             |  2 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
 .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
 MdePkg/Include/Library/BaseLib.h              |  5 ++
 .../Include/Register/RiscV64/RiscVEncoding.h  |  3 ++
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 +
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 49 +++++++++++++++++--
 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S    |  7 +++
 8 files changed, 67 insertions(+), 4 deletions(-)

-- 
2.34.1



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Re: [edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension

Posted by Sunil V L 3 months, 2 weeks ago

On Mon, Jan 08, 2024 at 05:06:46PM +0530, Sunil V L wrote:
> This series adds the support for RISC-V Sstc extension in EDK2 timer
> implementation. Sstc extension allows S-mode software to program the
> timer directly without using SBI calls.
> 
> Currently, PCD variable is used to detect whether feature is enabled. By
> default the feature is enabled and platforms need to set the PCD to
> disable the feature if Sstc is not supported.
> 
> For RiscVVirtQemu, it is disabled by default (until extension discovery
> feature is enabled).
> 
> Changes since v1:
> 	1) Updated "PATCH 3" to address Laszlo's comments.
> 	2) Updated RB tag for PATCH 4.
> 
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> 
Thank you very much for reviews!. Merged as #5232.

Thanks,
Sunil


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