From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112779+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112779+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120074; cv=none; d=zohomail.com; s=zohoarc; b=PIX6xq+eT/Zga2vpgupfzhypYCxxW107Zatozsts8Sfc8KOVH5S1FK4Z0zO1rF7iPViggF51PuAP9fECroOq3YdPQV/yyqz679dxdxOhbPQP+gSL6N5nZdKGZyn9wAZRmGWMs4m9+5Bm8eoi7Rz/kaPjZ0NThbA4HKi1lUgiRBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120074; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=WGuTaPA76zG/0YTi+lxGe6E1TdRENW/UQ24w2ZjD2dE=; b=cM1XWw0QlYn5w+NbhJUnTWtC17D7YpD9gK9knFatl3CizXiUIM1jCbtRlpSB7IkTcDiAPPiRblzeWOw/YNCJ4oyNgvAffb7y6a5uOJUPQc2gxp1jo0yxYDD+ylQ/GdfOy899Oh2jNe94eICkF7IJljT0C1okOhhJKzbVQ+xxsqU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112779+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703120074904247.45007000309636; Wed, 20 Dec 2023 16:54:34 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=FCu7AywxO//9JZIJ0A0QULGu86tTGYLsw8saanX9v5g=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120074; v=1; b=gbL8tG6/6sw8RwoDtYUw3kXobBpAdg0nuOfhT5w4YpIgxJkbTjKZjlwng5Yh4abbT7tbvlkM FKFS9kenXZ9CA/oAUd53pfiLSKDOK0cS6CJngAuG62PA/AYaa9UDwS5UqAERuuXCyCrdVgKoBnD FJqi8pQwTBkyt5xyRx9v1mIA= X-Received: by 127.0.0.2 with SMTP id evjwYY1788612xXDeF5Ao0c0; Wed, 20 Dec 2023 16:54:34 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.41711.1703120073790794913 for ; Wed, 20 Dec 2023 16:54:33 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKHJu0D004353; Wed, 20 Dec 2023 16:54:33 -0800 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v3tbcvg83-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:33 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:31 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:31 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id A80255C68E5; Wed, 20 Dec 2023 16:54:30 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 1/8] Silicon/Marvell: New Marvell Odyssey processor Date: Wed, 20 Dec 2023 16:54:20 -0800 Message-ID: <20231221005427.13932-2-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ZWbY3YT9FsOEEA238eJgcEEeEec4gsLq X-Proofpoint-GUID: ZWbY3YT9FsOEEA238eJgcEEeEec4gsLq Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: gjVcqhyz0BkTHEoHuJDx95lgx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120075742100002 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch creates ArmPlatformPkg for Odyssey SoC by overriding some of the files in original ArmPlatformPkg. Differences from standard ArmPlatformPkg are marked with "--- MRVL Override" comment. Signed-off-by: Narinder Dhillon --- .../PrePi/AArch64/ModuleEntryPoint.S | 136 ++++++++++ .../ArmPlatformPkg/PrePi/PeiMPCore.inf | 110 ++++++++ .../Override/ArmPlatformPkg/PrePi/PrePi.c | 238 ++++++++++++++++++ 3 files changed, 484 insertions(+) create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/M= oduleEntryPoint.S create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore= .inf create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEn= tryPoint.S b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEn= tryPoint.S new file mode 100644 index 0000000000..481d794154 --- /dev/null +++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoin= t.S @@ -0,0 +1,136 @@ +// +// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// + +#include +GCC_ASM_IMPORT(mDeviceTreeBaseAddress) // --- MRVL Override: defined in P= rePi.c +GCC_ASM_IMPORT(mSystemMemoryEnd) // --- MRVL Override +ASM_FUNC(_ModuleEntryPoint) + + // --- MRVL Override start + // Save the boot parameter to a global variable + adr x10, mDeviceTreeBaseAddress + str x1, [x10] + // --- MRVL Override end + + // Do early platform specific actions + bl ASM_PFX(ArmPlatformPeiBootAction) + + // Get ID of this CPU in multi-core system + bl ASM_PFX(ArmReadMpidr) + // Keep a copy of the MpId register value + mov x10, x0 + +_SetSVCMode: +// Check if we can install the stack at the top of the System Memory or if= we need +// to install the stacks at the bottom of the Firmware Device (case the FD= is located +// at the top of the DRAM) +_SystemMemoryEndInit: + ldr x1, mSystemMemoryEnd + + // --- MRVL Override start + // mSystemMemoryEnd shall be set by SMC call within ArmPlatformPeiBootAc= tion + cmp x1, #0xffffffffffffffff + bne _SetupStackPosition + // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs + MOV64 (x1, FixedPcdGet64(PcdSystemMemoryBase) + FixedPcdGet64(PcdSystemM= emorySize) - 1) + + // Update the global variable + adr x2, mSystemMemoryEnd + str x1, [x2] + // --- MRVL Override end + +_SetupStackPosition: + // x1 =3D SystemMemoryTop + + // Calculate Top of the Firmware Device + MOV64 (x2, FixedPcdGet64(PcdFdBaseAddress)) + MOV32 (x3, FixedPcdGet32(PcdFdSize) - 1) + sub x3, x3, #1 + add x3, x3, x2 // x3 =3D FdTop =3D PcdFdBaseAddress + PcdFdSize + + // UEFI Memory Size (stacks are allocated in this region) + MOV32 (x4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize)) + + // + // Reserve the memory for the UEFI region (contain stacks on its top) + // + + // Calculate how much space there is between the top of the Firmware and= the Top of the System Memory + subs x0, x1, x3 // x0 =3D SystemMemoryTop - FdTop + b.mi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case w= hen the PrePi is in XIP memory outside of the DRAM + cmp x0, x4 + b.ge _SetupStack + + // Case the top of stacks is the FdBaseAddress + mov x1, x2 + +_SetupStack: + // x1 contains the top of the stack (and the UEFI Memory) + + // Because the 'push' instruction is equivalent to 'stmdb' (decrement be= fore), we need to increment + // one to the top of the stack. We check if incrementing one does not ov= erflow (case of DRAM at the + // top of the memory space) + adds x11, x1, #1 + b.cs _SetupOverflowStack + +_SetupAlignedStack: + mov x1, x11 + b _GetBaseUefiMemory + +_SetupOverflowStack: + // Case memory at the top of the address space. Ensure the top of the st= ack is EFI_PAGE_SIZE + // aligned (4KB) + and x1, x1, ~EFI_PAGE_MASK + +_GetBaseUefiMemory: + // Calculate the Base of the UEFI Memory + sub x11, x1, x4 + +_GetStackBase: + // r1 =3D The top of the Mpcore Stacks + // Stack for the primary core =3D PrimaryCoreStack + MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)) + sub x12, x1, x2 + + // Stack for the secondary core =3D Number of Cores - 1 + MOV32 (x1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreS= econdaryStackSize)) + sub x12, x12, x1 + + // x12 =3D The base of the MpCore Stacks (primary stack & secondary stac= ks) + mov x0, x12 + mov x1, x10 + //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackS= ize) + MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)) + MOV32 (x3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)) + bl ASM_PFX(ArmPlatformStackSet) + + // Is it the Primary Core ? + mov x0, x10 + bl ASM_PFX(ArmPlatformIsPrimaryCore) + cmp x0, #1 + bne _PrepareArguments + +_PrepareArguments: + mov x0, x10 + mov x1, x11 + mov x2, x12 + + // Move sec startup address into a data register + // Ensure we're jumping to FV version of the code (not boot remapped ali= as) + ldr x4, =3DASM_PFX(CEntryPoint) + + // Set the frame pointer to NULL so any backtraces terminate here + mov x29, xzr + + // Jump to PrePiCore C code + // x0 =3D MpId + // x1 =3D UefiMemoryBase + // x2 =3D StacksBase + blr x4 + +_NeverReturn: + b _NeverReturn diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf b/= Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf new file mode 100644 index 0000000000..49d9e406d7 --- /dev/null +++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -0,0 +1,110 @@ +#/** @file +# +# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmPlatformPrePiMPCore + FILE_GUID =3D d959e387-7b91-452c-90e0-a1dbac90ddb8 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + DEFINE ORG_SOURCES_PATH =3D ArmPlatformPkg/PrePi # --- MRVL Overr= ide + +[Sources] + $(ORG_SOURCES_PATH)/PrePi.h # --- MRVL Override + PrePi.c + $(ORG_SOURCES_PATH)/MainMPCore.c # --- MRVL Override + +[Sources.ARM] + $(ORG_SOURCES_PATH)/Arm/ArchPrePi.c # --- MRVL Override + $(ORG_SOURCES_PATH)/Arm/ModuleEntryPoint.S | GCC # --- MRVL Override + $(ORG_SOURCES_PATH)/Arm/ModuleEntryPoint.asm | RVCT # --- MRVL Override + +[Sources.AArch64] + $(ORG_SOURCES_PATH)/AArch64/ArchPrePi.c # --- MRVL Override + AArch64/ModuleEntryPoint.S + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + BaseLib + CacheMaintenanceLib + DebugLib + DebugAgentLib + ArmLib + ArmGicLib + IoLib + TimerLib + SerialPortLib + ExtractGuidedSectionLib + LzmaDecompressLib + DebugAgentLib + PrePiLib + ArmPlatformLib + ArmPlatformStackLib + MemoryAllocationLib + HobLib + PrePiHobListPointerLib + PlatformPeiLib + MemoryInitPeiLib + FdtLib # --- MRVL Override + +[Ppis] + gArmMpCoreInfoPpiGuid + +[Guids] + gArmMpCoreInfoGuid + gEfiFirmwarePerformanceGuid + gFdtHobGuid # --- MRVL Override + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[FixedPcd] + gArmTokenSpaceGuid.PcdVFPEnabled + + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicSgiIntId + + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData + diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c b/Silico= n/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c new file mode 100644 index 0000000000..5168881b18 --- /dev/null +++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c @@ -0,0 +1,238 @@ +/** @file + + Copyright (c) 2011-2017, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "PrePi.h" +#include // fdt_totalsize // --- MRVL Override + +#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemo= ryEnd) ||\ + ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdF= dSize)) <=3D FixedPcdGet64 (PcdSystemMemoryBase))) + +UINT64 mSystemMemoryEnd =3D FixedPcdGet64 (PcdSystemMemoryBase) + + FixedPcdGet64 (PcdSystemMemorySize) - 1; + +UINT64 mDeviceTreeBaseAddress =3D 0; // --- MRVL Override +int fdt_check_header(const void *fdt); + +EFI_STATUS +GetPlatformPpi ( + IN EFI_GUID *PpiGuid, + OUT VOID **Ppi + ) +{ + UINTN PpiListSize; + UINTN PpiListCount; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + UINTN Index; + + PpiListSize =3D 0; + ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); + PpiListCount =3D PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR); + for (Index =3D 0; Index < PpiListCount; Index++, PpiList++) { + if (CompareGuid (PpiList->Guid, PpiGuid) =3D=3D TRUE) { + *Ppi =3D PpiList->Ppi; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +VOID +PrePiMain ( + IN UINTN UefiMemoryBase, + IN UINTN StacksBase, + IN UINT64 StartTimeStamp + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; + UINTN ArmCoreCount; + ARM_CORE_INFO *ArmCoreInfoTable; + EFI_STATUS Status; + CHAR8 Buffer[500]; // --- MRVL Override + UINTN CharCount; + UINTN StacksSize; + FIRMWARE_SEC_PERFORMANCE Performance; + + // If ensure the FD is either part of the System Memory or totally outsi= de of the System Memory (XIP) + ASSERT ( + IS_XIP () || + ((FixedPcdGet64 (PcdFdBaseAddress) >=3D FixedPcdGet64 (PcdSystemMemory= Base)) && + ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize= )) <=3D (UINT64)mSystemMemoryEnd)) + ); + + // Initialize the architecture specific bits + ArchInitialize (); + + // Initialize the Serial Port + SerialPortInitialize (); + CharCount =3D AsciiSPrint ( + Buffer, + sizeof (Buffer), + "UEFI firmware (version %s built at %a on %a)\n\r", + (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString), + __TIME__, + __DATE__ + ); + SerialPortWrite ((UINT8 *)Buffer, CharCount); + + // Initialize the Debug Agent for Source Level Debugging + InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + + // Declare the PI/UEFI memory region + HobList =3D HobConstructor ( + (VOID *)UefiMemoryBase, + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize), + (VOID *)UefiMemoryBase, + (VOID *)StacksBase // The top of the UEFI Memory is reserved= for the stacks + ); + PrePeiSetHobList (HobList); + + // --- MRVL Override start + // Build the FDT HOB + ASSERT(fdt_check_header ((VOID *)mDeviceTreeBaseAddress) =3D=3D 0); + DEBUG((DEBUG_INFO, "FDT address: %lx, size: %d\n", + mDeviceTreeBaseAddress, + fdt_totalsize((VOID *)mDeviceTreeBaseAddress))); + + BuildGuidDataHob (&gFdtHobGuid, &mDeviceTreeBaseAddress, sizeof(mDeviceT= reeBaseAddress)); + // --- MRVL Override end + + // Initialize MMU and Memory HOBs (Resource Descriptor HOBs) + Status =3D MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUef= iRegionSize)); + ASSERT_EFI_ERROR (Status); + + // Create the Stacks HOB (reserve the memory for all stacks) + if (ArmIsMpCore ()) { + StacksSize =3D PcdGet32 (PcdCPUCorePrimaryStackSize) + + ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdC= PUCoreSecondaryStackSize)); + } else { + StacksSize =3D PcdGet32 (PcdCPUCorePrimaryStackSize); + } + + BuildStackHob (StacksBase, StacksSize); + + // TODO: Call CpuPei as a library + BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize)); + + if (ArmIsMpCore ()) { + // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid + Status =3D GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCore= InfoPpi); + + // On MP Core Platform we must implement the ARM MP Core Info PPI (gAr= mMpCoreInfoPpiGuid) + ASSERT_EFI_ERROR (Status); + + // Build the MP Core Info Table + ArmCoreCount =3D 0; + Status =3D ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmC= oreInfoTable); + if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) { + // Build MPCore Info HOB + BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM= _CORE_INFO) * ArmCoreCount); + } + } + + // Store timer value logged at the beginning of firmware image execution + Performance.ResetEnd =3D GetTimeInNanoSecond (StartTimeStamp); + + // Build SEC Performance Data Hob + BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Pe= rformance)); + + // Set the Boot Mode + SetBootMode (ArmPlatformGetBootMode ()); + + // Initialize Platform HOBs (CpuHob and FvHob) + Status =3D PlatformPeim (); + ASSERT_EFI_ERROR (Status); + + // Now, the HOB List has been initialized, we can register performance i= nformation + PERF_START (NULL, "PEI", NULL, StartTimeStamp); + + // SEC phase needs to run library constructors by hand. + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compre= ssed FV. + Status =3D DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status =3D LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); +} + +VOID +CEntryPoint ( + IN UINTN MpId, + IN UINTN UefiMemoryBase, + IN UINTN StacksBase + ) +{ + UINT64 StartTimeStamp; + + // Initialize the platform specific controllers + ArmPlatformInitialize (MpId); + + if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ())= { + // Initialize the Timer Library to setup the Timer HW controller + TimerConstructor (); + // We cannot call yet the PerformanceLib because the HOB List has not = been initialized + StartTimeStamp =3D GetPerformanceCounter (); + } else { + StartTimeStamp =3D 0; + } + + // Data Cache enabled on Primary core when MMU is enabled. + ArmDisableDataCache (); + // Invalidate instruction cache + ArmInvalidateInstructionCache (); + // Enable Instruction Caches on all cores. + ArmEnableInstructionCache (); + + // Define the Global Variable region when we are not running in XIP + if (!IS_XIP ()) { + if (ArmPlatformIsPrimaryCore (MpId)) { + if (ArmIsMpCore ()) { + // Signal the Global Variable Region is defined (event: ARM_CPU_EV= ENT_DEFAULT) + ArmCallSEV (); + } + } else { + // Wait the Primary core has defined the address of the Global Varia= ble region (event: ARM_CPU_EVENT_DEFAULT) + ArmCallWFE (); + } + } + + // If not primary Jump to Secondary Main + if (ArmPlatformIsPrimaryCore (MpId)) { + InvalidateDataCacheRange ( + (VOID *)UefiMemoryBase, + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) + ); + + // Goto primary Main. + PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp); + } else { + SecondaryMain (MpId); + } + + // DXE Core should always load and never return + ASSERT (FALSE); +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112779): https://edk2.groups.io/g/devel/message/112779 Mute This Topic: https://groups.io/mt/103292509/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112780+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112780+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120075; cv=none; d=zohomail.com; s=zohoarc; b=X8IwZ8b4OgLfDy+61FLQcuoDWkRp0rl87uC/BghzfAUy/80zv09uNCTLpOqgH3c5lZgp6bG2UxeXEApQSVjfxakIXgTMogEXHJtmELgfUhdt12MPQJ5z0ucdhhDD3jVVcVlnxw8swyDjp70P2s7kDz1N3SlGi/xJF4RkdylIxnQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120075; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=RMmdM6qJjKsEn2oi20REc0zCAGkVhjUn5hfS/e7cgBQ=; b=TVbIzSf5FdwXsnNXN/0SrgEoLMmfD0StS6sYivwkDeZdgVXVe/HMDvRagXOKxPy8I/qd0oiYzXxS+79ZORAooJGeZpE+I8Y4O6iAKB5m7Rm/9Uvl9d0DEtETFLCVbhJ4mIvhwASHbBv5qaZceFXt4xPT/mmNOy20UP1cKxVkiRM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112780+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703120075297264.55105377117775; Wed, 20 Dec 2023 16:54:35 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=LWR1mogdFsde2LTMZKRDbimWF/cEqt5EWRynJvJqCJM=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120075; v=1; b=aWFQklDNaNzVfJFG/zMQeC22cX/uAty6RpaoyLAZMl3BH4rXZIs+AKMPZPHcVxgCZH85yJRG PBYpH1/JPzDB8sKijPmOHJ7Mb3J0j0VCWRldO50Nw6vropSwHvPoWnXMRfv7iZGnQWLh9/L1oSj 58m2pUnl3gx2JNDdCW0/yJho= X-Received: by 127.0.0.2 with SMTP id lvcWYY1788612xzkDUChitTG; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.41317.1703120073966219389 for ; Wed, 20 Dec 2023 16:54:33 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKHJu0E004353; Wed, 20 Dec 2023 16:54:33 -0800 X-Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v3tbcvg83-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:33 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:32 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:32 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id 834F33F705B; Wed, 20 Dec 2023 16:54:31 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 2/8] Silicon/Marvell: Odyssey ArmPlatformLib Date: Wed, 20 Dec 2023 16:54:21 -0800 Message-ID: <20231221005427.13932-3-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: QfPJ-Iy8fSlvrGoss_rnJzyBcGLhI0B3 X-Proofpoint-GUID: QfPJ-Iy8fSlvrGoss_rnJzyBcGLhI0B3 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Zfdx1oglgJAIJ1z3JS0MKIncx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120075793100003 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds ArmPlatformLib for Marvell Odyssey SoC. Signed-off-by: Narinder Dhillon --- .../AArch64/ArmPlatformHelper.S | 86 ++++++++++++ .../Library/ArmPlatformLib/ArmPlatformLib.c | 79 +++++++++++ .../Library/ArmPlatformLib/ArmPlatformLib.inf | 55 ++++++++ .../ArmPlatformLib/ArmPlatformLibMem.c | 131 ++++++++++++++++++ 4 files changed, 351 insertions(+) create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatf= ormHelper.S create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.i= nf create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMe= m.c diff --git a/Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatformHelp= er.S b/Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S new file mode 100644 index 0000000000..757c032f84 --- /dev/null +++ b/Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S @@ -0,0 +1,86 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include +#include +#include +#include +#include +#include + +/* x1 - node number + */ + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmGetCpuCountPerCluster) + +GCC_ASM_IMPORT(mSystemMemoryEnd) + +ASM_FUNC(ArmPlatformPeiBootAction) + adr x1, PrimaryCoreMpid + str w0, [x1] + ldr x0, =3DMV_SMC_ID_DRAM_SIZE + mov x1, xzr + smc #0 + sub x0, x0, #1 // Last valid address + adr x1, mSystemMemoryEnd + str x0, [x1] // Set mSystemMemoryEnd + + ret + + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32(w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + mov x0, #1 + mov x1, #0 + csel x0, x0, x1, eq + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) +/* + Affinity Level 0: single thread 0 + Affinity Level 1: clustering 0( + Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 16 = (Iliad) + Affinity Level 3: number of chip 0 + LinearId =3D Aff2 +*/ + and x0, x0, #ARM_CORE_AFF2 + lsr x0, x0, #16 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED + +PrimaryCoreMpid: .word 0x0 diff --git a/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c b/Sili= con/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000000..ed48a00950 --- /dev/null +++ b/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c @@ -0,0 +1,79 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include +#include // EFI_BOOT_MODE +#include // EFI_PEI_PPI_DESCRIPTOR +#include // ASSERT +#include // ArmPlatformIsPrimaryCore +#include // ARM_MP_CORE_INFO_PPI + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePei or ArmPlatformPkg/P= ei/PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + ASSERT(ArmPlatformIsPrimaryCore (MpId)); + + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + return EFI_UNSUPPORTED; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.inf b/Si= licon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000000..1a4b81adb4 --- /dev/null +++ b/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -0,0 +1,55 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2022 Marvell +# +# Marvell ARM Platform library +# Based on ArmPlatformPkg/Library/ArmPlatformLibNull +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmPlatformLib + FILE_GUID =3D 7ea0f45b-0e06-4e45-8353-9c28b091a11c + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec # Include ArmPlatformLib.h + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + +[LibraryClasses] + ArmLib + HobLib + DebugLib + MemoryAllocationLib + SmcLib + +[Sources] + ArmPlatformLib.c + ArmPlatformLibMem.c + +[Sources.AARCH64] + AArch64/ArmPlatformHelper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase + gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress + gMarvellSiliconTokenSpaceGuid.PcdIoSize + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMem.c b/S= ilicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMem.c new file mode 100644 index 0000000000..1626dea6c5 --- /dev/null +++ b/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMem.c @@ -0,0 +1,131 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell ARM Platform library +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull +**/ + +#include // Basic UEFI types +#include // DEBUG +#include // EFI_BOOT_MODE required by PiH= ob.h +#include // EFI_RESOURCE_ATTRIBUTE_TYPE +#include // BuildResourceDescriptorHob +#include // PcdGet64 +#include // ARM_MEMORY_REGION_ATTRIBUTE_W= RITE_BACK +#include // SmcGetRamSize +#include // AllocatePages + +// Number of Virtual Memory Map Descriptors +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 129 +#define MAX_NODES 1 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINT64 VirtualMemoryTableSize; + UINT64 MemoryBase; + UINT64 MemorySize; + UINTN Index =3D 0; + UINTN Node; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTableSize =3D sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VI= RTUAL_MEMORY_MAP_DESCRIPTORS; + VirtualMemoryTable =3D AllocatePages (EFI_SIZE_TO_PAGES (VirtualMemoryTa= bleSize)); + + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + CacheAttributes =3D DDR_ATTRIBUTES_CACHED; + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdFdBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdFdSize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + Index++; + + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + PcdGet64 (PcdFdBaseAddress), + PcdGet32 (PcdFdSize)); + + for (Node =3D 0; Node < MAX_NODES; Node++) { + MemoryBase =3D Node * FixedPcdGet64(PcdNodeDramBase); + MemorySize =3D SmcGetRamSize(Node); + + MemoryBase +=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : 0; + MemorySize -=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : 0; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemoryBase, + MemorySize); + + DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory %lx @ %lx\n", MemorySize, = MemoryBase)); + VirtualMemoryTable[Index].PhysicalBase =3D MemoryBase; + VirtualMemoryTable[Index].VirtualBase =3D MemoryBase; + VirtualMemoryTable[Index].Length =3D MemorySize; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + Index++; + } + + for (Node =3D 0; Node < MAX_NODES; Node++) { + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64(PcdIoBaseAdd= ress) + + Node * FixedPcdGet64(PcdNo= deIoBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64(PcdIoBaseAdd= ress) + + Node * FixedPcdGet64(PcdNo= deIoBaseAddress); + VirtualMemoryTable[Index].Length =3D FixedPcdGet64(PcdIoSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + DEBUG ((DEBUG_LOAD | DEBUG_INFO, + "IO %lx @ %lx\n", + VirtualMemoryTable[Index].Length, + VirtualMemoryTable[Index].PhysicalBase)); + + Index++; + } + + // End of Table + VirtualMemoryTable[Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + *VirtualMemoryMap =3D VirtualMemoryTable; +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112780): https://edk2.groups.io/g/devel/message/112780 Mute This Topic: https://groups.io/mt/103292510/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112781+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112781+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120076; cv=none; d=zohomail.com; s=zohoarc; b=G6v/RwEOI4ED7HxpLds9f97QZzECv3EKnj7ZeVZ396fRrZKheGJKkBdBuU5aGZMmeSPWVAz0zVvmWaIP0LTr8qxqP/HpGBELTyiFW7+Ycm0SlvHr5Ki8DzMkkThK/LKET9duy47Yix0dtgk71zyiueUxPCQei1bOtd7BxcFx1Aw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120076; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=PQqRsH0JDzPTBUxKGRQkPatLDAHTLSruJkqwab8g9zQ=; b=ZcsVoiLPaoZKFjCtwtW+OBlHAclZ0e5ElCKkRL8IzSFofPFn6l73hgw1DuZvOeah0LzSfVhGATIiPUUNQPLhaZGZhgWKliR7/EyCFVbRLRrXYitxscnH6Fp7K6pRT1INK91rggp2XZ74ZgAtn2F8K/kVibsTYWivKpSUyCqRr6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112781+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703120076314523.301765322534; Wed, 20 Dec 2023 16:54:36 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=06qACvXLgIV5wsMMJItaoPRKVDb0khqHbHWQNfCV+AM=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120076; v=1; b=C96wAZWA9Zjbv6IUqsrVmpket6MVpOXcdaU3xaqWU/iZv/MZbdbC8wNdI2dOewvNuKbdErWr 20pV/z0HS1OGXhCURqXyWbc5rm+2Y5bJnaQva+GwySctFjLXZO4FxuZoej8hn9nct7tzhIkwrco Cykqc3xBvG1nEEqcjikP3+mM= X-Received: by 127.0.0.2 with SMTP id cYpqYY1788612xFeZ9FeNJLm; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web10.41713.1703120075502527572 for ; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKH2Ed6004000; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v3tbcvg8e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:34 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:32 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:32 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id 473975C68E1; Wed, 20 Dec 2023 16:54:32 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 3/8] Silicon/Marvell: Odyssey SmcLib Date: Wed, 20 Dec 2023 16:54:22 -0800 Message-ID: <20231221005427.13932-4-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RNMiVDpd0Vd_Nny0h_8g_Ai4hTyM32qt X-Proofpoint-GUID: RNMiVDpd0Vd_Nny0h_8g_Ai4hTyM32qt Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: I9WvWnMgVCQEPqB0st3v8T7Wx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120077757100010 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch provides SMC call needed by Odyssey to determine available memory size. Signed-off-by: Narinder Dhillon --- Silicon/Marvell/Library/SmcLib/SmcLib.c | 24 +++++++++++++++ Silicon/Marvell/Library/SmcLib/SmcLib.inf | 29 +++++++++++++++++++ .../Include/Library/SmcLib.h | 28 ++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 Silicon/Marvell/Library/SmcLib/SmcLib.c create mode 100644 Silicon/Marvell/Library/SmcLib/SmcLib.inf create mode 100644 Silicon/Marvell/MarvellSiliconPkg/Include/Library/SmcLi= b.h diff --git a/Silicon/Marvell/Library/SmcLib/SmcLib.c b/Silicon/Marvell/Libr= ary/SmcLib/SmcLib.c new file mode 100644 index 0000000000..20a2fb2017 --- /dev/null +++ b/Silicon/Marvell/Library/SmcLib/SmcLib.c @@ -0,0 +1,24 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Source file for Marvell SMC Interface +* +**/ + +#include +#include // ArmCallSmc + +UINTN SmcGetRamSize ( IN UINTN Node ) +{ + ARM_SMC_ARGS ArmSmcArgs; + + ArmSmcArgs.Arg0 =3D MV_SMC_ID_DRAM_SIZE; + ArmSmcArgs.Arg1 =3D Node; + ArmCallSmc (&ArmSmcArgs); + + return ArmSmcArgs.Arg0; +} diff --git a/Silicon/Marvell/Library/SmcLib/SmcLib.inf b/Silicon/Marvell/Li= brary/SmcLib/SmcLib.inf new file mode 100644 index 0000000000..7fc1085b85 --- /dev/null +++ b/Silicon/Marvell/Library/SmcLib/SmcLib.inf @@ -0,0 +1,29 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# Marvell SMC Interface library +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmcLib + FILE_GUID =3D fee427a7-816a-4636-bb81-a640c8288f28 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SmcLib + +[Sources] + SmcLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + +[LibraryClasses] + ArmSmcLib diff --git a/Silicon/Marvell/MarvellSiliconPkg/Include/Library/SmcLib.h b/S= ilicon/Marvell/MarvellSiliconPkg/Include/Library/SmcLib.h new file mode 100644 index 0000000000..f2d0bed356 --- /dev/null +++ b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/SmcLib.h @@ -0,0 +1,28 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2023 Marvell +* +* Header file for for Marvell SMC Interface +* +**/ + +#ifndef __SMCLIB_H__ +#define __SMCLIB_H__ + +/* SMC function IDs for Marvell Service queries */ + +#define MV_SMC_ID_CALL_COUNT 0xc200ff00 +#define MV_SMC_ID_UID 0xc200ff01 + +#define MV_SMC_ID_VERSION 0xc200ff03 + +/* x1 - node number */ +#define MV_SMC_ID_DRAM_SIZE 0xc2000301 + + +UINTN SmcGetRamSize (IN UINTN Node); + +#endif --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112781): https://edk2.groups.io/g/devel/message/112781 Mute This Topic: https://groups.io/mt/103292511/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112782+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112782+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120076; cv=none; d=zohomail.com; s=zohoarc; b=ENZMcdeT4GKgr0SJw7dsW7SZdWzLUNQNrhQ4YbG08EyklP8RpE2bEwHKWRi1XtdF/5wjZdCQVW6zg6LYXX+xeW8dALHFc0GuLDeI/a6607mWM2y7GwAqSEdV8bJ54ZtgUTDF3uQuxWnYkrYDlqgZP7gNb+F04Th62jBfFKQXDUM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120076; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=bPHqkEfCCzNldRz/NxWf4OSGwWX1cRKOFgqDXMV4ER8=; b=KWJWx0fcB0l/YoKw4P9gmC43l3o9pXdeRTuy5syGlo5rck8NI6A2mopSnA4j4GMPvt+hpvk1IBzTQLfsUmlKAdZNrOi1K0+WeW8g86jgEu+7OAXJpV7oCREAFe1WB9lUwRV4O/TAIldIvp+KuP0akVzgBY6n9a3bwy6qXsrJVI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112782+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703120076746146.92517812933215; Wed, 20 Dec 2023 16:54:36 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=ynDvbKS7OWrVWSU1Cz3Q4uOBoF57A7KDC9on14jnkbY=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120076; v=1; b=kdK58xpdHbY07vR0wAI1lJY/f4Mo4vz7tlroiDlAZyJhT98JPrGtvcWDeidKX5MIeSqhcqxF hqPOohUil396Hwgi70RnqHmQXICSFTYBW4tEB3GNySYrBPjOVtV+Hbb5yRO1ide1ATQpW5Sos0X BE4E09gJnZrxqse++V13q2YQ= X-Received: by 127.0.0.2 with SMTP id 93yUYY1788612xCvGVf38EOO; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.41319.1703120075849678017 for ; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKH2Ed7004000; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v3tbcvg8e-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:35 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:33 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:33 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id 0D3B05C68E5; Wed, 20 Dec 2023 16:54:32 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 4/8] Silicon/Marvell: Odyssey watchdog driver Date: Wed, 20 Dec 2023 16:54:23 -0800 Message-ID: <20231221005427.13932-5-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: u0WzXOZSknfiTs7PZnA0JryWbN8KasSB X-Proofpoint-GUID: u0WzXOZSknfiTs7PZnA0JryWbN8KasSB Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: qeydIeChnGYIUwHtvq1tcfRpx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120077779100011 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds watchdog driver for Odyssey SoC. Signed-off-by: Narinder Dhillon --- .../Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c | 408 ++++++++++++++++++ .../Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf | 45 ++ 2 files changed, 453 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c create mode 100644 Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogD= xe.inf diff --git a/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c b/Sil= icon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c new file mode 100644 index 0000000000..12be08ff24 --- /dev/null +++ b/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdog.c @@ -0,0 +1,408 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for Marvell Watchdog driver +* +**/ + + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define GTI_CWD_WDOG(Core) (FixedPcdGet64(PcdGtiWatchdogBase64) + 0x400= 00 + Core * 0x8) +#define GTI_CWD_POKE(Core) (FixedPcdGet64(PcdGtiWatchdogBase64) + 0x500= 00 + Core * 0x8) + +typedef union _GTI_CWD_WDOG_UNION { + UINT64 U64; + struct { + UINTN Mode : 2; + UINTN State : 2; + UINTN Len : 16; + UINTN Cnt : 24; + UINTN DStop : 1; + UINTN GStop : 1; + UINTN Rsvd : 18; + } PACKED S; +} GTI_CWD_WDOG_UNION; + +#define CWD_WDOG_MODE_RST (BIT1 | BIT0) + +#define RST_BOOT_PNR_MUL(Val) ((Val >> 33) & 0x1F) + +EFI_EVENT mGtiExitBootServicesEvent =3D (EFI_EVENT)NULL; +UINT32 mSclk =3D 0; +BOOLEAN mHardwarePlatform =3D TRUE; + +/** + Stop the GTI watchdog timer from counting down by disabling interrupts. +**/ +STATIC +VOID +GtiWdtStop ( + VOID + ) +{ + GTI_CWD_WDOG_UNION Wdog; + + MmioWrite64(GTI_CWD_POKE(0), 0); + + Wdog.U64 =3D MmioRead64(GTI_CWD_WDOG(0)); + + // Disable WDT + if (Wdog.S.Mode !=3D 0) { + Wdog.S.Len =3D 1; + Wdog.S.Mode =3D 0; + MmioWrite64 (GTI_CWD_WDOG(0), Wdog.U64); + } +} + +/** + Starts the GTI WDT countdown by enabling interrupts. + The count down will start from the value stored in the Load register, + not from the value where it was previously stopped. +**/ +STATIC +VOID +GtiWdtStart ( + VOID + ) +{ + GTI_CWD_WDOG_UNION Wdog; + + // Reset the WDT + MmioWrite64 (GTI_CWD_POKE(0), 0); + + Wdog.U64 =3D MmioRead64 (GTI_CWD_WDOG(0)); + + // Enable countdown + if (Wdog.S.Mode =3D=3D 0) { + Wdog.S.Mode =3D CWD_WDOG_MODE_RST; + MmioWrite64 (GTI_CWD_WDOG(0), Wdog.U64); + } +} + +/** + On exiting boot services we must make sure the SP805 Watchdog Timer + is stopped. +**/ +VOID +EFIAPI +GtiExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + MmioWrite64 (GTI_CWD_POKE(0), 0); + GtiWdtStop (); +} + +/** + This function registers the handler NotifyFunction so it is called every= time + the watchdog timer expires. It also passes the amount of time since the= last + handler call to the NotifyFunction. + If NotifyFunction is not NULL and a handler is not already registered, + then the new handler is registered and EFI_SUCCESS is returned. + If NotifyFunction is NULL, and a handler is already registered, + then that handler is unregistered. + If an attempt is made to register a handler when a handler is already re= gistered, + then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fir= es. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so = it can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The watchdog timer handler was registered. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler = is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was = not + previously registered. + @retval EFI_UNSUPPORTED HW does not support this functionality. + +**/ +EFI_STATUS +EFIAPI +GtiWdtRegisterHandler ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction + ) +{ + // UNSUPPORTED - The hardware watchdog will reset the board + return EFI_UNSUPPORTED; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 = nS units. If + the timer hardware is not programmable, then EF= I_UNSUPPORTED is + returned. If the timer is programmable, then th= e timer period + will be rounded up to the nearest timer period = that is supported + by the timer hardware. If TimerPeriod is set to= 0, then the + timer interrupts will be disabled. + + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of t= he timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due = to a device error. + +**/ +EFI_STATUS +EFIAPI +GtiWdtSetTimerPeriod ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod // In 100ns un= its + ) +{ + UINT32 Clock; + UINT64 CountDown; + GTI_CWD_WDOG_UNION Wdog; + + if (TimerPeriod =3D=3D 0) { + + // This is a watchdog stop request + GtiWdtStop(); + + return EFI_SUCCESS; + } else { + // + // The system is reset only after the WDT expires for the 3rd time + // + + Clock =3D mSclk / 1000000; //MHz + CountDown =3D DivU64x32 (MultU64x32 (TimerPeriod, Clock), 30); + + // WDT counts in 1024 cycle steps + // Only upper 16 bits can be used + + Wdog.U64 =3D 0; + Wdog.S.Len =3D (CountDown + (0xFF << 10)) >> 18; + MmioWrite64 (GTI_CWD_WDOG(0), Wdog.U64); + + // Start the watchdog + if (mHardwarePlatform =3D=3D TRUE) { + GtiWdtStart(); + } + } + + return EFI_SUCCESS; +} + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 10= 0 ns units. If + 0 is returned, then the timer is currently disa= bled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeri= od. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +GtiWdtGetTimerPeriod ( + IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + UINT32 Clock; + UINT64 CountDown; + UINT64 ReturnValue; + GTI_CWD_WDOG_UNION Wdog; + + if (TimerPeriod =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Wdog.U64 =3D MmioRead64 (GTI_CWD_WDOG(0)); + + // Check if the watchdog is stopped + if (Wdog.S.Mode =3D=3D 0) { + // It is stopped, so return zero. + ReturnValue =3D 0; + } else { + // Convert the Watchdog ticks into TimerPeriod + Clock =3D mSclk / 1000000; //MHz + CountDown =3D Wdog.S.Len << 18; + + ReturnValue =3D MultU64x32(DivU64x32(3 * CountDown, Clock), 10); // us= ecs * 10 + } + + *TimerPeriod =3D ReturnValue; + + return EFI_SUCCESS; +} + +/** + Interface structure for the Watchdog Architectural Protocol. + + @par Protocol Description: + This protocol provides a service to set the amount of time to wait + before firing the watchdog timer, and it also provides a service to + register a handler that is invoked when the watchdog timer fires. + + @par When the watchdog timer fires, control will be passed to a handler + if one has been registered. If no handler has been registered, + or the registered handler returns, then the system will be + reset by calling the Runtime Service ResetSystem(). + + @param RegisterHandler + Registers a handler that will be called each time the + watchdogtimer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + NOTE: If the watchdog resets the system in hardware, then + this function will not have any chance of executing. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + +**/ +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer =3D { + (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) GtiWdtRegisterHandler, + (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) GtiWdtSetTimerPeriod, + (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) GtiWdtGetTimerPeriod +}; + +/** + Initialize the state information for the Watchdog Timer Architectural Pr= otocol. + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +GtiWdtInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle =3D NULL; + FDT_HANDLE SclkHandle =3D 0; + FDT_HANDLE RootHandle =3D 0; + CONST UINT32 *SclkFreq =3D NULL; + FDT_CLIENT_PROTOCOL *FdtClient =3D NULL; + CONST CHAR8 *Platform; + + DEBUG ((DEBUG_INFO, "GtiWdtInitialize: Start\n")); + // Stop the watchdog from triggering unexpectedly + GtiWdtStop (); + + // + // Make sure the Watchdog Timer Architectural Protocol has not been inst= alled in the system yet. + // This will avoid conflicts with the universal watchdog + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolG= uid); + + Status =3D gBS->LocateProtocol (&gFdtClientProtocolGuid, + NULL, + (VOID **)&FdtClient); + + if (EFI_ERROR (Status) || (FdtClient =3D=3D NULL)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR: cannot locate: gFdtClientProtocolGuid= \n", __func__)); + return EFI_ABORTED; + } + + Status =3D FdtClient->GetNode (FdtClient, "/soc@0/sclk", &SclkHandle); + if (EFI_ERROR (Status) || !SclkHandle) { + DEBUG ((DEBUG_ERROR, "%a: %s node not found!\n", __func__, L"/soc@0/sc= lk")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, "%a: Found: %s\n", __func__, L"/soc@0/sclk")); + Status =3D FdtClient->GetNodeProperty (FdtClient, + SclkHandle, + "clock-frequency", + (CONST VOID **)&SclkFreq, + NULL); + if (EFI_ERROR (Status) || NULL =3D=3D SclkFreq) { + DEBUG ((DEBUG_ERROR, "%a: %s property not found!\n", __func__, L"\"clo= ck-frequency\"")); + return EFI_NO_MAPPING; + } + + mSclk =3D FdtToCpu32(*SclkFreq); + DEBUG ((DEBUG_INFO, "%a: DT sclk =3D %d Mhz (0x%x)\n", __func__, mSclk/1= 000000, mSclk)); + + Status =3D FdtClient->GetNode (FdtClient, "/soc@0", &RootHandle); + if (!EFI_ERROR (Status) && RootHandle) { + Status =3D FdtClient->GetNodeProperty (FdtClient, + RootHandle, + "runplatform", + (CONST VOID **)&Platform, + NULL); + if (!EFI_ERROR (Status)) { + if (AsciiStrCmp (Platform, "HW_PLATFORM")) { + mHardwarePlatform =3D FALSE; + DEBUG ((DEBUG_INFO, "%a: Not a hardware platform\n", __func__)); + } + } + } + + // Register for an ExitBootServicesEvent + Status =3D gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + GtiExitBootServices, + NULL, + &mGtiExitBootServicesEvent); + ASSERT_EFI_ERROR(Status); + + // Install the Timer Architectural Protocol onto a new handle + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "GtiWdtInitialize: Exit\n")); + + return EFI_SUCCESS; +} diff --git a/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf = b/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf new file mode 100644 index 0000000000..f9aa4da246 --- /dev/null +++ b/Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf @@ -0,0 +1,45 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2022 Marvell +# +# Module definition file for Marvell Watchdog driver. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D GtiWatchdogDxe + FILE_GUID =3D 789F5711-6FD3-4170-BE11-EE4000037EA8 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D GtiWdtInitialize + +[Sources.common] + GtiWatchdog.c + +[Packages] + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gMarvellSiliconTokenSpaceGuid.PcdGtiWatchdogBase64 + +[Protocols] + gEfiWatchdogTimerArchProtocolGuid #PRODUCES + gFdtClientProtocolGuid #CONSUMED + +[Depex] + gFdtClientProtocolGuid --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112782): https://edk2.groups.io/g/devel/message/112782 Mute This Topic: https://groups.io/mt/103292512/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112783+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112783+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120077; cv=none; d=zohomail.com; s=zohoarc; b=IVxXahSHYWhqqcOHvwM8JPuucKkCHNXp1E+pJ+sbwKCuCt049DfXHmeM+jYC5ZhuvmlkcyaHhfBDOktia8FieqT2QAHbQhO0t1k6PXPxK5y+OE/nno/xDOLFrRBymZCGFmnXP1AccESfPlVy0ICqamoC97eM5a+BwIjPFAZLSzY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120077; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=YneV/WszFz0sSIRdzPnEpwv+Na8xAbIquUS6YD8PrYc=; b=huUwB+oEh6OTuB7UFvdOVhQM4Ia5I1mnrpfHWwd/Svct7IwxOMV4Ps5iGBQD3moqNDkfslLBKfFgj2SEKF+uQxSjrcnGDswTrnwik1Y9Vmxj+PoKr0C3/8Zl4RfljmqZog+KFrzddUsYV27LVhWOYirAgZVXR8GcdCSwIky94Fw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112783+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 170312007714512.335224538692955; Wed, 20 Dec 2023 16:54:37 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=quKomW33SM0XN/hR3+x5mJJiLQHV9h663zBoGAmqO6s=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120076; v=1; b=Oj8CvSh/jx34HQclI9xDTCWQZ34e82HlRTJtmVNxLpbe6fZ0N/K5tIQKhh5ppVNAgvprbdlw H7hr78h68HY67zBz7C8FdIqksbedw9lacYGSgNZUY6aLEN0OMCjv8hPIkHmHqHOWZZST6HaBfft sJnavsUzQxh+vz8zBN3PvlVU= X-Received: by 127.0.0.2 with SMTP id usDmYY1788612x6KUNn2WYQ2; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.41320.1703120076402504397 for ; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKH2Ed8004000; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v3tbcvg8e-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:35 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:34 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:34 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id C60BE3F706F; Wed, 20 Dec 2023 16:54:33 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 5/8] Silicon/Marvell: RTC driver Date: Wed, 20 Dec 2023 16:54:24 -0800 Message-ID: <20231221005427.13932-6-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dT57FHKy7WFpv-KTY2nFL0ZidmHmjDrt X-Proofpoint-GUID: dT57FHKy7WFpv-KTY2nFL0ZidmHmjDrt Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: mPeaj1V0ZkdXUo9yzBijD5JRx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120077755100009 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon Marvell Odyssey SoC does not have RTC on chip. This patch provides a dummy RTC driver to generate architectural protocol and help boot Odyssey SoC. Signed-off-by: Narinder Dhillon --- .../Marvell/Drivers/Null/RtcNull/RtcNullDxe.c | 280 ++++++++++++++++++ .../Marvell/Drivers/Null/RtcNull/RtcNullDxe.h | 37 +++ .../Drivers/Null/RtcNull/RtcNullDxe.inf | 46 +++ 3 files changed, 363 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.c create mode 100644 Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.h create mode 100644 Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.inf diff --git a/Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.c b/Silicon/Ma= rvell/Drivers/Null/RtcNull/RtcNullDxe.c new file mode 100644 index 0000000000..8a7956f35d --- /dev/null +++ b/Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.c @@ -0,0 +1,280 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Source file for NULL RTC Driver +* +**/ + +#include // Base defines +#include // DEBUG +#include // AllocateRuntimeZeroPo= ol +#include // ZeroMem +#include // gBS +#include // EfiConvertPointer +#include // gRT + +#include "RtcNullDxe.h" + +// all variables used across the driver +RTC_NULL_PRIVATE_DATA *mRtcPrivateData; +STATIC EFI_EVENT mRtcVirtualAddressChangeEvent; + +STATIC CONST INTN DayOfMonth[12] =3D + { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, = 30, 31 }; + +STATIC +BOOLEAN +IsLeapYear(IN EFI_TIME *Time) +{ + if (Time->Year % 4 =3D=3D 0) { + if (Time->Year % 100 =3D=3D 0) { + if (Time->Year % 400 =3D=3D 0) { + return TRUE; + } else { + return FALSE; + } + } else { + return TRUE; + } + } else { + return FALSE; + } +} + +BOOLEAN DayValid(IN EFI_TIME *Time) +{ + if (Time->Day < 1 || + Time->Day > DayOfMonth[Time->Month - 1] || + (Time->Month =3D=3D 2 && (!IsLeapYear (Time) && Time->Day > 28))) { + return FALSE; + } + + return TRUE; +} + +EFI_STATUS +GetDateTime( + IN RTC_NULL_PRIVATE_DATA *PrivateData, + OUT EFI_TIME *Time) +{ + + if (PrivateData =3D=3D NULL || Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ZeroMem(Time, sizeof(EFI_TIME)); + + return EFI_SUCCESS; +} + +EFI_STATUS +SetDateTime(IN RTC_NULL_PRIVATE_DATA *PrivateData, + IN EFI_TIME *Time) +{ + if (PrivateData =3D=3D NULL || Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ( (Time->Month < 1) || (Time->Month > 12) || + (Time->Second > 59) || (Time->Minute > 59) || + (Time->Hour > 23) || (!DayValid(Time)) || + (Time->Year < 1998) || (Time->Year > 2099) || + (Time->Nanosecond > 999999999) || + (Time->TimeZone < -1440) || ((Time->TimeZone > 1440) && + (Time->TimeZone !=3D 2047))) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ +EFI_STATUS + EFIAPI +GetTime(OUT EFI_TIME * Time, OUT EFI_TIME_CAPABILITIES * Capabilities) +{ + if (Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (mRtcPrivateData->Initialized =3D=3D FALSE) { + return EFI_UNSUPPORTED; + } + + return GetDateTime (mRtcPrivateData, Time); +} + + + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ +EFI_STATUS EFIAPI SetTime(IN EFI_TIME * Time) +{ + if (Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (mRtcPrivateData->Initialized =3D=3D FALSE) { + return EFI_UNSUPPORTED; + } + + return SetDateTime (mRtcPrivateData, Time); +} + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + +**/ +EFI_STATUS + EFIAPI +GetWakeupTime(OUT BOOLEAN * Enabled, + OUT BOOLEAN * Pending, OUT EFI_TIME * Time) +{ + return EFI_UNSUPPORTED; +} + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS EFIAPI SetWakeupTime(IN BOOLEAN Enabled, OUT EFI_TIME * Time) +{ + return EFI_UNSUPPORTED; +} + + +// Convert the mSmbus as well since the SmbusLib leaves this to the runtin= e DXEs + +EFIAPI VOID +RtcVirtualNotifyEvent(IN EFI_EVENT Event, IN VOID * Context) +{ + EfiConvertPointer (0x0, (VOID **) &mRtcPrivateData); +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS + EFIAPI +RtcNullDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE * SystemTable) +{ + EFI_TIME Time; + RTC_NULL_PRIVATE_DATA *Private =3D NULL; + EFI_STATUS Status =3D EFI_SUCCESS; + + DEBUG ((DEBUG_INFO, "RtcNullDxeInitialize\n")); + + /* Allocate the private data */ + Private =3D AllocateRuntimeZeroPool (sizeof (RTC_NULL_PRIVATE_DATA)); + + if (Private =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "RtcDxeInitialize: %r\n", Status)); + goto Exit; + } + + mRtcPrivateData =3D Private; + + Private->Initialized =3D FALSE; + Private->Bus =3D 0xFF; + Private->SlaveAddr =3D 0xFF; + + /* Check clock and init it to UNIX start time */ + Status =3D GetDateTime (mRtcPrivateData, &Time); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RtcNullDxeInitialize: %r\n", Status)); + goto Exit; + } + + if (Time.Year =3D=3D 1900) { + Time.Day =3D 1; + Time.Month =3D 1; + Time.Year =3D 1998; + Time.Second =3D 0; + Time.Minute =3D 0; + Time.Hour =3D 0; + Time.Daylight =3D 0; + Time.TimeZone =3D 0; + + Status =3D SetDateTime (mRtcPrivateData, &Time); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RtcDxeInitialize: %r\n", Status)); + goto Exit; + } + } + +Exit: + gRT->GetTime =3D GetTime; + gRT->SetTime =3D SetTime; + gRT->GetWakeupTime =3D GetWakeupTime; + gRT->SetWakeupTime =3D SetWakeupTime; + + Status =3D gBS->InstallMultipleProtocolInterfaces (&Private->RtcHandle, + &gEfiRealTimeClockArchP= rotocolGuid, + NULL, + NULL); + + Status =3D gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + RtcVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mRtcVirtualAddressChangeEvent); + ASSERT_EFI_ERROR(Status); + + return Status; +} diff --git a/Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.h b/Silicon/Ma= rvell/Drivers/Null/RtcNull/RtcNullDxe.h new file mode 100644 index 0000000000..dca99ef8f9 --- /dev/null +++ b/Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.h @@ -0,0 +1,37 @@ +/** @file +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* https://spdx.org/licenses +* +* Copyright (C) 2022 Marvell +* +* Header file for NULL RTC Driver +* +**/ + +#ifndef _RTC_NULL_DXE_H_ +#define _RTC_NULL_DXE_H_ + +#include + +#include +#include +#include +#include // gBS +#include // ZeroMem + +// +// Private data for driver. +// +#define RTC_NULL_DXE_PRIVATE_DATA_SIGNATURE SIGNATURE_32( 'R', 'T', 'C', = '_' ) + +typedef struct { + UINT32 Signature; + UINT8 Bus; + UINT8 SlaveAddr; + EFI_HANDLE RtcHandle; + BOOLEAN Initialized; +} RTC_NULL_PRIVATE_DATA; + + +#endif //_RTC_NULL_DXE_H_ diff --git a/Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.inf b/Silicon/= Marvell/Drivers/Null/RtcNull/RtcNullDxe.inf new file mode 100644 index 0000000000..d262e971fc --- /dev/null +++ b/Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.inf @@ -0,0 +1,46 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2022 Marvell +# Module description file of RTC NULL driver. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RtcNullDxe + FILE_GUID =3D 9c0a0971-b0f6-442e-ac01-0a3eb52c457d + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D RtcNullDxeInitialize + + +[Sources] + RtcNullDxe.c + RtcNullDxe.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + DebugLib + MemoryAllocationLib + UefiDriverEntryPoint + BaseMemoryLib + UefiBootServicesTableLib + UefiRuntimeLib + UefiRuntimeServicesTableLib + +[Guids] + gEfiEventVirtualAddressChangeGuid + +[Protocols] + gEfiRealTimeClockArchProtocolGuid ## PRODUCES + +[Depex] + TRUE + --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112783): https://edk2.groups.io/g/devel/message/112783 Mute This Topic: https://groups.io/mt/103292513/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112784+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112784+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120077; cv=none; d=zohomail.com; s=zohoarc; b=WXG8823WJFwptFyUQlvL24H/sd2Na4w2+x/LuMt0pVfwpHeS8c3lTbBYwvnHfJQCTG7GUGRy6CEa2h+12NuoJU4posk5Hk0dAbkAUFH/+YVjeb28gWNRMw24Qc0opIAkD/51FvGX41n/vIA8pKT3sjY1mj/S52wD4R3HK8MaHe8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120077; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=DSAXzy5O7ETdt4XM1l0eU3DhUF9KLyovdt2Mj0dFuD0=; b=gyMW7uQHnxuBC0j4++jjMT7WlIQ39dMj9m123qBauaGEWunUkXr2aSpbnY5a37AIFFHMelW/cd6FBSxBvXtM33KlW1F8crnXdJeyogTcVOksvJBqjWNLjdF2vfgzyMJztVGneJbffvOzNp4TY1z8IBmekE5tY6I41ZFdpeJiBnE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112784+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 170312007776249.45159769868144; Wed, 20 Dec 2023 16:54:37 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=alU72RTOskEW/WjlIiH81QlcolEz6ulDI5xYjnyYpQ0=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120077; v=1; b=eFu7ncb2Gdh5oufB9lTrkP4RXJWtevAcZm6EJ3eeTZxb+t7YICBJ0RHRrycyAWnIM+gzxjP1 Dt8Lw63UGZuDCDrDU3YwetqxSc6xbUyo4L4vqmeOB84JrxvntSnjoY4gmbRyEuk3TewqBfAN8gu N+WVMOHBDlQlRGqni1qtvOm8= X-Received: by 127.0.0.2 with SMTP id FT7jYY1788612x76wWGS8Gbt; Wed, 20 Dec 2023 16:54:37 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.148.174]) by mx.groups.io with SMTP id smtpd.web11.41321.1703120076826044605 for ; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKH2Ed9004000; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v3tbcvg8e-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:36 -0800 (PST) X-Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:35 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id 8BE2C5C68E1; Wed, 20 Dec 2023 16:54:34 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 6/8] Silicon/Marvell: Device tree driver Date: Wed, 20 Dec 2023 16:54:25 -0800 Message-ID: <20231221005427.13932-7-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 1DMqccE8Bjj75pNwbivEB_CClF6nt-E9 X-Proofpoint-GUID: 1DMqccE8Bjj75pNwbivEB_CClF6nt-E9 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: m6XYodKLk8EWyjbY9a3ZR4kgx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120079710100025 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds a device tree driver that is used to read board configuration information from a device tree. Signed-off-by: Narinder Dhillon --- .../Drivers/Fdt/FdtClientDxe/FdtClientDxe.c | 382 ++++++++++++++++++ .../Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf | 43 ++ .../Include/Protocol/FdtClient.h | 180 +++++++++ 3 files changed, 605 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.i= nf create mode 100644 Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtC= lient.h diff --git a/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c b/Sili= con/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c new file mode 100644 index 0000000000..aa4f773458 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.c @@ -0,0 +1,382 @@ +/** @file +* FDT client driver +* +* Copyright (c) 2016, Cavium Inc. All rights reserved.
+* Copyright (c) 2016, Linaro Ltd. All rights reserved.
+* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +STATIC VOID *mDeviceTreeBase; + +STATIC +EFI_STATUS +GetNodeProperty ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + OUT CONST VOID **Prop, + OUT UINT32 *PropSize OPTIONAL + ) +{ + INT32 Len; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Prop !=3D NULL); + + *Prop =3D fdt_getprop (mDeviceTreeBase, Node, PropertyName, &Len); + if (*Prop =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + if (PropSize !=3D NULL) { + *PropSize =3D Len; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SetNodeProperty ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + IN CONST VOID *Prop, + IN UINT32 PropSize + ) +{ + INT32 Ret; + + ASSERT (mDeviceTreeBase !=3D NULL); + + Ret =3D fdt_setprop (mDeviceTreeBase, Node, PropertyName, Prop, PropSize= ); + if (Ret !=3D 0) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +FindCompatibleNode ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *CompatibleString, + IN FDT_HANDLE PrevNode, + OUT FDT_HANDLE *Node + ) +{ + FDT_HANDLE Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_node_offset_by_compatible (mDeviceTreeBase, PrevNode, Com= patibleString); + + if (Offset < 0) { + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetOrInsertChosenNode ( + IN FDT_CLIENT_PROTOCOL *This, + OUT INT32 *Node + ) +{ + INT32 NewNode; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + NewNode =3D fdt_path_offset (mDeviceTreeBase, "/chosen"); + + if (NewNode < 0) { + NewNode =3D fdt_add_subnode (mDeviceTreeBase, 0, "/chosen"); + } + + if (NewNode < 0) { + return EFI_OUT_OF_RESOURCES; + } + + *Node =3D NewNode; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNodeDepth ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT INT32 *Depth +) +{ + *Depth =3D fdt_node_depth (mDeviceTreeBase, Node); + + if (*Depth < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetParentNode ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT FDT_HANDLE *Parent +) +{ + *Parent =3D fdt_parent_offset (mDeviceTreeBase, Node); + + if (*Parent < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNode ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *Path, + OUT FDT_HANDLE *Node +) +{ + *Node =3D fdt_path_offset (mDeviceTreeBase, Path); + + if (*Node < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNodePath ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Node, + OUT CHAR8 *Path, + IN INT32 Size +) +{ + INT32 Result; + + Result =3D fdt_get_path (mDeviceTreeBase, Node, Path, Size); + + if (Result < 0) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNodeByPropertyValue ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE StartNode, + IN CHAR8 *Property, + IN VOID *Value, + IN INT32 Size, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_node_offset_by_prop_value (mDeviceTreeBase, StartNode, + Property, Value, + Size); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetSubnodeByPropertyValue( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + IN CHAR8 *PropertyName, + IN VOID *PropertyValue, + IN INT32 PropertyLength, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + CONST VOID *Property; + INT32 Length; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_first_subnode (mDeviceTreeBase, Parent); + + while (Offset > 0) { + Property =3D fdt_getprop (mDeviceTreeBase, Offset, PropertyName, &Leng= th); + + if ((Property !=3D NULL) && + (PropertyLength =3D=3D Length) && + (CompareMem (Property, PropertyValue, Length) =3D=3D 0)) { + *Node =3D Offset; + return EFI_SUCCESS; + } + + Offset =3D fdt_next_subnode(mDeviceTreeBase, Offset); + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +GetNodeByPHandle ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE PHandle, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_node_offset_by_phandle (mDeviceTreeBase, PHandle); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetFirstSubnode ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + OUT FDT_HANDLE *Node +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Node !=3D NULL); + + Offset =3D fdt_first_subnode (mDeviceTreeBase, Parent); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Node =3D Offset; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetNextSubnode ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Subnode, + OUT FDT_HANDLE *Next +) +{ + INT32 Offset; + + ASSERT (mDeviceTreeBase !=3D NULL); + ASSERT (Next !=3D NULL); + + Offset =3D fdt_next_subnode (mDeviceTreeBase, Subnode); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Result: %d\n", Offset)); + return EFI_NOT_FOUND; + } + + *Next =3D Offset; + + return EFI_SUCCESS; +} + +STATIC FDT_CLIENT_PROTOCOL mFdtClientProtocol =3D { + GetNodeProperty, + SetNodeProperty, + FindCompatibleNode, + GetOrInsertChosenNode, + GetNodeDepth, + GetParentNode, + GetNode, + GetNodePath, + GetNodeByPropertyValue, + GetSubnodeByPropertyValue, + GetNodeByPHandle, + GetFirstSubnode, + GetNextSubnode +}; + +EFI_STATUS +EFIAPI +InitializeFdtClientDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + VOID *Hob; + VOID *DeviceTreeBase; + + Hob =3D GetFirstGuidHob (&gFdtHobGuid); + + if (Hob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + DeviceTreeBase =3D GET_GUID_HOB_DATA (Hob); + mDeviceTreeBase =3D (VOID *)*(UINT64 *)DeviceTreeBase; + if (fdt_check_header (mDeviceTreeBase)) { + DEBUG ((DEBUG_ERROR, "No DTB found @ 0x%p\n", DeviceTreeBase)); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, "DTB @ 0x%p\n", mDeviceTreeBase)); + + return gBS->InstallMultipleProtocolInterfaces (&ImageHandle, + &gFdtClientProtocolGuid, &mFdtClie= ntProtocol, + NULL); +} diff --git a/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf b/Si= licon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf new file mode 100644 index 0000000000..23bcf8810f --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf @@ -0,0 +1,43 @@ +## @file +# FDT client driver +# +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FdtClientDxe + FILE_GUID =3D 9A871B00-1C16-4F61-8D2C-93B6654B5AD6 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeFdtClientDxe + +[Sources] + FdtClientDxe.c + +[Packages] + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + FdtLib + HobLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gFdtClientProtocolGuid ## PRODUCES + +[Guids] + gFdtHobGuid + gFdtTableGuid + +[Depex] + TRUE diff --git a/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtClient.h= b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtClient.h new file mode 100644 index 0000000000..dd9af0bf8f --- /dev/null +++ b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/FdtClient.h @@ -0,0 +1,180 @@ +/** @file + + DISCLAIMER: the FDT_CLIENT_PROTOCOL introduced here is a work in progres= s, + and should not be used outside of the EDK II tree. + + Copyright (C) 2023 Marvell + Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FDT_CLIENT_H__ +#define __FDT_CLIENT_H__ + +#define FDT_CLIENT_PROTOCOL_GUID { \ + 0xE11FACA0, 0x4710, 0x4C8E, {0xA7, 0xA2, 0x01, 0xBA, 0xA2, 0x59, 0x1B, 0= x4C} \ + } + +#define FdtToCpu32(Value) SwapBytes32(Value) +#define CpuToFdt32(Value) SwapBytes32(Value) + +#define FdtToCpu64(Value) SwapBytes64(Value) +#define CpuToFdt64(Value) SwapBytes64(Value) + +// +// Protocol interface structure +// +typedef int FDT_HANDLE; +#define FDT_START_HANDLE -1 +typedef struct _FDT_CLIENT_PROTOCOL FDT_CLIENT_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NODE_PROPERTY) ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + OUT CONST VOID **Prop, + OUT UINT32 *PropSize OPTIONAL + ); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_SET_NODE_PROPERTY) ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + IN CONST CHAR8 *PropertyName, + IN CONST VOID *Prop, + IN UINT32 PropSize + ); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_FIND_COMPATIBLE_NODE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *CompatibleString, + IN FDT_HANDLE PrevNode, + OUT FDT_HANDLE *Node + ); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_FIND_COMPATIBLE_NODE_PROPERTY) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *CompatibleString, + IN CONST CHAR8 *PropertyName, + OUT CONST VOID **Prop, + OUT UINT32 *PropSize OPTIONAL + ); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_OR_INSERT_CHOSEN_NODE) ( + IN FDT_CLIENT_PROTOCOL *This, + OUT FDT_HANDLE *Node + ); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NODE_DEPTH) ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT FDT_HANDLE *Depth +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_PARENT_NODE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN FDT_HANDLE Node, + OUT FDT_HANDLE *Parent +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NODE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST CHAR8 *Path, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NODE_PATH) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Node, + OUT CHAR8 *Path, + IN INT32 Size +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NODE_BY_PROPERTY_VALUE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE StartNode, + IN CHAR8 *Property, + IN VOID *Value, + IN INT32 Size, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_SUBNODE_BY_PROPERTY_VALUE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + IN CHAR8 *PropertyName, + IN VOID *PropertyValue, + IN INT32 PropertyLength, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NODE_BY_PHANDLE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE PHandle, + OUT FDT_HANDLE *Node +); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_FIRST_SUBNODE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Parent, + OUT FDT_HANDLE *Node + ); + +typedef +EFI_STATUS +(EFIAPI *FDT_CLIENT_GET_NEXT_SUBNODE) ( + IN FDT_CLIENT_PROTOCOL *This, + IN CONST FDT_HANDLE Subnode, + OUT FDT_HANDLE *Next + ); + +struct _FDT_CLIENT_PROTOCOL { + FDT_CLIENT_GET_NODE_PROPERTY GetNodeProperty; + FDT_CLIENT_SET_NODE_PROPERTY SetNodeProperty; + + FDT_CLIENT_FIND_COMPATIBLE_NODE FindCompatibleNode; + + FDT_CLIENT_GET_OR_INSERT_CHOSEN_NODE GetOrInsertChosenNode; + + FDT_CLIENT_GET_NODE_DEPTH GetNodeDepth; + FDT_CLIENT_GET_PARENT_NODE GetParentNode; + FDT_CLIENT_GET_NODE GetNode; + FDT_CLIENT_GET_NODE_PATH GetNodePath; + FDT_CLIENT_GET_NODE_BY_PROPERTY_VALUE GetNodeByPropertyValue; + FDT_CLIENT_GET_SUBNODE_BY_PROPERTY_VALUE GetSubnodeByPropertyValue; + FDT_CLIENT_GET_NODE_BY_PHANDLE GetNodeByPHandle; + FDT_CLIENT_GET_FIRST_SUBNODE GetFirstSubnode; + FDT_CLIENT_GET_NEXT_SUBNODE GetNextSubnode; + +}; + +extern EFI_GUID gFdtClientProtocolGuid; + +#endif --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112784): https://edk2.groups.io/g/devel/message/112784 Mute This Topic: https://groups.io/mt/103292514/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112785+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112785+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120081; cv=none; d=zohomail.com; s=zohoarc; b=TyeAfS1+ZarvjQnA8R2/K0C+d7F6gp5Bes56rG4/bgTs7Fbbv1B9zVWjReXX5LuhDldk+TzbLAP8IyN7Yg/eXde72acG1MwMZIPMYZpG0yNW+IQx1GHSJ2twIzthtu7JBcC0pbm33m/JkTOwS/kU2zF1CA7Mpt8bEBhsag4vhsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120081; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=zKwW18tAhcuJ0hBqny2wG/1NGm+cVdH4QVTSQ532l+Q=; b=oDM4tdGydm5noh6UhyZ76Oa4bjFwNDEsEJD/VJ55kUuANdMM3HO15coZHxWU45jAkqygsZeZcy9f55vbLyF7mGrjx8UEaH0W+Cwd7zYQ1vAiSuo/JhI9pZuwGo7kkuY9EsxYoXXQM743HIE4jbaX0C3C/7VUcyxSpRt+qK2CHpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112785+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703120081884607.9127538301673; Wed, 20 Dec 2023 16:54:41 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=iu3CEaxlT0oa+PXo4O5thctkjvoFiS4AXrtFYRcO7uQ=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120081; v=1; b=ZXoBkippkrHtZqN4ErKFHtVgwEO/cBi0ExIpR5P11YZudJ/tFUVxuXj2yr34cNgNdwfo3yTI PhFITeOIqc1rpXFo4Vk63WYipUwwvnUX5oYixEIP69ojS3b+S+3nsYkoXp8QXS2YCIDSBKklNqI M5J6k+k+FELnwZbZB4OVt9Fc= X-Received: by 127.0.0.2 with SMTP id 60qXYY1788612xF0gDX0ojHf; Wed, 20 Dec 2023 16:54:41 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mx.groups.io with SMTP id smtpd.web10.41716.1703120080550837526 for ; Wed, 20 Dec 2023 16:54:40 -0800 X-Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKDJaGv028364; Wed, 20 Dec 2023 16:54:39 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3v3ntrn6w9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:38 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id 54AA25C68E5; Wed, 20 Dec 2023 16:54:35 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 7/8] Silicon/Marvell: Driver to dump board configuration Date: Wed, 20 Dec 2023 16:54:26 -0800 Message-ID: <20231221005427.13932-8-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: juFJUlO2eRxh8U-MWXZqifwtSaQWWJhv X-Proofpoint-ORIG-GUID: juFJUlO2eRxh8U-MWXZqifwtSaQWWJhv Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5MgmcjsMOREKih1AFdxqglH9x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120083749100031 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds an EDK2 shell command to dump board configuration device tree. Signed-off-by: Narinder Dhillon --- .../Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c | 361 ++++++++++++++++++ .../Drivers/Fdt/FdtPlatformDxe/FdtPlatform.h | 102 +++++ .../Fdt/FdtPlatformDxe/FdtPlatformDxe.inf | 60 +++ .../Fdt/FdtPlatformDxe/FdtPlatformDxe.uni | 106 +++++ .../Drivers/Fdt/FdtPlatformDxe/README.txt | 69 ++++ .../Drivers/Fdt/FdtPlatformDxe/ShellDumpFdt.c | 283 ++++++++++++++ 6 files changed, 981 insertions(+) create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.h create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformD= xe.inf create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformD= xe.uni create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/README.txt create mode 100644 Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/ShellDumpFdt= .c diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c b/Sil= icon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c new file mode 100644 index 0000000000..8faa135003 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.c @@ -0,0 +1,361 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + https://spdx.org/licenses + + Copyright (C) 2023 Marvell + + Copyright (c) 2015, ARM Ltd. All rights reserved.
+ +**/ + +#include "FdtPlatform.h" + +#include + +#include +#include +#include +#include + +#include + +// +// Internal variables +// + +STATIC CONST EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL mShellDynCmdProtocolDumpFd= t =3D { + L"dumpfdt", // Name of the command + ShellDynCmdDumpFdtHandler, // Handler + ShellDynCmdDumpFdtGetHelp // GetHelp +}; + +STATIC CONST EFI_GUID mFdtPlatformDxeHiiGuid =3D { + 0x8afa7610, 0x62b1, 0x46aa, + {0xb5, 0x34, 0xc3, 0xde, 0xff, 0x39, 0x77, 0x8c} + }; + +EFI_HANDLE mFdtPlatformDxeHiiHandle; +VOID *mFdtBlobBase; + +EFI_STATUS +DeleteFdtNode ( + IN VOID *FdtAddr, + CONST CHAR8 *NodePath, + CONST CHAR8 *Compatible +) +{ + INTN Offset =3D -1; + INTN Return; + + if ((NodePath !=3D NULL) && (Compatible !=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (NodePath !=3D NULL) { + Offset =3D fdt_path_offset (FdtAddr, NodePath); + + DEBUG ((DEBUG_INFO, "Offset: %d\n", Offset)); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Error getting the device node %a offset: %a\n", + NodePath, fdt_strerror (Offset))); + return EFI_NOT_FOUND; + } + } + + if (Compatible !=3D NULL) { + Offset =3D fdt_node_offset_by_compatible (FdtAddr, -1, Compatible); + + DEBUG ((DEBUG_INFO, "Offset: %d\n", Offset)); + + if (Offset < 0) { + DEBUG ((DEBUG_ERROR, "Error getting the device node for %a offset: %= a\n", + Compatible, fdt_strerror (Offset))); + return EFI_NOT_FOUND; + } + } + + if (Offset >=3D 0) { + Return =3D fdt_del_node (FdtAddr, Offset); + + DEBUG ((DEBUG_INFO, "Return: %d\n", Return)); + + if (Return < 0) { + DEBUG ((DEBUG_ERROR, "Error deleting the device node %a: %a\n", + NodePath, fdt_strerror (Return))); + return EFI_NOT_FOUND; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +DeleteRtcNode ( + IN VOID *FdtAddr + ) +{ + INT32 Offset, NameLen, Return; + BOOLEAN Found; + CONST CHAR8 *Name; + + Found =3D FALSE; + for (Offset =3D fdt_next_node(FdtAddr, 0, NULL); + Offset >=3D 0; + Offset =3D fdt_next_node(FdtAddr, Offset, NULL)) { + + Name =3D fdt_get_name(FdtAddr, Offset, &NameLen); + if (!Name) { + continue; + } + + if ((Name[0] =3D=3D 'r') && (Name[1] =3D=3D 't') && (Name[2] =3D=3D 'c= ')) { + Found =3D TRUE; + break; + } + } + + if (Found =3D=3D TRUE) { + Return =3D fdt_del_node (FdtAddr, Offset); + + if (Return < 0) { + DEBUG ((DEBUG_ERROR, "Error deleting the device node %a\n", Name)); + return EFI_NOT_FOUND; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FdtFixup( + IN VOID *FdtAddr + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + if (FeaturePcdGet(PcdFixupFdt)) { + Status |=3D DeleteFdtNode (FdtAddr, (CHAR8*)PcdGetPtr (PcdFdtConfigRoo= tNode), NULL); + + // Hide the RTC + Status |=3D DeleteRtcNode (FdtAddr); + } + + if (!EFI_ERROR(Status)) { + fdt_pack(FdtAddr); + } + + return EFI_SUCCESS; +} + + +/** + Install the FDT specified by its device path in text form. + + @retval EFI_SUCCESS The FDT was installed. + @retval EFI_NOT_FOUND Failed to locate a protocol or a file. + @retval EFI_INVALID_PARAMETER Invalid device path. + @retval EFI_UNSUPPORTED Device path not supported. + @retval EFI_OUT_OF_RESOURCES An allocation failed. +**/ +STATIC +EFI_STATUS +InstallFdt ( + VOID +) +{ + EFI_STATUS Status; + UINTN FdtBlobSize; + VOID *FdtConfigurationTableBase; + VOID *HobList; + EFI_HOB_GUID_TYPE *GuidHob; + + // + // Get the HOB list. If it is not present, then ASSERT. + // + HobList =3D GetHobList (); + ASSERT (HobList !=3D NULL); + + // + // Search for FDT GUID HOB. If it is not present, then + // there's nothing we can do. It may not exist on the update path. + // + GuidHob =3D GetNextGuidHob (&gFdtHobGuid, HobList); + if (GuidHob !=3D NULL) { + mFdtBlobBase =3D (VOID *)*(UINT64 *)(GET_GUID_HOB_DATA (GuidHob)); + FdtBlobSize =3D fdt_totalsize((VOID *)mFdtBlobBase); + + // + // Ensure that the FDT header is valid and that the Size of the Device= Tree + // is smaller than the size of the read file + // + if (fdt_check_header (mFdtBlobBase)) { + DEBUG ((DEBUG_ERROR, "InstallFdt() - FDT blob seems to be corrupt\= n")); + mFdtBlobBase =3D NULL; + Status =3D EFI_LOAD_ERROR; + goto Error; + } + } else { + Status =3D EFI_NOT_FOUND; + goto Error; + } + + Status =3D EFI_SUCCESS; + + if (FeaturePcdGet(PcdPublishFdt)) { + FdtConfigurationTableBase =3D AllocateRuntimeCopyPool (FdtBlobSize, mF= dtBlobBase); + + if (FdtConfigurationTableBase =3D=3D NULL) { + goto Error; + } + + Status =3D FdtFixup((VOID*)FdtConfigurationTableBase); + + if (EFI_ERROR (Status)) { + FreePool (FdtConfigurationTableBase); + goto Error; + } + + // + // Install the FDT into the Configuration Table + // + Status =3D gBS->InstallConfigurationTable ( + &gFdtTableGuid, + FdtConfigurationTableBase + ); + + if (EFI_ERROR (Status)) { + FreePool (FdtConfigurationTableBase); + } + } + +Error: + return Status; +} + +/** + Main entry point of the FDT platform driver. + + @param[in] ImageHandle The firmware allocated handle for the present = driver + UEFI image. + @param[in] *SystemTable A pointer to the EFI System table. + + @retval EFI_SUCCESS The driver was initialized. + @retval EFI_OUT_OF_RESOURCES The "End of DXE" event could not be alloc= ated or + there was not enough memory in pool to in= stall + the Shell Dynamic Command protocol. + @retval EFI_LOAD_ERROR Unable to add the HII package. + +**/ +EFI_STATUS +FdtPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // + // Install the Device Tree from its expected location + // + Status =3D InstallFdt (); + + ASSERT_EFI_ERROR(Status); + + // + // Register the strings for the user interface in the HII Database. + // This shows the way to the multi-language support, even if + // only the English language is actually supported. The strings to regis= ter + // are stored in the "ShellSetFdtStrings[]" array. This array is + // built by the building process from the "*.uni" file associated to + // the present driver (cf. FdtPlatfromDxe.inf). Examine your Build + // folder under your package's DEBUG folder and you will find the array + // defined in a xxxStrDefs.h file. + // + mFdtPlatformDxeHiiHandle =3D HiiAddPackages ( + &mFdtPlatformDxeHiiGuid, + ImageHandle, + FdtPlatformDxeStrings, + NULL + ); + if (mFdtPlatformDxeHiiHandle !=3D NULL) { + // We install dynamic EFI command on separate handles as we cannot reg= ister + // more than one protocol of the same protocol interface on the same h= andle. + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiShellDynamicCommandProtocolGuid, + &mShellDynCmdProtocolDumpFdt, + NULL + ); + if (EFI_ERROR (Status)) { + HiiRemovePackages (mFdtPlatformDxeHiiHandle); + } + } else { + Status =3D EFI_LOAD_ERROR; + } + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_WARN, + "Unable to install \"dumpfdt\" EFI Shell command - %r \n", + Status + )); + } + + return Status; +} + +/** + Transcode one of the EFI return code used by the model into an EFI Shell= return code. + + @param[in] Status EFI return code. + + @return Transcoded EFI Shell return code. + +**/ +SHELL_STATUS +EfiCodeToShellCode ( + IN EFI_STATUS Status + ) +{ + SHELL_STATUS ShellStatus; + + switch (Status) { + case EFI_SUCCESS : + ShellStatus =3D SHELL_SUCCESS; + break; + + case EFI_INVALID_PARAMETER : + ShellStatus =3D SHELL_INVALID_PARAMETER; + break; + + case EFI_UNSUPPORTED : + ShellStatus =3D SHELL_UNSUPPORTED; + break; + + case EFI_DEVICE_ERROR : + ShellStatus =3D SHELL_DEVICE_ERROR; + break; + + case EFI_WRITE_PROTECTED : + case EFI_SECURITY_VIOLATION : + ShellStatus =3D SHELL_ACCESS_DENIED; + break; + + case EFI_OUT_OF_RESOURCES : + ShellStatus =3D SHELL_OUT_OF_RESOURCES; + break; + + case EFI_NOT_FOUND : + ShellStatus =3D SHELL_NOT_FOUND; + break; + + default : + ShellStatus =3D SHELL_ABORTED; + } + + return ShellStatus; +} diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.h b/Sil= icon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.h new file mode 100644 index 0000000000..22517b6d28 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatform.h @@ -0,0 +1,102 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + https://spdx.org/licenses + + Copyright (C) 2023 Marvell + + Copyright (c) 2015, ARM Ltd. All rights reserved.
+ +**/ + +#ifndef __FDT_PLATFORM_DXE_H__ +#define __FDT_PLATFORM_DXE_H__ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +extern EFI_HANDLE mFdtPlatformDxeHiiHandle; + +/** + Transcode one of the EFI return code used by the model into an EFI Shell= return code. + + @param[in] Status EFI return code. + + @return Transcoded EFI Shell return code. + +**/ +SHELL_STATUS +EfiCodeToShellCode ( + IN EFI_STATUS Status + ); + +/** + Run the FDT installation process. + + Loop in priority order over the device paths from which the FDT has + been asked to be retrieved for. For each device path, try to install + the FDT. Stop as soon as an installation succeeds. + + @param[in] SuccessfullDevicePath If not NULL, address where to store t= he + pointer to the text device path from + which the FDT was successfully retrie= ved. + Not used if the FDT installation fail= ed. + The returned address is the address of + an allocated buffer that has to be + freed by the caller. + + @retval EFI_SUCCESS The FDT was installed. + @retval EFI_NOT_FOUND Failed to locate a protocol or a file. + @retval EFI_INVALID_PARAMETER Invalid device path. + @retval EFI_UNSUPPORTED Device path not supported. + @retval EFI_OUT_OF_RESOURCES An allocation failed. + +**/ +EFI_STATUS +RunFdtInstallation ( + OUT CHAR16 **SuccessfullDevicePath + ); + +SHELL_STATUS +EFIAPI +ShellDynCmdDumpFdtHandler ( + IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This, + IN EFI_SYSTEM_TABLE *SystemTable, + IN EFI_SHELL_PARAMETERS_PROTOCOL *ShellParameters, + IN EFI_SHELL_PROTOCOL *Shell + ); + +/** + This is the shell command "dumpfdt" help handler function. This + function returns the formatted help for the "dumpfdt" command. + The format matchs that in Appendix B of the revision 2.1 of the + UEFI Shell Specification. + + @param[in] This The instance of the EFI_SHELL_DYNAMIC_COMMAND_PROT= OCOL. + @param[in] Language The pointer to the language string to use. + + @return CHAR16* Pool allocated help string, must be freed by caller. +**/ +CHAR16* +EFIAPI +ShellDynCmdDumpFdtGetHelp ( + IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This, + IN CONST CHAR8 *Language + ); + +#endif /* __FDT_PLATFORM_DXE_H__ */ diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf = b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf new file mode 100644 index 0000000000..1c3496d13f --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf @@ -0,0 +1,60 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# Copyright (c) 2015, ARM Ltd. All rights reserved.
+# +#**/ + +[Defines] + INF_VERSION =3D 0x00010006 + BASE_NAME =3D FdtPlatformDxe + MODULE_UNI_FILE =3D FdtPlatformDxe.uni + FILE_GUID =3D 6e9a4c69-57c6-4fcd-b083-4f2c3bdb6051 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 0.1 + ENTRY_POINT =3D FdtPlatformEntryPoint + +[Sources.common] + FdtPlatform.c + FdtPlatformDxe.uni + ShellDumpFdt.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/ARM/ARM.dec + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec + ShellPkg/ShellPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + FdtLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + HiiLib + ShellLib + HobLib + +[Protocols] + gEfiShellDynamicCommandProtocolGuid + +[Guids] + gFdtHobGuid + gFdtTableGuid + +[FeaturePcd] + gMarvellSiliconTokenSpaceGuid.PcdPublishFdt + gMarvellSiliconTokenSpaceGuid.PcdFixupFdt + +[FixedPcd] + gMarvellSiliconTokenSpaceGuid.PcdFdtConfigRootNode + +[Depex] + TRUE diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.uni = b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.uni new file mode 100644 index 0000000000..828fb9a609 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.uni @@ -0,0 +1,106 @@ +// *++ +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// https://spdx.org/licenses +// +// Copyright (C) 2023 Marvell +// +// Copyright (c) 2014, ARM Ltd. All rights reserved.
+// +// +// Module Name: +// +// FdtPlatformDxe +// +// Abstract: +// +// String definitions for the EFI Shell 'setfdt' command +// +// Revision History: +// +// --*/ + +/=3D# + +#langdef en-US "English" + +#string STR_SETFDT_INSTALLING #language en-US "Installing the FD= T ...\r\n" +#string STR_SETFDT_INSTALL_SUCCEEDED #language en-US "Installation of\r= \n'%s'\r\ncompleted.\r\n" + +#string STR_SETFDT_UPDATING #language en-US "Updating the FDT = device path ...\r\n" +#string STR_SETFDT_UPDATE_SUCCEEDED #language en-US "Update of the FDT= device path '%s' completed.\r\n" +#string STR_SETFDT_UPDATE_DELETED #language en-US "The UEFI variable= "Fdt" was deleted.\r\n" + +#string STR_SETFDT_INVALID_DEVICE_PATH #language en-US "Invalid device pa= th.\r\n" +#string STR_SETFDT_INVALID_PATH #language en-US "The EFI Shell or = device file path '%s' is invalid.\r\n" +#string STR_SETFDT_ERROR #language en-US "Error - %r.\r\n" +#string STR_SETFDT_DEVICE_PATH_LIST #language en-US "FDT device paths = :\r\n" +#string STR_SETFDT_DEVICE_PATH #language en-US "'%s'\r\n" + +#string STR_GET_HELP_SETFDT #language en-US "" +".TH setfdt 0 "Define and/or install a new Flat Device Tree (FDT) for the = platform."\r\n" +".SH NAME\r\n" +"Define and/or re-install a Flat Device Tree (FDT)\r\n" +".SH SYNOPSIS\r\n" +"setfdt [-i] [fdt_path]\r\n" +".SH OPTIONS\r\n" +"-i run the FDT installation process\r\n" +"file_path EFI Shell file path or device path to a FDT\r\n" +"\r\n" +".SH DESCRIPTION\r\n" +"NOTES:\r\n" +"1. If a valid EFI Shell file path is passed to the command, then the\r\n" +" command translates the EFI Shell file path into a device path in the\r= \n" +" text form and saves it in the non volatile UEFI variable "Fdt". If\r\n" +" the path to the FDT is a device path in the text form, it is saved as\= r\n" +" it is in the non volatile UEFI variable "Fdt". The next time the FDT\r= \n" +" installation process is run, it will first try to install the FDT from= \r\n" +" the device path specified by the UEFI variable "Fdt".\r\n" +" \r\n +"2. If the option -i is passed to the command, then the FDT installation\r= \n" +" process is run. If a path to the FDT is passed to the command as well,= \r\n" +" the update of the "Fdt" UEFI variable is done first before to launch\r= \n" +" the FDT installation process.\r\n" +" \r\n +".SH RETURNVALUES\r\n" +"SHELL_SUCCESS Operation(s) completed.\r\n" +"SHELL_ABORTED Operation aborted.\r\n" +"SHELL_INVALID_PARAMETER Invalid argument(s).\r\n" +"SHELL_NOT_FOUND Failed to locate a protocol or a file.\r\n" +"SHELL_UNSUPPORTED Device path not supported.\r\n" +"SHELL_OUT_OF_RESOURCES A memory allocation failed.\r\n" +"SHELL_DEVICE ERROR Hardware failure.\r\n" +"SHELL_ACCESS_DENIED Access to the Fdt UEFI variable for modification= denied.\r\n" +".SH EXAMPLES\r\n" +"EXAMPLES:\r\n" +"1. Relaunch the FDT installation process :\r\n" +" Shell> setfdt -i\r\n" +" \r\n" +"2. Set the EFI Shell file path 'fs0:\>fdt.dtb' to be the default path\r\n" +" to the FDT :\r\n" +" Shell> setfdt fs0:fdt.dtb\r\n" +" \r\n" +"3. Set a TFTP device path to be the default path to the FDT :\r\n" +" Shell> setfdt MAC(0002f700570b,0x1)/IPv4(192.168.1.1)/fdt.dtb\r\n" +" where . 00:02:f7:00:57:0b is the MAC address of the network\r\n" +" interface card to be used. The 'ifconfig -l' EFI Shell\r\n" +" command allows to get the MAC address of the network\r\n" +" interface cards.\r\n" +" . 192.168.1.1 is the address of the TFTP server.\r\n" +" . fdt.dtb is the file path to the FDT file on the server.\r\n" +"4. Display the FDT device paths from the highest to the lowest\r\n" +" priority :\r\n" +" Shell> setfdt\r\n" +"5. Delete the "Fdt" UEFI variable :\r\n" +" Shell> setfdt ""\r\n" +"\r\n" + +#string STR_GET_HELP_DUMPFDT #language en-US "" +".TH dumpfdt 0 "Dump installed Flat Device Tree (FDT) of the platform."\r\= n" +".SH NAME\r\n" +"Dump current Flat Device Tree (FDT)\r\n" +".SH SYNOPSIS\r\n" +"dumpfdt\r\n" +"\r\n" +".SH DESCRIPTION\r\n" +"\r\n" diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/README.txt b/Silico= n/Marvell/Drivers/Fdt/FdtPlatformDxe/README.txt new file mode 100644 index 0000000000..fe0ee0ba1b --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/README.txt @@ -0,0 +1,69 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + https://spdx.org/licenses + + Copyright (C) 2023 Marvell + + Copyright (c) 2015, ARM Ltd. All rights reserved.
+ +**/ + +The purpose of the FdtPlatformDxe UEFI driver is to install the Flat Device +Tree (FDT) of the platform the UEFI frimware is running on into the UEFI +Configuration Table. The FDT is identified within the UEFI Configuration +Table by the "gFdtTableGuid" GUID defined in "EmbeddedPkg.dec". + +Once installed, an UEFI application or OS boot loader can get from the UEFI +Configuration Table the FDT of the platform from the "gFdtTableGuid" GUID. + +The installation is done after each boot at the end of the DXE phase, +just before the BDS phase. It is done at the end of the DXE phase to be su= re +that all drivers have been dispatched. That way, all UEFI protocols that m= ay +be needed to retrieve the FDT can be made available. It is done before the= BDS +phase to be able to provide the FDT during that phase. + +The present driver tries to retrieve the FDT from the device paths defined= in the +"gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" PCD. The "PcdFdtDevicePaths" P= CD +contains a list a device paths. The device paths are in the text form and +separated by semi-colons. The present driver tries the device paths in the= order +it finds them in the "PcdFdtDevicePaths" PCD as long as he did not install +succesfully a FDT. + +The "PcdFdtDevicePaths" PCD is a dynamic PCD that can be modified during t= he +DXE phase. This allows for exemple to select the right FDT when a binary is +intended to run on several platforms and/or variants of a platform. + +If the driver manages to download a FDT from one of the device paths menti= oned +above then it installs it in the UEFI Configuration table and the run over= the +device paths is stopped. + +For development purposes only, if the feature PCD "gEmbeddedTokenSpaceGuid. +PcdOverridePlatformFdt" is equal to TRUE, then before to try to install the +FDT from the device paths listed in the "PcdFdtDevicePaths" PCD, the prese= nt +driver tries to install it using the device path defined by the UEFI varia= ble +"Fdt". If the variable does not exist or the installation using the device= path +defined by the UEFI variable fails then the installation proceeds as descr= ibed +above. + +Furthermore and again for development purposes only, if the feature PCD +"PcdOverridePlatformFdt" is equal to TRUE, the current driver provides the= EFI +Shell command "setfdt" to define the location of the FDT by the mean of an= EFI +Shell file path (like "fs2:\boot\fdt.dtb") or a device path. + +If the path passed in to the command is a valid EFI Shell file path, the +command translates it into the corresponding device path and stores that +device path in the "Fdt" UEFI variable asking for the variable to be non +volatile. + +If the path passed in to the command is not recognised as a valid EFI +Shell device path, the command handles it as device path and stored +in the "Fdt" UEFI variable as it is. + +Finally, the "-i" option of the "setfdt" command allows to trigger the FDT +installation process. The installation process is completed when the comma= nd +returns. The command can be invoked with the "-i" option only and in that +case the "Fdt" UEFI variable is not updated and the command just runs the +FDT installation process. If the command is invoked with the "-i" option a= nd +an EFI Shell file path then first the "Fdt" UEFI variable is updated accor= dingly +and then the FDT installation process is run. diff --git a/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/ShellDumpFdt.c b/Si= licon/Marvell/Drivers/Fdt/FdtPlatformDxe/ShellDumpFdt.c new file mode 100644 index 0000000000..cf570b1576 --- /dev/null +++ b/Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/ShellDumpFdt.c @@ -0,0 +1,283 @@ +/** @file + + SPDX-License-Identifier: BSD-2-Clause-Patent + https://spdx.org/licenses + + Copyright (C) 2023 Marvell + + Copyright (c) 2015, ARM Ltd. All rights reserved.
+ +**/ + +#include "FdtPlatform.h" + +extern VOID *mFdtBlobBase; + +#define ALIGN(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) +#define PALIGN(p, a) ((void *)(ALIGN ((unsigned long)(p), (a)))) +#define GET_CELL(p) (p +=3D 4, *((const uint32_t *)(p-4))) + +STATIC +UINTN +IsPrintableString ( + IN CONST VOID* data, + IN UINTN len + ) +{ + CONST CHAR8 *s =3D data; + CONST CHAR8 *ss; + + // Zero length is not + if (len =3D=3D 0) { + return 0; + } + + // Must terminate with zero + if (s[len - 1] !=3D '\0') { + return 0; + } + + ss =3D s; + while (*s/* && isprint (*s)*/) { + s++; + } + + // Not zero, or not done yet + if (*s !=3D '\0' || (s + 1 - ss) < len) { + return 0; + } + + return 1; +} + +STATIC +VOID +PrintData ( + IN CONST CHAR8* data, + IN UINTN len + ) +{ + UINTN i; + CONST CHAR8 *p =3D data; + + // No data, don't print + if (len =3D=3D 0) + return; + + if (IsPrintableString (data, len)) { + Print (L" =3D \"%a\"", (const char *)data); + } else if ((len % 4) =3D=3D 0) { + Print (L" =3D <"); + for (i =3D 0; i < len; i +=3D 4) { + Print (L"0x%08x%a", fdt32_to_cpu (GET_CELL (p)), i < (len - 4) ? " "= : ""); + } + Print (L">"); + } else { + Print (L" =3D ["); + for (i =3D 0; i < len; i++) + Print (L"%02x%a", *p++, i < len - 1 ? " " : ""); + Print (L"]"); + } +} + +STATIC +VOID +DumpFdt ( + IN VOID* FdtBlob + ) +{ + struct fdt_header *bph; + UINT32 off_dt; + UINT32 off_str; + CONST CHAR8* p_struct; + CONST CHAR8* p_strings; + CONST CHAR8* p; + CONST CHAR8* s; + CONST CHAR8* t; + UINT32 tag; + UINTN sz; + UINTN depth; + UINTN shift; + UINT32 version; + + { + // Can 'memreserve' be printed by below code? + INTN num =3D fdt_num_mem_rsv (FdtBlob); + INTN i, err; + UINT64 addr =3D 0, size =3D 0; + + for (i =3D 0; i < num; i++) { + err =3D fdt_get_mem_rsv (FdtBlob, i, &addr, &size); + if (err) { + DEBUG ((DEBUG_ERROR, "Error (%d) : Cannot get memreserve section (= %d)\n", err, i)); + } + else { + Print (L"/memreserve/ \t0x%lx \t0x%lx;\n", addr, size); + } + } + } + + depth =3D 0; + shift =3D 4; + + bph =3D FdtBlob; + off_dt =3D fdt32_to_cpu (bph->off_dt_struct); + off_str =3D fdt32_to_cpu (bph->off_dt_strings); + p_struct =3D (CONST CHAR8*)FdtBlob + off_dt; + p_strings =3D (CONST CHAR8*)FdtBlob + off_str; + version =3D fdt32_to_cpu (bph->version); + + p =3D p_struct; + while ((tag =3D fdt32_to_cpu (GET_CELL (p))) !=3D FDT_END) { + if (tag =3D=3D FDT_BEGIN_NODE) { + s =3D p; + p =3D PALIGN (p + AsciiStrLen (s) + 1, 4); + + if (*s =3D=3D '\0') + s =3D "/"; + + Print (L"%*s%a {\n", depth * shift, L" ", s); + + depth++; + continue; + } + + if (tag =3D=3D FDT_END_NODE) { + depth--; + + Print (L"%*s};\n", depth * shift, L" "); + continue; + } + + if (tag =3D=3D FDT_NOP) { + /* Print (L"%*s// [NOP]\n", depth * shift, L" "); */ + continue; + } + + if (tag !=3D FDT_PROP) { + Print (L"%*s ** Unknown tag 0x%08x\n", depth * shift, L" ", tag); + break; + } + sz =3D fdt32_to_cpu (GET_CELL (p)); + s =3D p_strings + fdt32_to_cpu (GET_CELL (p)); + if (version < 16 && sz >=3D 8) + p =3D PALIGN (p, 8); + t =3D p; + + p =3D PALIGN (p + sz, 4); + + Print (L"%*s%a", depth * shift, L" ", s); + PrintData (t, sz); + Print (L";\n"); + } +} + +/** + This is the shell command "dumpfdt" handler function. This function hand= les + the command when it is invoked in the shell. + + @param[in] This The instance of the + EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL. + @param[in] SystemTable The pointer to the UEFI system table. + @param[in] ShellParameters The parameters associated with the command. + @param[in] Shell The instance of the shell protocol used in = the + context of processing this command. + + @return SHELL_SUCCESS The operation was successful. + @return SHELL_ABORTED Operation aborted due to internal erro= r. + @return SHELL_NOT_FOUND Failed to locate the Device Tree into = the EFI Configuration Table + @return SHELL_OUT_OF_RESOURCES A memory allocation failed. + +**/ +SHELL_STATUS +EFIAPI +ShellDynCmdDumpFdtHandler ( + IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This, + IN EFI_SYSTEM_TABLE *SystemTable, + IN EFI_SHELL_PARAMETERS_PROTOCOL *ShellParameters, + IN EFI_SHELL_PROTOCOL *Shell + ) +{ + SHELL_STATUS ShellStatus; + EFI_STATUS Status; + VOID *FdtBlob; + + ShellStatus =3D SHELL_SUCCESS; + + // + // Install the Shell and Shell Parameters Protocols on the driver + // image. This is necessary for the initialisation of the Shell + // Library to succeed in the next step. + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &gImageHandle, + &gEfiShellProtocolGuid, Shell, + &gEfiShellParametersProtocolGuid, ShellParameters, + NULL + ); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; + } + + // + // Initialise the Shell Library as we are going to use it. + // Assert that the return code is EFI_SUCCESS as it should. + // To anticipate any change is the codes returned by + // ShellInitialize(), leave in case of error. + // + Status =3D ShellInitialize (); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return SHELL_ABORTED; + } + + if (PcdGetBool (PcdPublishFdt)) { + Status =3D EfiGetSystemConfigurationTable (&gFdtTableGuid, &FdtBlob); + + if (EFI_ERROR (Status)) { + Print (L"ERROR: Did not find the Fdt Blob.\n"); + return EfiCodeToShellCode (Status); + } + } else { + FdtBlob =3D mFdtBlobBase; + } + + DumpFdt (FdtBlob); + + gBS->UninstallMultipleProtocolInterfaces ( + gImageHandle, + &gEfiShellProtocolGuid, Shell, + &gEfiShellParametersProtocolGuid, ShellParameters, + NULL + ); + + return ShellStatus; +} + +/** + This is the shell command "dumpfdt" help handler function. This + function returns the formatted help for the "dumpfdt" command. + The format matchs that in Appendix B of the revision 2.1 of the + UEFI Shell Specification. + + @param[in] This The instance of the EFI_SHELL_DYNAMIC_COMMAND_PROT= OCOL. + @param[in] Language The pointer to the language string to use. + + @return CHAR16* Pool allocated help string, must be freed by caller. +**/ +CHAR16* +EFIAPI +ShellDynCmdDumpFdtGetHelp ( + IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This, + IN CONST CHAR8 *Language + ) +{ + // + // This allocates memory. The caller has to free the allocated memory. + // + return HiiGetString ( + mFdtPlatformDxeHiiHandle, + STRING_TOKEN (STR_GET_HELP_DUMPFDT), + Language + ); +} --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112785): https://edk2.groups.io/g/devel/message/112785 Mute This Topic: https://groups.io/mt/103292517/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 15 13:19:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112786+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112786+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=marvell.com ARC-Seal: i=1; a=rsa-sha256; t=1703120082; cv=none; d=zohomail.com; s=zohoarc; b=G0+G+cYcj5azHiJwhYjvkFTfXTpkGzLpQZ9UOWT3/ZDHATTpSljgeWlQRL9BAHxGIHFfVRkXRvou8BCyBLsV0ndSqnMWOgGargKRoYe00GxcMGOhzIB+cuNrqcj6/IM6jhFVAkGRdU4BSRrms339R5pbHCOBK+ES9jGmlNethwA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703120082; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=7OPt01RwYx77NwgF3ppqFrP+6cysqb/KTADXuZXmKl8=; b=mgJ7TwZGJQy3Ke2hmRkuIE4mT46sziDWd/7KuTgm+VwmOIzyWV+6V51fRxUCTY0Nd9TXaZZW0NMs0cDfFK+dZWaMBwBixpUwIcKWxJuxU8s2fdQhhAKlR5sPFUT16Igr59+BiLy3aeZrhvTxY5zI/6OtiGDA3xc9Vhub5Jy33K0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112786+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703120082339411.0492948354266; Wed, 20 Dec 2023 16:54:42 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=w6YkS2O1LDjxFclLd5VMFwVaPFdyfNyxbMJWsxsf6lc=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1703120082; v=1; b=HPo/JWZ9ReKIL4vsFmBcTTIY5fibiqv4/Mc8//m+NGTnmpTTz01HSj+PbySPZkGQPEPHvLZz n9s4l/tZM9CySDstXRfUFp8bTZKAggbMdozqSO8SKvl3P613lWgIJV/2aYSkFg3Ntoe9eORzXkl rzRdzsx7AS28c4Skc3cCOse0= X-Received: by 127.0.0.2 with SMTP id R01XYY1788612xi7KFu4k3H6; Wed, 20 Dec 2023 16:54:42 -0800 X-Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mx.groups.io with SMTP id smtpd.web10.41717.1703120081323876095 for ; Wed, 20 Dec 2023 16:54:41 -0800 X-Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BKDJaGw028364; Wed, 20 Dec 2023 16:54:40 -0800 X-Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3v3ntrn6w9-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 16:54:40 -0800 (PST) X-Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 20 Dec 2023 16:54:36 -0800 X-Received: from MRVL-5Lp9he46Ey.marvell.com (unknown [10.193.15.34]) by maili.marvell.com (Postfix) with ESMTP id 331FE5C68E1; Wed, 20 Dec 2023 16:54:36 -0800 (PST) From: "Narinder Dhillon" To: CC: , , , Narinder Dhillon Subject: [edk2-devel] [edk2-platforms PATCH v2 8/8] Silicon/Marvell: Odyssey project description files Date: Wed, 20 Dec 2023 16:54:27 -0800 Message-ID: <20231221005427.13932-9-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-1-ndhillon@marvell.com> References: <20231221005427.13932-1-ndhillon@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: zer_8XG82colZYwvXAzIOGnzaiMWAWaZ X-Proofpoint-ORIG-GUID: zer_8XG82colZYwvXAzIOGnzaiMWAWaZ Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ndhillon@marvell.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: TsrpPFNqpQt4NLEfQ222d924x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703120083774100032 Content-Type: text/plain; charset="utf-8" From: Narinder Dhillon This patch adds Odyssey SoC project description file, flash description file, and PCD's. Signed-off-by: Narinder Dhillon --- Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc | 216 ++++++++++ Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf | 304 ++++++++++++++ .../MarvellSiliconPkg/MarvellSiliconPkg.dec | 19 + Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc | 394 ++++++++++++++++++ 4 files changed, 933 insertions(+) create mode 100644 Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc create mode 100644 Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf create mode 100644 Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc diff --git a/Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc b/Platform/Marvell/= OdysseyPkg/OdysseyPkg.dsc new file mode 100644 index 0000000000..ade2faa8bb --- /dev/null +++ b/Platform/Marvell/OdysseyPkg/OdysseyPkg.dsc @@ -0,0 +1,216 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# The main build description file for OdysseyPkg. +#**/ + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D OdysseyPkg # PLAT=3Dody + PLATFORM_GUID =3D 7E7000DE-F50F-46AE-9B2C-903225F72B13 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 +!ifdef $(EDK2_OUT_DIR) # Custom output directory, e.g. -D EDK2_OUT_DIR=3DB= uild/XYZ + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/Marvell/$(PLATFORM_NAME)/$(P= LATFORM_NAME).fdf + +# dsc.inc file can be used in case there are different variants/boards of = Odyssey family. +# Per-board additional components shall be defined in exclusive dsc.inc fi= les. +!include Silicon/Marvell/$(PLATFORM_NAME)/$(PLATFORM_NAME).dsc.inc + +[LibraryClasses] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf # used by PlatformSmbiosDxe + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf # used by SmcLib + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf # used by Sp= iNorDxe + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf # used by UsbKbDxe + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLib= Null.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf # used by Ba= seBmpSupportLib +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf +!endif +# ShellPkg/Application/Shell/Shell.inf -> UefiShellCommandLib -> OrderedCo= llectionLib + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf # used by CapsuleApp + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + +[BuildOptions] +# GCC will generate code that runs on processors as idicated by -march +# Single =3D (append) allows flags appendixes coming from [BuildOptions] d= efined in specific INFs. + GCC:*_*_AARCH64_PLATFORM_FLAGS =3D -DPLAT=3D0xBF -march=3Darmv8.2-a -fdi= agnostics-color -fno-diagnostics-show-caret +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFixedAtBuild.common] + + # Generic Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x8020000A0000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x8020000B0000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|0x1A + + # BIT0 - Initialization message.
+ # BIT1 - Warning message.
+ # BIT2 - Load Event message.
+ # BIT3 - File System message.
+ # BIT6 - Information message.
+ # DEBUG_ERROR 0x80000000 // Error + # NOTE: Adjust according to needs. See MdePkg.dec for bits definition. + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F + + # The size of volatile buffer. This buffer is used to store VOLATILE att= ribute variables. + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x00040000 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Set ARM PCD: Odyssey: up to 80 Neoverse V2 cores (code named Demeter) + # Used to setup secondary cores stacks and ACPI PPTT. + gArmPlatformTokenSpaceGuid.PcdCoreCount|80 + + # Stacks for MPCores in Normal World, Non-Trusted DRAM + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # System Memory (40 - 1TB of DRAM) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00004000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x10000000000 + + # Size of the region used by UEFI in permanent memory (Reserved 128MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000 + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x87e028000000 + + # ARM General Interrupt Controller + gArmTokenSpaceGuid.PcdGicDistributorBase|0x801000000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x801000080000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x801000020000 + + # Hardcoded terminal: TTYTERM, NOT defined in UEFI SPEC + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # UART port Divisor setting based on clock 16.66Mhz and baud 115200 + gArmPlatformTokenSpaceGuid.PL011UartInteger|9 + gArmPlatformTokenSpaceGuid.PL011UartFractional|2 + +[PcdsDynamicDefault.common] + + # Indicates if Variable driver will enable emulated variable NV mode. + # Reset by SpiNorDxe driver when SPI is in place and can handle storing = EFI Variables. + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + + # UEFI is placed in RAM by bootloader + Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf { + + # SoC specific implementation of ArmPlatformLib + ArmPlatformLib|Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib= .inf + } + + # + # PEI Phase modules + # + # PEI phase is skipped. SEC jumps directly to DXE. + + # + # Core DXE modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # DXE Status codes + # +!if $(DEBUG) =3D=3D 1 + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf +!endif + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePol= icyLibRuntimeDxe.inf + } + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + # Produces gEfiFaultTolerantWriteProtocolGuid needed for non-volatile UE= FI variable storage. + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # RTC Support + Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.inf + + # + # ARM Support + # + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Multiple Console IO support + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf diff --git a/Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf b/Platform/Marvell/= OdysseyPkg/OdysseyPkg.fdf new file mode 100644 index 0000000000..b8822a0340 --- /dev/null +++ b/Platform/Marvell/OdysseyPkg/OdysseyPkg.fdf @@ -0,0 +1,304 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# The main Flash Description File for OdysseyPkg. +#**/ + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.ODYSSEY_AARCH64_EFI] # Name must match with FV_PREFIX from bootloader= /uefi/Makefile +BaseAddress =3D 0x04000000|gArmTokenSpaceGuid.PcdFdBaseAddress # UEFI i= n DRAM + 64MB. +Size =3D 0x01000000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the device (16MiB). +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x1000 + +# 2.5 M should be enough for all modules +0x00000000|0x00820000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +BlockSize =3D 0x40 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 16 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D d248e9b7-9ce3-43a7-868e-70c17c4b3819 + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf # gEfi= PcdProtocolGuid + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf # gHar= dwareInterruptProtocolGuid + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf # gEfi= CpuArchProtocolGuid + } + + # + # Core DXE modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf # (in OdysseyPkg.dsc.inc) + + # + # DXE Status codes + # +!if $(DEBUG) =3D=3D 1 + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatu= sCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandle= rRuntimeDxe.inf +!endif + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConf= igDxe.inf +!endif + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu= ntimeDxe.inf + INF Silicon/Marvell/Drivers/Wdt/GtiWatchdogDxe/GtiWatchdogDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + # Produces gEfiFaultTolerantWriteProtocolGuid needed for non-volatile UE= FI variable storage. + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf + + # RTC Support + INF Silicon/Marvell/Drivers/Null/RtcNull/RtcNullDxe.inf + + # + # ARM Support + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe= .inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + # FV Filesystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.i= nf + + # SectionExtraction + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + + # + # FDT support + # + # The UEFI driver is at the end of the list of the driver to be dispatch= ed + # after the device drivers (eg: Ethernet) to ensure we have support for = them. + INF Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf + INF Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + # + # SEC Phase modules + # + INF Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf + + # + # PEI Phase modules + # + # PEI phase is skipped. SEC jumps directly to DXE. + + # + # DXE Phase modules stored in separate LZMA compressed FV. + # + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec b/Sili= con/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec index 1e17152f13..0fb46d1330 100644 --- a/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec +++ b/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec @@ -42,6 +42,8 @@ # that depend on the lowlevel platform initialization having been comple= ted gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } =20 + gFdtClientProtocolGuid =3D { 0xE11FACA0, 0x4710, 0x4C8E, { 0xA7, 0xA2, 0= x01, 0xBA, 0xA2, 0x59, 0x1B, 0x4C } } + [PcdsFixedAtBuild.common] #Board description gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 @@ -198,6 +200,23 @@ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004 gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005 =20 +# FDT + # FDT configuration node to be stripped before passing to OS + gMarvellSiliconTokenSpaceGuid.PcdFdtConfigRootNode|"/marvell,ebf"|VOID*|= 0x50000090 + + gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase|0x10000000000|UINT64|0x000= 00004 + gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress|0x800000000000|UINT64|0x0= 0000005 + gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress|0x100000000000|UINT64= |0x00000006 + gMarvellSiliconTokenSpaceGuid.PcdIoSize|0xF0000000000|UINT64|0x00000007 + + gMarvellSiliconTokenSpaceGuid.PcdGtiWatchdogBase64|0x802000000000|UINT64= |0x00000008 + +[PcdsFeatureFlag.common] + # Publish FDT to the OS as Configuration Table with gFdtTableGuid + gMarvellSiliconTokenSpaceGuid.PcdPublishFdt|FALSE|BOOLEAN|0x50000091 + # Fixup the FDT or not (taken into consideration only when PcdPublishFdt= =3D TRUE) + gMarvellSiliconTokenSpaceGuid.PcdFixupFdt|TRUE|BOOLEAN|0x50000092 + [Protocols] gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} diff --git a/Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc b/Silicon/Marvel= l/OdysseyPkg/OdysseyPkg.dsc.inc new file mode 100644 index 0000000000..1c69ca8696 --- /dev/null +++ b/Silicon/Marvell/OdysseyPkg/OdysseyPkg.dsc.inc @@ -0,0 +1,394 @@ +#/** @file +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# https://spdx.org/licenses +# +# Copyright (C) 2023 Marvell +# +# DSC include file for OdysseyPkg. +# +# This file can be included to platform DSC file +# by using "!include OdysseyPkg.dsc.inc" // path relative to platform DSC= file. +# +#**/ + +[Defines] + SECURE_BOOT_ENABLE =3D FALSE + MIN_IMAGE =3D FALSE + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + +[LibraryClasses.common] +!if $(TARGET) =3D=3D RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf + + # + # Assume everything is fixed at build + # + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf +#!if $(MIN_IMAGE) =3D=3D FALSE + # Networking Requirements + DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf + UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf +#!endif + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/Def= aultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.= inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + + # Boot manager + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf + + # Silicon Specific Libraries + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + # ARM PL011 UART Library + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartCloc= kLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The S= tandard IO window + # in the debugger will show load and unload commands for symbols. You ca= n cut and paste this + # into the command window to load symbols. We should be able to use a sc= ript to do this, but + # the version of RVD I have does not support scripts accessing system me= mory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffEx= traActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePe= CoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgent= TimerLibNull.inf + + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + # RunAxf support via Dynamic Shell Command protocol + # It uses the Shell libraries. + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tr= ee + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + + # Platform Support Libraries + SmcLib|Silicon/Marvell/Library/SmcLib/SmcLib.inf + +[LibraryClasses.common.SEC] + + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib= /PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCusto= mDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe= moryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.= inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + # ARM PL011 UART Runtime Library + #SerialPortLib|Silicon/Marvell/Library/PL011SerialPortRuntimeLib/PL011Se= rialPortRuntimeLib.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf +!endif + +[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER] + # + # PSCI support in EL3 may not be available if we are not running under a= PSCI + # compliant secure firmware, but since the default VExpress EfiResetSyst= emLib + # cannot be supported at runtime (due to the fact that the syscfg MMIO r= egisters + # cannot be runtime remapped), it is our best bet to get ResetSystem fun= ctionality + # on these platforms. + # + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSyste= mLib.inf + +[LibraryClasses.ARM, LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. + # This library provides the instrinsic functions generate by a given com= piler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM imag= es. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + +[BuildOptions] + RVCT:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsFeatureFlag.common] + + # Use the Vector Table location in CpuDxe. We will not copy the Vector T= able at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER= )" +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"MARVELL UEFI 5= .0.0" +!endif + +!ifdef $(RELEASE_DATE) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"$(RELEASE_= DATE)" +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"2022" +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 # BIT0 - = Enable Performance Measurement. + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Verbose + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80304FCF + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # RunAxf support via Dynamic Shell Command protocol + # We want to use the Shell Libraries but do not want it to initialise + # automatically. We initialise the libraries when the command is called = by the + # Shell. + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + # Define PcdBootManagerMenuFile as FILE_GUID of bootloader/uefi/MdeModul= ePkg/Application/UiApp/UiApp.inf + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # Max capsule size + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1400000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizePopulateCapsule|0x1400000 + + # Use MPIDR Affinity Level 2 to identify the PrimaryCore + # Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 1= 6 (Iliad) + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xFF0000 + +[PcdsDynamicHii.common.DEFAULT] +!if $(MIN_IMAGE) =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 +!endif + +[Components.common] + + # FV Filesystem + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # SectionExtraction + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf { + + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/Dx= eExtractGuidedSectionLib.inf + } + + # + # FDT support + # + Silicon/Marvell/Drivers/Fdt/FdtPlatformDxe/FdtPlatformDxe.inf + Silicon/Marvell/Drivers/Fdt/FdtClientDxe/FdtClientDxe.inf + + # No EMMC/SD Interface + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + } + + ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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