From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112593+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112593+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634122; cv=none; d=zohomail.com; s=zohoarc; b=GN8VOXmKMhl36kBT8aJAg6UCIKJCPEqcQv4r8VabthI2/z6GW04ieJIjHWROHqGYxBzizJHQatet6BSPitjp1T9QwV3RfojFOK5W8+2ITeB+NK9kThpPDh9Ca7BbCyei+lJhM9T/adrland9sanaqhkS3LWCfAZcfU5w1uJOsB4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634122; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=u+7iVnDRODjy0cvyERkxMI5a/pCAooGq25xF7WqkpQk=; b=dLaYsogXPoFVvoXyLBX/LhM63plFatPmE3j5QYEW13P+Vd+O41LIHNpzNZmPW+CiRvd7eTT+ih2PlFzr3nOUCieZcTfqTxtTG83Zw4q448Nu0p0sePfSAA+TMoUeLcwjw8lCQiBfc1lWClbl1+ynoYcbgwxJyzqsYcfX16gzygs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112593+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634122892461.319410530691; Fri, 15 Dec 2023 01:55:22 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=Qe7nmvQ/H1yuBARXelOV2E3+gPtYzXmW60kVUQqPdeM=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634122; v=1; b=dwI/yhnlucLzjp14fDi61T6gwbZPdhNJqX3Bxrm204FAeT3L2GmscN5GDdXvbniyMeiDPqUU WupxTHOUMeg6wnrWoCLVYS4t5Emm/7Xi1+wAttAzCjk3CZFM8GpTZT4g8MdZUAYIjUd8qhIz8aC lxCB6Q1FLiyBiK5pXBT0ZUL8= X-Received: by 127.0.0.2 with SMTP id XBE8YY1788612xQicZmJ0Dpc; Fri, 15 Dec 2023 01:55:22 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:22 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343073" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343073" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884237" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884237" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:19 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v4 1/8] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize Semaphore Sync between BSP and AP Date: Fri, 15 Dec 2023 17:55:08 +0800 Message-Id: <20231215095515.9484-2-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: jaBWo4Qn5xvIINl1nmzBS1jWx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634124730100005 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to define 3 new functions (WaitForBsp & ReleaseBsp & ReleaseOneAp) used for the semaphore sync between BSP & AP. With the change, BSP and AP Sync flow will be easy understand as below: BSP: ReleaseAllAPs or ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAllAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu Reviewed-by: Laszlo Ersek Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 72 ++++++++++++++++++++++++++++---= ---- 1 file changed, 58 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index b279f5dfcc..54542262a2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -120,10 +120,11 @@ LockdownSemaphore ( =20 return Value; } =20 /** + Used for BSP to wait all APs. Wait all APs to performs an atomic compare exchange operation to release= semaphore. =20 @param NumberOfAPs AP number =20 **/ @@ -139,10 +140,11 @@ WaitForAllAPs ( WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); } } =20 /** + Used for BSP to release all APs. Performs an atomic compare exchange operation to release semaphore for each AP. =20 **/ VOID @@ -157,10 +159,52 @@ ReleaseAllAPs ( ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); } } } =20 +/** + Used for BSP to release one AP. + + @param ApSem IN: 32-bit unsigned integer + OUT: original integer + 1 +**/ +VOID +ReleaseOneAp ( + IN OUT volatile UINT32 *ApSem + ) +{ + ReleaseSemaphore (ApSem); +} + +/** + Used for AP to wait BSP. + + @param ApSem IN: 32-bit unsigned integer + OUT: original integer - 1 +**/ +VOID +WaitForBsp ( + IN OUT volatile UINT32 *ApSem + ) +{ + WaitForSemaphore (ApSem); +} + +/** + Used for AP to release BSP. + + @param BspSem IN: 32-bit unsigned integer + OUT: original integer + 1 +**/ +VOID +ReleaseBsp ( + IN OUT volatile UINT32 *BspSem + ) +{ + ReleaseSemaphore (BspSem); +} + /** Check whether the index of CPU perform the package level register programming during System Management Mode initialization. =20 The index of Processor specified by mPackageFirstThreadIndex[PackageInde= x] @@ -632,11 +676,11 @@ BSPHandler ( // Signal all APs it's time for backup MTRRs // ReleaseAllAPs (); =20 // - // WaitForSemaphore() may wait for ever if an AP happens to enter SM= M at + // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // Note: For HT capable CPUs, threads within a core share the same s= et of MTRRs. // We do the backup first and then set MTRR to avoid race condition = for threads // in the same core. @@ -652,11 +696,11 @@ BSPHandler ( // Let all processors program SMM MTRRs together // ReleaseAllAPs (); =20 // - // WaitForSemaphore() may wait for ever if an AP happens to enter SM= M at + // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // ReplaceOSMtrrs (CpuIndex); =20 @@ -898,50 +942,50 @@ APHandler ( =20 if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfi= gureMtrrs ()) { // // Notify BSP of arrival at this point // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Backup OS MTRRs // MtrrGetAllMtrrs (&Mtrrs); =20 // // Signal BSP the completion of this AP // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for BSP's signal to program MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Replace OS MTRRs with SMI MTRRs // ReplaceOSMtrrs (CpuIndex); =20 // // Signal BSP the completion of this AP // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 while (TRUE) { // // Wait for something to happen // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Check if BSP wants to exit SMM // if (!(*mSmmMpSyncData->InsideSmm)) { @@ -977,16 +1021,16 @@ APHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for the signal from BSP to program MTRRs // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); @@ -994,26 +1038,26 @@ APHandler ( } =20 // // Notify BSP the readiness of this AP to Reset states/semaphore for thi= s processor // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); =20 // // Wait for the signal from BSP to Reset states/semaphore for this proce= ssor // - WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; =20 // // Notify BSP the readiness of this AP to exit SMM // - ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); + ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); } =20 /** Checks whether the input token is the current used token. =20 @@ -1277,11 +1321,11 @@ InternalSmmStartupThisAp ( mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; } =20 - ReleaseSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run); + ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); =20 if (Token =3D=3D NULL) { AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112593): https://edk2.groups.io/g/devel/message/112593 Mute This Topic: https://groups.io/mt/103187891/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112594+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112594+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634125; cv=none; d=zohomail.com; s=zohoarc; b=NoaQj7eolwCWGKhfSrCx/o2sxtxrtoMxrM8vy9Rs4ywf1qAKPja8Yo44usa5eyl6X2BJvLXu+L9XTLvK4caSIei75t/h0JmJ/NxVXNoB17v2oh25eQUYAaUFCNFOjZLMKzw//Pm6FX+9D3fI3jhG/opwhlaRthzXE3De2aaaYdQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634125; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=3tIsCn7HPMzGGR5FnEw3MBXQbSQBQkqiXvsJNrKTZN4=; b=mYE/SlD7GKDDHSIHa4kIPAqmK72T33gxr7RKcVWeP2T+a2XnkEzVNamek1MlCCZvSTRgst6rzuIPcP+oN0z9Z9iu+w9CyDpk3yNbcHu7kv7rpCXWchX7OZN+ybdyr2LVGq5vTvsB0ON7r5EMCnyQO4ZTdjH5+FkOJ3ERjzWn51Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112594+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634125176252.65148948556146; Fri, 15 Dec 2023 01:55:25 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=DJuWRMeswbKl2sw034rukF8Llhj1I+31A6KGXjaaT5c=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634124; v=1; b=fIerq50DdfxjNe0GFNB1uxSfU/OVc5xsGa9HrHgz9eetxIouUy9Shkn9m285rMDD5CTkaL9i d6KOx7MKlzli55Q4T2ypAXMzfbyEozpgZxgyeZeQ3ueJNrxlazoNr93sueQlA63e2c+G1MYc4o2 Ou25NjDKolVIq2ahriA7q+qo= X-Received: by 127.0.0.2 with SMTP id YKVzYY1788612xrD9gZDTWqA; Fri, 15 Dec 2023 01:55:24 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:24 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343077" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343077" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884252" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884252" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:22 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v4 2/8] UefiCpuPkg: Adds SmmCpuSyncLib library class Date: Fri, 15 Dec 2023 17:55:09 +0800 Message-Id: <20231215095515.9484-3-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: oqFu6sIXIUk6AFrr00BzeBLZx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634126589100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. For the new SmmCpuSyncLib, it provides 3 sets of APIs: 1. ContextInit/ContextDeinit/ContextReset: ContextInit() is called in driver's entrypoint to allocate and initialize the SMM CPU Sync context. ContextDeinit() is called in driver's unload function to deinitialize SMM CPU Sync context. ContextReset() is called before CPU exist SMI, which allows CPU to check into the next SMI from this point. 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: When SMI happens, all processors including BSP enter to SMM mode by calling CheckInCpu(). The elected BSP calls LockDoor() so that CheckInCpu() will return the error code after that. CheckOutCpu() can be called in error handling flow for the CPU who calls CheckInCpu() earlier. GetArrivedCpuCount() returns the number of checked-in CPUs. 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of APs and release one specific AP. WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. The 4 APIs are used to synchronize the running flow among BSP and APs. BSP and AP Sync flow can be easy understand as below: BSP: ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- UefiCpuPkg/Include/Library/SmmCpuSyncLib.h | 290 +++++++++++++++++++++++++= ++++ UefiCpuPkg/UefiCpuPkg.dec | 3 + 2 files changed, 293 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/SmmCpuSyncLib.h diff --git a/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h b/UefiCpuPkg/Includ= e/Library/SmmCpuSyncLib.h new file mode 100644 index 0000000000..4d273095c9 --- /dev/null +++ b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h @@ -0,0 +1,290 @@ +/** @file + Library that provides SMM CPU Sync related operations. + + The lib provides 3 sets of APIs: + 1. ContextInit/ContextDeinit/ContextReset: + + ContextInit() is called in driver's entrypoint to allocate and initial= ize the SMM CPU Sync context. + ContextDeinit() is called in driver's unload function to deinitialize = the SMM CPU Sync context. + ContextReset() is called by one of CPUs after all CPUs are ready to ex= it SMI, which allows CPU to + check into the next SMI from this point. + + 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: + When SMI happens, all processors including BSP enter to SMM mode by ca= lling CheckInCpu(). + CheckOutCpu() can be called in error handling flow for the CPU who cal= ls CheckInCpu() earlier. + The elected BSP calls LockDoor() so that CheckInCpu() and CheckOutCpu(= ) will return the error code after that. + GetArrivedCpuCount() returns the number of checked-in CPUs. + + 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp + WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number o= f APs and release one specific AP. + WaitForBsp() & ReleaseBsp() are called from APs to wait and release BS= P. + The 4 APIs are used to synchronize the running flow among BSP and APs. + BSP and AP Sync flow can be easy understand as below: + BSP: ReleaseOneAp --> AP: WaitForBsp + BSP: WaitForAPs <-- AP: ReleaseBsp + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_CPU_SYNC_LIB_H_ +#define SMM_CPU_SYNC_LIB_H_ + +#include + +// +// Opaque structure for SMM CPU Sync context. +// +typedef struct SMM_CPU_SYNC_CONTEXT SMM_CPU_SYNC_CONTEXT; + +/** + Create and initialize the SMM CPU Sync context. It is to allocate and in= itialize the + SMM CPU Sync context. + + If Context is NULL, then ASSERT(). + + @param[in] NumberOfCpus The number of Logical Processors in th= e system. + @param[out] Context Pointer to the new created and initial= ized SMM CPU Sync context object. + NULL will be returned if any error hap= pen during init. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l created and initialized. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availab= le to create and initialize SMM CPU Sync context. + @retval RETURN_BUFFER_TOO_SMALL Overflow happen + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus, + OUT SMM_CPU_SYNC_CONTEXT **Context + ); + +/** + Deinit an allocated SMM CPU Sync context. The resources allocated in Smm= CpuSyncContextInit() will + be freed. + + If Context is NULL, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context object t= o be deinitialized. + +**/ +VOID +EFIAPI +SmmCpuSyncContextDeinit ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context + ); + +/** + Reset SMM CPU Sync context. SMM CPU Sync context will be reset to the in= itialized state. + + This function is called by one of CPUs after all CPUs are ready to exit = SMI, which allows CPU to + check into the next SMI from this point. + + If Context is NULL, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context object t= o be reset. + +**/ +VOID +EFIAPI +SmmCpuSyncContextReset ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context + ); + +/** + Get current number of arrived CPU in SMI. + + BSP might need to know the current number of arrived CPU in SMI to make = sure all APs + in SMI. This API can be for that purpose. + + If Context is NULL, then ASSERT(). + + @param[in] Context Pointer to the SMM CPU Sync context object. + + @retval Current number of arrived CPU in SMI. + +**/ +UINTN +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN SMM_CPU_SYNC_CONTEXT *Context + ); + +/** + Performs an atomic operation to check in CPU. + + When SMI happens, all processors including BSP enter to SMM mode by call= ing SmmCpuSyncCheckInCpu(). + + If Context is NULL, then ASSERT(). + If CpuIndex exceeds the range of all CPUs in the system, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check in CPU index. + + @retval RETURN_SUCCESS Check in CPU (CpuIndex) successfully. + @retval RETURN_ABORTED Check in CPU failed due to SmmCpuSyncL= ockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckInCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation to check out CPU. + + This function can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + The caller shall make sure the CPU specified by CpuIndex has already che= cked-in. + + If Context is NULL, then ASSERT(). + If CpuIndex exceeds the range of all CPUs in the system, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check out CPU index. + + @retval RETURN_SUCCESS Check out CPU (CpuIndex) successfully. + @retval RETURN_ABORTED Check out CPU failed due to SmmCpuSync= LockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation lock door for CPU checkin and checkout. Aft= er this function: + CPU can not check in via SmmCpuSyncCheckInCpu(). + CPU can not check out via SmmCpuSyncCheckOutCpu(). + + The CPU specified by CpuIndex is elected to lock door. The caller shall = make sure the CpuIndex + is the actual CPU calling this function to avoid the undefined behavior. + + If Context is NULL, then ASSERT(). + If CpuCount is NULL, then ASSERT(). + If CpuIndex exceeds the range of all CPUs in the system, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which CPU to lock door. + @param[out] CpuCount Number of arrived CPU in SMI after loo= k door. + +**/ +VOID +EFIAPI +SmmCpuSyncLockDoor ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + OUT UINTN *CpuCount + ); + +/** + Used by the BSP to wait for APs. + + The number of APs need to be waited is specified by NumberOfAPs. The BSP= is specified by BspIndex. + The caller shall make sure the BspIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The caller shall make sure the NumberOfAPs have already checked-in to av= oid the undefined behavior. + + If Context is NULL, then ASSERT(). + If NumberOfAPs >=3D All CPUs in system, then ASSERT(). + If BspIndex exceeds the range of all CPUs in the system, then ASSERT(). + + Note: + This function is blocking mode, and it will return only after the number= of APs released by + calling SmmCpuSyncReleaseBsp(): + BSP: WaitForAPs <-- AP: ReleaseBsp + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] NumberOfAPs Number of APs need to be waited by BSP. + @param[in] BspIndex The BSP Index to wait for APs. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForAPs ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ); + +/** + Used by the BSP to release one AP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + The caller shall make sure the BspIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The caller shall make sure the CpuIndex has already checked-in to avoid = the undefined behavior. + + If Context is NULL, then ASSERT(). + If CpuIndex =3D=3D BspIndex, then ASSERT(). + If BspIndex or CpuIndex exceed the range of all CPUs in the system, then= ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP need to be released. + @param[in] BspIndex The BSP Index to release AP. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used by the AP to wait BSP. + + The AP is specified by CpuIndex. + The caller shall make sure the CpuIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The BSP is specified by BspIndex. + + If Context is NULL, then ASSERT(). + If CpuIndex =3D=3D BspIndex, then ASSERT(). + If BspIndex or CpuIndex exceed the range of all CPUs in the system, then= ASSERT(). + + Note: + This function is blocking mode, and it will return only after the AP rel= eased by + calling SmmCpuSyncReleaseOneAp(): + BSP: ReleaseOneAp --> AP: WaitForBsp + + @param[in,out] Context Pointer to the SMM CPU Sync context obj= ect. + @param[in] CpuIndex Indicate which AP wait BSP. + @param[in] BspIndex The BSP Index to be waited. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used by the AP to release BSP. + + The AP is specified by CpuIndex. + The caller shall make sure the CpuIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The BSP is specified by BspIndex. + + If Context is NULL, then ASSERT(). + If CpuIndex =3D=3D BspIndex, then ASSERT(). + If BspIndex or CpuIndex exceed the range of all CPUs in the system, then= ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP release BSP. + @param[in] BspIndex The BSP Index to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 61bd34ef17..cc785a3222 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -62,10 +62,13 @@ CpuPageTableLib|Include/Library/CpuPageTableLib.h =20 ## @libraryclass Provides functions for manipulating smram savestate r= egisters. MmSaveStateLib|Include/Library/MmSaveStateLib.h =20 + ## @libraryclass Provides functions for SMM CPU Sync Operation. + SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h + [LibraryClasses.RISCV64] ## @libraryclass Provides functions to manage MMU features on RISCV64 = CPUs. ## RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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a="750884266" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884266" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:24 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v4 3/8] MdePkg/MdeLibs.dsc.inc: Add SafeIntLib instance Date: Fri, 15 Dec 2023 17:55:10 +0800 Message-Id: <20231215095515.9484-4-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 9JRWe9p9wq7wspv4PaEC4240x1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634128544100013 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to add SafeIntLib in MdeLibs.dsc.inc Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu Reviewed-by: Michael D Kinney --- MdePkg/MdeLibs.dsc.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/MdePkg/MdeLibs.dsc.inc b/MdePkg/MdeLibs.dsc.inc index 4580481cb5..deb35c1a18 100644 --- a/MdePkg/MdeLibs.dsc.inc +++ b/MdePkg/MdeLibs.dsc.inc @@ -14,5 +14,6 @@ [LibraryClasses] ArmTrngLib|MdePkg/Library/BaseArmTrngLibNull/BaseArmTrngLibNull.inf RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLib= Null.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf SmmCpuRendezvousLib|MdePkg/Library/SmmCpuRendezvousLibNull/SmmCpuRendezv= ousLibNull.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112595): https://edk2.groups.io/g/devel/message/112595 Mute This Topic: https://groups.io/mt/103187893/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112596+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112596+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634129; cv=none; d=zohomail.com; s=zohoarc; b=XL7Dpucam5WMUbIluk4PA4NuIAfzR/lDDLY3CobUFHUwn1o/FmSYB43dgR26/4HVa2WBm/cSor94mq4odjPhfQlomdBMd7DxZARVwB4jeVVx3KbTBnyG+JUnFhXNGNa9TiTyaG/nVGcsJ6ssjmcSa1XM8C7Of1+2o61lQceKAbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634129; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8AhVyi6dhbpWkn5eufGC0St2/MCsz0VEreko9BJTI2U=; b=htPTR8SIP+0uWnwSJqOpyMLaf2S+efyrlvENRBHBZqinZ7jpckQJIZfmIdXmDYgxcCuMnI6ycHEW96ra5m0Pd7Iu3ODI2D/iNI8GwB5BZVrv4gLmLnrNownYFtaDf8F59i2BkI3UJWZtGL61NUDaVO4ubE63VwOpYZmwaiEbLYA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112596+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634129652956.812065900622; Fri, 15 Dec 2023 01:55:29 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=KhL/eXwH11SgFq0POD7r7sKJ0oW9ecQP1KaJwWbVxPA=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634129; v=1; b=jEN9VstxA+0CU2CUaEXbq7z7i1jIIWPVL7S/FpdpieBlDYse4aWJeuzvNTRpv//BHDjgqom2 5FJ7ElffqvEU4dQgqg7hCky01DgJW9d+R58DTY7ZaS2fUWCfjqc+Lq0bywc6WZIrOCR0s7bZ6cR ruPKnZVpJMytY3UOBIitBxPg= X-Received: by 127.0.0.2 with SMTP id N9yaYY1788612xDEqEvv2F7E; Fri, 15 Dec 2023 01:55:29 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:28 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343094" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343094" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884282" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884282" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:26 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v4 4/8] UefiCpuPkg: Implements SmmCpuSyncLib library instance Date: Fri, 15 Dec 2023 17:55:11 +0800 Message-Id: <20231215095515.9484-5-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: B2RnDgHaBDdOOhLBD47oH47gx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634130617100017 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implements SmmCpuSyncLib Library instance. The instance refers the existing SMM CPU driver (PiSmmCpuDxeSmm) sync implementation and behavior: 1.Abstract Counter and Run semaphores into SmmCpuSyncCtx. 2.Abstract CPU arrival count operation to SmmCpuSyncGetArrivedCpuCount(), SmmCpuSyncCheckInCpu(), SmmCpuSyncCheckOutCpu(), SmmCpuSyncLockDoor(). Implementation is aligned with existing SMM CPU driver. 3. Abstract SMM CPU Sync flow to: BSP: SmmCpuSyncReleaseOneAp --> AP: SmmCpuSyncWaitForBsp BSP: SmmCpuSyncWaitForAPs <-- AP: SmmCpuSyncReleaseBsp Semaphores release & wait during sync flow is same as existing SMM CPU driver. 4.Same operation to Counter and Run semaphores by leverage the atomic compare exchange. Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c | 651 +++++++++++++++++= ++++ UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf | 34 ++ UefiCpuPkg/UefiCpuPkg.dsc | 2 + 3 files changed, 687 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c b/UefiCpuPkg/= Library/SmmCpuSyncLib/SmmCpuSyncLib.c new file mode 100644 index 0000000000..1d03a4e95b --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c @@ -0,0 +1,651 @@ +/** @file + SMM CPU Sync lib implementation. + + The lib provides 3 sets of APIs: + 1. ContextInit/ContextDeinit/ContextReset: + + ContextInit() is called in driver's entrypoint to allocate and initial= ize the SMM CPU Sync context. + ContextDeinit() is called in driver's unload function to deinitialize = the SMM CPU Sync context. + ContextReset() is called by one of CPUs after all CPUs are ready to ex= it SMI, which allows CPU to + check into the next SMI from this point. + + 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: + When SMI happens, all processors including BSP enter to SMM mode by ca= lling CheckInCpu(). + CheckOutCpu() can be called in error handling flow for the CPU who cal= ls CheckInCpu() earlier. + The elected BSP calls LockDoor() so that CheckInCpu() and CheckOutCpu(= ) will return the error code after that. + GetArrivedCpuCount() returns the number of checked-in CPUs. + + 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp + WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number o= f APs and release one specific AP. + WaitForBsp() & ReleaseBsp() are called from APs to wait and release BS= P. + The 4 APIs are used to synchronize the running flow among BSP and APs. + BSP and AP Sync flow can be easy understand as below: + BSP: ReleaseOneAp --> AP: WaitForBsp + BSP: WaitForAPs <-- AP: ReleaseBsp + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include + +/// +/// The implementation shall place one semaphore on exclusive cache line f= or good performance. +/// +typedef volatile UINT32 SMM_CPU_SYNC_SEMAPHORE; + +typedef struct { + /// + /// Used for control each CPU continue run or wait for signal + /// + SMM_CPU_SYNC_SEMAPHORE *Run; +} SMM_CPU_SYNC_SEMAPHORE_FOR_EACH_CPU; + +struct SMM_CPU_SYNC_CONTEXT { + /// + /// Indicate all CPUs in the system. + /// + UINTN NumberOfCpus; + /// + /// Address of semaphores. + /// + VOID *SemBuffer; + /// + /// Size of semaphores. + /// + UINTN SemBufferPages; + /// + /// Indicate CPUs entered SMM after lock door. + /// + UINTN LockedCpuCount; + /// + /// Indicate CPUs entered SMM before lock door. + /// + SMM_CPU_SYNC_SEMAPHORE *CpuCount; + /// + /// Define an array of structure for each CPU semaphore due to the size = alignment + /// requirement. With the array of structure for each CPU semaphore, it'= s easy to + /// reach the specific CPU with CPU Index for its own semaphore access: = CpuSem[CpuIndex]. + /// + SMM_CPU_SYNC_SEMAPHORE_FOR_EACH_CPU CpuSem[]; +}; + +/** + Performs an atomic compare exchange operation to get semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param[in,out] Sem IN: 32-bit unsigned integer + OUT: original integer - 1 if Sem is not locked. + OUT: original integer if Sem is locked (MAX_UINT3= 2). + + @retval Original integer - 1 if Sem is not locked. + Original integer if Sem is locked (MAX_UINT32). + +**/ +STATIC +UINT32 +InternalWaitForSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + for ( ; ;) { + Value =3D *Sem; + if (Value =3D=3D MAX_UINT32) { + return Value; + } + + if ((Value !=3D 0) && + (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value - 1 + ) =3D=3D Value)) + { + break; + } + + CpuPause (); + } + + return Value - 1; +} + +/** + Performs an atomic compare exchange operation to release semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param[in,out] Sem IN: 32-bit unsigned integer + OUT: original integer + 1 if Sem is not locked. + OUT: original integer if Sem is locked (MAX_UINT3= 2). + + @retval Original integer + 1 if Sem is not locked. + Original integer if Sem is locked (MAX_UINT32). + +**/ +STATIC +UINT32 +InternalReleaseSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value =3D *Sem; + } while (Value + 1 !=3D 0 && + InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value + 1 + ) !=3D Value); + + if (Value =3D=3D MAX_UINT32) { + return Value; + } + + return Value + 1; +} + +/** + Performs an atomic compare exchange operation to lock semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param[in,out] Sem IN: 32-bit unsigned integer + OUT: -1 + + @retval Original integer + +**/ +STATIC +UINT32 +InternalLockdownSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value =3D *Sem; + } while (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + (UINT32)-1 + ) !=3D Value); + + return Value; +} + +/** + Create and initialize the SMM CPU Sync context. It is to allocate and in= itialize the + SMM CPU Sync context. + + If Context is NULL, then ASSERT(). + + @param[in] NumberOfCpus The number of Logical Processors in th= e system. + @param[out] Context Pointer to the new created and initial= ized SMM CPU Sync context object. + NULL will be returned if any error hap= pen during init. + + @retval RETURN_SUCCESS The SMM CPU Sync context was successfu= l created and initialized. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availab= le to create and initialize SMM CPU Sync context. + @retval RETURN_BUFFER_TOO_SMALL Overflow happen + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus, + OUT SMM_CPU_SYNC_CONTEXT **Context + ) +{ + RETURN_STATUS Status; + UINTN ContextSize; + UINTN CacheLineSize; + UINTN OneSemSize; + UINTN NumSem; + UINTN TotalSemSize; + UINTN SemAddr; + UINTN CpuIndex; + SMM_CPU_SYNC_SEMAPHORE_FOR_EACH_CPU *CpuSem; + + ASSERT (Context !=3D NULL); + + // + // Calculate ContextSize + // + Status =3D SafeUintnMult (NumberOfCpus, sizeof (SMM_CPU_SYNC_SEMAPHORE_F= OR_EACH_CPU), &ContextSize); + if (RETURN_ERROR (Status)) { + return Status; + } + + Status =3D SafeUintnAdd (ContextSize, sizeof (SMM_CPU_SYNC_CONTEXT), &Co= ntextSize); + if (RETURN_ERROR (Status)) { + return Status; + } + + // + // Allocate Buffer for Context + // + *Context =3D AllocatePool (ContextSize); + if (*Context =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + + (*Context)->LockedCpuCount =3D 0; + + // + // Save NumberOfCpus + // + (*Context)->NumberOfCpus =3D NumberOfCpus; + + // + // Calculate total semaphore size + // + CacheLineSize =3D GetSpinLockProperties (); + OneSemSize =3D ALIGN_VALUE (sizeof (SMM_CPU_SYNC_SEMAPHORE), CacheLin= eSize); + + Status =3D SafeUintnAdd (1, NumberOfCpus, &NumSem); + if (RETURN_ERROR (Status)) { + goto ON_ERROR; + } + + Status =3D SafeUintnMult (NumSem, OneSemSize, &TotalSemSize); + if (RETURN_ERROR (Status)) { + goto ON_ERROR; + } + + // + // Allocate for Semaphores in the *Context + // + (*Context)->SemBufferPages =3D EFI_SIZE_TO_PAGES (TotalSemSize); + (*Context)->SemBuffer =3D AllocatePages ((*Context)->SemBufferPages= ); + if ((*Context)->SemBuffer =3D=3D NULL) { + Status =3D RETURN_OUT_OF_RESOURCES; + goto ON_ERROR; + } + + // + // Assign Global Semaphore pointer + // + SemAddr =3D (UINTN)(*Context)->SemBuffer; + (*Context)->CpuCount =3D (SMM_CPU_SYNC_SEMAPHORE *)SemAddr; + *(*Context)->CpuCount =3D 0; + + SemAddr +=3D OneSemSize; + + // + // Assign CPU Semaphore pointer + // + CpuSem =3D (*Context)->CpuSem; + for (CpuIndex =3D 0; CpuIndex < NumberOfCpus; CpuIndex++) { + CpuSem->Run =3D (SMM_CPU_SYNC_SEMAPHORE *)SemAddr; + *CpuSem->Run =3D 0; + + CpuSem++; + SemAddr +=3D OneSemSize; + } + + return RETURN_SUCCESS; + +ON_ERROR: + FreePool (*Context); + return Status; +} + +/** + Deinit an allocated SMM CPU Sync context. The resources allocated in Smm= CpuSyncContextInit() will + be freed. + + If Context is NULL, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context object t= o be deinitialized. + +**/ +VOID +EFIAPI +SmmCpuSyncContextDeinit ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context + ) +{ + ASSERT (Context !=3D NULL); + + FreePages (Context->SemBuffer, Context->SemBufferPages); + + FreePool (Context); +} + +/** + Reset SMM CPU Sync context. SMM CPU Sync context will be reset to the in= itialized state. + + This function is called by one of CPUs after all CPUs are ready to exit = SMI, which allows CPU to + check into the next SMI from this point. + + If Context is NULL, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context object t= o be reset. + +**/ +VOID +EFIAPI +SmmCpuSyncContextReset ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context + ) +{ + ASSERT (Context !=3D NULL); + + Context->LockedCpuCount =3D 0; + *Context->CpuCount =3D 0; +} + +/** + Get current number of arrived CPU in SMI. + + BSP might need to know the current number of arrived CPU in SMI to make = sure all APs + in SMI. This API can be for that purpose. + + If Context is NULL, then ASSERT(). + + @param[in] Context Pointer to the SMM CPU Sync context object. + + @retval Current number of arrived CPU in SMI. + +**/ +UINTN +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN SMM_CPU_SYNC_CONTEXT *Context + ) +{ + UINT32 Value; + + ASSERT (Context !=3D NULL); + + Value =3D *Context->CpuCount; + + if (Value =3D=3D (UINT32)-1) { + return Context->LockedCpuCount; + } + + return Value; +} + +/** + Performs an atomic operation to check in CPU. + + When SMI happens, all processors including BSP enter to SMM mode by call= ing SmmCpuSyncCheckInCpu(). + + If Context is NULL, then ASSERT(). + If CpuIndex exceeds the range of all CPUs in the system, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check in CPU index. + + @retval RETURN_SUCCESS Check in CPU (CpuIndex) successfully. + @retval RETURN_ABORTED Check in CPU failed due to SmmCpuSyncL= ockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckInCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex + ) +{ + ASSERT (Context !=3D NULL); + + ASSERT (CpuIndex < Context->NumberOfCpus); + + // + // Check to return if CpuCount has already been locked. + // + if (InternalReleaseSemaphore (Context->CpuCount) =3D=3D MAX_UINT32) { + return RETURN_ABORTED; + } + + return RETURN_SUCCESS; +} + +/** + Performs an atomic operation to check out CPU. + + This function can be called in error handling flow for the CPU who calls= CheckInCpu() earlier. + The caller shall make sure the CPU specified by CpuIndex has already che= cked-in. + + If Context is NULL, then ASSERT(). + If CpuIndex exceeds the range of all CPUs in the system, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Check out CPU index. + + @retval RETURN_SUCCESS Check out CPU (CpuIndex) successfully. + @retval RETURN_ABORTED Check out CPU failed due to SmmCpuSync= LockDoor() has been called by one elected CPU. + +**/ +RETURN_STATUS +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex + ) +{ + ASSERT (Context !=3D NULL); + + ASSERT (CpuIndex < Context->NumberOfCpus); + + if (InternalWaitForSemaphore (Context->CpuCount) =3D=3D MAX_UINT32) { + return RETURN_ABORTED; + } + + return RETURN_SUCCESS; +} + +/** + Performs an atomic operation lock door for CPU checkin and checkout. Aft= er this function: + CPU can not check in via SmmCpuSyncCheckInCpu(). + CPU can not check out via SmmCpuSyncCheckOutCpu(). + + The CPU specified by CpuIndex is elected to lock door. The caller shall = make sure the CpuIndex + is the actual CPU calling this function to avoid the undefined behavior. + + If Context is NULL, then ASSERT(). + If CpuCount is NULL, then ASSERT(). + If CpuIndex exceeds the range of all CPUs in the system, then ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which CPU to lock door. + @param[out] CpuCount Number of arrived CPU in SMI after loo= k door. + +**/ +VOID +EFIAPI +SmmCpuSyncLockDoor ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + OUT UINTN *CpuCount + ) +{ + ASSERT (Context !=3D NULL); + + ASSERT (CpuCount !=3D NULL); + + ASSERT (CpuIndex < Context->NumberOfCpus); + + // + // Temporarily record the CpuCount into the LockedCpuCount before lock d= oor. + // Recording before lock door is to avoid the Context->CpuCount is locke= d but possible + // Context->LockedCpuCount is not updated. + // + Context->LockedCpuCount =3D *Context->CpuCount; + + // + // Lock door operation + // + *CpuCount =3D InternalLockdownSemaphore (Context->CpuCount); + + // + // Update the LockedCpuCount + // + Context->LockedCpuCount =3D *CpuCount; +} + +/** + Used by the BSP to wait for APs. + + The number of APs need to be waited is specified by NumberOfAPs. The BSP= is specified by BspIndex. + The caller shall make sure the BspIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The caller shall make sure the NumberOfAPs have already checked-in to av= oid the undefined behavior. + + If Context is NULL, then ASSERT(). + If NumberOfAPs >=3D All CPUs in system, then ASSERT(). + If BspIndex exceeds the range of all CPUs in the system, then ASSERT(). + + Note: + This function is blocking mode, and it will return only after the number= of APs released by + calling SmmCpuSyncReleaseBsp(): + BSP: WaitForAPs <-- AP: ReleaseBsp + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] NumberOfAPs Number of APs need to be waited by BSP. + @param[in] BspIndex The BSP Index to wait for APs. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForAPs ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ) +{ + UINTN Arrived; + + ASSERT (Context !=3D NULL); + + ASSERT (NumberOfAPs < Context->NumberOfCpus); + + ASSERT (BspIndex < Context->NumberOfCpus); + + for (Arrived =3D 0; Arrived < NumberOfAPs; Arrived++) { + InternalWaitForSemaphore (Context->CpuSem[BspIndex].Run); + } +} + +/** + Used by the BSP to release one AP. + + The AP is specified by CpuIndex. The BSP is specified by BspIndex. + The caller shall make sure the BspIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The caller shall make sure the CpuIndex has already checked-in to avoid = the undefined behavior. + + If Context is NULL, then ASSERT(). + If CpuIndex =3D=3D BspIndex, then ASSERT(). + If BspIndex or CpuIndex exceed the range of all CPUs in the system, then= ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP need to be released. + @param[in] BspIndex The BSP Index to release AP. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + ASSERT (Context !=3D NULL); + + ASSERT (BspIndex !=3D CpuIndex); + + ASSERT (CpuIndex < Context->NumberOfCpus); + + ASSERT (BspIndex < Context->NumberOfCpus); + + InternalReleaseSemaphore (Context->CpuSem[CpuIndex].Run); +} + +/** + Used by the AP to wait BSP. + + The AP is specified by CpuIndex. + The caller shall make sure the CpuIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The BSP is specified by BspIndex. + + If Context is NULL, then ASSERT(). + If CpuIndex =3D=3D BspIndex, then ASSERT(). + If BspIndex or CpuIndex exceed the range of all CPUs in the system, then= ASSERT(). + + Note: + This function is blocking mode, and it will return only after the AP rel= eased by + calling SmmCpuSyncReleaseOneAp(): + BSP: ReleaseOneAp --> AP: WaitForBsp + + @param[in,out] Context Pointer to the SMM CPU Sync context obj= ect. + @param[in] CpuIndex Indicate which AP wait BSP. + @param[in] BspIndex The BSP Index to be waited. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + ASSERT (Context !=3D NULL); + + ASSERT (BspIndex !=3D CpuIndex); + + ASSERT (CpuIndex < Context->NumberOfCpus); + + ASSERT (BspIndex < Context->NumberOfCpus); + + InternalWaitForSemaphore (Context->CpuSem[CpuIndex].Run); +} + +/** + Used by the AP to release BSP. + + The AP is specified by CpuIndex. + The caller shall make sure the CpuIndex is the actual CPU calling this f= unction to avoid the undefined behavior. + The BSP is specified by BspIndex. + + If Context is NULL, then ASSERT(). + If CpuIndex =3D=3D BspIndex, then ASSERT(). + If BspIndex or CpuIndex exceed the range of all CPUs in the system, then= ASSERT(). + + @param[in,out] Context Pointer to the SMM CPU Sync context ob= ject. + @param[in] CpuIndex Indicate which AP release BSP. + @param[in] BspIndex The BSP Index to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseBsp ( + IN OUT SMM_CPU_SYNC_CONTEXT *Context, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + ASSERT (Context !=3D NULL); + + ASSERT (BspIndex !=3D CpuIndex); + + ASSERT (CpuIndex < Context->NumberOfCpus); + + ASSERT (BspIndex < Context->NumberOfCpus); + + InternalReleaseSemaphore (Context->CpuSem[BspIndex].Run); +} diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf b/UefiCpuPk= g/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf new file mode 100644 index 0000000000..6b0d49c30a --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf @@ -0,0 +1,34 @@ +## @file +# SMM CPU Synchronization lib. +# +# This is SMM CPU Synchronization lib used for SMM CPU sync operations. +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmmCpuSyncLib + FILE_GUID =3D 1ca1bc1a-16a4-46ef-956a-ca500fd3381f + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SmmCpuSyncLib|DXE_SMM_DRIVER + +[Sources] + SmmCpuSyncLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + MemoryAllocationLib + SafeIntLib + SynchronizationLib + +[Pcd] + +[Protocols] diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 074fd77461..28eed85bce 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -54,10 +54,11 @@ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCp= uPlatformHookLibNull.inf SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib= .inf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf CcExitLib|UefiCpuPkg/Library/CcExitLibNull/CcExitLibNull.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf @@ -154,10 +155,11 @@ UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.i= nf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf + UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf UefiCpuPkg/Library/CcExitLibNull/CcExitLibNull.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf UefiCpuPkg/SecCore/SecCore.inf UefiCpuPkg/SecCore/SecCoreNative.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112596): https://edk2.groups.io/g/devel/message/112596 Mute This Topic: https://groups.io/mt/103187894/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112597+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112597+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634132; cv=none; d=zohomail.com; s=zohoarc; b=OWa95HHv9r61dzVp9THS4/kHDZrjf4TNVW/iFazmvRj4d1+2PTEQyxIKMON7cfwd9T4mxLlOoEpHhbhl8Y4C+E4ShrSSwQKr4DPh+sGEq9cgJhuA24qxX52c0OtX4eimzNAa2Cpz0QkAHTBqAaos2ezmWAE8Hi/VQDxti+9K6q8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634132; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=SUXVJX/jCZmE3sZ/iKAsxr053Yg2TFkgToPml88fxsI=; b=JyCf2ZyivaugPGx4DreDd4XML0pC62O/gyDTi1v/PzMhxm++frVS9bHkjUJrD5aC7YfOVSxm75xm1zK88pRkobLJ7AZbZY2B5LQ4uenHFvrYOsn0S9qBZhfx5YHBVDQ5F9exOS9Xjmj/AyXupfe8Q2bmPTOQMLl8i72u4HH1I0U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112597+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634132605961.7868461412779; Fri, 15 Dec 2023 01:55:32 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=sm6Tk2WzLaB/9rOhJ10DAex+MgE3gvmDnlWJgWLBeA0=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634132; v=1; b=NNei4ZKXVIH/9BGw0aqwemn/zRdXIdRBxjo4Opt8eYovIdAROA3wYe+a2kt+6Ai6lkdcIliY 93p4I67ub68YU+pw6iZxQKkIaim+HcSLSCRVCDY/nWE3WnaVF+QCIfe4x5gbF/sxS2UlB9Azp0E ZWRmJCEkNKJAAvnXlFThVVg0= X-Received: by 127.0.0.2 with SMTP id YrQXYY1788612xzrP4tFKjKK; Fri, 15 Dec 2023 01:55:32 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:31 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343108" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343108" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884297" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884297" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:28 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Eric Dong , Ray Ni , Zeng Star , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v4 5/8] OvmfPkg: Specifies SmmCpuSyncLib instance Date: Fri, 15 Dec 2023 17:55:12 +0800 Message-Id: <20231215095515.9484-6-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: eSpawBPCMAXG1vk335ex8MR9x1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634134635100023 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to specify SmmCpuSyncLib instance for OvmfPkg. Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + 4 files changed, 4 insertions(+) diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 1660548e07..af594959a9 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -907,10 +907,11 @@ } UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmC= puPlatformHookLibQemu.inf SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLi= b.inf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf } =20 # # Variable driver stack (SMM) # diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 6e8488007c..28379961a7 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -952,10 +952,11 @@ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmC= puPlatformHookLibQemu.inf SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLi= b.inf MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.i= nf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf } =20 # # Variable driver stack (SMM) # diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 413ea71984..5e9eee628a 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -970,10 +970,11 @@ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmC= puPlatformHookLibQemu.inf SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLi= b.inf MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.i= nf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf } =20 # # Variable driver stack (SMM) # diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index f000092d70..bf4c7906c4 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -1040,10 +1040,11 @@ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmC= puPlatformHookLibQemu.inf SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLi= b.inf MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.i= nf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf } =20 # # Variable driver stack (SMM) # --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112597): https://edk2.groups.io/g/devel/message/112597 Mute This Topic: https://groups.io/mt/103187895/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112598+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112598+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634134; cv=none; d=zohomail.com; s=zohoarc; b=Nj9TNETMG9k+VvFO0quQUU/yZPcbAiUcx1IzDGXGdAXDqrlblnASUHYYAFt65tyErJHmt6SEl6wPkvLl97j4OyLpML+L+UfnJeIjN7IEb0wa9hmgYnVgd8RftYR4ugfA9tNj7+5ixiArzxcUeMfdnGch1KPSoeCHjG4lynKSHGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634134; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=DDNS4GROfJmrDEJPqZg1QxQ9zwt6Kfx3JzL4SMAbB78=; b=blmcMXTMSogoTMGfsA4vmQ3+kglFHMoIZZ+onQfLqWlHmfs1TpeALL30E7n1x5Er28BoJI4+hBRM5Iv9bEeIMO7GNta9dFD+kMT1HlE2zF1DlRFSXsM8cjHJq8+Jb7H0T5P9RqVCnV0xvMpOe0I4PHRMqLtnvOHxSoUUbC443Jk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112598+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634134860371.7678280662378; Fri, 15 Dec 2023 01:55:34 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=cz9Y4qILW8EpHYETw2cXokXGU/1SYrb4FR7kpm8xVgk=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634134; v=1; b=pbNgOK8C+N2Sl/UrikznyT3tewWkoncV+dQDdLIYkMetePcxefOV00Wgzm7YEXfRU8gvfl3f xWVpN8DTn1olHc+BvmEUhRMy5fHGRsUuYty+jfktl1loPpFSpYNHVHdjTppaF9B9TWcM6Zrps76 yzqemhVUw6cap3WW7n3BFEEQ= X-Received: by 127.0.0.2 with SMTP id s71zYY1788612x3SlKPZug6K; Fri, 15 Dec 2023 01:55:34 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:34 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343115" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343115" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884305" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884305" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:31 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Guo Dong , Sean Rhodes , James Lu , Gua Guo , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v4 6/8] UefiPayloadPkg: Specifies SmmCpuSyncLib instance Date: Fri, 15 Dec 2023 17:55:13 +0800 Message-Id: <20231215095515.9484-7-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: XwbbHbS0fQh1r5LjjHR4EmBQx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634136613100027 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is to specify SmmCpuSyncLib instance for UefiPayloadPkg. Cc: Laszlo Ersek Cc: Guo Dong Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu Reviewed-by: Gua Guo Reviewed-by: Ray Ni --- UefiPayloadPkg/UefiPayloadPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index a65f9d5b83..b8b13ad201 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -253,10 +253,11 @@ # MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf =20 # # Platform # !if $(CPU_TIMER_LIB_ENABLE) =3D=3D TRUE && $(UNIVERSAL_PAYLOAD) =3D=3D TRUE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112598): https://edk2.groups.io/g/devel/message/112598 Mute This Topic: https://groups.io/mt/103187896/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112599+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112599+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634137; cv=none; d=zohomail.com; s=zohoarc; b=VHwAfzNAF5ZFff0n8aqgzdz6mejIk1jVapRg63ObO4qBvOUQuFFpjWAQ33ZZl5Dhg1VTT2djVJtaSukERqCfp0NZMySsxztYqdBwiKLDOZFLfG+dTFlfEHyIH15HFFPfVYPoj3zw7kJqjnUvOD42xCB64iKiSuNYDvmrMah7q8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634137; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=UWyAqRAUaMGCuAUiBFhvFwK6CaIMq2GbQVJY4Ol23Lc=; b=BLse/MyRzD86GJVd0ow8fbyjIuNKCWdtjKnpxVnPzX1fN13HO98sfs/MI7jEKnQZHuEWmI5b7ZAQM/jgPndmGYPHDF8qiTl+p5ZmeT+4lQNKzTYiLQbs1QZvuAPSlTk8Rl3lQ+XolLOqQ7WlwloTTj9k6RvORN3D2g9CbV6gDok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112599+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634137042387.415792297404; Fri, 15 Dec 2023 01:55:37 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=WNTIOfr6/oKKELnTPG0zDkyBR80HIfdg0KX9kafMSL0=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634136; v=1; b=sK7KocFfdHP7WIK4aZ4zKXp9pXh/KwxKkSpuMWYJ5JWpmlLibpxDVBtPR4t6eGgiunqnsG4G Zg/v6ktkbrbRB4PxMZqF87zPoqjwkAkrySzpmUBZB5nnIfEOnlgZrO62naOETGUWavSgch6vmNN CaKyuFalBPE3GjYmo1XqtMJc= X-Received: by 127.0.0.2 with SMTP id RIVoYY1788612xA9dGXU54xT; Fri, 15 Dec 2023 01:55:36 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:36 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343122" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343122" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884313" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884313" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:34 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v4 7/8] UefiCpuPkg/PiSmmCpuDxeSmm: Simplify RunningApCount decrement Date: Fri, 15 Dec 2023 17:55:14 +0800 Message-Id: <20231215095515.9484-8-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: einaaxyPgLRJ13Z1LB4olqGux1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634138618100029 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To decrease the count of RunningApCount, InterlockedDecrement is enough to achieve that. This patch is to simplify RunningApCount decrement. Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 54542262a2..9b477b6695 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1450,11 +1450,11 @@ InternalSmmStartupAllAPs ( =20 // // Decrease the count to mark this processor(AP or BSP) as finished. // if (ProcToken !=3D NULL) { - WaitForSemaphore (&ProcToken->RunningApCount); + InterlockedDecrement (&ProcToken->RunningApCount); } } } =20 ReleaseAllAPs (); --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112599): https://edk2.groups.io/g/devel/message/112599 Mute This Topic: https://groups.io/mt/103187897/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 14 17:37:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112600+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112600+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1702634139; cv=none; d=zohomail.com; s=zohoarc; b=fWwmiwNbjw2WR1md1dIyFgQpIcuRox8oG5HNtTNFxOv+Y0hLSzFAPd/FFKGPfnW135NBoVm10fb6d60bczg+09TEHiidGPnEq3BRGaim7ZNh4hxEHN0mmVLZzvpll2QYO7GC0K9rvnN2g/88d19d+mUObuy0x/y3CPZC2sY/MCk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702634139; h=Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=RYoeIbs1H6R1iYcotzRHIteN3NFzZ+PRPwllM/kuKQo=; b=JQtQg18MDCbO0YySEs95SQ1Ah10Wt9IcC/+sjd62bcw+lzBai9PIJ2TbjHzS9p5f9LVkQYTO2kZKRQf5ejxLLdQIaldfRaD8qlklxC6qM4LJnMJWkL6wYUm/vKaZpUO00cV1mqVRZ3gpLB5VFSKpcEorysi7nxibk3jMzmDdt5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112600+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1702634139790295.6477092866437; Fri, 15 Dec 2023 01:55:39 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=x++woCtiw2CGTBRrB6PUe31U+edM4i5i5NQrBuH0iAc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1702634139; v=1; b=Wams9aWhRV7SGSN2fanPTohF5vQn0nOOiGd2YioCgsxh+/85bIcP4KXdU8gFyyIrdzbfVC9C n+fPkI7OL0nq/xU0+EBD//hjV7KYRR2zkkk1kDJTKwvJ5nREbB+IMRqECqYPYILTMvLxpLQx1kt IaeBtVkg4KWPWXxuTYiZBGjQ= X-Received: by 127.0.0.2 with SMTP id fwtmYY1788612xfzRMWLndo7; Fri, 15 Dec 2023 01:55:39 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by mx.groups.io with SMTP id smtpd.web10.59154.1702634120783643851 for ; Fri, 15 Dec 2023 01:55:38 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="2343128" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="2343128" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 01:55:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10924"; a="750884321" X-IronPort-AV: E=Sophos;i="6.04,278,1695711600"; d="scan'208";a="750884321" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga006.jf.intel.com with ESMTP; 15 Dec 2023 01:55:36 -0800 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Laszlo Ersek , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v4 8/8] UefiCpuPkg/PiSmmCpuDxeSmm: Consume SmmCpuSyncLib Date: Fri, 15 Dec 2023 17:55:15 +0800 Message-Id: <20231215095515.9484-9-jiaxin.wu@intel.com> In-Reply-To: <20231215095515.9484-1-jiaxin.wu@intel.com> References: <20231215095515.9484-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: S2in7rO6XShNtemAUVvk664Sx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1702634140650100033 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is the SmmCpuSyncLib Library class define the SMM CPU sync flow, which is aligned with existing SMM CPU driver sync behavior. This patch is to consume SmmCpuSyncLib instance directly. With this change, SMM CPU Sync flow/logic can be customized with different implementation no matter for any purpose, e.g. performance tuning, handle specific register, etc. Cc: Laszlo Ersek Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 274 +++++++----------------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + 3 files changed, 68 insertions(+), 213 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 9b477b6695..4fbb0bba87 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -27,122 +27,10 @@ MM_COMPLETION mSmmStartupThisApToken; // // Processor specified by mPackageFirstThreadIndex[PackageIndex] will do t= he package-scope register check. // UINT32 *mPackageFirstThreadIndex =3D NULL; =20 -/** - Performs an atomic compare exchange operation to get semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: original integer - 1 - @return Original integer - 1 - -**/ -UINT32 -WaitForSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - for ( ; ;) { - Value =3D *Sem; - if ((Value !=3D 0) && - (InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - Value - 1 - ) =3D=3D Value)) - { - break; - } - - CpuPause (); - } - - return Value - 1; -} - -/** - Performs an atomic compare exchange operation to release semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: original integer + 1 - @return Original integer + 1 - -**/ -UINT32 -ReleaseSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (Value + 1 !=3D 0 && - InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - Value + 1 - ) !=3D Value); - - return Value + 1; -} - -/** - Performs an atomic compare exchange operation to lock semaphore. - The compare exchange operation must be performed using - MP safe mechanisms. - - @param Sem IN: 32-bit unsigned integer - OUT: -1 - @return Original integer - -**/ -UINT32 -LockdownSemaphore ( - IN OUT volatile UINT32 *Sem - ) -{ - UINT32 Value; - - do { - Value =3D *Sem; - } while (InterlockedCompareExchange32 ( - (UINT32 *)Sem, - Value, - (UINT32)-1 - ) !=3D Value); - - return Value; -} - -/** - Used for BSP to wait all APs. - Wait all APs to performs an atomic compare exchange operation to release= semaphore. - - @param NumberOfAPs AP number - -**/ -VOID -WaitForAllAPs ( - IN UINTN NumberOfAPs - ) -{ - UINTN BspIndex; - - BspIndex =3D mSmmMpSyncData->BspIndex; - while (NumberOfAPs-- > 0) { - WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); - } -} - /** Used for BSP to release all APs. Performs an atomic compare exchange operation to release semaphore for each AP. =20 @@ -154,57 +42,15 @@ ReleaseAllAPs ( { UINTN Index; =20 for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { if (IsPresentAp (Index)) { - ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run); + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SyncContext, Index, gSmmCpuP= rivate->SmmCoreEntryContext.CurrentlyExecutingCpu); } } } =20 -/** - Used for BSP to release one AP. - - @param ApSem IN: 32-bit unsigned integer - OUT: original integer + 1 -**/ -VOID -ReleaseOneAp ( - IN OUT volatile UINT32 *ApSem - ) -{ - ReleaseSemaphore (ApSem); -} - -/** - Used for AP to wait BSP. - - @param ApSem IN: 32-bit unsigned integer - OUT: original integer - 1 -**/ -VOID -WaitForBsp ( - IN OUT volatile UINT32 *ApSem - ) -{ - WaitForSemaphore (ApSem); -} - -/** - Used for AP to release BSP. - - @param BspSem IN: 32-bit unsigned integer - OUT: original integer + 1 -**/ -VOID -ReleaseBsp ( - IN OUT volatile UINT32 *BspSem - ) -{ - ReleaseSemaphore (BspSem); -} - /** Check whether the index of CPU perform the package level register programming during System Management Mode initialization. =20 The index of Processor specified by mPackageFirstThreadIndex[PackageInde= x] @@ -292,35 +138,35 @@ AllCpusInSmmExceptBlockedDisabled ( =20 BlockedCount =3D 0; DisabledCount =3D 0; =20 // - // Check to make sure mSmmMpSyncData->Counter is valid and not locked. + // Check to make sure the CPU arrival count is valid and not locked. // - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); + ASSERT (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) <=3D = mNumberOfCpus); =20 // // Check whether all CPUs in SMM. // - if (*mSmmMpSyncData->Counter =3D=3D mNumberOfCpus) { + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) =3D=3D mN= umberOfCpus) { return TRUE; } =20 // // Check for the Blocked & Disabled Exceptions Case. // GetSmmDelayedBlockedDisabledCount (NULL, &BlockedCount, &DisabledCount); =20 // - // *mSmmMpSyncData->Counter might be updated by all APs concurrently. Th= e value + // The CPU arrival count might be updated by all APs concurrently. The v= alue // can be dynamic changed. If some Aps enter the SMI after the BlockedCo= unt & - // DisabledCount check, then the *mSmmMpSyncData->Counter will be increa= sed, thus - // leading the *mSmmMpSyncData->Counter + BlockedCount + DisabledCount >= mNumberOfCpus. + // DisabledCount check, then the CPU arrival count will be increased, th= us + // leading the retrieved CPU arrival count + BlockedCount + DisabledCoun= t > mNumberOfCpus. // since the BlockedCount & DisabledCount are local variable, it's ok he= re only for // the checking of all CPUs In Smm. // - if (*mSmmMpSyncData->Counter + BlockedCount + DisabledCount >=3D mNumber= OfCpus) { + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) + Blocked= Count + DisabledCount >=3D mNumberOfCpus) { return TRUE; } =20 return FALSE; } @@ -396,11 +242,11 @@ SmmWaitForApArrival ( PERF_FUNCTION_BEGIN (); =20 DelayedCount =3D 0; BlockedCount =3D 0; =20 - ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); + ASSERT (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) <=3D = mNumberOfCpus); =20 LmceEn =3D FALSE; LmceSignal =3D FALSE; if (mMachineCheckSupported) { LmceEn =3D IsLmceOsEnabled (); @@ -447,11 +293,11 @@ SmmWaitForApArrival ( // d) We don't add code to check SMI disabling status to skip sending IP= I to SMI disabled APs, because: // - In traditional flow, SMI disabling is discouraged. // - In relaxed flow, CheckApArrival() will check SMI disabling statu= s before calling this function. // In both cases, adding SMI-disabling checking code increases overhe= ad. // - if (*mSmmMpSyncData->Counter < mNumberOfCpus) { + if (SmmCpuSyncGetArrivedCpuCount (mSmmMpSyncData->SyncContext) < mNumber= OfCpus) { // // Send SMI IPIs to bring outside processors in // for (Index =3D 0; Index < mMaxNumberOfCpus; Index++) { if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate-= >ProcessorInfo[Index].ProcessorId !=3D INVALID_APIC_ID)) { @@ -610,18 +456,20 @@ VOID BSPHandler ( IN UINTN CpuIndex, IN SMM_CPU_SYNC_MODE SyncMode ) { + UINTN CpuCount; UINTN Index; MTRR_SETTINGS Mtrrs; UINTN ApCount; BOOLEAN ClearTopLevelSmiResult; UINTN PresentCount; =20 ASSERT (CpuIndex =3D=3D mSmmMpSyncData->BspIndex); - ApCount =3D 0; + CpuCount =3D 0; + ApCount =3D 0; =20 PERF_FUNCTION_BEGIN (); =20 // // Flag BSP's presence @@ -659,28 +507,31 @@ BSPHandler ( // Wait for APs to arrive // SmmWaitForApArrival (); =20 // - // Lock the counter down and retrieve the number of APs + // Lock door for late coming CPU checkin and retrieve the Arrived numb= er of APs // *mSmmMpSyncData->AllCpusInSync =3D TRUE; - ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; + + SmmCpuSyncLockDoor (mSmmMpSyncData->SyncContext, CpuIndex, &CpuCount); + + ApCount =3D CpuCount - 1; =20 // // Wait for all APs to get ready for programming MTRRs // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex); =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal all APs it's time for backup MTRRs // ReleaseAllAPs (); =20 // - // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at + // SmmCpuSyncWaitForAPs() may wait for ever if an AP happens to ente= r SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // Note: For HT capable CPUs, threads within a core share the same s= et of MTRRs. // We do the backup first and then set MTRR to avoid race condition = for threads // in the same core. @@ -688,28 +539,28 @@ BSPHandler ( MtrrGetAllMtrrs (&Mtrrs); =20 // // Wait for all APs to complete their MTRR saving // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex= ); =20 // // Let all processors program SMM MTRRs together // ReleaseAllAPs (); =20 // - // WaitForAllAPs() may wait for ever if an AP happens to enter SMM at + // SmmCpuSyncWaitForAPs() may wait for ever if an AP happens to ente= r SMM at // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has be= en set // to a large enough value to avoid this situation. // ReplaceOSMtrrs (CpuIndex); =20 // // Wait for all APs to complete their MTRR programming // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex= ); } } =20 // // The BUSY lock is initialized to Acquired state @@ -741,14 +592,18 @@ BSPHandler ( // make those APs to exit SMI synchronously. APs which arrive later will= be excluded and // will run through freely. // if ((SyncMode !=3D SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfig= ureMtrrs ()) { // - // Lock the counter down and retrieve the number of APs + // Lock door for late coming CPU checkin and retrieve the Arrived numb= er of APs // *mSmmMpSyncData->AllCpusInSync =3D TRUE; - ApCount =3D LockdownSemaphore (mSmmMpSyncData->= Counter) - 1; + + SmmCpuSyncLockDoor (mSmmMpSyncData->SyncContext, CpuIndex, &CpuCount); + + ApCount =3D CpuCount - 1; + // // Make sure all APs have their Present flag set // while (TRUE) { PresentCount =3D 0; @@ -771,11 +626,11 @@ BSPHandler ( ReleaseAllAPs (); =20 // // Wait for all APs to complete their pending tasks // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex); =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Signal APs to restore MTRRs // @@ -788,11 +643,11 @@ BSPHandler ( MtrrSetAllMtrrs (&Mtrrs); =20 // // Wait for all APs to complete MTRR programming // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex); } =20 // // Stop source level debug in BSP handler, the code below will not be // debugged. @@ -816,11 +671,11 @@ BSPHandler ( =20 // // Gather APs to exit SMM synchronously. Note the Present flag is cleare= d by now but // WaitForAllAps does not depend on the Present flag. // - WaitForAllAPs (ApCount); + SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex); =20 // // At this point, all APs should have exited from APHandler(). // Migrate the SMM MP performance logging to standard SMM performance lo= gging. // Any SMM MP performance logging after this point will be migrated in n= ext SMI. @@ -842,11 +697,11 @@ BSPHandler ( } =20 // // Allow APs to check in from this point on // - *mSmmMpSyncData->Counter =3D 0; + SmmCpuSyncContextReset (mSmmMpSyncData->SyncContext); *mSmmMpSyncData->AllCpusInSync =3D FALSE; mSmmMpSyncData->AllApArrivedWithException =3D FALSE; =20 PERF_FUNCTION_END (); } @@ -912,21 +767,21 @@ APHandler ( =20 if (!(*mSmmMpSyncData->InsideSmm)) { // // Give up since BSP is unable to enter SMM // and signal the completion of this AP - // Reduce the mSmmMpSyncData->Counter! + // Reduce the CPU arrival count! // - WaitForSemaphore (mSmmMpSyncData->Counter); + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SyncContext, CpuIndex); return; } } else { // // Don't know BSP index. Give up without sending IPI to BSP. - // Reduce the mSmmMpSyncData->Counter! + // Reduce the CPU arrival count! // - WaitForSemaphore (mSmmMpSyncData->Counter); + SmmCpuSyncCheckOutCpu (mSmmMpSyncData->SyncContext, CpuIndex); return; } } =20 // @@ -942,50 +797,50 @@ APHandler ( =20 if ((SyncMode =3D=3D SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfi= gureMtrrs ()) { // // Notify BSP of arrival at this point // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); } =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Wait for the signal from BSP to backup MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Backup OS MTRRs // MtrrGetAllMtrrs (&Mtrrs); =20 // // Signal BSP the completion of this AP // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Wait for BSP's signal to program MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Replace OS MTRRs with SMI MTRRs // ReplaceOSMtrrs (CpuIndex); =20 // // Signal BSP the completion of this AP // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); } =20 while (TRUE) { // // Wait for something to happen // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Check if BSP wants to exit SMM // if (!(*mSmmMpSyncData->InsideSmm)) { @@ -1021,16 +876,16 @@ APHandler ( =20 if (SmmCpuFeaturesNeedConfigureMtrrs ()) { // // Notify BSP the readiness of this AP to program MTRRs // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Wait for the signal from BSP to program MTRRs // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Restore OS MTRRs // SmmCpuFeaturesReenableSmrr (); @@ -1038,26 +893,26 @@ APHandler ( } =20 // // Notify BSP the readiness of this AP to Reset states/semaphore for thi= s processor // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Wait for the signal from BSP to Reset states/semaphore for this proce= ssor // - WaitForBsp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncWaitForBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); =20 // // Reset states/semaphore for this processor // *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; =20 // // Notify BSP the readiness of this AP to exit SMM // - ReleaseBsp (mSmmMpSyncData->CpuData[BspIndex].Run); + SmmCpuSyncReleaseBsp (mSmmMpSyncData->SyncContext, CpuIndex, BspIndex); } =20 /** Checks whether the input token is the current used token. =20 @@ -1321,11 +1176,11 @@ InternalSmmStartupThisAp ( mSmmMpSyncData->CpuData[CpuIndex].Status =3D CpuStatus; if (mSmmMpSyncData->CpuData[CpuIndex].Status !=3D NULL) { *mSmmMpSyncData->CpuData[CpuIndex].Status =3D EFI_NOT_READY; } =20 - ReleaseOneAp (mSmmMpSyncData->CpuData[CpuIndex].Run); + SmmCpuSyncReleaseOneAp (mSmmMpSyncData->SyncContext, CpuIndex, gSmmCpuPr= ivate->SmmCoreEntryContext.CurrentlyExecutingCpu); =20 if (Token =3D=3D NULL) { AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); } @@ -1725,14 +1580,15 @@ SmiRendezvous ( // goto Exit; } else { // // Signal presence of this processor - // mSmmMpSyncData->Counter is increased here! - // "ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0" means BSP has= already ended the synchronization. + // CPU check in here! + // "SmmCpuSyncCheckInCpu (mSmmMpSyncData->SyncContext, CpuIndex)" retu= rn error means failed + // to check in CPU. BSP has already ended the synchronization. // - if (ReleaseSemaphore (mSmmMpSyncData->Counter) =3D=3D 0) { + if (RETURN_ERROR (SmmCpuSyncCheckInCpu (mSmmMpSyncData->SyncContext, C= puIndex))) { // // BSP has already ended the synchronization, so QUIT!!! // Existing AP is too late now to enter SMI since BSP has already en= ded the synchronization!!! // =20 @@ -1824,12 +1680,10 @@ SmiRendezvous ( } else { APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode); } } =20 - ASSERT (*mSmmMpSyncData->CpuData[CpuIndex].Run =3D=3D 0); - // // Wait for BSP's signal to exit SMI // while (*mSmmMpSyncData->AllCpusInSync) { CpuPause (); @@ -1945,12 +1799,10 @@ InitializeSmmCpuSemaphores ( SemaphoreBlock =3D AllocatePages (Pages); ASSERT (SemaphoreBlock !=3D NULL); ZeroMem (SemaphoreBlock, TotalSize); =20 SemaphoreAddr =3D (UINTN)SemaphoreBloc= k; - mSmmCpuSemaphores.SemaphoreGlobal.Counter =3D (UINT32 *)SemaphoreA= ddr; - SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm =3D (BOOLEAN *)Semaphore= Addr; SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync =3D (BOOLEAN *)Semaphore= Addr; SemaphoreAddr +=3D SemaphoreSize; mSmmCpuSemaphores.SemaphoreGlobal.PFLock =3D (SPIN_LOCK *)Semapho= reAddr; @@ -1960,12 +1812,10 @@ InitializeSmmCpuSemaphores ( SemaphoreAddr +=3D SemaphoreSize; =20 SemaphoreAddr =3D (UINTN)SemaphoreBlock + Globa= lSemaphoresSize; mSmmCpuSemaphores.SemaphoreCpu.Busy =3D (SPIN_LOCK *)SemaphoreAddr; SemaphoreAddr +=3D ProcessorCount * SemaphoreSiz= e; - mSmmCpuSemaphores.SemaphoreCpu.Run =3D (UINT32 *)SemaphoreAddr; - SemaphoreAddr +=3D ProcessorCount * SemaphoreSiz= e; mSmmCpuSemaphores.SemaphoreCpu.Present =3D (BOOLEAN *)SemaphoreAddr; =20 mPFLock =3D mSmmCpuSemaphores.SemaphoreGlobal.PFLo= ck; mConfigSmmCodeAccessCheckLock =3D mSmmCpuSemaphores.SemaphoreGlobal.Code= AccessCheckLock; =20 @@ -1980,10 +1830,12 @@ VOID EFIAPI InitializeMpSyncData ( VOID ) { + RETURN_STATUS Status; + UINTN CpuIndex; =20 if (mSmmMpSyncData !=3D NULL) { // // mSmmMpSyncDataSize includes one structure of SMM_DISPATCHER_MP_SYNC= _DATA, one @@ -2009,32 +1861,36 @@ InitializeMpSyncData ( } } =20 mSmmMpSyncData->EffectiveSyncMode =3D mCpuSmmSyncMode; =20 - mSmmMpSyncData->Counter =3D mSmmCpuSemaphores.SemaphoreGlobal.Co= unter; + Status =3D SmmCpuSyncContextInit (gSmmCpuPrivate->SmmCoreEntryContext.= NumberOfCpus, &mSmmMpSyncData->SyncContext); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "InitializeMpSyncData: SmmCpuSyncContextInit re= turn error %r!\n", Status)); + CpuDeadLoop (); + return; + } + + ASSERT (mSmmMpSyncData->SyncContext !=3D NULL); + mSmmMpSyncData->InsideSmm =3D mSmmCpuSemaphores.SemaphoreGlobal.In= sideSmm; mSmmMpSyncData->AllCpusInSync =3D mSmmCpuSemaphores.SemaphoreGlobal.Al= lCpusInSync; ASSERT ( - mSmmMpSyncData->Counter !=3D NULL && mSmmMpSyncData->InsideSmm !=3D = NULL && + mSmmMpSyncData->InsideSmm !=3D NULL && mSmmMpSyncData->AllCpusInSync !=3D NULL ); - *mSmmMpSyncData->Counter =3D 0; *mSmmMpSyncData->InsideSmm =3D FALSE; *mSmmMpSyncData->AllCpusInSync =3D FALSE; =20 mSmmMpSyncData->AllApArrivedWithException =3D FALSE; =20 for (CpuIndex =3D 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.Nu= mberOfCpus; CpuIndex++) { mSmmMpSyncData->CpuData[CpuIndex].Busy =3D (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaph= oreSize * CpuIndex); - mSmmMpSyncData->CpuData[CpuIndex].Run =3D - (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreS= ize * CpuIndex); mSmmMpSyncData->CpuData[CpuIndex].Present =3D (BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemap= horeSize * CpuIndex); *(mSmmMpSyncData->CpuData[CpuIndex].Busy) =3D 0; - *(mSmmMpSyncData->CpuData[CpuIndex].Run) =3D 0; *(mSmmMpSyncData->CpuData[CpuIndex].Present) =3D FALSE; } } } =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index f18345881b..a2fa4f6734 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -52,10 +52,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include #include #include +#include =20 #include #include =20 #include @@ -403,11 +404,10 @@ SmmRelocationSemaphoreComplete ( /// typedef struct { SPIN_LOCK *Busy; volatile EFI_AP_PROCEDURE2 Procedure; volatile VOID *Parameter; - volatile UINT32 *Run; volatile BOOLEAN *Present; PROCEDURE_TOKEN *Token; EFI_STATUS *Status; } SMM_CPU_DATA_BLOCK; =20 @@ -421,29 +421,28 @@ typedef struct { // // Pointer to an array. The array should be located immediately after th= is structure // so that UC cache-ability can be set together. // SMM_CPU_DATA_BLOCK *CpuData; - volatile UINT32 *Counter; volatile UINT32 BspIndex; volatile BOOLEAN *InsideSmm; volatile BOOLEAN *AllCpusInSync; volatile SMM_CPU_SYNC_MODE EffectiveSyncMode; volatile BOOLEAN SwitchBsp; volatile BOOLEAN *CandidateBsp; volatile BOOLEAN AllApArrivedWithException; EFI_AP_PROCEDURE StartupProcedure; VOID *StartupProcArgs; + SMM_CPU_SYNC_CONTEXT *SyncContext; } SMM_DISPATCHER_MP_SYNC_DATA; =20 #define SMM_PSD_OFFSET 0xfb00 =20 /// /// All global semaphores' pointer /// typedef struct { - volatile UINT32 *Counter; volatile BOOLEAN *InsideSmm; volatile BOOLEAN *AllCpusInSync; SPIN_LOCK *PFLock; SPIN_LOCK *CodeAccessCheckLock; } SMM_CPU_SEMAPHORE_GLOBAL; @@ -451,11 +450,10 @@ typedef struct { /// /// All semaphores for each processor /// typedef struct { SPIN_LOCK *Busy; - volatile UINT32 *Run; volatile BOOLEAN *Present; SPIN_LOCK *Token; } SMM_CPU_SEMAPHORE_CPU; =20 /// diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index 372596f24c..793220aba3 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -101,10 +101,11 @@ SmmCpuFeaturesLib PeCoffGetEntryPointLib PerformanceLib CpuPageTableLib MmSaveStateLib + SmmCpuSyncLib =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## CONSUMES gEfiSmmConfigurationProtocolGuid ## PRODUCES gEfiSmmCpuProtocolGuid ## PRODUCES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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