From nobody Fri May 17 11:05:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+111121+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+111121+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699855197; cv=none; d=zohomail.com; s=zohoarc; b=AhM55aX8wWCns7QK1VVCpdSNsy+oLDu0RgrdbLj8Mn+ChGBxhG15M2DUJvb2uauF28esOSOOYte9THBAMcDYMaOM7Z3udXqAiJrEymI0T3H+3jahLnhdmiqZw2ZmeM1buWCGj9ew82vbhKOTVRSQNMZsZmx15zR5wykgL2YRyiM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699855197; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=ALy5enDF529fQq1VEGJZ0BYQ/MSCdldANLNaxNSGVIk=; b=ZK9bhGg+t3ntdOq/kEIb4WPV7PdFeDZ+UJkceD05q3+N47R/mNTmFj9iiEz4iMwtYh5GhPkauVY0KFGAjxvOzfKdE/+r52WjZRYWnM2+B/8jOatGtTpX2JOh7MTz3U6rc31fdBSTYPgHJ0GSbnRd+8D3WAaK0Zl9rhyEXrYYYU8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+111121+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1699855197792580.8069194971041; Sun, 12 Nov 2023 21:59:57 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=AMPM61SPwfx9QvyykhWxxg7b2p5W1CDDxlBeEVQGA2E=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1699855197; v=1; b=LR5LxAkT5eu+DYqrREE5YSO2PWRfefpju9TVuVc1zZ9olMxoUgAskPeOyMv9cXvjzf7Yo4ZJ gzBxwtrar/uuc/8q4DRkbE6UzzRFJvsmJaY1h4x8LoQIj4zELZEJypmsBPZ0JLUWV9tSP4UFvQv h0ciKHS9ROI85Y9hoO2jWQAA= X-Received: by 127.0.0.2 with SMTP id JarVYY1788612xgsI3UTf3cs; Sun, 12 Nov 2023 21:59:57 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.31633.1699855196531823285 for ; Sun, 12 Nov 2023 21:59:56 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10892"; a="476603916" X-IronPort-AV: E=Sophos;i="6.03,298,1694761200"; d="scan'208";a="476603916" X-Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2023 21:59:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,298,1694761200"; d="scan'208";a="12004934" X-Received: from shwdeopenlab813.ccr.corp.intel.com ([10.239.55.230]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2023 21:59:53 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Yuanhao Xie , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4] UefiCpuPkg/MpInitLib: Enable execute disable bit. Date: Mon, 13 Nov 2023 13:59:48 +0800 Message-Id: <20231113055948.1773-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: p6HB48xjloH0iqLoDpq76Qnmx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1699855198733100002 Content-Type: text/plain; charset="utf-8" From: Yuanhao Xie This patch synchronizes the No-Execute bit in the IA32_EFER register for the APs before the RestoreVolatileRegisters operation. The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP calling the SwitchApContext function to initiate a specialized start-up signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI. Due to this change, the logic for "Enable execute disable bit" in MpFuncs.nasm is no longer executed. However, to ensure the proper setup of the page table, it is necessary to synchronize the IA32_EFER.NXE for APs before executing RestoreVolatileRegisters . Based on SDM: If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning instruction fetches are not allowed from the 4-KByte page controlled by this entry. Conversely, if it is set to 0, it is reserved. Signed-off-by: Yuanhao Xie Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Reviewed-by: Laszlo Ersek --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 14 +++++++++++--- UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 9a6ec5db5c..f29e66a14f 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -910,9 +910,16 @@ DxeApEntryPoint ( CPU_MP_DATA *CpuMpData ) { - UINTN ProcessorNumber; + UINTN ProcessorNumber; + MSR_IA32_EFER_REGISTER EferMsr; =20 GetProcessorNumber (CpuMpData, &ProcessorNumber); + if (CpuMpData->EnableExecuteDisableForSwitchContext) { + EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + EferMsr.Bits.NXE =3D 1; + AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); + } + RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALS= E); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); PlaceAPInMwaitLoopOrRunLoop ( @@ -2188,8 +2195,9 @@ MpInitLibInitialize ( if (MpHandOff->WaitLoopExecutionMode =3D=3D sizeof (VOID *)) { ASSERT (CpuMpData->ApLoopMode !=3D ApInHltLoop); =20 - CpuMpData->FinishedCount =3D 0; - CpuMpData->InitFlag =3D ApInitDone; + CpuMpData->FinishedCount =3D 0; + CpuMpData->InitFlag =3D ApInitDone; + CpuMpData->EnableExecuteDisableForSwitchContext =3D IsBspExecuteDisa= bleEnabled (); SaveCpuMpData (CpuMpData); // // In scenarios where both the PEI and DXE phases run in the same diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 763db4963d..af296f6ac0 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -270,6 +270,7 @@ struct _CPU_MP_DATA { UINT64 TotalTime; EFI_EVENT WaitEvent; UINTN **FailedCpuList; + BOOLEAN EnableExecuteDisableForSwitchContext; =20 AP_INIT_STATE InitFlag; BOOLEAN SwitchBspFlag; --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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