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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: uENbbDhsYRzPIceKDaWQQrdLx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1695393703131100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to dynamically generate the CPU nodes in SSDT. Signed-off-by: Sami Mujawar Reviewed-by: Pierre Gondois --- Notes: v3: - No code change from v2 patch series. [SAMI] =20 v2: - No code change from v1 patch series. [SAMI] Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslT= ables/Dsdt.asl | 38 +------------------- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.c | 8 ++++- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.h | 2 +- 3 files changed, 9 insertions(+), 39 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/AslTables/Dsdt.asl b/Platform/ARM/VExpressPkg/ConfigurationManager/= ConfigurationManagerDxe/AslTables/Dsdt.asl index 3acc0c6bc1b48b747e011022f2300b2fe3fa994b..f60430b94c867ee9744a3355b0e= a377aff42b1c4 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /AslTables/Dsdt.asl +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /AslTables/Dsdt.asl @@ -1,7 +1,7 @@ /** @file Differentiated System Description Table Fields (DSDT) =20 - Copyright (c) 2014-2021, ARM Ltd. All rights reserved.
+ Copyright (c) 2014-2023, ARM Ltd. All rights reserved.
Copyright (c) 2013, Al Stone All rights reserved. =20 @@ -11,42 +11,6 @@ =20 DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-VEXP", 1) { Scope(_SB) { - // - // Processor - // - Device(CPU0) { - Name(_HID, "ACPI0007") - Name(_UID, Zero) - } - Device(CPU1) { - Name(_HID, "ACPI0007") - Name(_UID, One) - } - Device(CPU2) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - Device(CPU3) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - Device(CPU4) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - Device(CPU5) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - Device(CPU6) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - Device(CPU7) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } - // SMC91X Device (NET0) { Name (_HID, "LNRO0003") diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.c index 58a4bf9890bc2a701dab558a1987f9a51662481a..4df2d6cdae58df344804a8b4120= 8a3adb8ee0110 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c @@ -77,7 +77,13 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInf= o =3D { CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2), NULL }, - + // SSDT Cpu Hierarchy Table + { + EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtCpuTopology), + NULL + }, // Note: The last 3 tables in this list are for FVP RevC only. // IORT Table - FVP RevC { diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.h b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.h index aebf0a355291df5df5f588e8b7076e21eda9a152..1b52c2ebc7efb633c748f731660= 6e3dbe4e0b21c 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.h +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.h @@ -89,7 +89,7 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) ( =20 /** The number of ACPI tables to install */ -#define PLAT_ACPI_TABLE_COUNT 9 +#define PLAT_ACPI_TABLE_COUNT 10 =20 /** The number of platform generic timer blocks */ --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Fri, 22 Sep 2023 14:41:25 +0000 X-Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 22 Sep 2023 14:41:25 +0000 X-Received: from E114225.Arm.com (10.1.196.36) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 22 Sep 2023 14:41:24 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , , Subject: [edk2-devel] [PATCH edk2-platforms v3 2/3] Platform/ARM: FVP: Specify TRBE interrupt in MADT GICC Date: Fri, 22 Sep 2023 15:41:22 +0100 Message-ID: <20230922144123.41164-3-sami.mujawar@arm.com> In-Reply-To: <20230922144123.41164-1-sami.mujawar@arm.com> References: <20230922144123.41164-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT045:EE_|PA4PR08MB5934:EE_|DBAEUR03FT034:EE_|PA4PR08MB6079:EE_ X-MS-Office365-Filtering-Correlation-Id: 10755651-34a5-486b-13af-08dbbb7a0a13 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB5934 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 27556261-86cb-4a18-cd55-08dbbb7a03c9 X-Microsoft-Antispam-Message-Info: peRETwz9ITmEXqko0PNgZU/znMb42CsL7GzcFNGHYvDHqmitL2dHElO4qHM8f1JEQPg7oEfYUfcXRlLfF+BsBa1zPG7O3iMg3iMULItZE6XdKDDzEDtaZlsnREvc9c715P33SqtVXyXbMsC605G9xMrGfUAxMCL3KN617nqfDUVq0MFsyQD5iTiwvr+kWLkNpfiz17ZTNnpo2KqDzOFaVyE6Ofg8b3XqBIEpjzI5XpC1idUvfzoiCAr1T9p79eek3e+2FdW3Jue7PjBPrPRSYT9x4eql/SAwXFDv1B5jGEehVRxWth72eY8NubyKAmbnogwr8EGD+eAqQ1ZGnyJ8ZsKCRjJ5zndO5ihYYFn6NSXtZuc4+n5J84G4V2KNKi6oP+OZQqi8G0twJJ9g4Q3trhQFJjOrib18dSRAOZtc+DpPqbbwBKKoSsrrfehtm9RAJycMRGnWRkUgHKOVWJLFSQgWasZk/AMQD7URHZMBauHYdoqhmAN5bsY1ZL9AF4DBZ0A/ZU/H3prdqYRojlH3DvOFytkQR6WDclOul9FcQj6S0XUi9rAuT+z45TjrMtty86ZStwcZ2ZmH6TDHvsFoQa/JzeivIQMqzXIv3cD5gU54276Jba9dcrGkmiT8oZWWdzMAhL/pKa+xc8y/4jAmgKyBc47XlXRstCEKILdRjB3pnejz6GY4x2UNkYGlw6/vVhyXlsw014N/uSBDXyhVPzPRvKP3N7Phki6yx3e5aPnGe++b57sfNNrFuwl7z84qkUT2+4KutlWSgAPTrg/i7o8IKE0j6YFjfMMsMxfbYWYjLVzYe7bh76kPce/qs8f7 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2023 14:41:43.2483 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10755651-34a5-486b-13af-08dbbb7a0a13 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6079 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: hBzjjJ11U7xEVCPHBqpQDJrux1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1695393710947100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When TRBE is enabled the FVP model uses the PPI 15 (i.e. INT ID 31) as the TRBE interrupt. Ref: https://www.kernel.org/doc/Documentation/ devicetree/bindings/arm/arm,trace-buffer-extension.yaml Therefore, check the debug feature register ID_AA64DFR0_EL1.TraceBuffer field to see if TRBE is enabled and configure the TRBE interrupt in the GICC structure in the MADT ACPI table. Note: To enable TRBE support in the FVP REvC model 1. Build TF-A with the CTX_INCLUDE_AARCH32_REGS=3D0 build flag set, otherwise this results in an exception when booting TF-A. 2. Set the model parameters to enable TRBE -C cluster0.has_trbe=3D1 -C cluster1.has_trbe=3D1 Signed-off-by: Sami Mujawar Reviewed-by: Pierre Gondois --- Notes: v3: - Use macros instead of magic numbers in TRBE feature [Pierre] detection code. - Implemented helper functions in ArmLib to detect if [Sami] the TRBE feature is present and used it instead. Ref: https://edk2.groups.io/g/devel/message/108986 =20 v2: - Incorrect comment for TRBE interrupt number [Jeshua] - Fixed comment to specify TRBE interrupt as [Sami] PPI 15 Ref: https://edk2.groups.io/g/devel/message/107426 =20 V2: - Incorrect comment for TRBE interrupt number [Jeshua] - Fixed comment to specify TRBE interrupt as [Sami] PPI 15 Ref: https://edk2.groups.io/g/devel/message/107426 Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.c | 31 +++++++++++++++----- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManagerDxe.inf | 3 +- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.c index 4df2d6cdae58df344804a8b41208a3adb8ee0110..749d8eaf52de0888e9e44173f4f= 84aa41c4c70b5 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c @@ -1,7 +1,7 @@ /** @file Configuration Manager Dxe =20 - Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2017 - 2023, Arm Limited. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -37,8 +37,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo= =3D { { // FADT Table { - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), NULL }, @@ -51,8 +51,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo= =3D { }, // MADT Table { - EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), NULL }, @@ -109,15 +109,15 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepository= Info =3D { }, =20 // Boot architecture information - { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags + { EFI_ACPI_6_5_ARM_PSCI_COMPLIANT }, // BootArchFlags =20 #ifdef HEADLESS_PLATFORM // Fixed feature flag information - { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags + { EFI_ACPI_6_5_HEADLESS }, // Fixed feature flags #endif =20 // Power management profile information - { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Pro= file + { EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Pro= file =20 /* GIC CPU Interface information GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficien= cy) @@ -474,6 +474,8 @@ InitializePlatformRepository ( ) { EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Index; + UINT16 TrbeInterrupt; =20 PlatformRepo =3D This->PlatRepoInfo; =20 @@ -491,6 +493,19 @@ InitializePlatformRepository ( PlatformRepo->GicCInfo[6].MPIDR =3D GET_MPID_MT (1, 2, 0); PlatformRepo->GicCInfo[7].MPIDR =3D GET_MPID_MT (1, 3, 0); } + + TrbeInterrupt =3D 0; + + // The ID_AA64DFR0_EL1.TraceBuffer field identifies support for FEAT_TRB= E. + if (ArmHasTrbe ()) { + // TRBE Interrupt is PPI 15 on FVP model. + TrbeInterrupt =3D 31; + } + + for (Index =3D 0; Index < PLAT_CPU_COUNT; Index++) { + PlatformRepo->GicCInfo[Index].TrbeInterrupt =3D TrbeInterrupt; + } + return EFI_SUCCESS; } =20 diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/VExpressPkg/Configuratio= nManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf index b53daf51d4b1afd45e41d0debb0b9f084f135f6a..dd08f8597768d4de62941c5fd74= e329c431582b0 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManagerDxe.inf +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManagerDxe.inf @@ -1,7 +1,7 @@ ## @file # Configuration Manager Dxe # -# Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2017 - 2023, Arm Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent ## @@ -34,6 +34,7 @@ [Packages] Platform/ARM/VExpressPkg/ArmVExpressPkg.dec =20 [LibraryClasses] + ArmLib ArmPlatformLib PrintLib UefiBootServicesTableLib --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: oEUSNVhS9e0qHTWbPmWIG0urx1787277AA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1695393716804100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When ETE is enabled in the FVP model the firmware can check the debug feature register ID_AA64DFR0_EL1.TraceVer field to identify the presence of FEAT_ETE and add an ETE device to the CPU node in the AML CPU hierarchy. This enables the Operating System driver to probe and enable ETE support. Note: To enable ETE support in the FVP REvC model 1. Build TF-A with the CTX_INCLUDE_AARCH32_REGS=3D0 build flag set, otherwise this results in an exception when booting TF-A 2. Set the model parameters to enable TRBE as this is required for ETE -C cluster0.has_trbe=3D1 -C cluster1.has_trbe=3D1 3. Set the ETE plugin for the model --plugin \libete-plugin.[so|dll] Signed-off-by: Sami Mujawar Reviewed-by: Pierre Gondois --- Notes: v3: - Use macros instead of magic numbers in ETE feature [Pierre] detection code. - Implemented helper functions in ArmLib to detect if [Sami] the ETE feature is present and used it instead. Ref: https://edk2.groups.io/g/devel/message/108986 =20 v2: - No code change from v1 patch series. [SAMI] Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.c | 25 ++++++++++++++++++++ Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.c index 749d8eaf52de0888e9e44173f4f84aa41c4c70b5..5b5d1f9d04c0f27bf32cca62f51= c259152e16711 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c @@ -365,6 +365,11 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryI= nfo =3D { FixedPcdGet32 (PcdPciBusMin), FixedPcdGet32 (PcdPciBusMax) }, + + // Embedded Trace device info + { + ArmEtTypeEte + } }; =20 /** A helper function for returning the Configuration Manager Objects. @@ -476,6 +481,7 @@ InitializePlatformRepository ( EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; UINTN Index; UINT16 TrbeInterrupt; + CM_OBJECT_TOKEN EtToken; =20 PlatformRepo =3D This->PlatRepoInfo; =20 @@ -495,6 +501,7 @@ InitializePlatformRepository ( } =20 TrbeInterrupt =3D 0; + EtToken =3D CM_NULL_TOKEN; =20 // The ID_AA64DFR0_EL1.TraceBuffer field identifies support for FEAT_TRB= E. if (ArmHasTrbe ()) { @@ -502,8 +509,14 @@ InitializePlatformRepository ( TrbeInterrupt =3D 31; } =20 + // The ID_AA64DFR0_EL1.TraceVer field identifies the presence of FEAT_ET= E. + if (ArmHasEte ()) { + EtToken =3D (CM_OBJECT_TOKEN)&PlatformRepo->EtInfo; + } + for (Index =3D 0; Index < PLAT_CPU_COUNT; Index++) { PlatformRepo->GicCInfo[Index].TrbeInterrupt =3D TrbeInterrupt; + PlatformRepo->GicCInfo[Index].EtToken =3D EtToken; } =20 return EFI_SUCCESS; @@ -975,6 +988,18 @@ GetArmNameSpaceObject ( ); break; =20 + case EArmObjEtInfo: + if (Token =3D=3D (CM_OBJECT_TOKEN)&PlatformRepo->EtInfo) { + Status =3D HandleCmObject ( + CmObjectId, + &PlatformRepo->EtInfo, + sizeof (PlatformRepo->EtInfo), + 1, + CmObject + ); + } + break; + default: { Status =3D EFI_NOT_FOUND; DEBUG (( diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.h b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.h index 1b52c2ebc7efb633c748f7316606e3dbe4e0b21c..be2b512911f897dc57328673ae4= f4a2014ec20fb 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.h +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.h @@ -171,6 +171,8 @@ typedef struct PlatformRepositoryInfo { /// PCI configuration space information CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo; =20 + CM_ARM_ET_INFO EtInfo; + /// System ID UINT32 SysId; } EDKII_PLATFORM_REPOSITORY_INFO; --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)' -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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