[edk2-devel] [PATCH v5 0/7] Add RISC-V MMU support

Tuan Phan posted 7 patches 9 months, 2 weeks ago
Failed in applying to current master (apply log)
MdePkg/Include/Library/BaseLib.h              |   5 +
.../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
.../VirtNorFlashStaticLib.c                   |   3 +-
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf           |  10 +
OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h  |  68 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 730 ++++++++++++++++++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  27 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S    |  31 +
UefiCpuPkg/UefiCpuPkg.dec                     |   5 +
UefiCpuPkg/UefiCpuPkg.dsc                     |   1 +
17 files changed, 967 insertions(+), 22 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
[edk2-devel] [PATCH v5 0/7] Add RISC-V MMU support
Posted by Tuan Phan 9 months, 2 weeks ago
This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.

There are two parts:
1. Add MMU base library. MMU will be enabled during
CpuDxe initialization.
2. Fix all resources should be populated in HOB
or added to GCD by driver before accessing when MMU enabled.

All changes can be found in the branch tphan/riscv_mmu at:
https://github.com/pttuan/edk2.git

Changes in V5:
  - Rebased master.
  - Fix CI issue.

Changes in v4:
  - Rebased master.
  - Added VirtNorFlashDxe to APRIORI DXE list.

Changes in v3:
  - Move MMU library to UefiCpuPkg.
  - Add Andrei reviewed-by.

Changes in v2:
  - Move MMU core to a library.
  - Setup SATP mode as highest possible that HW supports.

Tuan Phan (7):
  MdePkg/BaseLib: RISC-V: Support getting satp register value
  MdePkg/Register: RISC-V: Add satp mode bits shift definition
  OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
  OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
    devices
  OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
  OvmfPkg: RiscVVirt: Remove satp bare mode setting
  UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode

 MdePkg/Include/Library/BaseLib.h              |   5 +
 .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
 .../VirtNorFlashStaticLib.c                   |   3 +-
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
 OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf           |  10 +
 OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
 OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
 UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h  |  68 ++
 .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 730 ++++++++++++++++++
 .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  27 +
 .../Library/BaseRiscVMmuLib/RiscVMmuCore.S    |  31 +
 UefiCpuPkg/UefiCpuPkg.dec                     |   5 +
 UefiCpuPkg/UefiCpuPkg.dsc                     |   1 +
 17 files changed, 967 insertions(+), 22 deletions(-)
 create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
 create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
 create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
 create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S

-- 
2.25.1



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