From nobody Tue May 21 03:17:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+106902+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106902+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1689240820; cv=none; d=zohomail.com; s=zohoarc; b=jaVhtwtbLTnBqTU+AA3wR8wqT3MXNJUTgW+RSRTQStmVgRDKzdMxnnf49JHMYBOSUrG+QCmvSUB2sM5IcC4YbCPeEoWp2os8TMynVogQpQ7yUFH+qwUg/TGDa79wj2euY91kJQKgnIjb8SYldyp5tG1hRGH+CPhid/1ItDKH7qg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1689240820; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wFTMTZD/DGyzdzH7cqZhzJ7XEo6fV46ySHxc+2Mvp/E=; b=EwV0t6VTxistW0hYtT32XA/Dr9JYsOw/H4XDNwYDmiMbsDGqyjzit8Q8fA500x+tZP0VK3hsZEzW9mNSucnUzy2Sx2sjwCs4qpZogZsW3bQn0HelGxGFw0iv89GnrB0CPEXRTwrivOsp3J4PfIMqAqcqvcvCuGy4jqvad+cg0w4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106902+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1689240820233573.4284730513227; Thu, 13 Jul 2023 02:33:40 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=01nPvIjkIpzhDA4j+9zRcxd5r2vW9cKdaK5DoRrWBFc=; c=relaxed/simple; d=groups.io; h=X-Received:X-Received:X-Received:X-Gm-Message-State:X-Google-Smtp-Source:X-Received:X-Received:From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Unsubscribe:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:Content-Transfer-Encoding; s=20140610; t=1689240819; v=1; b=jVlHd6BlZPXworXX7lCvdWCzs2CmVLAfvctabSh+dDiRPwa8YG4q3LPALazn874TW0P3HTYp FO8L1lUBcZ4MMHj2p/PoE3bXguF6lHwZdxRgDI0HXcnf32ZyUMfLY8BosTe2Iuh4Vy6sStTaOVs 7BKVgxaeBQAC8yQVe0rbIFZw= X-Received: by 127.0.0.2 with SMTP id v1L7YY1788612xa6iC0y1iUG; Thu, 13 Jul 2023 02:33:39 -0700 X-Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) by mx.groups.io with SMTP id smtpd.web10.4365.1689240819177824291 for ; Thu, 13 Jul 2023 02:33:39 -0700 X-Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-666eef03ebdso246859b3a.1 for ; Thu, 13 Jul 2023 02:33:39 -0700 (PDT) X-Gm-Message-State: J1mSM6wu4RTVuwlHGVzZiQZPx1787277AA= X-Google-Smtp-Source: APBJJlHXK8jlVTIDn1tdKCEwgI89CiSdCiJSAjGJ0tA62qnQL0Xn+e3cP2+pqnS7T4Mf64xrMczZzg== X-Received: by 2002:a05:6a20:4406:b0:131:b3fa:eaaa with SMTP id ce6-20020a056a20440600b00131b3faeaaamr453363pzb.61.1689240818388; Thu, 13 Jul 2023 02:33:38 -0700 (PDT) X-Received: from dhaval.blr.rivosinc.com ([49.249.129.34]) by smtp.gmail.com with ESMTPSA id d11-20020a170902b70b00b001b898595be7sm5431178pls.291.2023.07.13.02.33.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 02:33:38 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sunil V L , Andrei Warkentin Subject: [edk2-devel] [PATCH v4 1/1] MdePkg:Implement RISCV CMO Date: Thu, 13 Jul 2023 15:03:31 +0530 Message-Id: <20230713093331.267164-2-dhaval@rivosinc.com> In-Reply-To: <20230713093331.267164-1-dhaval@rivosinc.com> References: <20230713093331.267164-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1689240820687100005 Content-Type: text/plain; charset="utf-8" From: Dhaval Sharma Implementing code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs Notes: 1. CMO only supports block based Operations. Meaning complete cache flush/invd/clean Operations are not available. In that case we fallback on fence.i instructions. 2. Rely on the fact that platform init has initialized CMO and this implementation just checks if it is enabled. 3. In order to avoid compiler dependency injecting byte code. Test: 1. Ensured correct instructions are refelecting in asm 2. Able to boot platform with RiscVVirtQemu config 3. Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Sunil V L Cc: Andrei Warkentin Signed-off-by: Dhaval Sharma --- Notes: v4: - Removed CMO specific directory in Base Lib - Implemented compiler independent code for CMO - Merged CMO implementation with fence.i - Added logic to confirm CMO is enabled MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 4 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 200 ++++++++++++++++= ++-- MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 -- MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S | 64 +++++++ 5 files changed, 254 insertions(+), 37 deletions(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 03c7b02e828b..53389389448c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuBreakpoint.S | GCC RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC - RiscV64/FlushCache.S | GCC + RiscV64/RiscVCacheMgmt.S | GCC RiscV64/CpuScratch.S | GCC RiscV64/ReadTimer.S | GCC RiscV64/RiscVMmu.S | GCC diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..ea1493578bd5 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -85,6 +85,10 @@ /* Supervisor Configuration */ #define CSR_SENVCFG 0x10a =20 +/* Defined CBO bits*/ +#define SENVCFG_CBCFE 0x40UL +#define SENVCFG_CBIE 0x30UL + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..8b853e5b69fa 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -1,7 +1,8 @@ /** @file - RISC-V specific functionality for cache. + Implement Risc-V Cache Management Operations =20 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2023, Rivos Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -10,13 +11,21 @@ #include #include =20 +#define RV64_CACHE_BLOCK_SIZE 64 + +typedef enum { + Clean, + Flush, + Invld, +} CACHE_OP; + /** RISC-V invalidate instruction cache. =20 **/ VOID EFIAPI -RiscVInvalidateInstCacheAsm ( +RiscVInvalidateInstCacheAsm_Fence ( VOID ); =20 @@ -26,13 +35,144 @@ RiscVInvalidateInstCacheAsm ( **/ VOID EFIAPI -RiscVInvalidateDataCacheAsm ( +RiscVInvalidateDataCacheAsm_Fence ( VOID ); =20 +/** + RISC-V flush cache block. Atomically perform a clean operation + followed by an invalidate operation + +**/ +VOID +EFIAPI +RiscVCpuCacheFlushAsm_Cbo ( + UINTN + ); + +/** +Perform a write transfer to another cache or to memory if the +data in the copy of the cache block have been modified by a store +operation + +**/ +VOID +EFIAPI +RiscVCpuCacheCleanAsm_Cbo ( + UINTN + ); + +/** +Deallocate the copy of the cache block + +**/ +VOID +EFIAPI +RiscVCpuCacheInvalAsm_Cbo ( + UINTN + ); + +/** +Verify CBOs are supported by this HW +CBCFE =3D=3D Cache Block Clean and Flush instruction Enable +CBIE =3D=3D Cache Block Invalidate instruction Enable + +**/ +UINTN +RiscvIsCbcfeEnabledAsm ( + VOID + ); + +UINTN +RiscvIsCbiEnabledAsm ( + VOID + ); + +/** + Performs required opeartion on cache lines in the cache coherency domain + of the calling CPU. If Address is not aligned on a cache line boundary, + then entire cache line containing Address is operated. If Address + Leng= th + is not aligned on a cache line boundary, then the entire cache line + containing Address + Length -1 is operated. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the cache lines to + invalidate. If the CPU is in a physical addressing mode, + then Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction + cache. + + @param Op Type of CMO operation to be performed + + @return Address. + +**/ +VOID * +EFIAPI +CacheOpCacheRange ( + IN VOID *Address, + IN UINTN Length, + IN CACHE_OP Op + ) +{ + UINTN CacheLineSize; + UINTN Start; + UINTN End; + + if (Length =3D=3D 0) { + return Address; + } + + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address)); + + // + // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H + // + CacheLineSize =3D RV64_CACHE_BLOCK_SIZE; + + Start =3D (UINTN)Address; + // + // Calculate the cache line alignment + // + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1); + Start &=3D ~((UINTN)CacheLineSize - 1); + + DEBUG ( + (DEBUG_INFO, + "%a Performing Cache Management Operation %d \n", __func__, Op) + ); + + do { + switch (Op) { + case Invld: + RiscVCpuCacheInvalAsm_Cbo (Start); + break; + case Flush: + RiscVCpuCacheFlushAsm_Cbo (Start); + break; + case Clean: + RiscVCpuCacheCleanAsm_Cbo (Start); + break; + default: + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported operation\n")); + break; + } + + Start =3D Start + CacheLineSize; + } while (Start !=3D End); + + return Address; +} + /** Invalidates the entire instruction cache in cache coherency domain of the - calling CPU. + calling CPU. Risc-V does not have currently an CBO implementation which = can + invalidate entire I-cache. Hence using Fence instruction for now. P.S. F= ence + instruction may or may not implement full I-cache invd functionality on = all + implementations. =20 **/ VOID @@ -41,7 +181,7 @@ InvalidateInstructionCache ( VOID ) { - RiscVInvalidateInstCacheAsm (); + RiscVInvalidateInstCacheAsm_Fence (); } =20 /** @@ -76,12 +216,17 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - DEBUG ( - (DEBUG_WARN, - "%a:RISC-V unsupported function.\n" - "Invalidating the whole instruction cache instead.\n", __func__) - ); - InvalidateInstructionCache (); + if (RiscvIsCbiEnabledAsm () =3D=3D RETURN_SUCCESS) { + CacheOpCacheRange (Address, Length, Invld); + } else { + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__) + ); + InvalidateInstructionCache (); + } + return Address; } =20 @@ -137,7 +282,12 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscvIsCbcfeEnabledAsm () =3D=3D RETURN_SUCCESS) { + CacheOpCacheRange (Address, Length, Flush); + } else { + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + } + return Address; } =20 @@ -192,7 +342,12 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscvIsCbcfeEnabledAsm () =3D=3D RETURN_SUCCESS) { + CacheOpCacheRange (Address, Length, Clean); + } else { + DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + } + return Address; } =20 @@ -213,7 +368,12 @@ InvalidateDataCache ( VOID ) { - RiscVInvalidateDataCacheAsm (); + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__) + ); + RiscVInvalidateDataCacheAsm_Fence (); } =20 /** @@ -250,6 +410,16 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__)); + if (RiscvIsCbiEnabledAsm () =3D=3D RETURN_SUCCESS) { + CacheOpCacheRange (Address, Length, Invld); + } else { + DEBUG ( + (DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__) + ); + InvalidateDataCache (); + } + return Address; } diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/FlushCache.S deleted file mode 100644 index 7c10fdd268af..000000000000 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ /dev/null @@ -1,21 +0,0 @@ -//------------------------------------------------------------------------= ------ -// -// RISC-V cache operation. -// -// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
-// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------= ------ - -.align 3 -ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm) -ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) - -ASM_PFX(RiscVInvalidateInstCacheAsm): - fence.i - ret - -ASM_PFX(RiscVInvalidateDataCacheAsm): - fence - ret diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVCacheMgmt.S new file mode 100644 index 000000000000..ecf391632221 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -0,0 +1,64 @@ +//------------------------------------------------------------------------= ------ +// +// RISC-V cache operation. +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// Copyright (c) 2022, Rivos Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include + +.align 3 +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm_Fence) +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm_Fence) + +ASM_PFX(RiscVInvalidateInstCacheAsm_Fence): + fence.i + ret + +ASM_PFX(RiscVInvalidateDataCacheAsm_Fence): + fence + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsm_Cbo) +ASM_PFX (RiscVCpuCacheFlushAsm_Cbo): + + .long 0x0025200f + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsm_Cbo) +ASM_PFX (RiscVCpuCacheCleanAsm_Cbo): + .long 0x0015200f + ret + +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsm_Cbo) +ASM_PFX (RiscVCpuCacheInvalAsm_Cbo): + .long 0x0005200f + ret + +ASM_GLOBAL ASM_PFX(RiscvIsCbiEnabledAsm) +ASM_PFX(RiscvIsCbiEnabledAsm): + li a0, 3 + csrr a1, CSR_SENVCFG + and a1, a1, SENVCFG_CBIE + beqz a1, skip + + and a1, a1, 0x10 + beqz a1, skip + + mv a0, x0 +skip: + ret + +ASM_GLOBAL ASM_PFX(RiscvIsCbcfeEnabledAsm) +ASM_PFX(RiscvIsCbcfeEnabledAsm): + li a0, 3 + csrr a1, CSR_SENVCFG + and a1, a1, SENVCFG_CBCFE + beqz a1, next + + mv a0, x0 +next: + ret --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106902): https://edk2.groups.io/g/devel/message/106902 Mute This Topic: https://groups.io/mt/100117169/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-