From nobody Fri May 10 08:07:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+106303+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106303+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1687545670; cv=none; d=zohomail.com; s=zohoarc; b=Ia5BhLMbJ4/pd7mLToMlfI6dJ4pdzXofzq+y20cs1boQ4Nsy8VABWu3U0WSgZ9YceOAEXc+XScQSi/B7kezmOvsCG5N/KD63pooKVVv0cgiavhJXVnS0rEzgkKjt0RU3R6o4ehueDrIZLV3yPdfelzF7ygGAYv4EyfdlzdIfDIw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687545670; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4f4Bfh0HJB84iOk0FwcRIFiPQ2oElYqNrCKQMs7mNTk=; b=OCVvXYNYZOS3E87cZa/BXoqWnpyK+75SekOEJlkrvWGItOS2ri5e6QKXAwnHzqByoItphzeaCSiGlYheQLthgZlRsJgCDW9dIYrMt1FC884mzhHvgiygF7/KpQn70sFvA4IsrOLouA7lo4qMRt3fDCbIHHdynXTfDquaGgNG8tA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+106303+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16875456705901015.9475931580606; Fri, 23 Jun 2023 11:41:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 439wYY1788612xocUMIxI0xA; Fri, 23 Jun 2023 11:41:10 -0700 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web10.6042.1687545669519241004 for ; Fri, 23 Jun 2023 11:41:09 -0700 X-Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6686708c986so775933b3a.0 for ; Fri, 23 Jun 2023 11:41:09 -0700 (PDT) X-Gm-Message-State: Po5H41FLuCUlE3Pq38J9J0SDx1787277AA= X-Google-Smtp-Source: ACHHUZ4g9WbXhgBfptpagCkSfN6b8y0m6h1D8evRRk5fwuMuF6el8leQ0cjaeP5uMgZCai5nisyZTg== X-Received: by 2002:a05:6a20:748d:b0:10c:89cc:bc5f with SMTP id p13-20020a056a20748d00b0010c89ccbc5fmr26399384pzd.20.1687545668571; Fri, 23 Jun 2023 11:41:08 -0700 (PDT) X-Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:08 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Date: Fri, 23 Jun 2023 11:39:28 -0700 Message-Id: <20230623183934.23905-2-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545670; bh=QU7yY//9MdBURR8RQeYs74Al4GSMTp2hbW3bKxVmI1Y=; h=Cc:Date:From:Reply-To:Subject:To; b=cJOep0XoEHHyk8ExzRWyZIhZIsPezh8+dOIZZFy0gf7Eg3c+bpb7+TBdpM37+3kHm1f 1srd1pkqJ6YvAlUUQXP74ZwHKrLBxzMQ+nU57I1sXbSmrQ+QvG8E0vd/1PYRtq/2tVlgG LC493BeTnCUO/hCPhYzhjB+mX2fxa+LrSUc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545671079100005 Content-Type: text/plain; charset="utf-8" Add an API to retrieve satp register value. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- MdePkg/Include/Library/BaseLib.h | 5 +++++ MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); =20 +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/Bas= eLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) + csrr a0, CSR_SATP + ret --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:09 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Date: Fri, 23 Jun 2023 11:39:29 -0700 Message-Id: <20230623183934.23905-3-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545671; bh=V7cKv/LaMbRgmZZYqW2JEK/p6kcrR6Iu3EbuFfuvmd8=; h=Cc:Date:From:Reply-To:Subject:To; b=UYgNXMqAyrGukryOsCiioAzLCelVKj0Qcd5IQ1S1DDNJRqfLULRuZ9LaNxLeS7yvas9 VduQQevZx+s4KZOItELG5HV+lhZ8BieNdRcKZV75YH1QygBdumRJgzRTol0VRKe5JtFd7 /dpbldR63PNwZtRkqS9FCJjOQmYNFeOON3A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545673348100011 Content-Type: text/plain; charset="utf-8" The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L Reviewed-by: Michael D Kinney --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL =20 -#define SATP64_MODE 0xF000000000000000ULL -#define SATP64_ASID 0x0FFFF00000000000ULL -#define SATP64_PPN 0x00000FFFFFFFFFFFULL +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:10 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Date: Fri, 23 Jun 2023 11:39:30 -0700 Message-Id: <20230623183934.23905-4-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545672; bh=0rhb7KoY48rm+96HoY2Z2bPOUs3260B4mHbQLHANa1M=; h=Cc:Date:From:Reply-To:Subject:To; b=M2YnUs591k/jTBdbIKrsrABeYh/uQBSIfj4Pj2MjRD4Uhxcw+AD9qSthVb6JnsMTOx9 gkGxy/Zjl4JHxJcc5oL4m9FxocqkT1UOfZTxrNVbZeAYJTpT7xjoKhV4u7Jj3T3yulRUR Ro/dHTJWwhDSQ5u13ecI1OXV5iRGTUP2Zw0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545675329100015 Content-Type: text/plain; charset="utf-8" The size should be for single region, not the whole firmware FD. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- .../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlash= StaticLib.c b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlas= hStaticLib.c index fdc2ccb6294e..33f3a01b06f4 100644 --- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticL= ib.c +++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticL= ib.c @@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =3D { FixedPcdGet32 (PcdOvmfFdBaseAddress), FixedPcdGet64 (PcdFlashNvStorageVariableBase), - FixedPcdGet32 (PcdOvmfFirmwareFdSize), + FixedPcdGet32 (PcdOvmfFirmwareFdSize) - + (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32 (PcdOvmfF= dBaseAddress)), QEMU_NOR_BLOCK_SIZE }; =20 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:12 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Date: Fri, 23 Jun 2023 11:39:31 -0700 Message-Id: <20230623183934.23905-5-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545674; bh=CXeObUXLnlnP2t/ydaUVqTKiJJG/RBWtGj0c8fvBlXc=; h=Cc:Date:From:Reply-To:Subject:To; b=GmLmX2jq5hC5wdtBGaPpv4EpSvyCxlqFfaclnRSfry+qP3GwIm8DObbeDgsWVvZkCBb tBr/flrMWtvQNCxUjXCVwYTvf9gJVY71mjM3UZoB6GehKFlqT80f9oEEPTqEhm8YcNVGf RjsQ8hJM54mV385GPTORxVqFzxYQMUAVQbs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545675362100017 Content-Type: text/plain; charset="utf-8" Normally, DXE driver would add device resource to GCD before start using. But some key resources such as uart used for printing info at very early stage. Those resources should be populated to HOB in SEC phase so they are added to GCD before MMU enabled. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platf= orm.c index 3645c27b0b12..c66432473067 100644 --- a/OvmfPkg/RiscVVirt/Sec/Platform.c +++ b/OvmfPkg/RiscVVirt/Sec/Platform.c @@ -21,6 +21,64 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include =20 +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +STATIC +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + /* Align to EFI_PAGE_SIZE */ + MemorySize =3D ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Populate IO resources from FDT that not added to GCD by its + driver in the DXE phase. + + @param FdtBase Fdt base address + @param Compatible Compatible string + +**/ +STATIC +VOID +PopulateIoResources ( + VOID *FdtBase, + CONST CHAR8 *Compatible + ) +{ + UINT64 *Reg; + INT32 Node, LenP; + + Node =3D fdt_node_offset_by_compatible (FdtBase, -1, Compatible); + while (Node !=3D -FDT_ERR_NOTFOUND) { + Reg =3D (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP); + if (Reg) { + ASSERT (LenP =3D=3D (2 * sizeof (UINT64))); + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1])); + } + + Node =3D fdt_node_offset_by_compatible (FdtBase, Node, Compatible); + } +} + /** @retval EFI_SUCCESS The address of FDT is passed in HOB. EFI_UNSUPPORTED Can't locate FDT. @@ -80,5 +138,9 @@ PlatformPeimInitialization ( =20 BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSiz= e)); =20 + PopulateIoResources (Base, "ns16550a"); + PopulateIoResources (Base, "qemu,fw-cfg-mmio"); + PopulateIoResources (Base, "virtio,mmio"); + return EFI_SUCCESS; } --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:13 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Date: Fri, 23 Jun 2023 11:39:32 -0700 Message-Id: <20230623183934.23905-6-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545675; bh=p5a4WQMnCcOU7OW/sEI84YxYuAjCqAfNk5eyEsB46ds=; h=Cc:Date:From:Reply-To:Subject:To; b=uh+Rhfu7XSMIdNCZ/KhjjEA72eYAKZpvJ6leGxJyVC07cD8YNI9FzUUz4iqIAbdVNkc Ji4olJEC7vpHOIXwV57nf4vcllzhEcSdvYC2DgKBX2ZJ9VsyXZzg8niIC0J07oPPuTSj0 H13ZHepwPau8G/viRFZhq0wzTZIE7ZN/Nro= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545677131100021 Content-Type: text/plain; charset="utf-8" Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it is the backend flash driver. Signed-off-by: Tuan Phan Reviewed-by: Sunil V L --- OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVV= irtQemu.fdf index 21e4ba67379f..9ab8eb3ba7d8 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -53,6 +53,16 @@ READ_STATUS =3D TRUE READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE =20 +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf +} + # # DXE Phase modules # --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:15 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting Date: Fri, 23 Jun 2023 11:39:33 -0700 Message-Id: <20230623183934.23905-7-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545677; bh=BxwkzL8P7+Qpc+jzM18XKzumWf8RoFGfvsIgOZnownw=; h=Cc:Date:From:Reply-To:Subject:To; b=Uwrq2PvZDSWd1Wx9SzJFasGu4IPdL1CpCBrQDMQ2CZ4sdVObEJClqjgV6sVhIEx22+3 o0/etWk+DdTp8sU4e94FR6lDf3I2SR8aEfgkJlzQFPdU0DxxkTb/Fop5LN6ljAGmhZaYO CluXNaOH6xc2d9TqofbNCqr55QcXXdPOCak= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545679125100025 Content-Type: text/plain; charset="utf-8" There is no point to set satp to bare mode as that should be the default mode when booting edk2. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c index 0e2690c73687..aad71ee5dcbb 100644 --- a/OvmfPkg/RiscVVirt/Sec/Memory.c +++ b/OvmfPkg/RiscVVirt/Sec/Memory.c @@ -85,21 +85,6 @@ AddMemoryRangeHob ( AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); } =20 -/** - Configure MMU -**/ -STATIC -VOID -InitMmu ( - ) -{ - // - // Set supervisor translation mode to Bare mode - // - RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 6= 0); - DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.= \n", __func__)); -} - /** Publish system RAM and reserve memory regions. =20 @@ -327,7 +312,8 @@ MemoryPeimInitialization ( =20 AddReservedMemoryMap (FdtPointer); =20 - InitMmu (); + /* Make sure SEC is booting with bare mode */ + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) = =3D=3D (SATP_MODE_OFF << SATP64_MODE_SHIFT)); =20 BuildMemoryTypeInformationHob (); =20 --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:16 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [edk2-devel] [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Date: Fri, 23 Jun 2023 11:39:34 -0700 Message-Id: <20230623183934.23905-8-tphan@ventanamicro.com> In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1687545679; bh=M3pXtJFCG68UNuEiSfde7qusuwaHqCNnH1mm133QX6k=; h=Cc:Date:From:Reply-To:Subject:To; b=JiTXdWEcrVbQDm4SfPZRzWDivQ11JsHiKrurhgnniilGWMcxDtGjZst5apf/fV7IAm9 iMrJjevKpQwD+br5FN6yBiMX9MJDUiX8jpjvgq7tf28Gprx2AtxBGPqisrlxPSZGWZDAX LN89Jno1ZqyFj5jplrQexdd9tpV4sO7HxDY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1687545680110100029 Content-Type: text/plain; charset="utf-8" During CpuDxe initialization, MMU will be setup with the highest mode that HW supports. Reviewed-by: Andrei Warkentin Signed-off-by: Tuan Phan Reviewed-by: Sunil V L --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + 8 files changed, 677 insertions(+), 2 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc index 731f54f73f81..bc204ba5fe52 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -83,6 +83,7 @@ # RISC-V Architectural Libraries CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/= PlatformBootManagerLib.inf ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemL= ib.inf =20 diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/C= puDxe.c index 25fe3f54c325..2af3b6223450 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -296,8 +296,7 @@ CpuSetMemoryAttributes ( IN UINT64 Attributes ) { - DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __f= unc__)); - return EFI_SUCCESS; + return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes); } =20 /** @@ -340,6 +339,12 @@ InitializeCpu ( // DisableInterrupts (); =20 + // + // Enable MMU + // + Status =3D RiscVConfigureMmu (); + ASSERT_EFI_ERROR (Status); + // // Install Boot protocol // diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/C= puDxe.h index 49f4e119665a..68e6d038b66e 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -15,11 +15,13 @@ #include #include #include +#include #include #include #include #include #include +#include =20 /** Flush CPU data cache. If the instruction cache is fully coherent diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxe= RiscV64/CpuDxeRiscV64.inf index e8fa25446aef..6d52085df0d5 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf @@ -37,6 +37,8 @@ TimerLib PeCoffGetEntryPointLib RiscVSbiLib + RiscVMmuLib + CacheMaintenanceLib =20 [Sources] CpuDxe.c diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h b/UefiCpuPkg/Incl= ude/Library/BaseRiscVMmuLib.h new file mode 100644 index 000000000000..f71d6a4a1e7b --- /dev/null +++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h @@ -0,0 +1,39 @@ +/** @file + + Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef BASE_RISCV_MMU_LIB_H_ +#define BASE_RISCV_MMU_LIB_H_ + +VOID +EFIAPI +RiscVLocalTlbFlushAll ( + VOID + ); + +VOID +EFIAPI +RiscVLocalTlbFlush ( + UINTN VirtAddr + ); + +EFI_STATUS +EFIAPI +RiscVSetMemoryAttributes ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN UINT64 Attributes + ); + +EFI_STATUS +EFIAPI +RiscVConfigureMmu ( + VOID + ); + +#endif /* BASE_RISCV_MMU_LIB_H_ */ diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpu= Pkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c new file mode 100644 index 000000000000..e6841b793bfc --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c @@ -0,0 +1,569 @@ +/** @file +* MMU implementation for RISC-V +* +* Copyright (c) 2011-2020, ARM Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RISCV_PG_V BIT0 +#define RISCV_PG_R BIT1 +#define RISCV_PG_W BIT2 +#define RISCV_PG_X BIT3 +#define RISCV_PG_G BIT5 +#define RISCV_PG_A BIT6 +#define RISCV_PG_D BIT7 +#define PTE_ATTRIBUTES_MASK 0xE + +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL +#define PTE_PPN_SHIFT 10 +#define RISCV_MMU_PAGE_SHIFT 12 + +STATIC UINTN mMaxRootTableLevel; +STATIC UINTN mBitPerLevel; +STATIC UINTN mTableEntryCount; + +STATIC +BOOLEAN +RiscVMmuEnabled ( + VOID + ) +{ + return ((RiscVGetSupervisorAddressTranslationRegister () & + SATP64_MODE) !=3D (SATP_MODE_OFF << SATP64_MODE_SHIFT)); +} + +STATIC +UINTN +RiscVGetRootTranslateTable ( + VOID + ) +{ + return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) << + RISCV_MMU_PAGE_SHIFT; +} + +STATIC +BOOLEAN +IsValidPte ( + IN UINTN Entry + ) +{ + if (!(Entry & RISCV_PG_V) || + (((Entry & (RISCV_PG_R | RISCV_PG_W)) =3D=3D RISCV_PG_W))) + { + return FALSE; + } + + return TRUE; +} + +STATIC +UINTN +SetValidPte ( + IN UINTN Entry + ) +{ + /* Set Valid and Global mapping bits */ + return Entry | RISCV_PG_G | RISCV_PG_V; +} + +STATIC +BOOLEAN +IsBlockEntry ( + IN UINTN Entry + ) +{ + return IsValidPte (Entry) && + (Entry & (RISCV_PG_X | RISCV_PG_R)); +} + +STATIC +BOOLEAN +IsTableEntry ( + IN UINTN Entry + ) +{ + return IsValidPte (Entry) && + !IsBlockEntry (Entry); +} + +STATIC +UINTN +SetTableEntry ( + IN UINTN Entry + ) +{ + Entry =3D SetValidPte (Entry); + Entry &=3D ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R); + + return Entry; +} + +STATIC +VOID +ReplaceTableEntry ( + IN UINTN *Entry, + IN UINTN Value, + IN UINTN RegionStart, + IN BOOLEAN IsLiveBlockMapping + ) +{ + *Entry =3D Value; + + if (IsLiveBlockMapping && RiscVMmuEnabled ()) { + RiscVLocalTlbFlush (RegionStart); + } +} + +STATIC +UINTN +GetPpnfromPte ( + UINTN Entry, + UINTN Level + ) +{ + return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT); +} + +STATIC +UINTN +SetPpnToPte ( + UINTN Entry, + UINTN Address, + UINTN Level + ) +{ + UINTN Ppn; + + Ppn =3D ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT); + ASSERT (~(Ppn & ~PTE_PPN_MASK)); + Entry &=3D ~PTE_PPN_MASK; + return Entry | Ppn; +} + +STATIC +VOID +FreePageTablesRecursive ( + IN UINTN *TranslationTable, + IN UINTN Level + ) +{ + UINTN Index; + + if (Level < mMaxRootTableLevel - 1) { + for (Index =3D 0; Index < mTableEntryCount; Index++) { + if (IsTableEntry (TranslationTable[Index])) { + FreePageTablesRecursive ( + (UINTN *)(GetPpnfromPte ((TranslationTable[Index]), Level) << + RISCV_MMU_PAGE_SHIFT), + Level + 1 + ); + } + } + } + + FreePages (TranslationTable, 1); +} + +STATIC +EFI_STATUS +UpdateRegionMappingRecursive ( + IN UINTN RegionStart, + IN UINTN RegionEnd, + IN UINTN AttributeSetMask, + IN UINTN AttributeClearMask, + IN UINTN *PageTable, + IN UINTN Level, + IN BOOLEAN TableIsLive + ) +{ + EFI_STATUS Status; + UINTN BlockShift; + UINTN BlockMask; + UINTN BlockEnd; + UINTN *Entry; + UINTN EntryValue; + UINTN *TranslationTable; + BOOLEAN NextTableIsLive; + + ASSERT (Level < mMaxRootTableLevel); + ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) =3D=3D 0); + + BlockShift =3D (mMaxRootTableLevel - Level - 1) * mBitPerLevel + RISCV_M= MU_PAGE_SHIFT; + BlockMask =3D MAX_ADDRESS >> (64 - BlockShift); + + DEBUG ( + ( + DEBUG_VERBOSE, + "%a(%d): %llx - %llx set %lx clr %lx\n", + __func__, + Level, + RegionStart, + RegionEnd, + AttributeSetMask, + AttributeClearMask + ) + ); + + for ( ; RegionStart < RegionEnd; RegionStart =3D BlockEnd) { + BlockEnd =3D MIN (RegionEnd, (RegionStart | BlockMask) + 1); + Entry =3D &PageTable[(RegionStart >> BlockShift) & (mTableEntryCoun= t - 1)]; + + // + // If RegionStart or BlockEnd is not aligned to the block size at this + // level, we will have to create a table mapping in order to map less + // than a block, and recurse to create the block or page entries at + // the next level. No block mappings are allowed at all at level 0, + // so in that case, we have to recurse unconditionally. + // + if ((Level =3D=3D 0) || + (((RegionStart | BlockEnd) & BlockMask) !=3D 0) || IsTableEntry (*= Entry)) + { + ASSERT (Level < mMaxRootTableLevel - 1); + if (!IsTableEntry (*Entry)) { + // + // No table entry exists yet, so we need to allocate a page table + // for the next level. + // + TranslationTable =3D AllocatePages (1); + if (TranslationTable =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (TranslationTable, EFI_PAGE_SIZE); + + if (IsBlockEntry (*Entry)) { + // + // We are splitting an existing block entry, so we have to popul= ate + // the new table with the attributes of the block entry it repla= ces. + // + Status =3D UpdateRegionMappingRecursive ( + RegionStart & ~BlockMask, + (RegionStart | BlockMask) + 1, + *Entry & PTE_ATTRIBUTES_MASK, + PTE_ATTRIBUTES_MASK, + TranslationTable, + Level + 1, + FALSE + ); + if (EFI_ERROR (Status)) { + // + // The range we passed to UpdateRegionMappingRecursive () is b= lock + // aligned, so it is guaranteed that no further pages were all= ocated + // by it, and so we only have to free the page we allocated he= re. + // + FreePages (TranslationTable, 1); + return Status; + } + } + + NextTableIsLive =3D FALSE; + } else { + TranslationTable =3D (UINTN *)(GetPpnfromPte (*Entry, Level) << RI= SCV_MMU_PAGE_SHIFT); + NextTableIsLive =3D TableIsLive; + } + + // + // Recurse to the next level + // + Status =3D UpdateRegionMappingRecursive ( + RegionStart, + BlockEnd, + AttributeSetMask, + AttributeClearMask, + TranslationTable, + Level + 1, + NextTableIsLive + ); + if (EFI_ERROR (Status)) { + if (!IsTableEntry (*Entry)) { + // + // We are creating a new table entry, so on failure, we can free= all + // allocations we made recursively, given that the whole subhier= archy + // has not been wired into the live page tables yet. (This is not + // possible for existing table entries, since we cannot revert t= he + // modifications we made to the subhierarchy it represents.) + // + FreePageTablesRecursive (TranslationTable, Level + 1); + } + + return Status; + } + + if (!IsTableEntry (*Entry)) { + EntryValue =3D SetPpnToPte (0, (UINTN)TranslationTable, Level); + EntryValue =3D SetTableEntry (EntryValue); + ReplaceTableEntry ( + Entry, + EntryValue, + RegionStart, + TableIsLive + ); + } + } else { + EntryValue =3D (*Entry & ~AttributeClearMask) | AttributeSetMask; + // + // We don't have page fault exception handler when a virtual page is= accessed and + // the A bit is clear, or is written and the D bit is clear. + // So just set A for read and D for write permission. + // + if (AttributeSetMask & RISCV_PG_R) { + EntryValue |=3D RISCV_PG_A; + } + + if (AttributeSetMask & RISCV_PG_W) { + EntryValue |=3D RISCV_PG_D; + } + + EntryValue =3D SetPpnToPte (EntryValue, RegionStart, Level); + EntryValue =3D SetValidPte (EntryValue); + ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive); + } + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +UpdateRegionMapping ( + IN UINTN RegionStart, + IN UINTN RegionLength, + IN UINTN AttributeSetMask, + IN UINTN AttributeClearMask, + IN UINTN *RootTable, + IN BOOLEAN TableIsLive + ) +{ + if (((RegionStart | RegionLength) & EFI_PAGE_MASK) !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + return UpdateRegionMappingRecursive ( + RegionStart, + RegionStart + RegionLength, + AttributeSetMask, + AttributeClearMask, + RootTable, + 0, + TableIsLive + ); +} + +STATIC +UINTN +GcdAttributeToPageAttribute ( + IN UINTN GcdAttributes + ) +{ + UINTN RiscVAttributes =3D RISCV_PG_R | RISCV_PG_W | RISCV_PG_X; + + // Determine protection attributes + if (GcdAttributes & EFI_MEMORY_RO) { + RiscVAttributes &=3D ~(RISCV_PG_W); + } + + // Process eXecute Never attribute + if (GcdAttributes & EFI_MEMORY_XP) { + RiscVAttributes &=3D ~RISCV_PG_X; + } + + return RiscVAttributes; +} + +EFI_STATUS +EFIAPI +RiscVSetMemoryAttributes ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINTN Length, + IN UINTN Attributes + ) +{ + UINTN PageAttributesSet =3D GcdAttributeToPageAttribute (Attributes); + + if (!RiscVMmuEnabled ()) { + return EFI_SUCCESS; + } + + DEBUG ( + ( + DEBUG_VERBOSE, + "%a: Set %llX page attribute 0x%X\n", + __func__, + BaseAddress, + PageAttributesSet + ) + ); + + return UpdateRegionMapping ( + BaseAddress, + Length, + PageAttributesSet, + PTE_ATTRIBUTES_MASK, + (UINTN *)RiscVGetRootTranslateTable (), + TRUE + ); +} + +STATIC +EFI_STATUS +RiscVMmuSetSatpMode ( + UINTN SatpMode + ) +{ + VOID *TranslationTable; + UINTN SatpReg; + UINTN Ppn; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap; + UINTN NumberOfDescriptors; + UINTN Index; + EFI_STATUS Status; + + switch (SatpMode) { + case SATP_MODE_OFF: + return EFI_SUCCESS; + case SATP_MODE_SV39: + mMaxRootTableLevel =3D 3; + mBitPerLevel =3D 9; + mTableEntryCount =3D 512; + break; + case SATP_MODE_SV48: + mMaxRootTableLevel =3D 4; + mBitPerLevel =3D 9; + mTableEntryCount =3D 512; + break; + case SATP_MODE_SV57: + mMaxRootTableLevel =3D 5; + mBitPerLevel =3D 9; + mTableEntryCount =3D 512; + break; + default: + return EFI_INVALID_PARAMETER; + } + + // Allocate pages for translation table + TranslationTable =3D AllocatePages (1); + if (TranslationTable =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (TranslationTable, mTableEntryCount * sizeof (UINTN)); + + NumberOfDescriptors =3D 0; + MemoryMap =3D NULL; + Status =3D gDS->GetMemorySpaceMap ( + &NumberOfDescriptors, + &MemoryMap + ); + ASSERT_EFI_ERROR (Status); + + for (Index =3D 0; Index < NumberOfDescriptors; Index++) { + if (MemoryMap[Index].GcdMemoryType =3D=3D EfiGcdMemoryTypeMemoryMapped= Io) { + // Default Read/Write attribute for memory mapped IO + UpdateRegionMapping ( + MemoryMap[Index].BaseAddress, + MemoryMap[Index].Length, + RISCV_PG_R | RISCV_PG_W, + PTE_ATTRIBUTES_MASK, + TranslationTable, + FALSE + ); + } else if (MemoryMap[Index].GcdMemoryType =3D=3D EfiGcdMemoryTypeSyste= mMemory) { + // Default Read/Write/Execute attribute for system memory + UpdateRegionMapping ( + MemoryMap[Index].BaseAddress, + MemoryMap[Index].Length, + RISCV_PG_R | RISCV_PG_W | RISCV_PG_X, + PTE_ATTRIBUTES_MASK, + TranslationTable, + FALSE + ); + } + } + + FreePool ((VOID *)MemoryMap); + + if (GetInterruptState ()) { + DisableInterrupts (); + } + + Ppn =3D (UINTN)TranslationTable >> RISCV_MMU_PAGE_SHIFT; + ASSERT (!(Ppn & ~(SATP64_PPN))); + + SatpReg =3D Ppn; + SatpReg |=3D (SatpMode << + SATP64_MODE_SHIFT) & SATP64_MODE; + RiscVSetSupervisorAddressTranslationRegister (SatpReg); + /* Check if HW support the setup satp mode */ + if (SatpReg !=3D RiscVGetSupervisorAddressTranslationRegister ()) { + DEBUG ( + ( + DEBUG_VERBOSE, + "%a: HW does not support SATP mode:%d\n", + __func__, + SatpMode + ) + ); + FreePageTablesRecursive (TranslationTable, 0); + return EFI_DEVICE_ERROR; + } + + RiscVLocalTlbFlushAll (); + + if (GetInterruptState ()) { + EnableInterrupts (); + } + + return Status; +} + +EFI_STATUS +EFIAPI +RiscVConfigureMmu ( + VOID + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + INTN ModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MOD= E_SV39 }; + INTN Idx; + + /* Try to setup MMU with highest mode as possible */ + for (Idx =3D 0; Idx < ARRAY_SIZE (ModeSupport); Idx++) { + Status =3D RiscVMmuSetSatpMode (ModeSupport[Idx]); + if (Status =3D=3D EFI_DEVICE_ERROR) { + continue; + } else if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ( + ( + DEBUG_INFO, + "%a: SATP mode %d successfully configured\n", + __func__, + ModeSupport[Idx] + ) + ); + break; + } + + return Status; +} diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiC= puPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf new file mode 100644 index 000000000000..2819c871b2a2 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf @@ -0,0 +1,26 @@ +## @file +# +# Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001b + BASE_NAME =3D BaseRiscVMmuLib + FILE_GUID =3D d3bc42ee-c9eb-4339-ba11-06747083d3ae + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVMmuLib + +[Sources] + BaseRiscVMmuLib.c + RiscVMmuCore.S + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S b/UefiCpuPkg= /Library/BaseRiscVMmuLib/RiscVMmuCore.S new file mode 100644 index 000000000000..42eec4cbdf83 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S @@ -0,0 +1,31 @@ +/** @file +* +* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +.text + .align 3 + +// +// Local tlb flush all. +// +// +ASM_FUNC (RiscVLocalTlbFlushAll) +sfence.vma +ret + +// +// Local tlb flush at a virtual address +// @retval a0 : virtual address. +// +ASM_FUNC ( + RiscVLocalTlbFlush + ) +sfence.vma a0 +ret --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106309): https://edk2.groups.io/g/devel/message/106309 Mute This Topic: https://groups.io/mt/99724481/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-