Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + 1 file changed, 1 insertion(+)
From: Hunter Chang <hunter.chang@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4371
Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec
gEndOfSiInitPpiGuid indicates the end of all of the silicon init.
Add it to IntellSiliconPkg for AFP improvement.
Signed-off-by: Hunter Chang <hunter.chang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Tina Chen <tina.chen@intel.com>
Cc: Arthur Chen <arthur.g.chen@intel.com>
---
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 +
1 file changed, 1 insertion(+)
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index ec8690a8d6..c540ef40ad 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -113,6 +113,7 @@
gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }
gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } }
gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1D, 0x10, 0x38, 0xF3, 0x68, 0xF2 }}
+ gEndOfSiInitPpiGuid = { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88 }}
[Protocols]
## Protocols that provide services for the Intel(R) PCH SPI Host Controller Compatibility Interface
--
2.26.2.windows.1
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Reviewed-by: Isaac Oram <isaac.w.oram@intel.com> -----Original Message----- From: Chang, Hunter <hunter.chang@intel.com> Sent: Tuesday, June 13, 2023 5:40 AM To: devel@edk2.groups.io Cc: Chang, Hunter <hunter.chang@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Chen, Tina <tina.chen@intel.com>; Chen, Arthur G <arthur.g.chen@intel.com> Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC file From: Hunter Chang <hunter.chang@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4371 Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec gEndOfSiInitPpiGuid indicates the end of all of the silicon init. Add it to IntellSiliconPkg for AFP improvement. Signed-off-by: Hunter Chang <hunter.chang@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Tina Chen <tina.chen@intel.com> Cc: Arthur Chen <arthur.g.chen@intel.com> --- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec index ec8690a8d6..c540ef40ad 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -113,6 +113,7 @@ gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1D, 0x10, 0x38, 0xF3, 0x68, 0xF2 }}+ gEndOfSiInitPpiGuid = { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} [Protocols] ## Protocols that provide services for the Intel(R) PCH SPI Host Controller Compatibility Interface-- 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106581): https://edk2.groups.io/g/devel/message/106581 Mute This Topic: https://groups.io/mt/99504366/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Is this event signaled regardless of FSP API/Dispatch mode? > -----Original Message----- > From: Chang, Hunter <hunter.chang@intel.com> > Sent: Tuesday, June 13, 2023 8:40 PM > To: devel@edk2.groups.io > Cc: Chang, Hunter <hunter.chang@intel.com>; Ni, Ray <ray.ni@intel.com>; > Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W > <isaac.w.oram@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Chen, Tina > <tina.chen@intel.com>; Chen, Arthur G <arthur.g.chen@intel.com> > Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC > file > > From: Hunter Chang <hunter.chang@intel.com> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4371 > > Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec > gEndOfSiInitPpiGuid indicates the end of all of the silicon init. > Add it to IntellSiliconPkg for AFP improvement. > > Signed-off-by: Hunter Chang <hunter.chang@intel.com> > > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> > Cc: Isaac Oram <isaac.w.oram@intel.com> > Cc: Ashraf Ali S <ashraf.ali.s@intel.com> > Cc: Tina Chen <tina.chen@intel.com> > Cc: Arthur Chen <arthur.g.chen@intel.com> > --- > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index ec8690a8d6..c540ef40ad 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -113,6 +113,7 @@ > gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, > 0xaf, 0x2b, 0x25, 0x68, 0x4a } } > > gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, > 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } > > gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1D, > 0x10, 0x38, 0xF3, 0x68, 0xF2 }} > > + gEndOfSiInitPpiGuid = { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2E, > 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} > > > > [Protocols] > > ## Protocols that provide services for the Intel(R) PCH SPI Host Controller > Compatibility Interface > > -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106061): https://edk2.groups.io/g/devel/message/106061 Mute This Topic: https://groups.io/mt/99504366/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076/xyzzy [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
currently it is signaled in both API/Dispatch mode. -----Original Message----- From: Ni, Ray <ray.ni@intel.com> Sent: Tuesday, June 13, 2023 10:15 PM To: Chang, Hunter <hunter.chang@intel.com>; devel@edk2.groups.io Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Chen, Tina <tina.chen@intel.com>; Chen, Arthur G <arthur.g.chen@intel.com> Subject: RE: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC file Is this event signaled regardless of FSP API/Dispatch mode? > -----Original Message----- > From: Chang, Hunter <hunter.chang@intel.com> > Sent: Tuesday, June 13, 2023 8:40 PM > To: devel@edk2.groups.io > Cc: Chang, Hunter <hunter.chang@intel.com>; Ni, Ray > <ray.ni@intel.com>; Chaganty, Rangasai V > <rangasai.v.chaganty@intel.com>; Oram, Isaac W > <isaac.w.oram@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; > Chen, Tina <tina.chen@intel.com>; Chen, Arthur G > <arthur.g.chen@intel.com> > Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid > definition in DEC file > > From: Hunter Chang <hunter.chang@intel.com> > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4371 > > Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec > gEndOfSiInitPpiGuid indicates the end of all of the silicon init. > Add it to IntellSiliconPkg for AFP improvement. > > Signed-off-by: Hunter Chang <hunter.chang@intel.com> > > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> > Cc: Isaac Oram <isaac.w.oram@intel.com> > Cc: Ashraf Ali S <ashraf.ali.s@intel.com> > Cc: Tina Chen <tina.chen@intel.com> > Cc: Arthur Chen <arthur.g.chen@intel.com> > --- > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index ec8690a8d6..c540ef40ad 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -113,6 +113,7 @@ > gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, > 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } > > gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { > 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } > > gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, > 0x1D, 0x10, 0x38, 0xF3, 0x68, 0xF2 }} > > + gEndOfSiInitPpiGuid = { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, > + 0x2E, > 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} > > > > [Protocols] > > ## Protocols that provide services for the Intel(R) PCH SPI Host > Controller Compatibility Interface > > -- > 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106070): https://edk2.groups.io/g/devel/message/106070 Mute This Topic: https://groups.io/mt/99504366/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> -----Original Message----- From: Chang, Hunter <hunter.chang@intel.com> Sent: Tuesday, June 13, 2023 6:10 PM To: devel@edk2.groups.io Cc: Chang, Hunter <hunter.chang@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Chen, Tina <tina.chen@intel.com>; Chen, Arthur G <arthur.g.chen@intel.com> Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC file From: Hunter Chang <hunter.chang@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4371 Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec gEndOfSiInitPpiGuid indicates the end of all of the silicon init. Add it to IntellSiliconPkg for AFP improvement. Signed-off-by: Hunter Chang <hunter.chang@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Isaac Oram <isaac.w.oram@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Tina Chen <tina.chen@intel.com> Cc: Arthur Chen <arthur.g.chen@intel.com> --- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec index ec8690a8d6..c540ef40ad 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -113,6 +113,7 @@ gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } } gIntelDieInfoPpiGuid = { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1D, 0x10, 0x38, 0xF3, 0x68, 0xF2 }}+ gEndOfSiInitPpiGuid = { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88 }} [Protocols] ## Protocols that provide services for the Intel(R) PCH SPI Host Controller Compatibility Interface-- 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106060): https://edk2.groups.io/g/devel/message/106060 Mute This Topic: https://groups.io/mt/99504366/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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