From nobody Sun May 19 10:01:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104759+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104759+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683864955; cv=none; d=zohomail.com; s=zohoarc; b=lv8celnKdkM6Wckdj1wkfEpSKxo+/8534nMKGeW2a0KADXI5B8wkpX7XjiU1yZ8Ax5b4ZHrGBmrJp2p+Uhul8RKtidJt9BGU9bUBt8lqYfCCLRuG+Hn9xVlYWMIYlxMy7T/fjDv6gkSSo0GTexfftvWozhQq/3uR8by6AjSm9Fw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683864955; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=EO3HjgzV12Y3clvo3M/Zx8Dp8y9wuQjnyQEX3ed6x2w=; b=idd4MvLaHQ/N5muZnlVkjHMTAVznEldUSvAq5NjkSp6Ios6RclxZ/QfIcWkz9JCgFz6NadYWV5DHTYqif3rj3Y4bSmI6+UxaEAmB1WJBRq98KnQa1lJ9qTSSbZz6W5XqGjHLEKNuRZ9HA1oQu3V6RIt45R5Kli2xWACDaaC1has= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104759+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683864955349573.760702776559; Thu, 11 May 2023 21:15:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XQFoYY1788612xcLjNL8VGEj; Thu, 11 May 2023 21:15:55 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:54 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193828" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193828" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658295" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658295" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:52 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 1/5] UefiCpuPkg/SecCore: Migrate page table to permanent memory Date: Fri, 12 May 2023 12:15:44 +0800 Message-Id: <20230512041548.6416-2-jiaxin.wu@intel.com> In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: 7xc7xZSKKS3D3KvGr3m5VOZbx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683864955; bh=zDnGz7qeHtcBhT798jKumWPEbOTf93UGdUixp5V1oIU=; h=Cc:Date:From:Reply-To:Subject:To; b=gtJr832yTNwcyyQ2OCoimzu3/2GGfLQd1iC/Do2+QOHbbEoBBglgpl9gBo76pjA1I4I DuuTB4VyN4tZ26xW3qp8AZa6T837uDh3Fo2ECQ7uuNP8Xu2HIn9Dq8jcuH3gV8tHPUbov lEjEzQN3W3YNJL9d/Fn71/kmZZdaLZMo8N4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683864957210100007 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Background: For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code). Existi= ng code doesn't cover the higher address access above 512G before memory-disco= vered callback. That will be potential problem if system access the higher address after the transition from temporary RAM to permanent MEM RAM. Solution: This patch is to migrate page table to permanent memory to map entire physi= cal address space if CR0.PG is set during temporary RAM Done. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 152 +++++++++++++++++++++++++++++++= ++++ UefiCpuPkg/SecCore/SecMain.h | 4 + 4 files changed, 158 insertions(+) diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf index 3758aded3b..cab69b8b97 100644 --- a/UefiCpuPkg/SecCore/SecCore.inf +++ b/UefiCpuPkg/SecCore/SecCore.inf @@ -53,10 +53,11 @@ CpuExceptionHandlerLib ReportStatusCodeLib PeiServicesLib PeiServicesTablePointerLib HobLib + CpuPageTableLib =20 [Ppis] ## SOMETIMES_CONSUMES ## PRODUCES gEfiSecPlatformInformationPpiGuid diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecC= oreNative.inf index 1ee6ff7d88..fa241cca94 100644 --- a/UefiCpuPkg/SecCore/SecCoreNative.inf +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf @@ -50,10 +50,11 @@ CpuExceptionHandlerLib ReportStatusCodeLib PeiServicesLib PeiServicesTablePointerLib HobLib + CpuPageTableLib =20 [Ppis] ## SOMETIMES_CONSUMES ## PRODUCES gEfiSecPlatformInformationPpiGuid diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 95375850ec..8ec0b654fb 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -70,10 +70,139 @@ MigrateGdt ( AsmWriteGdtr (&Gdtr); =20 return EFI_SUCCESS; } =20 +/** + Migrate page table to permanent memory mapping entire physical address s= pace. + + @retval EFI_SUCCESS The PageTable was migrated successfully. + @retval EFI_UNSUPPORTED Unsupport to migrate page table to perma= nent memory if IA-32e Mode not actived. + @retval EFI_OUT_OF_RESOURCES The PageTable could not be migrated due = to lack of available memory. + +**/ +EFI_STATUS +MigratePageTable ( + VOID + ) +{ + EFI_STATUS Status; + IA32_CR4 Cr4; + BOOLEAN Page5LevelSupport; + UINT32 RegEax; + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; + BOOLEAN Page1GSupport; + PAGING_MODE PagingMode; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxExtendedFunctionId; + UINTN PageTable; + EFI_PHYSICAL_ADDRESS Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + + VirPhyAddressSize.Uint32 =3D 0; + PageTable =3D 0; + BufferSize =3D 0; + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + + // + // Check Page5Level Support or not. + // + Cr4.UintN =3D AsmReadCr4 (); + Page5LevelSupport =3D (Cr4.Bits.LA57 ? TRUE : FALSE); + + // + // Check Page1G Support or not. + // + Page1GSupport =3D FALSE; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &(RegEdx.Uint32)); + if ((RegEdx.Bits.Page1GB) !=3D 0) { + Page1GSupport =3D TRUE; + } + } + + // + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. + // + if (Page5LevelSupport) { + PagingMode =3D Page1GSupport ? Paging5Level1GB : Paging5Level; + } else { + PagingMode =3D Page1GSupport ? Paging4Level1GB : Paging4Level; + } + + // + // Get Maximum Physical Address Bits + // Get the number of address lines; Maximum Physical Address is 2^Physic= alAddressBits - 1. + // If CPUID does not supported, then use a max value of 36 as per SDM 3A= , 4.1.4. + // + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, N= ULL); + if (MaxExtendedFunctionId >=3D CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL); + } else { + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; + } + + if ((PagingMode =3D=3D Paging4Level1GB) || (PagingMode =3D=3D Paging4Lev= el)) { + // + // The max lineaddress bits is 48 for 4 level page table. + // + VirPhyAddressSize.Bits.PhysicalAddressBits =3D MIN (VirPhyAddressSize.= Bits.PhysicalAddressBits, 48); + } + + // + // Get required buffer size for the pagetable that will be created. + // + Status =3D PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, LShi= ftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), &MapAttribute, &MapM= ask, NULL); + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return Status; + } + + // + // Allocate required Buffer. + // + Status =3D PeiServicesAllocatePages ( + EfiBootServicesData, + EFI_SIZE_TO_PAGES (BufferSize), + &Buffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Create PageTable in permanent memory. + // + Status =3D PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, = &BufferSize, 0, LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), = &MapAttribute, &MapMask, NULL); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Write the Pagetable to CR3. + // + AsmWriteCr3 (PageTable); + + DEBUG (( + DEBUG_INFO, + "MigratePageTable: Created PageTable =3D 0x%lx, BufferSize =3D %x, Pag= ingMode =3D 0x%lx, Support Max Physical Address Bits =3D %d\n", + PageTable, + BufferSize, + (UINTN)PagingMode, + VirPhyAddressSize.Bits.PhysicalAddressBits + )); + + return Status; +} + // // These are IDT entries pointing to 10:FFFFFFE4h. // UINT64 mIdtEntryTemplate =3D 0xffff8e000010ffe4ULL; =20 @@ -451,10 +580,11 @@ SecTemporaryRamDone ( EFI_STATUS Status2; UINTN Index; BOOLEAN State; EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi; + IA32_CR0 Cr0; =20 // // Republish Sec Platform Information(2) PPI // RepublishSecPlatformInformationPpi (); @@ -492,10 +622,32 @@ SecTemporaryRamDone ( if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) { Status =3D MigrateGdt (); ASSERT_EFI_ERROR (Status); } =20 + // + // Migrate page table to permanent memory mapping entire physical addres= s space if CR0.PG is set. + // + Cr0.UintN =3D AsmReadCr0 (); + if (Cr0.Bits.PG !=3D 0) { + // + // CR4.PAE must be enabled. + // + ASSERT ((AsmReadCr4 () & BIT5) !=3D 0); + + // + // Assume CPU runs in 64bit mode if paging is enabled. + // + ASSERT (sizeof (UINTN) =3D=3D sizeof (UINT64)); + + Status =3D MigratePageTable (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "SecTemporaryRamDone: Failed to migrate page tab= le to permanent memory: %r.\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + // // Disable Temporary RAM after Stack and Heap have been migrated at this= point. // SecPlatformDisableTemporaryMemory (); =20 diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h index 880e6cd1b8..b50d96e45b 100644 --- a/UefiCpuPkg/SecCore/SecMain.h +++ b/UefiCpuPkg/SecCore/SecMain.h @@ -17,10 +17,11 @@ #include #include =20 #include =20 +#include #include #include #include #include #include @@ -30,10 +31,13 @@ #include #include #include #include #include +#include +#include +#include =20 #define SEC_IDT_ENTRY_COUNT 34 =20 typedef struct _SEC_IDT_TABLE { // --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104759): https://edk2.groups.io/g/devel/message/104759 Mute This Topic: https://groups.io/mt/98843220/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 10:01:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104760+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104760+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683864957; cv=none; d=zohomail.com; s=zohoarc; b=YSb7UBbVf64XNJ6pUmgwO9+5EmQL2YZ9NycdstHfe7EYUy4d9/geanbAf86t2g4mifSJZYTLnCnJmg7WrJSEkV9u565MxDvpn67wrwp7t4OpEX1L+vemYyuNqhONe9k6VdadbfRVNMcQUsJcyA0B7CVIP71uysnhF+jJEc6oBH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683864957; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=oVfNIIZVg1FYxlKK6CucUDtShgUpbHJZENPSxG3Ne3E=; b=BjE3clcLirgT2hXCxs8pckl7H+fqgjSKTZ9d32a4rQbt4j1XsoqktZd2O1prjjmbKl7AhkuqiQDXuWvfUYnsS/1chf4HTwdDmZd59IXioXFF329t5EU3x014ZhFxtnNMMBi0tL4oXhZmvr+dlD1RUCjuw4VR/YkSMhsnOT16NEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104760+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683864957724577.4574577642684; Thu, 11 May 2023 21:15:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id EHjdYY1788612x4w4h15OhsG; Thu, 11 May 2023 21:15:57 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:56 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193853" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193853" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658299" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658299" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:54 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 2/5] UefiCpuPkg/CpuMpPei: Enable PAE page table if CR0.PG is not set Date: Fri, 12 May 2023 12:15:45 +0800 Message-Id: <20230512041548.6416-3-jiaxin.wu@intel.com> In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: Hl5CJDuWbFMqpzo2Nar0k4dCx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683864957; bh=OID5btgtItmUIIzD9rIhG13gBC1UmP7FklfHU8Cc3a0=; h=Cc:Date:From:Reply-To:Subject:To; b=eXP1Bh05DlqZOxBPDixbgNJCayTOFlL0GGBm4mWJ3oYThN2zMqXXq8nFZ66aA8l9yF4 hMOzYD8SAVENkaLE8bFapo7i1F39EsN1R5oWV+CV1wvoMjXvtXaOnIJQSnEAEChNLWQTT C4E7z9PXsSh8JpWWUB/q5OoFVtt+sU0c6Dc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683864958700100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some security features depends on the page table enabling. So, This patch is to enable the page table if page table has not been enabled during the transition from Temporary RAM to Permanent RAM. Note: If page table is not enabled before this point, which means the system IA-32e Mode is not activated. Because on Intel 64 processors, IA-32e Mode operation requires physical address extensions with 4 or 5 levels of enhanc= ed paging structures (see Section 4.5, "4 - Level Paging and 5 -Level Paging" and Section 9.8, "Initializing IA-32e Mode"). So, just enable PAE page table if CR0.PG is not set. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 + UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 1 + UefiCpuPkg/CpuMpPei/CpuPaging.c | 215 ++++++++++++++++-------------------= ---- 3 files changed, 88 insertions(+), 129 deletions(-) diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h index 0649c48d14..1b9a94e18f 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h @@ -26,10 +26,11 @@ #include #include #include #include #include +#include =20 extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; =20 /** This service retrieves the number of logical processor in the platform diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf b/UefiCpuPkg/CpuMpPei/CpuMpPe= i.inf index 7444bdb968..865be5627e 100644 --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.inf +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.inf @@ -44,10 +44,11 @@ CpuExceptionHandlerLib MpInitLib BaseMemoryLib CpuLib MemoryAllocationLib + CpuPageTableLib =20 [Guids] gEdkiiMigratedFvInfoGuid ## = SOMETIMES_CONSUMES ## HOB =20 [Ppis] diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c b/UefiCpuPkg/CpuMpPei/CpuPagin= g.c index a471f089c8..b282e1cf14 100644 --- a/UefiCpuPkg/CpuMpPei/CpuPaging.c +++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c @@ -115,42 +115,10 @@ AllocatePageTableMemory ( } =20 return Address; } =20 -/** - Get the address width supported by current processor. - - @retval 32 If processor is in 32-bit mode. - @retval 36-48 If processor is in 64-bit mode. - -**/ -UINTN -GetPhysicalAddressWidth ( - VOID - ) -{ - UINT32 RegEax; - - if (sizeof (UINTN) =3D=3D 4) { - return 32; - } - - AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D CPUID_VIR_PHY_ADDRESS_SIZE) { - AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL); - RegEax &=3D 0xFF; - if (RegEax > 48) { - return 48; - } - - return (UINTN)RegEax; - } - - return 36; -} - /** Get the type of top level page table. =20 @retval Page512G PML4 paging. @retval Page1G PAE paging. @@ -381,120 +349,91 @@ ConvertMemoryPageAttributes ( =20 return RETURN_SUCCESS; } =20 /** - Get maximum size of page memory supported by current processor. - - @param[in] TopLevelType The type of top level page entry. + Enable PAE Page Table. =20 - @retval Page1G If processor supports 1G page and PML4. - @retval Page2M For all other situations. + @retval EFI_SUCCESS The PAE Page Table was enabled successfu= lly. + @retval EFI_OUT_OF_RESOURCES The PAE Page Table could not be enabled = due to lack of available memory. =20 **/ -PAGE_ATTRIBUTE -GetMaxMemoryPage ( - IN PAGE_ATTRIBUTE TopLevelType - ) -{ - UINT32 RegEax; - UINT32 RegEdx; - - if (TopLevelType =3D=3D Page512G) { - AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { - AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); - if ((RegEdx & BIT26) !=3D 0) { - return Page1G; - } - } - } - - return Page2M; -} - -/** - Create PML4 or PAE page table. - - @return The address of page table. - -**/ -UINTN -CreatePageTable ( +EFI_STATUS +EnablePaePageTable ( VOID ) { - RETURN_STATUS Status; - UINTN PhysicalAddressBits; - UINTN NumberOfEntries; - PAGE_ATTRIBUTE TopLevelPageAttr; - UINTN PageTable; - PAGE_ATTRIBUTE MaxMemoryPage; - UINTN Index; - UINT64 AddressEncMask; - UINT64 *PageEntry; - EFI_PHYSICAL_ADDRESS PhysicalAddress; - - TopLevelPageAttr =3D (PAGE_ATTRIBUTE)GetPageTableTopLevelType (); - PhysicalAddressBits =3D GetPhysicalAddressWidth (); - NumberOfEntries =3D (UINTN)1 << (PhysicalAddressBits - - mPageAttributeTable[TopLevelPageAttr]= .AddressBitOffset); + EFI_STATUS Status; + PAGING_MODE PagingMode; + + UINTN PageTable; + VOID *Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + + PagingMode =3D PagingPae; + PageTable =3D 0; + Buffer =3D NULL; + BufferSize =3D 0; + MapAttribute.Uint64 =3D 0; + MapMask.Uint64 =3D MAX_UINT64; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; =20 - PageTable =3D (UINTN)AllocatePageTableMemory (1); - if (PageTable =3D=3D 0) { - return 0; + // + // Get required buffer size for the pagetable that will be created. + // The Max size of LinearAddress for PAE is 2^32. + // + Status =3D PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, SIZE= _4GB, &MapAttribute, &MapMask, NULL); + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return Status; } =20 - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); - AddressEncMask &=3D mPageAttributeTable[TopLevelPageAttr].AddressMask; - MaxMemoryPage =3D GetMaxMemoryPage (TopLevelPageAttr); - PageEntry =3D (UINT64 *)PageTable; - - PhysicalAddress =3D 0; - for (Index =3D 0; Index < NumberOfEntries; ++Index) { - *PageEntry =3D PhysicalAddress | AddressEncMask | PAGE_ATTRIBUTE_BITS; + // + // Allocate required Buffer. + // + Buffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (BufferSize)); + ASSERT (Buffer !=3D NULL); + if (Buffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } =20 - // - // Split the top page table down to the maximum page size supported - // - if (MaxMemoryPage < TopLevelPageAttr) { - Status =3D SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TR= UE); - ASSERT_EFI_ERROR (Status); - } + // + // Create PageTable in permanent memory. + // The Max size of LinearAddress for PAE is 2^32. + // + Status =3D PageTableMap (&PageTable, PagingMode, Buffer, &BufferSize, 0,= LShiftU64 (1, 32), &MapAttribute, &MapMask, NULL); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status) || (PageTable =3D=3D 0)) { + return EFI_OUT_OF_RESOURCES; + } =20 - if (TopLevelPageAttr =3D=3D Page1G) { - // - // PDPTE[2:1] (PAE Paging) must be 0. SplitPage() might change them = to 1. - // - *PageEntry &=3D ~(UINT64)(IA32_PG_RW | IA32_PG_U); - } + // + // Write the Pagetable to CR3. + // + AsmWriteCr3 (PageTable); =20 - PageEntry +=3D 1; - PhysicalAddress +=3D mPageAttributeTable[TopLevelPageAttr].Length; - } + // + // Enable CR4.PAE + // + AsmWriteCr4 (AsmReadCr4 () | BIT5); =20 - return PageTable; -} + // + // Enable CR0.PG + // + AsmWriteCr0 (AsmReadCr0 () | BIT31); =20 -/** - Setup page tables and make them work. + DEBUG (( + DEBUG_INFO, + "EnablePaePageTable: Created PageTable =3D 0x%x, BufferSize =3D %x\n", + PageTable, + BufferSize + )); =20 -**/ -VOID -EnablePaging ( - VOID - ) -{ - UINTN PageTable; - - PageTable =3D CreatePageTable (); - ASSERT (PageTable !=3D 0); - if (PageTable !=3D 0) { - AsmWriteCr3 (PageTable); - AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE - AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG - } + return Status; } =20 /** Get the base address of current AP's stack. =20 @@ -622,10 +561,11 @@ MemoryDiscoveredPpiNotifyCallback ( { EFI_STATUS Status; BOOLEAN InitStackGuard; EDKII_MIGRATED_FV_INFO *MigratedFvInfo; EFI_PEI_HOB_POINTERS Hob; + IA32_CR0 Cr0; =20 // // Paging must be setup first. Otherwise the exception TSS setup during = MP // initialization later will not contain paging information and then fail // the task switch (for the sake of stack switch). @@ -635,12 +575,29 @@ MemoryDiscoveredPpiNotifyCallback ( if (IsIa32PaeSupported ()) { Hob.Raw =3D GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid); InitStackGuard =3D PcdGetBool (PcdCpuStackGuard); } =20 - if (InitStackGuard || (Hob.Raw !=3D NULL)) { - EnablePaging (); + // + // Some security features depends on the page table enabling. So, here + // is to enable the page table if page table has not been enabled yet. + // If page table is not enabled before this point, which means the system + // IA-32e Mode is not activated. Because on Intel 64 processors, IA-32e = Mode + // operation requires physical address extensions with 4 or 5 levels of + // enhanced paging structures (see Section 4.5, "4 - Level Paging and 5 - + // Level Paging" and Section 9.8, "Initializing IA-32e Mode"). So, just + // enable PAE page table if CR0.PG is not set. + // + Cr0.UintN =3D AsmReadCr0 (); + if ((Cr0.Bits.PG =3D=3D 0) && (InitStackGuard || (Hob.Raw !=3D NULL))) { + ASSERT (sizeof (UINTN) =3D=3D sizeof (UINT32)); + + Status =3D EnablePaePageTable (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "MemoryDiscoveredPpiNotifyCallback: Failed to en= able PAE page table: %r.\n", Status)); + ASSERT_EFI_ERROR (Status); + } } =20 Status =3D InitializeCpuMpWorker ((CONST EFI_PEI_SERVICES **)PeiServices= ); ASSERT_EFI_ERROR (Status); =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104760): https://edk2.groups.io/g/devel/message/104760 Mute This Topic: https://groups.io/mt/98843221/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 10:01:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104761+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104761+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683864959; cv=none; d=zohomail.com; s=zohoarc; b=Zay1bExGyH60QW3Bc6jQfzNy6fH/II3ErWjhwZrSjb1yLi+OawqdbnVzBcTcpmcCZl00P5ybCmznIU5z9+aJqpsIntuErjdPG+QUDK+sDalTicTYwlda3iEz2nLmVvSIuq6DKHfmN1tsOo61hzRt29YCqIDs82jcHr+M5tHryJc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683864959; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=L6z43UYDogOvkT0bKajjC/qBpOoi6sZn4qQRvht1kpY=; b=Pdlz8iQJvY6E5EcqAdUNowku0LNAbV+0+oJd+TqsU76PNagRWLzzhaoK8K56xGt56zRH6AOvjwx/V4RbCxY3RLq0q7E1Z3CQdxUjf8mnvIL/OfpPJaw9Bvjr0Qj8pRyNFct4KxocryaEuxGGvAFIcszVtgH5Wx1CfZosFJWVcbc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104761+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683864959825388.5563660426034; Thu, 11 May 2023 21:15:59 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 0qzxYY1788612xuqMnd7lKK0; Thu, 11 May 2023 21:15:59 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:59 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193872" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193872" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658305" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658305" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:56 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v2 3/5] MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. Date: Fri, 12 May 2023 12:15:46 +0800 Message-Id: <20230512041548.6416-4-jiaxin.wu@intel.com> In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: ccUcZgEuubUrHz61mTtHJqUFx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683864959; bh=OeTg6j+Iwcm1qjWGHBQRShA7VPE+bh/HLtX6DOrQQds=; h=Cc:Date:From:Reply-To:Subject:To; b=KBAxFg0mzxjrUW/e0BYe6BHXDGpvsM+uzf7KN7RpUuFLqXnczH59/JY0D5Qh0gW93HB 1A0Xz6L3+sTYjLVtwK/KsK35BCqPgdRMd7Go7puFDbMGy9fFx+WZAUGBaEITpyzO+DBgd yoHSoKU45AaDft+zV41dEoV8QP1kscv4Vwo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683864961993100015 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" System paging 5 level enabled or not can be checked via CR4.LA57, system preferred Page table Level (PcdUse5LevelPageTable) must align with previous level for 64bit long mode. This patch is to do the wise check: If cpu has already runned in 64bit long mode PEI, Page table Level in DXE must align with previous level. If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. Cc: Dandan Bi Cc: Liming Gao Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 ++++++++++++++++----= ---- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 18b121d768..a8e46eacc3 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -737,22 +737,37 @@ CreateIdentityMappingPageTables ( } else { PhysicalAddressBits =3D 36; } } =20 - Page5LevelSupport =3D FALSE; - if (PcdGetBool (PcdUse5LevelPageTable)) { - AsmCpuidEx ( - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, - NULL, - &EcxFlags.Uint32, - NULL - ); - if (EcxFlags.Bits.FiveLevelPage !=3D 0) { - Page5LevelSupport =3D TRUE; + // + // Check cpu runs in 64bit long mode or 32bit protected mode. + // + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { + // + // If cpu has already runned in 64bit long mode PEI, Page table Level = in DXE must align with previous level. + // + Cr4.UintN =3D AsmReadCr4 (); + Page5LevelSupport =3D Cr4.Bits.LA57 ? TRUE : FALSE; + ASSERT (PcdGetBool (PcdUse5LevelPageTable) =3D=3D Page5LevelSupport); + } else { + // + // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is= decided by PCD and feature capability. + // + Page5LevelSupport =3D FALSE; + if (PcdGetBool (PcdUse5LevelPageTable)) { + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, + NULL, + NULL, + &EcxFlags.Uint32, + NULL + ); + if (EcxFlags.Bits.FiveLevelPage !=3D 0) { + Page5LevelSupport =3D TRUE; + } } } =20 DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n", = PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104761): https://edk2.groups.io/g/devel/message/104761 Mute This Topic: https://groups.io/mt/98843222/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 10:01:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104762+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104762+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683864962; cv=none; d=zohomail.com; s=zohoarc; b=bHYYU5xAXx6kMh5Al/vnpMWsXmdyPVe3S4t3Rw6RhtYESIRtrqvPHYZjYFgCpHEa8hUgkjiSjhawWqdpSRJA7cx+d6rNEAiQ3Pvdk385d4xeyAzDwRs5SN/gtA/djuMaGP+qWC8kvQQ20QMJhj1FFMr2Ymf/7xP6tD8adXxdT/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683864962; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=DCayjBj18gsgSbPkpZtLYoR1PiZz9hqxcFZcglymUjA=; b=YI52r6ZRgrhg6Vo2r0X+cvQTGi5cqaXZ4WU+ofXfLjGbLtsOJIAeB8AEeEQe5C50xTpPYVK4lnojq//HaKu1Rjg185TBpczt4PTiqOYyNPkK/184gC7+bUjNmtdYwfAIvd0TOhuHsftQ2QtAG23kV/hWguKpiR4DEexYa9N5lpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104762+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683864962197549.845609976065; Thu, 11 May 2023 21:16:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PzgHYY1788612xTHIhe9UBBa; Thu, 11 May 2023 21:16:01 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:16:01 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193899" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193899" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:16:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658310" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658310" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:58 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v2 4/5] OvmfPkg: Add CpuPageTableLib required by SecCore & CpuMpPei Date: Fri, 12 May 2023 12:15:47 +0800 Message-Id: <20230512041548.6416-5-jiaxin.wu@intel.com> In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: 3fTpRJSrYSOwiAJmhcV7kog0x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683864961; bh=hCwTxZJoOwTo3Vi1eAu8kvFk9gTNxxuzxBZugyO9XH0=; h=Cc:Date:From:Reply-To:Subject:To; b=iH/BKuoyucu3gZbxgNEro/Mx3x3/f8UT5U5WLl6nBljFybhF3YZgZAuIYBS4nagcooM i0VbCUcOOwAJyDDe5BJop3Zmfa04F8epMxm9H8hwAFaP8/ol0zgLXR/tNb860EB2ndI8M AegV349Ui3I1orv/gNlsx5BaUEfzOLH501k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683864962700100017 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by SecCore & CpuMpPei in OvmfPkg. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/IntelTdx/IntelTdxX64.dsc | 3 +-- OvmfPkg/Microvm/MicrovmX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 3 +-- OvmfPkg/OvmfXen.dsc | 2 +- 8 files changed, 8 insertions(+), 9 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index b32049194d..dfcef0efca 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -145,10 +145,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -347,11 +348,10 @@ LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxDxeLib.inf !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf =20 diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 2a1139daaa..d4f86f8b71 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -162,10 +162,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -388,11 +389,10 @@ !endif !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf QemuLoadImageLib|OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib= .inf =20 diff --git a/OvmfPkg/IntelTdx/IntelTdxX64.dsc b/OvmfPkg/IntelTdx/IntelTdxX6= 4.dsc index d4403f11a7..0c21a713fc 100644 --- a/OvmfPkg/IntelTdx/IntelTdxX64.dsc +++ b/OvmfPkg/IntelTdx/IntelTdxX64.dsc @@ -149,10 +149,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -304,11 +305,10 @@ PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxDxeLib.inf PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf QemuLoadImageLib|OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib= .inf =20 @@ -576,11 +576,10 @@ # # Directly use DxeMpInitLib. It depends on DxeMpInitLibMpDepLib which # checks the Protocol of gEfiMpInitLibMpDepProtocolGuid. # - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.i= nf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NULL|OvmfPkg/Library/MpInitLibDepLib/DxeMpInitLibMpDepLib.inf } =20 UefiCpuPkg/CpuDxe/CpuDxe.inf { diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index 5f671bc384..5739e98f78 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -160,10 +160,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -387,11 +388,10 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf QemuLoadImageLib|OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib= .inf =20 diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index e333b8b418..0c044e34f8 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -165,10 +165,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 25974230a2..20f8686ee5 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -169,10 +169,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -400,11 +401,10 @@ !endif !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf QemuLoadImageLib|OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib= .inf =20 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index c1762ffca4..ce89817dda 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -182,10 +182,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -421,11 +422,10 @@ !endif !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf QemuLoadImageLib|OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib= .inf =20 @@ -814,11 +814,10 @@ # # Directly use DxeMpInitLib. It depends on DxeMpInitLibMpDepLib which # checks the Protocol of gEfiMpInitLibMpDepProtocolGuid. # - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.i= nf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NULL|OvmfPkg/Library/MpInitLibDepLib/DxeMpInitLibMpDepLib.inf } =20 UefiCpuPkg/CpuDxe/CpuDxe.inf { diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 1f44ec86c9..de445ebc0b 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -153,10 +153,11 @@ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf @@ -334,11 +335,10 @@ LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxDxeLib.inf !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf =20 [LibraryClasses.common.UEFI_APPLICATION] --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104762): https://edk2.groups.io/g/devel/message/104762 Mute This Topic: https://groups.io/mt/98843223/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 10:01:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104763+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104763+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683864964; cv=none; d=zohomail.com; s=zohoarc; b=Pb+wiVR7Z31W79jhNLllvNJXFsjyuumiLDTouH0eGOFxdpv9gT01cMiLQxqs2MJ7TIpAG3RflmZB9kl43nzWELD2ks03C/BiTlnwop4KtO+7nQ8oOikShjVXpWksYPZAodAKygcFowxJzrTA9Nqe1jH3/O2s++Pme4y456xvo54= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683864964; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=hZCvIp6rl0nR/7Od0Snhp//S/hnCYa07yiHGEnbkSok=; b=irs6VaSNXg5pNIb9mCqtxE6dCA7L7EoxYcrHWnnsshOj8KCgcy8sM3zadyj0fZuawdHWcS0OfX2/tMwuPqdcuZ9doHWhINjYg5KpUzBQ526dj/YA7Wi46TQGxzBjkb1/iMqc7FQQmAalEt3LPL0cKizjnYOclXbau0QKpS6LE88= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104763+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683864964174806.051553967064; Thu, 11 May 2023 21:16:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XEUfYY1788612xTIgYqhFGiL; Thu, 11 May 2023 21:16:03 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:16:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193917" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193917" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:16:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658316" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658316" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:16:01 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Guo Dong , Sean Rhodes , James Lu , Gua Guo , Ray Ni , Zeng Star Subject: [edk2-devel] [PATCH v2 5/5] UefiPayloadPkg: Add CpuPageTableLib required by SecCore & CpuMpPei Date: Fri, 12 May 2023 12:15:48 +0800 Message-Id: <20230512041548.6416-6-jiaxin.wu@intel.com> In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com X-Gm-Message-State: 2gci9yfnZ6VPAw96qme31PFFx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683864963; bh=w1FcHJknUR4djDI9sKW0eepmU6r3x7IlnNxJwrCt2FU=; h=Cc:Date:From:Reply-To:Subject:To; b=gMeiqx1sRxuGc6Sg5zpj7m1T9zcb6r8pWpyx3ePgR52IlPxvOLJlCPqNsdJHMdgv06p ExV+L3erbIlgc9ZVaz8Vo6PHv37F1H+H1OcqGwjzREUCUoAZlLZiTX15mUWSqXvTwBSgg jF0w5JWVANJneMdH65rgQo4yOTTLTWzZIMU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683864965181100021 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib required by SecCore & CpuMpPei in UefiPayloadPkg. Cc: Guo Dong Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Cc: Ray Ni Cc: Zeng Star Signed-off-by: Jiaxin Wu --- UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index 998d222909..615c5b4c6d 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -240,10 +240,11 @@ # CPU # MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 # # Platform # !if $(CPU_TIMER_LIB_ENABLE) =3D=3D TRUE && $(UNIVERSAL_PAYLOAD) =3D=3D TRUE @@ -343,11 +344,10 @@ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf !if $(SOURCE_DEBUG_ENABLE) DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf !if $(PERFORMANCE_MEASUREMENT_ENABLE) PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf !endif =20 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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