From nobody Fri May 17 15:35:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104257+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104257+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683533827; cv=none; d=zohomail.com; s=zohoarc; b=excIF6d1GmWudttxtCl1Ug3OY1Ad3ZtxbC6991PUDNkEKzdF0MPJVrUobaiB6y2UvqqT6rhfIgiLzw26G4RcjCQpXVDbj6hQN56s3cqw9kTQYPGXLPsu/KHDR+F3lcZ/uptYZr6yg/7iy2ZdcP93Y650C2LjPIiLUkc2iTSTD8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683533827; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=CLNcy/pKC+O6XXkOPGLGHgJhZCbI4NeumimFXz/xDs0=; b=V8xHH1p0hayXTKm29N9ItxhpIBnKw4zIRbrRFpyd4OhHzdFW9JNkEguQRYoKTcJC+Ss4SgzoHWkMBcGnzCp79D2hzJtfcMFXOTFYBJaLg7i25xOinVx8A9gs5hamocU1nFnZMCjKoXKXxtpDizr4rkPa89hKv7TD9250fZU9mZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104257+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683533827375997.7785602036842; Mon, 8 May 2023 01:17:07 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id tVWhYY1788612xOkRLeRiG8a; Mon, 08 May 2023 01:17:07 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.102321.1683533825808374340 for ; Mon, 08 May 2023 01:17:06 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329948369" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="329948369" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="731219025" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="731219025" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:03 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [edk2-devel] [PATCH v5 1/5] UefiCpuPkg/ResetVector: Rename macros about page table. Date: Mon, 8 May 2023 16:15:00 +0800 Message-Id: <20230508081504.1067-2-zhiguang.liu@intel.com> In-Reply-To: <20230508081504.1067-1-zhiguang.liu@intel.com> References: <20230508081504.1067-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: c3gDRP3IMyVBxaEudeJuhfTlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683533827; bh=+z3o9pqTlai4ztzf8/QLvaY4YuJZrvJt5epCihJbYHU=; h=Cc:Date:From:Reply-To:Subject:To; b=kAsXEzw0zXrdXEntUf2vUtBhfJLQ35bSUgjj0VYa3qKToaYtxDHOyfUhOqqcplUYWFK H4IZYZHXOz4QaHKwb+1YsgjUp3djmbiX998Vej34jZtm8aO0wLWnetFLjWZk9T1XvtDkL 5MzILvo09mVaSFKbsZKLwEZXOG1O32ouY3E= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683533828790100001 Content-Type: text/plain; charset="utf-8" This patch only renames macro, with no code logic impacted. Two purpose to rename macro: 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so that these two files can be easily combined later. 2. Some Macro names such as PDP are not accurate, since 4 level page entry also uses this macro. PAGE_NLE (no leaf entry) is better Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- .../ResetVector/Vtf0/X64/PageTables1G.asm | 26 +++++++++----- .../ResetVector/Vtf0/X64/PageTables2M.asm | 35 +++++++++++-------- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables1G.asm index 19bd3d5a92..20a61f949c 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -2,7 +2,7 @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512= GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Translation to a 1-GByte Page ; @@ -12,11 +12,18 @@ BITS 64 =20 %define ALIGN_TOP_TO_4K_FOR_PAGING =20 -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_PRESENT) =20 -%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_ACCESSED + \ PAGE_READ_WRITE + \ PAGE_DIRTY + \ PAGE_PRESENT + \ @@ -25,10 +32,13 @@ BITS 64 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) =20 -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) +; +; Page table non-leaf entry +; +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) =20 -%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) +%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) =20 ALIGN 16 =20 @@ -37,7 +47,7 @@ TopLevelPageDirectory: ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) =20 TIMES 0x1000-PGTBLS_OFFSET($) DB 0 ; @@ -45,7 +55,7 @@ TopLevelPageDirectory: ; %assign i 0 %rep 512 - DQ PDP_1G(i) + DQ PAGE_PDPTE_1GB(i) %assign i i+1 %endrep TIMES 0x2000-PGTBLS_OFFSET($) DB 0 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables2M.asm index b97df384ac..1221b023fe 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -2,7 +2,7 @@ ; @file ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) ; -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -11,29 +11,36 @@ BITS 64 =20 %define ALIGN_TOP_TO_4K_FOR_PAGING =20 -%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \ +; +; Page table big leaf entry attribute: +; PDPTE 1GB entry or PDE 2MB entry +; +%define PAGE_BLE_ATTR (PAGE_SIZE + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ PAGE_READ_WRITE + \ PAGE_PRESENT) =20 -%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) +; +; Page table non-leaf entry attribute +; +%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) =20 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) =20 -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ - PAGE_PDP_ATTR) -%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) +%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_NLE_ATTR) +%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) =20 TopLevelPageDirectory: =20 ; ; Top level Page Directory Pointers (1 * 512GB entry) ; - DQ PDP(0x1000) + DQ PAGE_NLE(0x1000) =20 =20 ; @@ -41,10 +48,10 @@ TopLevelPageDirectory: ; TIMES 0x1000-PGTBLS_OFFSET($) DB 0 =20 - DQ PDP(0x2000) - DQ PDP(0x3000) - DQ PDP(0x4000) - DQ PDP(0x5000) + DQ PAGE_NLE(0x2000) + DQ PAGE_NLE(0x3000) + DQ PAGE_NLE(0x4000) + DQ PAGE_NLE(0x5000) =20 ; ; Page Table Entries (2048 * 2MB entries =3D> 4GB) @@ -53,7 +60,7 @@ TopLevelPageDirectory: =20 %assign i 0 %rep 0x800 - DQ PTE_2MB(i) + DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep =20 --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104257): https://edk2.groups.io/g/devel/message/104257 Mute This Topic: https://groups.io/mt/98757006/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 15:35:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104258+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104258+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683533855; cv=none; d=zohomail.com; s=zohoarc; b=CS50j0Gef1rClEifySggdvOEPZyPf+1XbOIzIgjvMLem64Gdh3hUKFEBtIu0X/Wrhnt0b5PCC1JugIRRuUWtEkM3XbIuQ05iGqMeGg22aYC/z6WujzZ34NvlZivVEvub+hWf55SG6or2y6vfMRSHetawNkaxU8/Nka7nXzN5oUU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683533855; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=bmxYDJcy8DNFcbpit1MjS8PJC4oNfpYer7njxi6sJBE=; b=CtSCqVP3j1XbS9ysBxuHBBBZT5q8T7XuLrlyXvvI1SOuTdmiwvjqyJWmDgztRkGGCi332HAMysEZxXTRUUC/13r4KfGg0J4SX1yP9bYINQzxujyIUf2UAtD2aUetBWPamq01rgxw6CaBgfgNWObqbirfhQ+uZQwNHEiVz754rYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104258+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683533855090371.6652760173472; Mon, 8 May 2023 01:17:35 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 09V8YY1788612xNq81ajIiab; Mon, 08 May 2023 01:17:34 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.102325.1683533854228983101 for ; Mon, 08 May 2023 01:17:34 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329948409" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="329948409" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="731219033" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="731219033" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:05 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [edk2-devel] [PATCH v5 2/5] UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector Date: Mon, 8 May 2023 16:15:01 +0800 Message-Id: <20230508081504.1067-3-zhiguang.liu@intel.com> In-Reply-To: <20230508081504.1067-1-zhiguang.liu@intel.com> References: <20230508081504.1067-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: qbnHUfLzB4bPdjZBaFdt5OSbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683533854; bh=OXEITN8cuw5Nt7sBHXIWg9gErjGZ7RyYTJ4KjW9bDjo=; h=Cc:Date:From:Reply-To:Subject:To; b=hYmnNkT8NwBHwI9Ii4e5yFd6MPFU3LbeIirk/0BZ/D1nu32gh8aXQH/+Ir0RH0tizXe RpywvAUPKoNrD5IHr2PJinq1QCw5W3aw78mTZH35HbmbwFP8V6QKY1fx/qwDK8izVmfRN DlnEsLyR7f1rkK/WBzTfGCM2epI/dRMBaKI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683533855473100001 Content-Type: text/plain; charset="utf-8" Currently, page table creation has many hard-code values about the offset to the start of page table. To simplify it, add Labels such as Pml4, Pdp and Pd, so that we can remove many hard-code values Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 4 +-- .../ResetVector/Vtf0/X64/PageTables1G.asm | 18 ++++------ .../ResetVector/Vtf0/X64/PageTables2M.asm | 34 ++++++++----------- 3 files changed, 24 insertions(+), 32 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg= /ResetVector/Vtf0/Ia32/PageTables64.asm index 87a4125d4b..f188da20ba 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -2,7 +2,7 @@ ; @file ; Sets the CR3 register for 64-bit paging ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -17,7 +17,7 @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; - mov eax, ADDR_OF(TopLevelPageDirectory) + mov eax, ADDR_OF(Pml4) mov cr3, eax =20 OneTimeCallRet SetCr3ForPageTables64 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables1G.asm index 20a61f949c..f5b8da0015 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm @@ -29,35 +29,31 @@ BITS 64 PAGE_PRESENT + \ PAGE_SIZE) =20 -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - ; ; Page table non-leaf entry ; -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) =20 %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) =20 ALIGN 16 =20 -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 =20 - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 +Pdp: ; - ; Next level Page Directory Pointers (512 * 1GB entries =3D> 512GB) + ; Page-directory pointer table (512 * 1GB entries =3D> 512GB) ; %assign i 0 %rep 512 DQ PAGE_PDPTE_1GB(i) %assign i i+1 %endrep - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 =20 EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables2M.asm index 1221b023fe..731dabad4d 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm @@ -28,36 +28,32 @@ BITS 64 PAGE_READ_WRITE + \ PAGE_PRESENT) =20 -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) - -%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ +%define PAGE_NLE(address) (ADDR_OF(address) + \ PAGE_NLE_ATTR) %define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) =20 -TopLevelPageDirectory: - +Pml4: ; - ; Top level Page Directory Pointers (1 * 512GB entry) + ; PML4 (1 * 512GB entry) ; - DQ PAGE_NLE(0x1000) - + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 =20 +Pdp: ; - ; Next level Page Directory Pointers (4 * 1GB entries =3D> 4GB) + ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) ; - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 - - DQ PAGE_NLE(0x2000) - DQ PAGE_NLE(0x3000) - DQ PAGE_NLE(0x4000) - DQ PAGE_NLE(0x5000) + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 =20 +Pd: ; - ; Page Table Entries (2048 * 2MB entries =3D> 4GB) + ; Page-Directory (2048 * 2MB entries =3D> 4GB) + ; Four pages below, each is pointed by one entry in Pdp. ; - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 - %assign i 0 %rep 0x800 DQ PAGE_PDE_2MB(i) --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104258): https://edk2.groups.io/g/devel/message/104258 Mute This Topic: https://groups.io/mt/98757008/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 15:35:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104259+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104259+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683533857; cv=none; d=zohomail.com; s=zohoarc; b=PESakhjkN5cUfcJltaWKq88fy4LUYYkHrCh6mnNY9lo4uhZSPDi9AS7oWWfmzYKORBzp8CCxB7+RmwL6eqB0LDK2xDyIvaurQRokC4NwfcunDTTpj0VKIxX6BnYPuYMu3Jby8zabV3/mFsM8ixTIlKqT2AsEYjQcuS6fmzWYwWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683533857; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=j+eOI5wjExLDcwr0igKG7W67r/G4PCGZ7MVNwNbD4Pc=; b=RhpQn/SnbvpOy4e06QxejvyacdfhUlVJPdNKho7yh+0/vRQMo5MEQC4mKr6wwrQ58fJaABCo4IvOfE7e/ZBYRAmREQIQ4fICF4TPSENgq+/MAtHYPcK7Rgh+UTK6o0C+oCAToeGRPCddv9SowU2KC5DBqQ1K0iN8Hzg7iPXswmA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104259+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683533857817341.3586988883974; Mon, 8 May 2023 01:17:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SxCbYY1788612x4NxZVqYykK; Mon, 08 May 2023 01:17:37 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.102325.1683533854228983101 for ; Mon, 08 May 2023 01:17:37 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329948458" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="329948458" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="731219040" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="731219040" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:07 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [edk2-devel] [PATCH v5 3/5] UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm Date: Mon, 8 May 2023 16:15:02 +0800 Message-Id: <20230508081504.1067-4-zhiguang.liu@intel.com> In-Reply-To: <20230508081504.1067-1-zhiguang.liu@intel.com> References: <20230508081504.1067-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: PBcKmKSNrOzERGyciPr8X9aCx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683533857; bh=xkbG1cwcbqxBeRIjEKr1cKqNDIltqo5kFbmZAwhkqSg=; h=Cc:Date:From:Reply-To:Subject:To; b=lqh9x1jsVCNKbD2TLUCwGjyDd+GrJlXhOi5R6r0bEVZKtboX/QDSg+SyPKMn6pxirpP 9eFaTIiRrBrZxEuVB3BNaeypvF/KHYLgbMNKw+9T4Uk6Xk+Eu2m7sqYuzIGlf+tP+U84g KCAFaHpcgVWKK6swQFEhoktMszNupogIZ0w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683533859445100006 Content-Type: text/plain; charset="utf-8" Combine PageTables1G.asm and PageTables2M.asm to reuse code. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +-- .../X64/{PageTables1G.asm =3D> PageTables.asm} | 38 ++++++++--- .../ResetVector/Vtf0/X64/PageTables2M.asm | 63 ------------------- 3 files changed, 33 insertions(+), 76 deletions(-) rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables1G.asm =3D> PageTables.a= sm} (57%) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVecto= r/Vtf0/Vtf0.nasmb index bdea1fb875..136361e62c 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -2,7 +2,7 @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -38,11 +38,7 @@ %include "PageTables.inc" =20 %ifdef ARCH_X64 - %ifdef PAGE_TABLE_1G - %include "X64/PageTables1G.asm" - %else - %include "X64/PageTables2M.asm" - %endif + %include "X64/PageTables.asm" %endif =20 %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables.asm similarity index 57% rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm rename to UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index f5b8da0015..9b492b063f 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -1,10 +1,11 @@ ;-------------------------------------------------------------------------= ----- ; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512= GB) +; Emits Page Tables for 1:1 mapping. +; If using 1G page table, map addresses 0 - 0x8000000000 (512GB), +; else, map addresses 0 - 0x100000000 (4GB) ; ; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent -; Linear-Address Translation to a 1-GByte Page ; ;-------------------------------------------------------------------------= ----- =20 @@ -36,6 +37,7 @@ BITS 64 PAGE_NLE_ATTR) =20 %define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR) +%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) =20 ALIGN 16 =20 @@ -46,14 +48,36 @@ Pml4: DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 =20 +%ifdef PAGE_TABLE_1G Pdp: ; ; Page-directory pointer table (512 * 1GB entries =3D> 512GB) ; -%assign i 0 -%rep 512 - DQ PAGE_PDPTE_1GB(i) - %assign i i+1 -%endrep + %assign i 0 + %rep 512 + DQ PAGE_PDPTE_1GB(i) + %assign i i+1 + %endrep +%else +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 =20 +Pd: + ; + ; Page-Directory (2048 * 2MB entries =3D> 4GB) + ; Four pages below, each is pointed by one entry in Pdp. + ; + %assign i 0 + %rep 0x800 + DQ PAGE_PDE_2MB(i) + %assign i i+1 + %endrep +%endif EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/= ResetVector/Vtf0/X64/PageTables2M.asm deleted file mode 100644 index 731dabad4d..0000000000 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm +++ /dev/null @@ -1,63 +0,0 @@ -;-------------------------------------------------------------------------= ----- -; @file -; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB) -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;-------------------------------------------------------------------------= ----- - -BITS 64 - -%define ALIGN_TOP_TO_4K_FOR_PAGING - -; -; Page table big leaf entry attribute: -; PDPTE 1GB entry or PDE 2MB entry -; -%define PAGE_BLE_ATTR (PAGE_SIZE + \ - PAGE_ACCESSED + \ - PAGE_DIRTY + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -; -; Page table non-leaf entry attribute -; -%define PAGE_NLE_ATTR (PAGE_ACCESSED + \ - PAGE_READ_WRITE + \ - PAGE_PRESENT) - -%define PAGE_NLE(address) (ADDR_OF(address) + \ - PAGE_NLE_ATTR) -%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR) - -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 - -Pd: - ; - ; Page-Directory (2048 * 2MB entries =3D> 4GB) - ; Four pages below, each is pointed by one entry in Pdp. - ; -%assign i 0 -%rep 0x800 - DQ PAGE_PDE_2MB(i) - %assign i i+1 -%endrep - -EndOfPageTables: --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104259): https://edk2.groups.io/g/devel/message/104259 Mute This Topic: https://groups.io/mt/98757009/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 15:35:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104260+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104260+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683533858; cv=none; d=zohomail.com; s=zohoarc; b=BRaTlsoMMyVrreO+ORampc8SqrpwiKVVJgVRjvJ1SrosX9PwRlRr6W0VR/BhsnuHNOvWl7qrGE/pm3viVeVVfGVf/pPi1NaiWm3WgAB/vFxUSMqVKHt7mcNstQQh9YF2+eWSRkiwHGLmHt5S6dEgdAA7+CBVvNGdKTgA0Qi/P1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683533858; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xpJ6NYupmjTqmatorYX8QdHkzkpAesfuypJ4ngshDIk=; b=B0M2AoWCRIGcTgS2njvx3+vJXtSkq6yMmNxcaVVaN/p9OtTz5FJzqITeqZ6HmK2XalLgl6Saq7G2F20xkr4NbYQ6o0j/c0eWAxiD5FQzG2pAhOfYh6Z1PpWY4U3kLgs0TP8BXV1UTD+Uu73w/4L1dRShoTymtl/juiSkI190dR0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104260+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683533858363254.1732863556573; Mon, 8 May 2023 01:17:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SHy2YY1788612xk8RaguvVb1; Mon, 08 May 2023 01:17:38 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.102325.1683533854228983101 for ; Mon, 08 May 2023 01:17:37 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329948476" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="329948476" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="731219054" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="731219054" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:10 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [edk2-devel] [PATCH v5 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Date: Mon, 8 May 2023 16:15:03 +0800 Message-Id: <20230508081504.1067-5-zhiguang.liu@intel.com> In-Reply-To: <20230508081504.1067-1-zhiguang.liu@intel.com> References: <20230508081504.1067-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: uzRyKVy4nkme08NEZmDtSLa5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683533858; bh=pK7XzfIjB9+6zOos7xY6K5QKHd5dKPbujMoAFqniHXk=; h=Cc:Date:From:Reply-To:Subject:To; b=v3/f+W+7Rx5LmQ3y/YEc/T+OhleFVRoW2jA871VYA7ni4JZO0ugdfFAV8pBw9MX1fTb 1wE3sK2/W1/qWlt786otiTJkTNvKz0AmGv9ZYHR8yq/xmmeQpKTFeH/sOWabF5NJ/QrBL 86SQLHwziEoQZEiYQc/4Ml2oN0JyVi5SA1o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683533859439100004 Content-Type: text/plain; charset="utf-8" In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve debuggability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- .../ResetVector/Vtf0/X64/PageTables.asm | 33 ++++++++++--------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/Re= setVector/Vtf0/X64/PageTables.asm index 9b492b063f..d66fb62c34 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -41,13 +41,6 @@ BITS 64 =20 ALIGN 16 =20 -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - %ifdef PAGE_TABLE_1G Pdp: ; @@ -59,15 +52,6 @@ Pdp: %assign i i+1 %endrep %else -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 =20 Pd: ; @@ -79,5 +63,22 @@ Pd: DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries =3D> 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 + %endif + +Pml4: + ; + ; PML4 (1 * 512GB entry) + ; + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 EndOfPageTables: --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104260): https://edk2.groups.io/g/devel/message/104260 Mute This Topic: https://groups.io/mt/98757010/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 17 15:35:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+104261+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104261+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1683533859; cv=none; d=zohomail.com; s=zohoarc; b=jRzQHBDVd7zxObPQQh7rvT/BToritpjIU+cj7u7vWfpxCPRo7i9SiF8oLyvFbKO8ccIvmrPwJGmfCw6C6i1gvAlJbvBohMwLnNKcKXWnQfwPAW4ar+YqV1V7mn4JyUTtPjghMzRWqAMQffoDh3K/JUHM4Yvu9aoCih9zd5cPqQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683533859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=vQH2RZH6hHAaYCrpAyquSbjPiAzA7U2l2akj+FW74ME=; b=ap0sradn1BV8FWvHOt4XzebPxw+VJ97wh4OJtIHW1HOXyMAnjDtSTklxCfjxByLA4wucGD5lOjg6Zz7/4LdyBtGbTGsxsk95Uf1/UtW4iB/bH7r6YbHfprAoARFd6KEErqWxTjtthSstZJtG7ql1oON65gXwCN2v4XSB3UzY/io= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+104261+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1683533859397532.4964995976575; Mon, 8 May 2023 01:17:39 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Jzc4YY1788612xKgyDXbZXfF; Mon, 08 May 2023 01:17:38 -0700 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.102325.1683533854228983101 for ; Mon, 08 May 2023 01:17:38 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329948488" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="329948488" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="731219087" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="731219087" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:12 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [edk2-devel] [PATCH v5 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector Date: Mon, 8 May 2023 16:15:04 +0800 Message-Id: <20230508081504.1067-6-zhiguang.liu@intel.com> In-Reply-To: <20230508081504.1067-1-zhiguang.liu@intel.com> References: <20230508081504.1067-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: ShNS5XUtE2KKw3xXzbkebmjax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1683533858; bh=clrxVP3bPCgzp5hLFIGjBl7aKBYy41DoA/Fa9AUnKC4=; h=Cc:Date:From:Reply-To:Subject:To; b=ZvUNMuwZbwg9MQDXdMqmo3MgBqgWcKO9RQ2QqKJ3oSqsr3e661ikuPs0tiaXPuCpPQl FyoRRASzjKXUwsoLi/cheDklYrRjhLkizp5H1cgrSTCoS+LWFDzodk/R9ccTQ4wCATy37 AlhtChobQ7hpHaO75ij77WlclReAkfGGIOI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1683533861432100011 Content-Type: text/plain; charset="utf-8" Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu Acked-by: Gerd Hoffmann Reviewed-by: Ray Ni Tested-by: Gerd Hoffmann --- .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 25 +++++++++++++++++-- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ------------------ UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 - .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++ 4 files changed, 32 insertions(+), 27 deletions(-) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuP= kg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm index 6891397c2a..f119f941a5 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -2,7 +2,7 @@ ; @file ; Transition from 32 bit flat protected mode into 64 bit flat protected mo= de ; -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -14,7 +14,28 @@ BITS 32 ; Transition32FlatTo64Flat: =20 - OneTimeCall SetCr3ForPageTables64 +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contai= ns leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downg= rade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level pagin= g if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downg= rade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=3D1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + + mov eax, ADDR_OF(Pml4) + mov cr3, eax +SetCr3Done: =20 mov eax, cr4 bts eax, 5 ; enable PAE diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg= /ResetVector/Vtf0/Ia32/PageTables64.asm deleted file mode 100644 index f188da20ba..0000000000 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ /dev/null @@ -1,24 +0,0 @@ -;-------------------------------------------------------------------------= ----- -; @file -; Sets the CR3 register for 64-bit paging -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;-------------------------------------------------------------------------= ----- - -BITS 32 - -; -; Modified: EAX -; -SetCr3ForPageTables64: - - ; - ; These pages are built into the ROM image in X64/PageTables.asm - ; - mov eax, ADDR_OF(Pml4) - mov cr3, eax - - OneTimeCallRet SetCr3ForPageTables64 - diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVecto= r/Vtf0/Vtf0.nasmb index 136361e62c..5a6563bd34 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -54,7 +54,6 @@ =20 %ifdef ARCH_X64 %include "Ia32/Flat32ToFlat64.asm" -%include "Ia32/PageTables64.asm" %endif =20 %include "Ia16/Real16ToFlat32.asm" diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/Re= setVector/Vtf0/X64/PageTables.asm index d66fb62c34..7960b141be 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -81,4 +81,13 @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104261): https://edk2.groups.io/g/devel/message/104261 Mute This Topic: https://groups.io/mt/98757011/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-