From nobody Sat May 18 15:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103529+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103529+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682406198; cv=none; d=zohomail.com; s=zohoarc; b=VhcUy5AbXAdKdLWHHRGVch0wZApFpxo0CSX7Goos0VT3aKdqx/Py4b64axUc2t3j5RcT6TiQiikTf88ZERlT7QhCQ1gZIdnsXoAMgsKJ7xOAUbxzKLdOykd4FluiZzWDqaoporQWViuH7pre3zHdxbjctNRIGWGnzcJkFmn6aTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682406198; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=nS1DuH6bcFnm4aN/Fn3phDOLJ9w7Ys2hyRH8CYg6lvM=; b=O1ucx0KhhdIa0hmXyVgZLgIUEOluff9SnvB701uoO50GJnb+Rk5nt19i0x1k1jFmdqGLo8DcvuOxen4fg+r5/YkhNoMtH28VRs9XewAEJxKyl+gg4xGfcVUctg1AymqkHZ6yZUTeB0DBU0bNocA1jAFpow9iTzwhhbTUvyRDxGw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103529+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682406198010168.66576119673118; Tue, 25 Apr 2023 00:03:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZHq2YY1788612xh8eclPD98J; Tue, 25 Apr 2023 00:03:17 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.73794.1682406195842322329 for ; Tue, 25 Apr 2023 00:03:17 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="374623045" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="374623045" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="867781551" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="867781551" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:15 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [edk2-devel] [PATCH 1/5] SimicsOpenBoardPkg: Build gEfiSmmSmramMemoryGuid Hob in S3 path Date: Tue, 25 Apr 2023 15:03:00 +0800 Message-Id: <20230425070304.2120-2-zhiguang.liu@intel.com> In-Reply-To: <20230425070304.2120-1-zhiguang.liu@intel.com> References: <20230425070304.2120-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: GSvaXDzjVQgo0CtVXdmJdNqJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682406197; bh=caqBUGHcpnSgsyuM1DkWoLD1phSF6NtteM3KVhMrW1k=; h=Cc:Date:From:Reply-To:Subject:To; b=s5LPPMENmcEeIZYUM8oLpljOUdgU9IE8O2yyvbHW0q4Dt8NrXJEfy1H8Fy1mJeKYquq dhJOE7MS+l2Xmq2izTEjBTp15S+rA8d53pCIqfr5TGE5d7GwM8zJfR2TqMDYvUTr/uuSs IuprLG/voIESb8+l0YI/1r65E7MErmXsXL4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682406198405100003 Content-Type: text/plain; charset="utf-8" gEfiSmmSmramMemoryGuid Hob is needed for SmmRelocation feature even for S3 path. So in MemDetect.c, remove specical code path for S3 about creating gEfiSmmSmramMemoryGuid Hob and adding some memory descriptor, which does no harm in S3 path. Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu --- .../SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 107 +++++++----------- 1 file changed, 42 insertions(+), 65 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c b/Plat= form/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c index 127afffc00..d80ac1d213 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c @@ -405,79 +405,56 @@ QemuInitializeRam ( LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); =20 - if (mBootMode =3D=3D BOOT_ON_S3_RESUME) { - // - // Create the following memory HOB as an exception on the S3 boot path. - // - // Normally we'd create memory HOBs only on the normal boot path. Howe= ver, - // CpuMpPei specifically needs such a low-memory HOB on the S3 path as - // well, for "borrowing" a subset of it temporarily, for the AP startup - // vector. - // - // CpuMpPei saves the original contents of the borrowed area in perman= ent - // PEI RAM, in a backup buffer allocated with the normal PEI services. - // CpuMpPei restores the original contents ("returns" the borrowed are= a) at - // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before - // transferring control to the OS's wakeup vector in the FACS. - // - // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to - // restore the original contents. Furthermore, we expect all such PEIMs - // (CpuMpPei included) to claim the borrowed areas by producing memory - // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en - // looking for an area to borrow. - // - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); - } else { - // - // Create memory HOBs - // - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + // + // Create memory HOBs + // + AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); =20 - if (FeaturePcdGet (PcdSmmSmramRequire)) { - UINT32 TsegSize; + if (FeaturePcdGet (PcdSmmSmramRequire)) { + UINT32 TsegSize; =20 - TsegSize =3D mX58TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, - TRUE); + TsegSize =3D mX58TsegMbytes * SIZE_1MB; + AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, + TRUE); =20 - BufferSize =3D sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); - SmramRanges =3D 1; + BufferSize =3D sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); + SmramRanges =3D 1; =20 - Hob.Raw =3D BuildGuidHob( - &gEfiSmmSmramMemoryGuid, - BufferSize - ); - ASSERT(Hob.Raw); - - SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.R= aw); - SmramHobDescriptorBlock->NumberOfSmmReservedRegions =3D SmramRanges; - - SmramIndex =3D 0; - for (Index =3D 0; Index < SmramRanges; Index++) { - // - // This is an SMRAM range, create an SMRAM descriptor - // - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart =3D = LowerMemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart =3D Lower= MemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize =3D T= segSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState =3D EF= I_SMRAM_CLOSED | EFI_CACHEABLE; - SmramIndex++; - } + Hob.Raw =3D BuildGuidHob( + &gEfiSmmSmramMemoryGuid, + BufferSize + ); + ASSERT(Hob.Raw); =20 - } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); - } + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.Raw= ); + SmramHobDescriptorBlock->NumberOfSmmReservedRegions =3D SmramRanges; =20 - // - // If QEMU presents an E820 map, then create memory HOBs for the >=3D4= GB RAM - // entries. Otherwise, create a single memory HOB with the flat >=3D4GB - // memory size read from the CMOS. - // - if (UpperMemorySize !=3D 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + SmramIndex =3D 0; + for (Index =3D 0; Index < SmramRanges; Index++) { + // + // This is an SMRAM range, create an SMRAM descriptor + // + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart =3D Lo= werMemorySize - TsegSize; + SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart =3D LowerMe= morySize - TsegSize; + SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize =3D Tse= gSize; + SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState =3D EFI_= SMRAM_CLOSED | EFI_CACHEABLE; + SmramIndex++; } + + } else { + AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } + + // + // If QEMU presents an E820 map, then create memory HOBs for the >=3D4GB= RAM + // entries. Otherwise, create a single memory HOB with the flat >=3D4GB + // memory size read from the CMOS. + // + if (UpperMemorySize !=3D 0) { + AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + } + } =20 /** --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103529): https://edk2.groups.io/g/devel/message/103529 Mute This Topic: https://groups.io/mt/98488191/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 15:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103530+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103530+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682406200; cv=none; d=zohomail.com; s=zohoarc; b=YlIFAUDkaeo+u4J/96kfH1ACpPNNMe+1rzVc82ncq4j7FCeoX6uiUN113NPIF0VojTOvJ9CukXWkQ/qYO+58VZmO8fHtxvHHvqrYb4WJ6+pKRdfHhlKcInMYEq4OaFn2rrUdud9lbGmg/u5hgB37MQYC4mvNOVSmjvfvs+4SK1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682406200; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ao+BSBr2JZw5UsG+cKucxXECLs1IaZVdYuSTJELmTY4=; b=ZUTw4kj3Rx8xN0GY4FHNYhit2ugnQKH1zyx0iPWYSDpumj3jt8VzK+Y9CjfYgFwr+wew6ITiqaOCyvz+5qKwbsdZhh/J5WMqjSOdJKgt/6KE1igJIwx35B5rWfxuoKAWWRDK9XIHHKGRi5FDhgw7aZTJZZOD/m++glpGil9lIKA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103530+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682406200800537.9336019603968; Tue, 25 Apr 2023 00:03:20 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cxOqYY1788612xj5DPWcuRBV; Tue, 25 Apr 2023 00:03:19 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.73794.1682406195842322329 for ; Tue, 25 Apr 2023 00:03:18 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="374623053" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="374623053" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="867781589" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="867781589" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:17 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [edk2-devel] [PATCH 2/5] SimicsOpenBoardPkg: Move AcpiVariableGuid hob to MemDetect Date: Tue, 25 Apr 2023 15:03:01 +0800 Message-Id: <20230425070304.2120-3-zhiguang.liu@intel.com> In-Reply-To: <20230425070304.2120-1-zhiguang.liu@intel.com> References: <20230425070304.2120-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: aqTzNSxQaAzYJA5XRpCrYQrSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682406199; bh=K7DArjxlhgVe2JbrZ/G3i9ihECuhAZlHpViEmcIWp/o=; h=Cc:Date:From:Reply-To:Subject:To; b=wvZvkVcZXc4eX5VVyMYMeW+IcNptk4gTlqeLAgE+Kgpj63W03sUxXoG9gwMobuItULN TvU2iQKlZzlsKwdhIO1gT85tLMEHgIZ5SSwDpRnmYsTSUFvJ2Oc96kINOlihxaMvcWm+K K9x1VWq/9T+KRFAjPUlPQHmZ17S63/ALyKs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682406201195100001 Content-Type: text/plain; charset="utf-8" Currently, MemDetect create gEfiSmmSmramMemoryGuid Hob containing one descriptor, which should be updated later, when AcpiVariableGuid hob use some buffer from SmRam. However, the Hob doesn't get updated, and this is a bug. Move the logic creating AcpiVariableGuid hob from PEIM SmmAccessPei.inf to MemDetect, so that in the same file, it has both knowleage about the smmram and the acpi data structure. So it can create the gEfiSmmSmramMemoryGuid Hob containing two descriptors. Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- .../SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 36 +++++++++++-------- .../SimicsPei/SimicsPei.inf | 1 + .../SimicsX58SktPkg/Smm/Access/SmmAccessPei.c | 8 ----- .../Smm/Access/SmmAccessPei.inf | 3 -- 4 files changed, 22 insertions(+), 26 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c b/Plat= form/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c index d80ac1d213..13ee415f40 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c @@ -391,11 +391,10 @@ QemuInitializeRam ( UINT64 LowerMemorySize; UINT64 UpperMemorySize; UINTN BufferSize; - UINT8 SmramIndex; UINT8 SmramRanges; EFI_PEI_HOB_POINTERS Hob; EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; - UINT8 Index; + VOID *GuidHob; =20 DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__)); =20 @@ -418,8 +417,8 @@ QemuInitializeRam ( AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); =20 - BufferSize =3D sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); - SmramRanges =3D 1; + SmramRanges =3D 2; + BufferSize =3D sizeof(EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (SmramRanges -= 1) * sizeof(EFI_SMRAM_DESCRIPTOR); =20 Hob.Raw =3D BuildGuidHob( &gEfiSmmSmramMemoryGuid, @@ -430,18 +429,25 @@ QemuInitializeRam ( SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)(Hob.Raw= ); SmramHobDescriptorBlock->NumberOfSmmReservedRegions =3D SmramRanges; =20 - SmramIndex =3D 0; - for (Index =3D 0; Index < SmramRanges; Index++) { - // - // This is an SMRAM range, create an SMRAM descriptor - // - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart =3D Lo= werMemorySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart =3D LowerMe= morySize - TsegSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize =3D Tse= gSize; - SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState =3D EFI_= SMRAM_CLOSED | EFI_CACHEABLE; - SmramIndex++; - } + // + // Create first SMRAM descriptor, which contains data structures used = in S3 resume. + // One page is enough for the data structure + // + SmramHobDescriptorBlock->Descriptor[0].PhysicalStart =3D LowerMemorySi= ze - TsegSize; + SmramHobDescriptorBlock->Descriptor[0].CpuStart =3D LowerMemorySize - = TsegSize; + SmramHobDescriptorBlock->Descriptor[0].PhysicalSize =3D EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[0].RegionState =3D EFI_SMRAM_CLOSE= D | EFI_CACHEABLE | EFI_ALLOCATED; + GuidHob =3D BuildGuidHob (&gEfiAcpiVariableGuid, sizeof(EFI_SMRAM_DESC= RIPTOR)); + ASSERT (GuidHob !=3D NULL); + CopyMem (GuidHob, &SmramHobDescriptorBlock->Descriptor[0], sizeof(EFI_= SMRAM_DESCRIPTOR)); =20 + // + // Create second SMRAM descriptor, which is free and will be used by S= MM foundation. + // + SmramHobDescriptorBlock->Descriptor[1].PhysicalStart =3D SmramHobDescr= iptorBlock->Descriptor[0].PhysicalStart + EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[1].CpuStart =3D SmramHobDescriptor= Block->Descriptor[0].CpuStart + EFI_PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[1].PhysicalSize =3D TsegSize - EFI= _PAGE_SIZE; + SmramHobDescriptorBlock->Descriptor[1].RegionState =3D EFI_SMRAM_CLOSE= D | EFI_CACHEABLE; } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf b/Pl= atform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf index 710fa680be..618ad4075f 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf @@ -40,6 +40,7 @@ [Guids] gEfiMemoryTypeInformationGuid gEfiSmmSmramMemoryGuid ## CONSUMES + gEfiAcpiVariableGuid =20 [LibraryClasses] BaseLib diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c b/Sili= con/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c index c54026b4d1..d489cc7513 100644 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c +++ b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c @@ -241,7 +241,6 @@ SmmAccessPeiEntryPoint ( EFI_STATUS Status; UINTN SmramMapSize; EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount]; - VOID *GuidHob; =20 // // This module should only be included if SMRAM support is required. @@ -322,13 +321,6 @@ SmmAccessPeiEntryPoint ( } DEBUG_CODE_END (); =20 - GuidHob =3D BuildGuidHob (&gEfiAcpiVariableGuid, sizeof SmramMap[DescIdx= SmmS3ResumeState]); - if (GuidHob =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState], sizeof SmramMap[De= scIdxSmmS3ResumeState]); - // // We're done. The next step should succeed, but even if it fails, we ca= n't // roll back the above BuildGuidHob() allocation, because PEI doesn't su= pport diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf b/Si= licon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf index 2b6b14f437..3c71e64fe9 100644 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf +++ b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf @@ -38,9 +38,6 @@ SimicsX58SktPkg/SktPkg.dec SimicsIch10Pkg/Ich10Pkg.dec =20 -[Guids] - gEfiAcpiVariableGuid - [LibraryClasses] BaseLib BaseMemoryLib --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103530): https://edk2.groups.io/g/devel/message/103530 Mute This Topic: https://groups.io/mt/98488192/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 15:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103531+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103531+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682406201; cv=none; d=zohomail.com; s=zohoarc; b=OyhglQXpzEJnuejLn72BoXGOq18rqWIxWm5VPtR5ysoTQMNY9FgeI93Ya38fN1xK5P8NDssW0XVUNQezNR1NWnSNpWgsQ4pFliu9ZWrODEUvZxVeAvgCq+D3tsYHCmXOcAqw3qWGnIqe5i20RbNp08BThREsOM0+o9UJNJIX5Yc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682406201; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0pPa0fc/LWqcFOaDYeXBKQRWIvBVFXmugTooI/rsA54=; b=Uj5fIMNaL4gu8F3TUSUxOlVitjqXu2GmwDwycdYXRPcwquXaTzjAIm+YWkDDKUphvvQQot4pKpeQSCaOoh3PuTd6Lo0Fxh2UvRvq/OZzz/53JHaSBCcs1nMDENRbUeLECozX95FawLBQ7T3bsjFJNx5tdr1IVdip2yK1C/NYvQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103531+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682406201796123.02151721492305; Tue, 25 Apr 2023 00:03:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1PlNYY1788612xUhs2ArpMH1; Tue, 25 Apr 2023 00:03:21 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.73794.1682406195842322329 for ; Tue, 25 Apr 2023 00:03:20 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="374623056" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="374623056" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="867781616" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="867781616" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:18 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [edk2-devel] [PATCH 3/5] SimicsOpenBoardPkg: Use SmmAccessLib instead of SmmAccessPei.inf Date: Tue, 25 Apr 2023 15:03:02 +0800 Message-Id: <20230425070304.2120-4-zhiguang.liu@intel.com> In-Reply-To: <20230425070304.2120-1-zhiguang.liu@intel.com> References: <20230425070304.2120-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: SIaeaKcsUekDiuWP3Zrrt3h2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682406201; bh=ok+7HPA/E9L/wM05c+2rYnMVdHVMgdRD6/YorCnhh6w=; h=Cc:Date:From:Reply-To:Subject:To; b=dJ3cr1Gji7SCPD3/HzqbknOFXuEp+29apozUJmXT7k34ao2++UVxq5hrwd1ky6Gqp8d GrNyuuGCLaOePctEwlgcMhg9phZZn9LDCxGqWcwft7jE8gjmuZoH4/rSF7biWsYkqNgJP FyAblLhSBzJ6rYKmsjapHaSyQtScwmzkkU8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682406203231100007 Content-Type: text/plain; charset="utf-8" SmmAccessPei.inf is a PEIM we should deleted, here is the reason: 1. It programs registers MCH_TOLUD to set the Low Usable DRAM, but reading LMCH_TOLUD always return zere in QSP platforms 2. It programs/reads MCH_TSEGMB to implemte some Smm Access service such as open/close/lock. However, this reading LMCH_TOLUD also always return zere in QSP platforms 3. It returns the hard-code Smm range information. However, there are two improper things about this. One is that we already have the hard code value about T-Seg base/size in MemDetect. The other Smm range informaton is already saved in gEfiSmmSmramMemoryGuid Hob. No need hard-code value. So, this patch uses another way, calling PeiInstallSmmAccessPpi from SmmAccessLib. The lib instance we choose will use the gEfiSmmSmramMemoryGuid Hob information. In a word, with the patch, we can avoid additional hard-code, and avoid programing unimplemented registers. Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu --- .../SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 7 +------ .../SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf | 1 - Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c | 9 +++++++++ .../Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf | 2 ++ 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc index 7b98baf764..fcae343146 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -142,6 +142,7 @@ # Silicon Package ##################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf =20 ##################################### # Platform Package @@ -190,12 +191,6 @@ ####################################### # Silicon Initialization Package ####################################### -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(SKT_PKG)/Smm/Access/SmmAccessPei.inf { - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } -!endif =20 ##################################### # Platform Package diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf index 221706ae03..844f9b6dcf 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf @@ -165,7 +165,6 @@ INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/Silic= onPolicyPeiPostMem.inf !include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf =20 INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf -INF $(SKT_PKG)/Smm/Access/SmmAccessPei.inf # S3 SMM PEI driver #INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf =20 diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c b/Plat= form/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c index 13ee415f40..f9a5487365 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 #include =20 @@ -472,6 +473,8 @@ InitializeRamRegions ( VOID ) { + EFI_STATUS Status; + QemuInitializeRam (); =20 if (mS3Supported && mBootMode !=3D BOOT_ON_S3_RESUME) { @@ -544,4 +547,10 @@ InitializeRamRegions ( ); } } + + // + // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case + // + Status =3D PeiInstallSmmAccessPpi (); + ASSERT_EFI_ERROR (Status); } diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf b/Pl= atform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf index 618ad4075f..cdc30ad582 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf @@ -36,6 +36,7 @@ SimicsX58SktPkg/SktPkg.dec SimicsIch10Pkg/Ich10Pkg.dec BoardModulePkg/BoardModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec =20 [Guids] gEfiMemoryTypeInformationGuid @@ -55,6 +56,7 @@ MtrrLib PcdLib CmosAccessLib + SmmAccessLib =20 [Pcd] gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103531): https://edk2.groups.io/g/devel/message/103531 Mute This Topic: https://groups.io/mt/98488193/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 15:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103532+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103532+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682406203; cv=none; d=zohomail.com; s=zohoarc; b=RxVhgBdSMWVnk89bj+AKg6gg64vaWqIa/zhF6LdlTiNSjIB2Rx9xY26y7CrHYxCXBMSAKH3PTrR66AHu7LZEq3tD12IE2DiKbq1RRA7+bwQ34t/oB8YTcGB26hDCz+YfLTy6x6nQ9vcDqf+YUmWjX0DSua84rO8v4dp2iw+DbL0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682406203; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7IaYAPX1XgwFcKIJcMr5SGxg/7IYJbauexq0asqzVNs=; b=RDo1kZZWXRZihJul5uQLCk93dhcidRMZcyPOwKK4d4ZLNSneNOz1A+nAY1Vonq/x+Rt8CaILWHMCFdovmK6sYRrMMFp+fubIEgB0/fo3WCLjUluMse7G5SF+S1SCBupn1UuPAla+m6QnC0TGBc+V26wlVYRWEBMzBY8nKFrL5PA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103532+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682406203077337.5230110113988; Tue, 25 Apr 2023 00:03:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id y4EGYY1788612xD8ZfyVjpTX; Tue, 25 Apr 2023 00:03:22 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.73794.1682406195842322329 for ; Tue, 25 Apr 2023 00:03:22 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="374623061" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="374623061" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="867781637" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="867781637" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:20 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [edk2-devel] [PATCH 4/5] SimicsOpenBoardPkg: Use another SmmAccess Driver Date: Tue, 25 Apr 2023 15:03:03 +0800 Message-Id: <20230425070304.2120-5-zhiguang.liu@intel.com> In-Reply-To: <20230425070304.2120-1-zhiguang.liu@intel.com> References: <20230425070304.2120-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: s8b3nQweue7QQcQmzI8WaiXHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682406202; bh=iyVCaHLJzg3FQy35CLeVG15eEBswwt6OKYjXxTfCT5s=; h=Cc:Date:From:Reply-To:Subject:To; b=NOm+OlPK2hVdMM+gOTatsOHhSIzZuHq3DpWWn7YSG0fylH8Bl+C5DzXdT02NnB+C37d lvFSu8Ja6ZT/mfm6z5OIsq/EDA9muQE5UKpf6l59+CODBt5uW413jsb70PUzgFtwswS/k p8Mog8hXE+KkkrU+FxP5InzYynq8mPHY/J0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682406204793100009 Content-Type: text/plain; charset="utf-8" Because of the similiar reason I mentioned in last commit, the SmmAccess2Dxe.inf driver should be deleted and the replacement will avoid hard-code and use gEfiSmmSmramMemoryGuid Hob to get Smm Range information. This can fix an exsiting bug, when gSmmBaseHobGuid may allocate buffer from smm range, and update gEfiSmmSmramMemoryGuid Hob. Current driver will return hard-code smm range and the buffer used by gSmmBaseHobGuid is marked as free range by mistake. Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu --- .../Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 2 +- Silicon/Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc index fcae343146..64c3af2584 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -278,7 +278,7 @@ !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf - $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf + IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf !endif =20 diff --git a/Silicon/Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf b/Silicon= /Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf index fdcb4fb9a7..ca3706578b 100644 --- a/Silicon/Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf +++ b/Silicon/Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf @@ -8,7 +8,7 @@ ## =20 !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - INF $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf + INF IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf !endif INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103532): https://edk2.groups.io/g/devel/message/103532 Mute This Topic: https://groups.io/mt/98488194/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sat May 18 15:08:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103533+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103533+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682406205; cv=none; d=zohomail.com; s=zohoarc; b=cXXtGa9zBU6jX5jUzCIqC311eknxrC2RTO2ReNYEjtjIr95y87glf7KzF4+aeKG7ZBnpiDT19vV6tUxJstE2YVFjHyYdiYPq46BHFKfyJB4ISbLUKYQmeUqz7DxGlz1sN8tXoSC25brxOXOG2+xeyIatJ9k0fjPB6ZcZvweTnYg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682406205; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sDlo1YmAmef9ULiaKDtdG993xAui9ycKP/nj7U5n71Q=; b=Fu9yP4ZPY3dl++HThMnCbhGqyaHKx4RYofULwi3NVJKPDXvvmwjGArui3sqWFriU6HNoeYgGZPKr+85wkSxLIIL3fYdZWBYcGRgSev0OviQYxRaw7BLESCkLQuP9OnyQXMduD9hzThv1K/XCkgPXsmaWmANFgEFR3Tk37FRUt2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103533+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682406205216547.7332172083728; Tue, 25 Apr 2023 00:03:25 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id PwNKYY1788612xGkVktBpNO2; Tue, 25 Apr 2023 00:03:24 -0700 X-Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.73794.1682406195842322329 for ; Tue, 25 Apr 2023 00:03:24 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="374623079" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="374623079" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10690"; a="867781673" X-IronPort-AV: E=Sophos;i="5.99,224,1677571200"; d="scan'208";a="867781673" X-Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2023 00:03:22 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Nate DeSimone , Ray Ni Subject: [edk2-devel] [PATCH 5/5] SimicsX58SktPkg: Remove unused Smm related modules Date: Tue, 25 Apr 2023 15:03:04 +0800 Message-Id: <20230425070304.2120-6-zhiguang.liu@intel.com> In-Reply-To: <20230425070304.2120-1-zhiguang.liu@intel.com> References: <20230425070304.2120-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: T7zsFR0gYrsaMyRV8JyMjWUTx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682406204; bh=wK/SdSA1/rT/BN+3FDc5YMB1B7hN0ViDneDxJoOT8J4=; h=Cc:Date:From:Reply-To:Subject:To; b=ArZ8ZiDV07h3yOKeqD38IwclBmCjDmXBkovSlTAMGoOI9NaQKcLcHNpDAvQDMevjRsc lsFhfRe6olLHbYoznx0g6YQiC/pXbg7nuOgtVLYK5KAhzw8+K3MMrIhyvVEUHuuFpu3E1 PSNjmEpyC+x0DMmG8VjoDfliDTdlKX1GDEY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682406206842100015 Content-Type: text/plain; charset="utf-8" In last two commit, I replace the two SMM related modules, and now no platform will use these two moduels. Remove them Cc: Nate DeSimone Cc: Ray Ni Signed-off-by: Zhiguang Liu Reviewed-by: Ray Ni --- .../Smm/Access/SmmAccess2Dxe.c | 148 -------- .../Smm/Access/SmmAccess2Dxe.inf | 54 --- .../SimicsX58SktPkg/Smm/Access/SmmAccessPei.c | 338 ------------------ .../Smm/Access/SmmAccessPei.inf | 62 ---- .../Smm/Access/SmramInternal.c | 200 ----------- .../Smm/Access/SmramInternal.h | 82 ----- 6 files changed, 884 deletions(-) delete mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c delete mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.= inf delete mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c delete mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.i= nf delete mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.c delete mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.h diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c b/Sil= icon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c deleted file mode 100644 index 5d3b2c14aa..0000000000 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c +++ /dev/null @@ -1,148 +0,0 @@ -/** @file - A DXE_DRIVER providing SMRAM access by producing EFI_SMM_ACCESS2_PROTOCO= L. - - X58 TSEG is expected to have been verified and set up by the SmmAccessPei - driver. - - Copyright (C) 2013, 2015, Red Hat, Inc.
- Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include - -#include "SmramInternal.h" - -/** - Opens the SMRAM area to be accessible by a boot-service driver. - - This function "opens" SMRAM so that it is visible while not inside of SM= M. - The function should return EFI_UNSUPPORTED if the hardware does not supp= ort - hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM - configuration is locked. - - @param[in] This The EFI_SMM_ACCESS2_PROTOCOL instance. - - @retval EFI_SUCCESS The operation was successful. - @retval EFI_UNSUPPORTED The system does not support opening and closin= g of - SMRAM. - @retval EFI_DEVICE_ERROR SMRAM cannot be opened, perhaps because it is - locked. -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccess2DxeOpen ( - IN EFI_SMM_ACCESS2_PROTOCOL *This - ) -{ - return SmramAccessOpen (&This->LockState, &This->OpenState); -} - -/** - Inhibits access to the SMRAM. - - This function "closes" SMRAM so that it is not visible while outside of = SMM. - The function should return EFI_UNSUPPORTED if the hardware does not supp= ort - hiding of SMRAM. - - @param[in] This The EFI_SMM_ACCESS2_PROTOCOL instance. - - @retval EFI_SUCCESS The operation was successful. - @retval EFI_UNSUPPORTED The system does not support opening and closin= g of - SMRAM. - @retval EFI_DEVICE_ERROR SMRAM cannot be closed. -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccess2DxeClose ( - IN EFI_SMM_ACCESS2_PROTOCOL *This - ) -{ - return SmramAccessClose (&This->LockState, &This->OpenState); -} - -/** - Inhibits access to the SMRAM. - - This function prohibits access to the SMRAM region. This function is us= ually - implemented such that it is a write-once operation. - - @param[in] This The EFI_SMM_ACCESS2_PROTOCOL instance. - - @retval EFI_SUCCESS The device was successfully locked. - @retval EFI_UNSUPPORTED The system does not support locking of SMRAM. -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccess2DxeLock ( - IN EFI_SMM_ACCESS2_PROTOCOL *This - ) -{ - return SmramAccessLock (&This->LockState, &This->OpenState); -} - -/** - Queries the memory controller for the possible regions that will support - SMRAM. - - @param[in] This The EFI_SMM_ACCESS2_PROTOCOL instance. - @param[in,out] SmramMapSize A pointer to the size, in bytes, of the - SmramMemoryMap buffer. - @param[in,out] SmramMap A pointer to the buffer in which firmware - places the current memory map. - - @retval EFI_SUCCESS The chipset supported the given resource. - @retval EFI_BUFFER_TOO_SMALL The SmramMap parameter was too small. The - current buffer size needed to hold the mem= ory - map is returned in SmramMapSize. -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccess2DxeGetCapabilities ( - IN CONST EFI_SMM_ACCESS2_PROTOCOL *This, - IN OUT UINTN *SmramMapSize, - IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap - ) -{ - return SmramAccessGetCapabilities (This->LockState, This->OpenState, - SmramMapSize, SmramMap); -} - -// -// LockState and OpenState will be filled in by the entry point. -// -STATIC EFI_SMM_ACCESS2_PROTOCOL mAccess2 =3D { - &SmmAccess2DxeOpen, - &SmmAccess2DxeClose, - &SmmAccess2DxeLock, - &SmmAccess2DxeGetCapabilities -}; - -// -// Entry point of this driver. -// -EFI_STATUS -EFIAPI -SmmAccess2DxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - // - // This module should only be included if SMRAM support is required. - // - ASSERT (FeaturePcdGet (PcdSmmSmramRequire)); - - GetStates (&mAccess2.LockState, &mAccess2.OpenState); - return gBS->InstallMultipleProtocolInterfaces (&ImageHandle, - &gEfiSmmAccess2ProtocolGuid, &mAccess2, - NULL); -} diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.inf b/S= ilicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.inf deleted file mode 100644 index eb8c8f93dd..0000000000 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.inf +++ /dev/null @@ -1,54 +0,0 @@ -## @file -# A DXE_DRIVER providing SMRAM access by producing EFI_SMM_ACCESS2_PROTOCO= L. -# -# X58 TSEG is expected to have been verified and set up by the SmmAccessPei -# driver. -# -# Copyright (C) 2013, 2015, Red Hat, Inc. -# Copyright (C) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D SmmAccess2Dxe - FILE_GUID =3D AC95AD3D-4366-44BF-9A62-E4B29D7A2206 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - PI_SPECIFICATION_VERSION =3D 0x00010400 - ENTRY_POINT =3D SmmAccess2DxeEntryPoint - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 -# - -[Sources] - SmmAccess2Dxe.c - SmramInternal.c - SmramInternal.h - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - SimicsX58SktPkg/SktPkg.dec - SimicsIch10Pkg/Ich10Pkg.dec - -[LibraryClasses] - DebugLib - PcdLib - PciLib - UefiBootServicesTableLib - UefiDriverEntryPoint - -[Protocols] - gEfiSmmAccess2ProtocolGuid ## PRODUCES - -[FeaturePcd] - gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire - -[Depex] - TRUE diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c b/Sili= con/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c deleted file mode 100644 index d489cc7513..0000000000 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c +++ /dev/null @@ -1,338 +0,0 @@ -/** @file - A PEIM with the following responsibilities: - - - verify & configure the X58 TSEG in the entry point, - - provide SMRAM access by producing PEI_SMM_ACCESS_PPI, - - set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and ex= pose - it via the gEfiAcpiVariableGuid GUID HOB. - - This PEIM runs from RAM, so we can write to variables with static storage - duration. - - Copyright (C) 2013, 2015, Red Hat, Inc.
- Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "SmramInternal.h" - -// -// PEI_SMM_ACCESS_PPI implementation. -// - -/** - Opens the SMRAM area to be accessible by a PEIM driver. - - This function "opens" SMRAM so that it is visible while not inside of SM= M. - The function should return EFI_UNSUPPORTED if the hardware does not supp= ort - hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM - configuration is locked. - - @param PeiServices General purpose services available to eve= ry - PEIM. - @param This The pointer to the SMM Access Interface. - @param DescriptorIndex The region of SMRAM to Open. - - @retval EFI_SUCCESS The region was successfully opened. - @retval EFI_DEVICE_ERROR The region could not be opened because lo= cked - by chipset. - @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. - -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccessPeiOpen ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_SMM_ACCESS_PPI *This, - IN UINTN DescriptorIndex - ) -{ - if (DescriptorIndex >=3D DescIdxCount) { - return EFI_INVALID_PARAMETER; - } - - // - // According to current practice, DescriptorIndex is not considered at a= ll, - // beyond validating it. - // - return SmramAccessOpen (&This->LockState, &This->OpenState); -} - -/** - Inhibits access to the SMRAM. - - This function "closes" SMRAM so that it is not visible while outside of = SMM. - The function should return EFI_UNSUPPORTED if the hardware does not supp= ort - hiding of SMRAM. - - @param PeiServices General purpose services available to e= very - PEIM. - @param This The pointer to the SMM Access Interface. - @param DescriptorIndex The region of SMRAM to Close. - - @retval EFI_SUCCESS The region was successfully closed. - @retval EFI_DEVICE_ERROR The region could not be closed because - locked by chipset. - @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. - -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccessPeiClose ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_SMM_ACCESS_PPI *This, - IN UINTN DescriptorIndex - ) -{ - if (DescriptorIndex >=3D DescIdxCount) { - return EFI_INVALID_PARAMETER; - } - - // - // According to current practice, DescriptorIndex is not considered at a= ll, - // beyond validating it. - // - return SmramAccessClose (&This->LockState, &This->OpenState); -} - -/** - Inhibits access to the SMRAM. - - This function prohibits access to the SMRAM region. This function is us= ually - implemented such that it is a write-once operation. - - @param PeiServices General purpose services available to e= very - PEIM. - @param This The pointer to the SMM Access Interface. - @param DescriptorIndex The region of SMRAM to Close. - - @retval EFI_SUCCESS The region was successfully locked. - @retval EFI_DEVICE_ERROR The region could not be locked because at - least one range is still open. - @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. - -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccessPeiLock ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_SMM_ACCESS_PPI *This, - IN UINTN DescriptorIndex - ) -{ - if (DescriptorIndex >=3D DescIdxCount) { - return EFI_INVALID_PARAMETER; - } - - // - // According to current practice, DescriptorIndex is not considered at a= ll, - // beyond validating it. - // - return SmramAccessLock (&This->LockState, &This->OpenState); -} - -/** - Queries the memory controller for the possible regions that will support - SMRAM. - - @param PeiServices General purpose services available to every - PEIM. - @param This The pointer to the SmmAccessPpi Interface. - @param SmramMapSize The pointer to the variable containing siz= e of - the buffer to contain the description - information. - @param SmramMap The buffer containing the data describing = the - Smram region descriptors. - - @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buff= er. - @retval EFI_SUCCESS The user provided a sufficiently-sized buf= fer. - -**/ -STATIC -EFI_STATUS -EFIAPI -SmmAccessPeiGetCapabilities ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_SMM_ACCESS_PPI *This, - IN OUT UINTN *SmramMapSize, - IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap - ) -{ - return SmramAccessGetCapabilities (This->LockState, This->OpenState, Smr= amMapSize, SmramMap); -} - -// -// LockState and OpenState will be filled in by the entry point. -// -STATIC PEI_SMM_ACCESS_PPI mAccess =3D { - &SmmAccessPeiOpen, - &SmmAccessPeiClose, - &SmmAccessPeiLock, - &SmmAccessPeiGetCapabilities -}; - - -STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] =3D { - { - EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, - &gPeiSmmAccessPpiGuid, &mAccess - } -}; - - -// -// Utility functions. -// -STATIC -UINT8 -CmosRead8 ( - IN UINT8 Index - ) -{ - IoWrite8 (0x70, Index); - return IoRead8 (0x71); -} - -STATIC -UINT32 -GetSystemMemorySizeBelow4gb ( - VOID - ) -{ - UINT32 Cmos0x34; - UINT32 Cmos0x35; - - Cmos0x34 =3D CmosRead8 (0x34); - Cmos0x35 =3D CmosRead8 (0x35); - - return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB; -} - - -// -// Entry point of this driver. -// -EFI_STATUS -EFIAPI -SmmAccessPeiEntryPoint ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - UINT16 HostBridgeDevId; - UINT32 EsmramcVal; - UINT32 TopOfLowRam, TopOfLowRamMb; - EFI_STATUS Status; - UINTN SmramMapSize; - EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount]; - - // - // This module should only be included if SMRAM support is required. - // - ASSERT (FeaturePcdGet (PcdSmmSmramRequire)); - - // - // Verify if we're running on a X58 machine type. - // - HostBridgeDevId =3D PciRead16 (SIMICS_HOSTBRIDGE_DID); - if (HostBridgeDevId !=3D INTEL_ICH10_DEVICE_ID) { - DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=3D0x%04x; only= " - "DID=3D0x%04x (X58) is supported\n", __FUNCTION__, HostBridgeDevId, - INTEL_ICH10_DEVICE_ID)); - goto WrongConfig; - } - - // - // Confirm if Simics supports SMRAM. - // - // With no support for it, the ESMRAMC (Extended System Management RAM - // Control) register reads as zero. If there is support, the cache-enable - // bits are hard-coded as 1 by Simics. - // - - TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); - ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) =3D=3D 0); - TopOfLowRamMb =3D TopOfLowRam >> 20; - DEBUG((EFI_D_INFO, "TopOfLowRam =3D0x%x; TopOfLowRamMb =3D0x%x \n", TopO= fLowRam, TopOfLowRamMb)); - - - // - // Set Top of Low Usable DRAM. - // - PciWrite32 (DRAMC_REGISTER_X58(MCH_TOLUD), TopOfLowRam); - DEBUG((EFI_D_INFO, "MCH_TOLUD =3D0x%x; \n", PciRead32(DRAMC_REGISTER_X58= (MCH_TOLUD)))); - - // - // Set TSEG Memory Base. - // - EsmramcVal =3D (TopOfLowRamMb - FixedPcdGet8(PcdX58TsegMbytes)) << MCH_T= SEGMB_MB_SHIFT; - // - // Set TSEG size, and disable TSEG visibility outside of SMM. Note that = the - // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility = is - // *restricted* to SMM. - // - EsmramcVal &=3D ~(UINT32)MCH_ESMRAMC_TSEG_MASK; - EsmramcVal |=3D FixedPcdGet8 (PcdX58TsegMbytes) =3D=3D 8 ? MCH_ESMRAMC_T= SEG_8MB : - FixedPcdGet8 (PcdX58TsegMbytes) =3D=3D 2 ? MCH_ESMRAMC_TSE= G_2MB : - MCH_ESMRAMC_TSEG_1MB; - EsmramcVal |=3D MCH_ESMRAMC_T_EN; - PciWrite32(DRAMC_REGISTER_X58(MCH_TSEGMB), EsmramcVal); - DEBUG((EFI_D_INFO, "MCH_TSEGMB =3D0x%x; \n", PciRead32(DRAMC_REGISTER_X5= 8(MCH_TSEGMB)))); - DEBUG((EFI_D_INFO, "MCH_TSEGMB_1 =3D0x%x; MCH_TSEGMB_2 =3D0x%x;\n", ((To= pOfLowRamMb - FixedPcdGet8(PcdX58TsegMbytes)) << MCH_TSEGMB_MB_SHIFT), Esmr= amcVal)); - - // - // Create the GUID HOB and point it to the first SMRAM range. - // - GetStates (&mAccess.LockState, &mAccess.OpenState); - SmramMapSize =3D sizeof SmramMap; - Status =3D SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenSt= ate, &SmramMapSize, SmramMap); - ASSERT_EFI_ERROR (Status); - - DEBUG_CODE_BEGIN (); - { - UINTN Count; - UINTN Idx; - - Count =3D SmramMapSize / sizeof SmramMap[0]; - DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTI= ON__, (INT32)Count)); - DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)= ", - "PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)")); - for (Idx =3D 0; Idx < Count; ++Idx) { - DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n", - SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize, - SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState)); - } - } - DEBUG_CODE_END (); - - // - // We're done. The next step should succeed, but even if it fails, we ca= n't - // roll back the above BuildGuidHob() allocation, because PEI doesn't su= pport - // releasing memory. - // - return PeiServicesInstallPpi (mPpiList); - -WrongConfig: - // - // We really don't want to continue in this case. - // - ASSERT (FALSE); - CpuDeadLoop (); - return EFI_UNSUPPORTED; -} diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf b/Si= licon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf deleted file mode 100644 index 3c71e64fe9..0000000000 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf +++ /dev/null @@ -1,62 +0,0 @@ -## @file -# A PEIM with the following responsibilities: -# -# - provide SMRAM access by producing PEI_SMM_ACCESS_PPI, -# - verify & configure the X58 TSEG in the entry point, -# - set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and ex= pose -# it via the gEfiAcpiVariableGuid GUIDed HOB. -# -# Copyright (C) 2013, 2015, Red Hat, Inc. -# Copyright (C) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D SmmAccessPei - FILE_GUID =3D 6C0E75B4-B0B9-44D1-8210-3377D7B4E066 - MODULE_TYPE =3D PEIM - VERSION_STRING =3D 1.0 - ENTRY_POINT =3D SmmAccessPeiEntryPoint - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 -# - -[Sources] - SmmAccessPei.c - SmramInternal.c - SmramInternal.h - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - SimicsX58SktPkg/SktPkg.dec - SimicsIch10Pkg/Ich10Pkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - HobLib - IoLib - PcdLib - PciLib - PeiServicesLib - PeimEntryPoint - -[FeaturePcd] - gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire - -[FixedPcd] - gSimicsX58PkgTokenSpaceGuid.PcdX58TsegMbytes - -[Ppis] - gPeiSmmAccessPpiGuid ## PRODUCES - -[Depex] - gEfiPeiMemoryDiscoveredPpiGuid diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.c b/Sil= icon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.c deleted file mode 100644 index 4b5a92f602..0000000000 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.c +++ /dev/null @@ -1,200 +0,0 @@ -/** @file - Functions and types shared by the SMM accessor PEI and DXE modules. - - Copyright (C) 2015, Red Hat, Inc. - Copyright (C) 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include -#include -#include -#include - -#include "SmramInternal.h" - -BOOLEAN gLockState; -BOOLEAN gOpenState; - -/** - Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and - OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL ob= ject, - from the D_LCK and T_EN bits. - - PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rel= y on - the LockState and OpenState fields being up-to-date on entry, and they n= eed - to restore the same invariant on exit, if they touch the bits in questio= n. - - @param[out] LockState Reflects the D_LCK bit on output; TRUE iff SMRAM = is - locked. - @param[out] OpenState Reflects the inverse of the T_EN bit on output; T= RUE - iff SMRAM is open. -**/ -VOID -GetStates ( - OUT BOOLEAN *LockState, - OUT BOOLEAN *OpenState -) -{ - UINT8 EsmramcVal; - - EsmramcVal =3D PciRead8(DRAMC_REGISTER_X58(MCH_TSEGMB)); - - *OpenState =3D !(EsmramcVal & MCH_ESMRAMC_T_EN); - *LockState =3D !*OpenState; - - *OpenState =3D gOpenState; - *LockState =3D gLockState; -} - -// -// The functions below follow the PEI_SMM_ACCESS_PPI and -// EFI_SMM_ACCESS2_PROTOCOL member declarations. The PeiServices and This -// pointers are removed (TSEG doesn't depend on them), and so is the -// DescriptorIndex parameter (TSEG doesn't support range-wise locking). -// -// The LockState and OpenState members that are common to both -// PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL are taken and updated in -// isolation from the rest of the (non-shared) members. -// - -EFI_STATUS -SmramAccessOpen ( - OUT BOOLEAN *LockState, - OUT BOOLEAN *OpenState - ) -{ - - // - // Open TSEG by clearing T_EN. - // - PciAnd8(DRAMC_REGISTER_X58(MCH_TSEGMB), - (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff)); - - gOpenState =3D TRUE; - gLockState =3D !gOpenState; - - GetStates (LockState, OpenState); - if (!*OpenState) { - return EFI_DEVICE_ERROR; - } - return EFI_SUCCESS; -} - -EFI_STATUS -SmramAccessClose ( - OUT BOOLEAN *LockState, - OUT BOOLEAN *OpenState - ) -{ - // - // Close TSEG by setting T_EN. - // - PciOr8(DRAMC_REGISTER_X58(MCH_TSEGMB), MCH_ESMRAMC_T_EN); - - gOpenState =3D FALSE; - gLockState =3D !gOpenState; - - GetStates (LockState, OpenState); - if (*OpenState) { - return EFI_DEVICE_ERROR; - } - return EFI_SUCCESS; -} - -EFI_STATUS -SmramAccessLock ( - OUT BOOLEAN *LockState, - IN OUT BOOLEAN *OpenState - ) -{ - if (*OpenState) { - return EFI_DEVICE_ERROR; - } - - // - // Close & lock TSEG by setting T_EN and D_LCK. - // - PciOr8 (DRAMC_REGISTER_X58(MCH_TSEGMB), MCH_ESMRAMC_T_EN); - - gOpenState =3D FALSE; - gLockState =3D !gOpenState; - - GetStates (LockState, OpenState); - if (*OpenState || !*LockState) { - return EFI_DEVICE_ERROR; - } - return EFI_SUCCESS; -} - -EFI_STATUS -SmramAccessGetCapabilities ( - IN BOOLEAN LockState, - IN BOOLEAN OpenState, - IN OUT UINTN *SmramMapSize, - IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap - ) -{ - UINTN OriginalSize; - UINT32 TsegMemoryBaseMb, TsegMemoryBase; - UINT64 CommonRegionState; - UINT8 TsegSizeBits; - - OriginalSize =3D *SmramMapSize; - *SmramMapSize =3D DescIdxCount * sizeof *SmramMap; - if (OriginalSize < *SmramMapSize) { - return EFI_BUFFER_TOO_SMALL; - } - - // - // Read the TSEG Memory Base register. - // - TsegMemoryBaseMb =3D PciRead32(DRAMC_REGISTER_X58(MCH_TSEGMB)); - - TsegMemoryBaseMb =3D 0xDF800000; - - TsegMemoryBase =3D (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20; - - // - // Precompute the region state bits that will be set for all regions. - // - CommonRegionState =3D (OpenState ? EFI_SMRAM_OPEN : EFI_SMRAM_CLOSED) | - (LockState ? EFI_SMRAM_LOCKED : 0) | - EFI_CACHEABLE; - - // - // The first region hosts an SMM_S3_RESUME_STATE object. It is located a= t the - // start of TSEG. We round up the size to whole pages, and we report it = as - // EFI_ALLOCATED, so that the SMM_CORE stays away from it. - // - SmramMap[DescIdxSmmS3ResumeState].PhysicalStart =3D TsegMemoryBase; - SmramMap[DescIdxSmmS3ResumeState].CpuStart =3D TsegMemoryBase; - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =3D - EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE))); - SmramMap[DescIdxSmmS3ResumeState].RegionState =3D - CommonRegionState | EFI_ALLOCATED; - - // - // Get the TSEG size bits from the ESMRAMC register. - // - TsegSizeBits =3D PciRead8 (DRAMC_REGISTER_X58(MCH_TSEGMB)) & - MCH_ESMRAMC_TSEG_MASK; - - TsegSizeBits =3D MCH_ESMRAMC_TSEG_8MB; - - // - // The second region is the main one, following the first. - // - SmramMap[DescIdxMain].PhysicalStart =3D - SmramMap[DescIdxSmmS3ResumeState].PhysicalStart + - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; - SmramMap[DescIdxMain].CpuStart =3D SmramMap[DescIdxMain].PhysicalStart; - SmramMap[DescIdxMain].PhysicalSize =3D - (TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB : - TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB : - SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; - SmramMap[DescIdxMain].RegionState =3D CommonRegionState; - - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.h b/Sil= icon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.h deleted file mode 100644 index 81180a9c8e..0000000000 --- a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.h +++ /dev/null @@ -1,82 +0,0 @@ -/** @file - Functions and types shared by the SMM accessor PEI and DXE modules. - - Copyright (C) 2015, Red Hat, Inc. - Copyright (C) 2019, Intel Corporation. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include - -// -// We'll have two SMRAM ranges. -// -// The first is a tiny one that hosts an SMM_S3_RESUME_STATE object, to be -// filled in by the CPU SMM driver during normal boot, for the PEI instanc= e of -// the LockBox library (which will rely on the object during S3 resume). -// -// The other SMRAM range is the main one, for the SMM core and the SMM dri= vers. -// -typedef enum { - DescIdxSmmS3ResumeState =3D 0, - DescIdxMain =3D 1, - DescIdxCount =3D 2 -} DESCRIPTOR_INDEX; - -/** - Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and - OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL ob= ject, - from the D_LCK and T_EN bits. - - PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rel= y on - the LockState and OpenState fields being up-to-date on entry, and they n= eed - to restore the same invariant on exit, if they touch the bits in questio= n. - - @param[out] LockState Reflects the D_LCK bit on output; TRUE iff SMRAM = is - locked. - @param[out] OpenState Reflects the inverse of the T_EN bit on output; T= RUE - iff SMRAM is open. -**/ -VOID -GetStates ( - OUT BOOLEAN *LockState, - OUT BOOLEAN *OpenState - ); - -// -// The functions below follow the PEI_SMM_ACCESS_PPI and -// EFI_SMM_ACCESS2_PROTOCOL member declarations. The PeiServices and This -// pointers are removed (TSEG doesn't depend on them), and so is the -// DescriptorIndex parameter (TSEG doesn't support range-wise locking). -// -// The LockState and OpenState members that are common to both -// PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL are taken and updated in -// isolation from the rest of the (non-shared) members. -// - -EFI_STATUS -SmramAccessOpen ( - OUT BOOLEAN *LockState, - OUT BOOLEAN *OpenState - ); - -EFI_STATUS -SmramAccessClose ( - OUT BOOLEAN *LockState, - OUT BOOLEAN *OpenState - ); - -EFI_STATUS -SmramAccessLock ( - OUT BOOLEAN *LockState, - IN OUT BOOLEAN *OpenState - ); - -EFI_STATUS -SmramAccessGetCapabilities ( - IN BOOLEAN LockState, - IN BOOLEAN OpenState, - IN OUT UINTN *SmramMapSize, - IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap - ); --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103533): https://edk2.groups.io/g/devel/message/103533 Mute This Topic: https://groups.io/mt/98488195/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-