From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103465+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103465+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330769; cv=none; d=zohomail.com; s=zohoarc; b=Oi4a+knMfbq92AyIWsZWr2f2oz7KAbo+L5l9UPYZRlcx5U5hk9MEGxlY0IL799l8MfTfHWwjemMTy6WbwKm5V/gAkX+beiwuUEVix+GsM04ALCaY3YzGUTizY70ziYkeWIv2htnryRngzykHmdLNLEagL23vDWR9joK6cvIcIwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330769; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ZM4ZjbDihbqP3tKJfYwPgW7hazlWyC22APLA6qA/51A=; b=JhES1wmJK2MDNlUE349S2SY9gVqzhMQyRovm4I2sQOvVGA/yeQZSxOV3WWC0WLIgMIb3m2za4fquy2gebh2IH+hLxWQ2wmWQrtVyY9MgLF2msso08Oi4D90EZysNW+1IHBSr9eMfeK1PO9I6ZjPAFCFytpw635rrblfypr6c5PM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103465+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330769662205.66705293135306; Mon, 24 Apr 2023 03:06:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id cG21YY1788612xHJVfhy0CrM; Mon, 24 Apr 2023 03:06:09 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:08 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897738" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897738" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766937" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766937" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:06 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Ray Ni Subject: [edk2-devel] [Patch V3 1/8] MdePkg: Move CpuPageTableLib defination to MdePkg Date: Mon, 24 Apr 2023 18:05:45 +0800 Message-Id: <20230424100552.2718-2-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: S6DzdADQ9hvEcGDswurFYYQHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330769; bh=gxI0S+YcTRCd48TFk250w7Hhm27nnWDkaAJ7iceXH3I=; h=Cc:Date:From:Reply-To:Subject:To; b=O26mhgG+JsptLOipI32Tr7dlwZJgS6xwKjuJ9evIv34H9SLYVrsMEQUWCmUW0DaitJK 9pjVa4hymzeb8bS7hJ0LAO9MIQoOWUsC+JCeNY5slICO2j0xjBrrH4DD7/BI/wfuJHHSM 2bxkXFH4EwJ624m7oXc82fLPC3yqTE+bLEI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330770304100005 Content-Type: text/plain; charset="utf-8" Move CpuPageTableLib defination from UefiCpuPkg to MdePkg. The lib instance still remains in UefiCpuPkg. Move CpuPageTableLib defination to a common location can avoid the case that MdeModulePkg need to depend on UefiCpuPkg since DxeIpl module in MdeModulePkg needs to consume CpuPageTableLib. Signed-off-by: Dun Tan Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Ray Ni --- {UefiCpuPkg =3D> MdePkg}/Include/Library/CpuPageTableLib.h | 0 MdePkg/MdePkg.dec | 5 ++++- UefiCpuPkg/UefiCpuPkg.dec | 3 --- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/MdePkg/Include/= Library/CpuPageTableLib.h similarity index 100% rename from UefiCpuPkg/Include/Library/CpuPageTableLib.h rename to MdePkg/Include/Library/CpuPageTableLib.h diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 7488ccda7a..dfbca2d746 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -4,7 +4,7 @@ # It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of # EFI1.10/UEFI2.7/PI1.7 and some Industry Standards. # -# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP
# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
@@ -321,6 +321,9 @@ ## @libraryclass Provides function to support TDX processing. TdxLib|Include/Library/TdxLib.h =20 + ## @libraryclass Provides function for manipulating x86 paging structu= res. + CpuPageTableLib|Include/Library/CpuPageTableLib.h + [LibraryClasses.RISCV64] ## @libraryclass Provides function to make ecalls to SBI BaseRiscVSbiLib|Include/Library/BaseRiscVSbiLib.h diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index a5528277ff..5ad41e9ae3 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -57,9 +57,6 @@ ## @libraryclass Provides function for loading microcode. MicrocodeLib|Include/Library/MicrocodeLib.h =20 - ## @libraryclass Provides function for manipulating x86 paging structu= res. - CpuPageTableLib|Include/Library/CpuPageTableLib.h - [Guids] gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }} gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }} --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103465): https://edk2.groups.io/g/devel/message/103465 Mute This Topic: https://groups.io/mt/98466783/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103466+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103466+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330771; cv=none; d=zohomail.com; s=zohoarc; b=k1jizBJvoJj+adQ2p71OWNiGN1vTvOhDlvTRhukpXCYCkhtEnJZmtaiBbJvmeHnErmKDDjin2ZkBVBo5CmzHYc1furiV45q9HMEeA4RlCPvtlu9bzogrNBbdgSj9N/mRqG1v/5OKs0JIRy2GEEg3B49cK/w4g6f9BdAd9xJGp84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330771; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xA7Prq27TZaeXxPIvSuzuAQnTQPoJWdEjR8PJx0LQSU=; b=cXRBQIk+U3GH10kZFXq5UqHh6O1cnvodMCUUgWfb+/ZsskKe+N4LYS1jlHgysP4/rjy1XQ0Cyqku+AwvJuoqbZdAjNHncc5UFbKA46uCHLr75Elp6igUUJuAO/oUwODh4yqiC2/U8/TYOsR3s0J+xTwgRhYOP13FX9p7ZyaIe7w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103466+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330771906962.8173628394547; Mon, 24 Apr 2023 03:06:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id NaOOYY1788612xkh73Qz8D3e; Mon, 24 Apr 2023 03:06:11 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:11 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897759" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897759" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766941" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766941" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:09 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Andrew Fish , Ray Ni Subject: [edk2-devel] [Patch V3 2/8] EmulatorPkg: Add CpuPageTableLib required by DxeIpl in DSC Date: Mon, 24 Apr 2023 18:05:46 +0800 Message-Id: <20230424100552.2718-3-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: e1pdZMhS98IH21uImyc4EKRrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330771; bh=zTAzeuVRnIbau9PBtKPFkDME+bm66/43tbqnoO/XyG0=; h=Cc:Date:From:Reply-To:Subject:To; b=jYP2hF1mKs1IBldNclzr+xQaVaVkO3bwdbXjwRe3s6R0kCjm0Z+LwwPYAjsPnRSMa0B xFKfvkcaE2dkw/14SNd7FipidNple5J3MoGYTKkywwm02Uc20OqdTGEmK9qCRqykA2QXM 4+Y/WNcv4M45cLYFaqgyQPp2Aa4rRZusQOI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330773987100011 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib instance required by DxeIpl in EmulatorPkg.dsc. Signed-off-by: Dun Tan Cc: Andrew Fish Reviewed-by: Ray Ni --- EmulatorPkg/EmulatorPkg.dsc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc index b44435d7e6..d1fb9d9256 100644 --- a/EmulatorPkg/EmulatorPkg.dsc +++ b/EmulatorPkg/EmulatorPkg.dsc @@ -4,7 +4,7 @@ # The Emulation Platform can be used to debug individual modules, prior to= creating # a real platform. This also provides an example for how an DSC is created. # -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# Portions copyright (c) 2010 - 2011, Apple Inc. All rights reserved.
# Copyright (c) Microsoft Corporation. # @@ -66,6 +66,7 @@ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 # # UEFI & PI --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103466): https://edk2.groups.io/g/devel/message/103466 Mute This Topic: https://groups.io/mt/98466784/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103467+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103467+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330774; cv=none; d=zohomail.com; s=zohoarc; b=D9Gh588MfKf9tVN7hdu5gwoh9qYP6yc3ygLTDdFel4oi5LmHzT4oYNZbWNnvGJljgym9U5P7gjijowwZ2zffZNdp2WEJ+t1/9AtkXLHf3h9ljoU5YPegsVP4roK3yhmRzqB+Efz0rS+r1T0HOGT8WrKljm1G8kO4aKIbfJmJ66s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330774; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=BNAY+e5TazkHjh4aOIj4NviUM3TuVJuY0xGERUeKI2w=; b=iAShZdWF4IE/Mciiz3tp08V1uEjYAIC5Z2gaX1yUIR0l0gZJQ1A5wjsqIdwnj9MgopBopnTof2u8505kH90xpUqpverw+qID3SNengBrZCdyJs77VBbsOC+/FjzlnBm88dICrm5yVcCLq/HgaxYZPW6IpChRPzN4rh4qgBtWQx0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103467+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330774251439.20950299621404; Mon, 24 Apr 2023 03:06:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 60TAYY1788612xSlmy40VnKR; Mon, 24 Apr 2023 03:06:13 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:13 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897795" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897795" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766968" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766968" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:11 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ray Ni Subject: [edk2-devel] [Patch V3 3/8] IntelFsp2Pkg: Add CpuPageTableLib required by DxeIpl in DSC Date: Mon, 24 Apr 2023 18:05:47 +0800 Message-Id: <20230424100552.2718-4-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 4AabfbxQkUXhuL3A8JMAYh5wx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330773; bh=AmY/IWZtvhNttnzaOtMZHdv6LrYx+73nQj9t2g34//U=; h=Cc:Date:From:Reply-To:Subject:To; b=b1y/cq+g9I9eDMzrc1M4KVIqPzeB4Hbix+2P+ABfxfkY88/SZ93KqwbbZk8fVT+5ZUg LlpsdnstH/vHvW95g/csmHifqg+fa3p5zETsbi/VSrpfSMHO9aBE0Q1zMHk7o9AoWCldI ci0PohcbT5UzefkPe3L9GA7tR8D8LBYY30M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330776298100002 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib instance required by DxeIpl in QemuFspPkg.dsc of IntelFsp2Pkg. Signed-off-by: Dun Tan Reviewed-by: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni --- IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc b/IntelFsp2Pkg/Tools/T= ests/QemuFspPkg.dsc index 3155812118..52052692dd 100644 --- a/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc +++ b/IntelFsp2Pkg/Tools/Tests/QemuFspPkg.dsc @@ -1,7 +1,7 @@ ## @file # FSP DSC build file for QEMU platform # -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the= BSD License @@ -114,6 +114,7 @@ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf !endif + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 =20 ##########################################################################= ###### --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103467): https://edk2.groups.io/g/devel/message/103467 Mute This Topic: https://groups.io/mt/98466785/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103468+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103468+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330776; cv=none; d=zohomail.com; s=zohoarc; b=jeeT7dfV2zuqIdvkGNwIQ8ADjg1NbF06KvsZ9+7DVPb/IroDsPn7CymVX5cjyATaxiESOUm8xYJqmFMXY7adBOZSHqe+ZuI3cyHAupqun6GKcaVzU1KjxVWGSyDrg83rjWWV2r9ncYWSCwPCEvkUvZhZPdY+e7K0PIi+0DchcQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330776; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ixrZdVa0jxVTWFSRxXZ/a9EqY29ASbquBgSWCTS9c2A=; b=dsJtE+XPv901RDRWfIl9TzTfWnxzWsRHOwuZ/ZM4VuKOG3WIOYCkn2uqByzOmgican+b72IjXHnl9/5wSMNs2e4lmKvCmZGFBbS5EXSLkZhC7vthbRgkBtUborTag4BD89yBHgYwjsRZE1+7to1zLiuAcCR7TOoRWcu52x5m+WU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103468+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330776649611.7493204512017; Mon, 24 Apr 2023 03:06:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jrNVYY1788612xdAJshmfur8; Mon, 24 Apr 2023 03:06:16 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:15 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897826" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897826" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766973" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766973" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:14 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Ray Ni Subject: [edk2-devel] [Patch V3 4/8] MdeModulePkg: Add CpuPageTableLib required by DxeIpl in DSC Date: Mon, 24 Apr 2023 18:05:48 +0800 Message-Id: <20230424100552.2718-5-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: 4ZbhymmCKiPDwDuchum7d69bx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330776; bh=Rq0TXUvl0qWsDFZw3kaa7JAZn6zBHCl0kJzAIQFrhsc=; h=Cc:Date:From:Reply-To:Subject:To; b=vaDygkwVBLXnNSGQE5ShVhuq/JyVt3yXa0JSK3T+6W4tA6dIZ26Dyk/LdPHZoLvembc h8u5bFObXQRqLWOq74sVSFDSTHvmFXX7Vw8rl2k1iI8K6buB/WCLE+njXXlEfr3+k4osF JudqArtXZPf16eGipt+uBMvrxU8yE8TY5lQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330776970100005 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib instance required by DxeIpl in MdeModulePkg.dsc. Signed-off-by: Dun Tan Acked-by: Jian J Wang Cc: Liming Gao Cc: Ray Ni --- MdeModulePkg/MdeModulePkg.dsc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc index 1014598f31..d95acabe83 100644 --- a/MdeModulePkg/MdeModulePkg.dsc +++ b/MdeModulePkg/MdeModulePkg.dsc @@ -2,7 +2,7 @@ # EFI/PI Reference Module Package for All Architectures # # (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
-# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) Microsoft Corporation. # Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# @@ -106,6 +106,7 @@ MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibN= ull.inf VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseV= ariableFlashInfoLib.inf IpmiCommandLib|MdeModulePkg/Library/BaseIpmiCommandLibNull/BaseIpmiComma= ndLibNull.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 [LibraryClasses.EBC.PEIM] IoLib|MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103468): https://edk2.groups.io/g/devel/message/103468 Mute This Topic: https://groups.io/mt/98466786/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103469+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103469+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330779; cv=none; d=zohomail.com; s=zohoarc; b=n9BhyLQREKfEMsmMxE+8CQxMyX8eHHSgxMhYvBlfqLs4pkwjMfDKzK/Lau4kWX2lxf3VLz4B+J8Dn2bfaMG78b7TZSsdO654TpoIn353NLTIHwa5gDpKfhlcpKS+ZIdYe8x1QHUYEC+9DIOVyBKb3agR+VnTLZ61YrykrbLozw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330779; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=tmTO99FpCu5PsmF/i+SSMiCbE9KMRrmsAnP+nV7jvuE=; b=gLzAt0sH7H+LxT/5kho3E+L35wof0GTlkQkptW7V71lqvEpvbTVfITycUZ3wEtzKYm4MaFFZf+DnPYIRHaatn/nImrDjpVEYjDxjb79CZFryvOxPgBFJD0ifpj9emp9Bbr5kDn46y1h1c6qk85ltuheHBn0P5oSGKWhBVCOPwho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103469+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330779373542.4939381393654; Mon, 24 Apr 2023 03:06:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id N0rTYY1788612x6c0kNPGlUi; Mon, 24 Apr 2023 03:06:19 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:18 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897852" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897852" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766980" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766980" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:16 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Ray Ni Subject: [edk2-devel] [Patch V3 5/8] OvmfPkg: Add CpuPageTableLib required by DxeIpl in DSC file Date: Mon, 24 Apr 2023 18:05:49 +0800 Message-Id: <20230424100552.2718-6-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: HXw9mwqgfHDKs8H8m21W8k9Sx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330779; bh=tDzbfnEoPDaAG73pMDWL6vBJ7wcnmYShqji2ThAE4tc=; h=Cc:Date:From:Reply-To:Subject:To; b=l7VOqt8eWnq4OafuMCB2lMcNUPp9z4ZJZ+bSEP9ug7dBnSgAuQO2B+9uWxD9qBGBCdU K0M8uY2lLwy7U3+GvI0AcUU0IvxNtXnaE8q+DWDO03k+I5gWB5Otp37+XEXZIkEL8mZVV dkq8OzAUqQ132xfGrAN/t/hLjjcCgyDcWZ4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330780362100002 Content-Type: text/plain; charset="utf-8" Add CpuPageTableLib instance required by DxeIpl in corresponding DSC files of OvmfPkg. Signed-off-by: Dun Tan Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Acked-by: Gerd Hoffmann Cc: Ray Ni --- OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +- OvmfPkg/Bhyve/BhyveX64.dsc | 3 ++- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/Microvm/MicrovmX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 3 ++- OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 2 +- OvmfPkg/OvmfXen.dsc | 2 +- 8 files changed, 10 insertions(+), 8 deletions(-) diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 943c4eed98..f8956f7147 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -169,6 +169,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf @@ -348,7 +349,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/Bhyve/BhyveX64.dsc b/OvmfPkg/Bhyve/BhyveX64.dsc index d0d2712c56..67f8a77c3a 100644 --- a/OvmfPkg/Bhyve/BhyveX64.dsc +++ b/OvmfPkg/Bhyve/BhyveX64.dsc @@ -1,6 +1,6 @@ # # Copyright (c) 2020, Rebecca Cran -# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) 2014, Pluribus Networks, Inc. # @@ -171,6 +171,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index cc2dd925bc..8a2fb8049f 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -190,6 +190,7 @@ MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLi= b.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif @@ -399,7 +400,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index e9aab51559..7ffb72e06e 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -193,6 +193,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf @@ -398,7 +399,6 @@ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf PciPcdProducerLib|OvmfPkg/Fdt/FdtPciPcdProducerLib/FdtPciPcdProducerLib.= inf PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExp= ressLib.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 86177bb948..77f10e2c86 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# Copyright (c) Microsoft Corporation. # @@ -193,6 +193,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 065b544506..156d6c1434 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -197,6 +197,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ibNull.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf !endif @@ -409,7 +410,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 3d405cd4ad..35bb011212 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -210,6 +210,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 !if $(SMM_REQUIRE) =3D=3D FALSE LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf @@ -430,7 +431,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 8bfc16c2d3..1174a166ae 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -173,6 +173,7 @@ MemEncryptTdxLib|OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxL= ib.inf PeiHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/PeiHardwareInfoLib.inf DxeHardwareInfoLib|OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf + CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf =20 !if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf @@ -334,7 +335,6 @@ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf - CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf NestedInterruptTplLib|OvmfPkg/Library/NestedInterruptTplLib/NestedInterr= uptTplLib.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103469): https://edk2.groups.io/g/devel/message/103469 Mute This Topic: https://groups.io/mt/98466787/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103470+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103470+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330782; cv=none; d=zohomail.com; s=zohoarc; b=FfPM+w/AfqBdnfMwWtvlVnncSKQyELMN/wbOEaCj0Iuxh977qS2eNxemYmdLCwmH3TQBoihg8gkFQySTHl31YcGQF9MfdmkZ1qoU57OZmIU4dpcFxl2ECuksQw+gQbeKOGV+p+AFjXEBYzJw2sN8/7/JHzubnn/HnCWc87Bi5P8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330782; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=1eacXUOIR5A697C25+19z4Biiem/JiuOeeTr7Kt1JTo=; b=ZmFe/nyG8U+z5Lw1N8oN8Q60Rn3HtRsP3Tyx6zYX2XkE8PLpTTo7Ok78kSGD+oJmZ6bveaBf7DmEUluvlMU7G6EOSI6RFOse1j/xfaEmrX+aKbxGtju/c5acXbYCGYvj3P564XLX0ClRT1T8EhiBMUB+s/l3bJUqnK1XDoMVqag= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103470+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330782425188.58529835203478; Mon, 24 Apr 2023 03:06:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id qX0OYY1788612xNhYU5bsc2M; Mon, 24 Apr 2023 03:06:22 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:21 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897876" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897876" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766990" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766990" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:19 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Ray Ni , Jian J Wang , Tom Lendacky Subject: [edk2-devel] [Patch V3 6/8] MdeModulePkg/DxeIpl: Create page table by CpuPageTableLib Date: Mon, 24 Apr 2023 18:05:50 +0800 Message-Id: <20230424100552.2718-7-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: QLQq4KZeQEc8JHzatoAxfTAHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330782; bh=F3AwYm34W5HnhiE2ugEzjLjhEFTtULrzz5OJTTfvxyg=; h=Cc:Date:From:Reply-To:Subject:To; b=rufvG25+c9N/X13CAsM83v++WuZVqzekdFei723PAdFGxcramR8gF+5yDixea7kHS8Y YyhM+aytfcR0QAjxf3D0ZNAUZg/u5dQ45sK2CxQERGEr+sbPryTgRynR3PO+wrrSEOinw 6D7WLVR6IgZnCti0VXAFMJ71G4Je1Ix1YJA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330784379100003 Content-Type: text/plain; charset="utf-8" Modify CreateIdentityMappingPageTables() to create page table based on CpuPageTableLib in DxeIpl module. This function can be used to create both IA32 PAE paging and long mode 4-level, 5-level paging structure. With the PageTableMap() API in the CpuPageTableLib, we can remove the complicated page table manipulating code. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Dandan Bi Cc: Liming Gao Cc: Ray Ni Cc: Jian J Wang Cc: Tom Lendacky --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.h | 3 ++- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 ++++- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 109 ++++---------------= ---------------------------------------------------------------------------= --------------- MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c | 5 +++-- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 567 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 167 ++++++++++---------= ---------------------------------------------------------------------------= ------------------------------------------------------------------------- 6 files changed, 177 insertions(+), 679 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h b/MdeModulePkg/Core/DxeI= plPeim/DxeIpl.h index 2f015befce..03e6f8cff7 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.h @@ -2,7 +2,7 @@ Master header file for DxeIpl PEIM. All source files in this module shou= ld include this file for common definitions. =20 -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -42,6 +42,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #define STACK_SIZE 0x20000 #define BSP_STORE_SIZE 0x4000 diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 052ea0ec1a..f636f042cb 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -5,7 +5,7 @@ # PPI to discover and dispatch the DXE Foundation and components that are # needed to run the DXE Foundation. # -# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.
@@ -80,6 +80,9 @@ PeiServicesTablePointerLib PerformanceLib =20 +[LibraryClasses.IA32, LibraryClasses.X64] + CpuPageTableLib + [LibraryClasses.ARM, LibraryClasses.AARCH64] ArmMmuLib =20 diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 4bc7b749b0..69d073fb58 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -1,7 +1,7 @@ /** @file Ia32-specific functionality for DxeLoad. =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -70,107 +70,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDe= scriptor =3D { 0 }; =20 -/** - Allocates and fills in the Page Directory and Page Table Entries to - establish a 4G page table. - - @param[in] StackBase Stack base address. - @param[in] StackSize Stack size. - - @return The address of page table. - -**/ -UINTN -Create4GPageTablesIa32Pae ( - IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize - ) -{ - UINT8 PhysicalAddressBits; - EFI_PHYSICAL_ADDRESS PhysicalAddress; - UINTN IndexOfPdpEntries; - UINTN IndexOfPageDirectoryEntries; - UINT32 NumberOfPdpEntriesNeeded; - PAGE_MAP_AND_DIRECTORY_POINTER *PageMap; - PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; - PAGE_TABLE_ENTRY *PageDirectoryEntry; - UINTN TotalPagesNum; - UINTN PageAddress; - UINT64 AddressEncMask; - - // - // Make sure AddressEncMask is contained to smallest supported address f= ield - // - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; - - PhysicalAddressBits =3D 32; - - // - // Calculate the table entries needed. - // - NumberOfPdpEntriesNeeded =3D (UINT32)LShiftU64 (1, (PhysicalAddressBits = - 30)); - - TotalPagesNum =3D NumberOfPdpEntriesNeeded + 1; - PageAddress =3D (UINTN)AllocatePageTableMemory (TotalPagesNum); - ASSERT (PageAddress !=3D 0); - - PageMap =3D (VOID *)PageAddress; - PageAddress +=3D SIZE_4KB; - - PageDirectoryPointerEntry =3D PageMap; - PhysicalAddress =3D 0; - - for (IndexOfPdpEntries =3D 0; IndexOfPdpEntries < NumberOfPdpEntriesNeed= ed; IndexOfPdpEntries++, PageDirectoryPointerEntry++) { - // - // Each Directory Pointer entries points to a page of Page Directory e= ntires. - // So allocate space for them and fill them in in the IndexOfPageDirec= toryEntries loop. - // - PageDirectoryEntry =3D (VOID *)PageAddress; - PageAddress +=3D SIZE_4KB; - - // - // Fill in a Page Directory Pointer Entries - // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry | AddressEncMask; - PageDirectoryPointerEntry->Bits.Present =3D 1; - - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < = 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += =3D SIZE_2MB) { - if ( (IsNullDetectionEnabled () && (PhysicalAddress =3D=3D 0)) - || ( (PhysicalAddress < StackBase + StackSize) - && ((PhysicalAddress + SIZE_2MB) > StackBase))) - { - // - // Need to split this 2M page that covers stack range. - // - Split2MPageTo4K (PhysicalAddress, (UINT64 *)PageDirectoryEntry, St= ackBase, StackSize, 0, 0); - } else { - // - // Fill in the Page Directory entries - // - PageDirectoryEntry->Uint64 =3D (UINT64)PhysicalAddress | A= ddressEncMask; - PageDirectoryEntry->Bits.ReadWrite =3D 1; - PageDirectoryEntry->Bits.Present =3D 1; - PageDirectoryEntry->Bits.MustBe1 =3D 1; - } - } - } - - for ( ; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPoint= erEntry++) { - ZeroMem ( - PageDirectoryPointerEntry, - sizeof (PAGE_MAP_AND_DIRECTORY_POINTER) - ); - } - - // - // Protect the page table by marking the memory used for page table to be - // read-only. - // - EnablePageTableProtection ((UINTN)PageMap, FALSE); - - return (UINTN)PageMap; -} - /** The function will check if IA32 PAE is supported. =20 @@ -299,9 +198,9 @@ HandOffToDxeCore ( // AsmWriteGdtr (&gGdt); // - // Create page table and save PageMapLevel4 to CR3 + // Create page table and save PageMapLevel4 or PageMapLevel5 to CR3 // - PageTables =3D CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZ= E, 0, 0); + PageTables =3D CreateIdentityMappingPageTables (TRUE, BaseOfStack, STA= CK_SIZE, 0, 0); =20 // // End of PEI phase signal @@ -422,7 +321,7 @@ HandOffToDxeCore ( PageTables =3D 0; BuildPageTablesIa32Pae =3D ToBuildPageTable (); if (BuildPageTablesIa32Pae) { - PageTables =3D Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE); + PageTables =3D CreateIdentityMappingPageTables (FALSE, BaseOfStack, = STACK_SIZE, 0, 0); if (IsEnableNonExecNeeded ()) { EnableExecuteDisableBit (); } diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c b/MdeModulePkg/= Core/DxeIplPeim/X64/DxeLoadFunc.c index fa2050cf02..2642092ee5 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c @@ -1,7 +1,7 @@ /** @file x64-specifc functionality for DxeLoad. =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -91,9 +91,10 @@ HandOffToDxeCore ( PageTables =3D 0; if (FeaturePcdGet (PcdDxeIplBuildPageTables)) { // - // Create page table and save PageMapLevel4 to CR3 + // Create page table and save PageMapLevel4 or PageMapLevel5 to CR3 // PageTables =3D CreateIdentityMappingPageTables ( + TRUE, (EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE, (EFI_PHYSICAL_ADDRESS)(UINTN)GhcbBase, diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 18b121d768..80482c7853 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -15,7 +15,7 @@ 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:In= struction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 -Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -186,55 +186,6 @@ EnableExecuteDisableBit ( } } =20 -/** - The function will check if page table entry should be splitted to smaller - granularity. - - @param Address Physical memory address. - @param Size Size of the given physical memory. - @param StackBase Base address of stack. - @param StackSize Size of stack. - @param GhcbBase Base address of GHCB pages. - @param GhcbSize Size of GHCB area. - - @retval TRUE Page table should be split. - @retval FALSE Page table should not be split. -**/ -BOOLEAN -ToSplitPageTable ( - IN EFI_PHYSICAL_ADDRESS Address, - IN UINTN Size, - IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize, - IN EFI_PHYSICAL_ADDRESS GhcbBase, - IN UINTN GhcbSize - ) -{ - if (IsNullDetectionEnabled () && (Address =3D=3D 0)) { - return TRUE; - } - - if (PcdGetBool (PcdCpuStackGuard)) { - if ((StackBase >=3D Address) && (StackBase < (Address + Size))) { - return TRUE; - } - } - - if (PcdGetBool (PcdSetNxForStack)) { - if ((Address < StackBase + StackSize) && ((Address + Size) > StackBase= )) { - return TRUE; - } - } - - if (GhcbBase !=3D 0) { - if ((Address < GhcbBase + GhcbSize) && ((Address + Size) > GhcbBase)) { - return TRUE; - } - } - - return FALSE; -} - /** Initialize a buffer pool for page table use only. =20 @@ -341,143 +292,42 @@ AllocatePageTableMemory ( } =20 /** - Split 2M page to 4K. - - @param[in] PhysicalAddress Start physical address the 2M page= covered. - @param[in, out] PageEntry2M Pointer to 2M page entry. - @param[in] StackBase Stack base address. - @param[in] StackSize Stack size. - @param[in] GhcbBase GHCB page area base address. - @param[in] GhcbSize GHCB page area size. - + This function creates a new page table or modifies the page MapAttribute= for the memory region + specified by BaseAddress and Length from their current attributes to the= attributes specified + by MapAttribute and Mask. + + @param[in] PageTable Pointer to Page table address. + @param[in] PagingMode The paging mode. + @param[in] BaseAddress The start of the linear address range. + @param[in] Length The length of the linear address range. + @param[in] MapAttribute The attribute of the linear address range. + @param[in] MapMask The mask used for attribute. **/ VOID -Split2MPageTo4K ( - IN EFI_PHYSICAL_ADDRESS PhysicalAddress, - IN OUT UINT64 *PageEntry2M, - IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize, - IN EFI_PHYSICAL_ADDRESS GhcbBase, - IN UINTN GhcbSize +CreateOrUpdatePageTable ( + IN UINTN *PageTable, + IN PAGING_MODE PagingMode, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN IA32_MAP_ATTRIBUTE *MapAttribute, + IN IA32_MAP_ATTRIBUTE *MapMask ) { - EFI_PHYSICAL_ADDRESS PhysicalAddress4K; - UINTN IndexOfPageTableEntries; - PAGE_TABLE_4K_ENTRY *PageTableEntry; - UINT64 AddressEncMask; - - // - // Make sure AddressEncMask is contained to smallest supported address f= ield - // - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; - - PageTableEntry =3D AllocatePageTableMemory (1); - ASSERT (PageTableEntry !=3D NULL); - - // - // Fill in 2M page entry. - // - *PageEntry2M =3D (UINT64)(UINTN)PageTableEntry | AddressEncMask | IA32_P= G_P | IA32_PG_RW; - - PhysicalAddress4K =3D PhysicalAddress; - for (IndexOfPageTableEntries =3D 0; IndexOfPageTableEntries < 512; Index= OfPageTableEntries++, PageTableEntry++, PhysicalAddress4K +=3D SIZE_4KB) { - // - // Fill in the Page Table entries - // - PageTableEntry->Uint64 =3D (UINT64)PhysicalAddress4K; - - // - // The GHCB range consists of two pages per CPU, the GHCB and a - // per-CPU variable page. The GHCB page needs to be mapped as an - // unencrypted page while the per-CPU variable page needs to be - // mapped encrypted. These pages alternate in assignment. - // - if ( (GhcbBase =3D=3D 0) - || (PhysicalAddress4K < GhcbBase) - || (PhysicalAddress4K >=3D GhcbBase + GhcbSize) - || (((PhysicalAddress4K - GhcbBase) & SIZE_4KB) !=3D 0)) - { - PageTableEntry->Uint64 |=3D AddressEncMask; - } - - PageTableEntry->Bits.ReadWrite =3D 1; - - if ((IsNullDetectionEnabled () && (PhysicalAddress4K =3D=3D 0)) || - (PcdGetBool (PcdCpuStackGuard) && (PhysicalAddress4K =3D=3D StackB= ase))) - { - PageTableEntry->Bits.Present =3D 0; - } else { - PageTableEntry->Bits.Present =3D 1; - } - - if ( PcdGetBool (PcdSetNxForStack) - && (PhysicalAddress4K >=3D StackBase) - && (PhysicalAddress4K < StackBase + StackSize)) - { - // - // Set Nx bit for stack. - // - PageTableEntry->Bits.Nx =3D 1; - } + RETURN_STATUS Status; + UINTN PageTableBufferSize; + VOID *PageTableBuffer; + + PageTableBufferSize =3D 0; + Status =3D PageTableMap (PageTable, PagingMode, NULL, &Page= TableBufferSize, BaseAddress, Length, MapAttribute, MapMask, NULL); + if (Status =3D=3D RETURN_BUFFER_TOO_SMALL) { + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTa= bleBufferSize)); + DEBUG ((DEBUG_INFO, "DxeIpl: 0x%x bytes needed for page table\n", Page= TableBufferSize)); + ASSERT (PageTableBuffer !=3D NULL); + Status =3D PageTableMap (PageTable, PagingMode, PageTableBuffer, &Page= TableBufferSize, BaseAddress, Length, MapAttribute, MapMask, NULL); } -} - -/** - Split 1G page to 2M. - - @param[in] PhysicalAddress Start physical address the 1G page= covered. - @param[in, out] PageEntry1G Pointer to 1G page entry. - @param[in] StackBase Stack base address. - @param[in] StackSize Stack size. - @param[in] GhcbBase GHCB page area base address. - @param[in] GhcbSize GHCB page area size. - -**/ -VOID -Split1GPageTo2M ( - IN EFI_PHYSICAL_ADDRESS PhysicalAddress, - IN OUT UINT64 *PageEntry1G, - IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize, - IN EFI_PHYSICAL_ADDRESS GhcbBase, - IN UINTN GhcbSize - ) -{ - EFI_PHYSICAL_ADDRESS PhysicalAddress2M; - UINTN IndexOfPageDirectoryEntries; - PAGE_TABLE_ENTRY *PageDirectoryEntry; - UINT64 AddressEncMask; =20 - // - // Make sure AddressEncMask is contained to smallest supported address f= ield - // - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; - - PageDirectoryEntry =3D AllocatePageTableMemory (1); - ASSERT (PageDirectoryEntry !=3D NULL); - - // - // Fill in 1G page entry. - // - *PageEntry1G =3D (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask | IA= 32_PG_P | IA32_PG_RW; - - PhysicalAddress2M =3D PhysicalAddress; - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { - if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSiz= e, GhcbBase, GhcbSize)) { - // - // Need to split this 2M page that covers NULL or stack range. - // - Split2MPageTo4K (PhysicalAddress2M, (UINT64 *)PageDirectoryEntry, St= ackBase, StackSize, GhcbBase, GhcbSize); - } else { - // - // Fill in the Page Directory entries - // - PageDirectoryEntry->Uint64 =3D (UINT64)PhysicalAddress2M | A= ddressEncMask; - PageDirectoryEntry->Bits.ReadWrite =3D 1; - PageDirectoryEntry->Bits.Present =3D 1; - PageDirectoryEntry->Bits.MustBe1 =3D 1; - } - } + ASSERT_RETURN_ERROR (Status); + ASSERT (PageTableBufferSize =3D=3D 0); } =20 /** @@ -657,19 +507,20 @@ EnablePageTableProtection ( } =20 /** - Allocates and fills in the Page Directory and Page Table Entries to + Create IA32 PAE paging or 4-level/5-level paging for long mode to establish a 1:1 Virtual to Physical mapping. =20 - @param[in] StackBase Stack base address. - @param[in] StackSize Stack size. - @param[in] GhcbBase GHCB base address. - @param[in] GhcbSize GHCB size. - - @return The address of 4 level page map. + @param[in] Is64BitPageTable Whether to create 64-bit page table. + @param[in] StackBase Stack base address. + @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB base address. + @param[in] GhcbSize GHCB size. =20 + @return PageTable Address **/ UINTN CreateIdentityMappingPageTables ( + IN BOOLEAN Is64BitPageTable, IN EFI_PHYSICAL_ADDRESS StackBase, IN UINTN StackSize, IN EFI_PHYSICAL_ADDRESS GhcbBase, @@ -680,274 +531,164 @@ CreateIdentityMappingPageTables ( CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32 RegEdx; UINT8 PhysicalAddressBits; - EFI_PHYSICAL_ADDRESS PageAddress; - UINTN IndexOfPml5Entries; - UINTN IndexOfPml4Entries; - UINTN IndexOfPdpEntries; - UINTN IndexOfPageDirectoryEntries; - UINT32 NumberOfPml5EntriesNeeded; - UINT32 NumberOfPml4EntriesNeeded; - UINT32 NumberOfPdpEntriesNeeded; - PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel5Entry; - PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; - PAGE_MAP_AND_DIRECTORY_POINTER *PageMap; - PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; - PAGE_TABLE_ENTRY *PageDirectoryEntry; - UINTN TotalPagesNum; - UINTN BigPageAddress; VOID *Hob; BOOLEAN Page5LevelSupport; BOOLEAN Page1GSupport; - PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; UINT64 AddressEncMask; IA32_CR4 Cr4; - - // - // Set PageMapLevel5Entry to suppress incorrect compiler/analyzer warnin= gs - // - PageMapLevel5Entry =3D NULL; + PAGING_MODE PagingMode; + UINTN PageTable; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + EFI_PHYSICAL_ADDRESS GhcbBase4K; + EFI_PHYSICAL_ADDRESS GhcbBaseEnd; =20 // // Make sure AddressEncMask is contained to smallest supported address f= ield // - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; - - Page1GSupport =3D FALSE; - if (PcdGetBool (PcdUse1GPageTable)) { - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D 0x80000001) { - AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); - if ((RegEdx & BIT26) !=3D 0) { - Page1GSupport =3D TRUE; + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & P= AGING_1G_ADDRESS_MASK_64; + Page5LevelSupport =3D FALSE; + Page1GSupport =3D FALSE; + + if (!Is64BitPageTable) { + PagingMode =3D PagingPae; + PhysicalAddressBits =3D 32; + } else { + if (PcdGetBool (PcdUse1GPageTable)) { + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000001) { + AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); + if ((RegEdx & BIT26) !=3D 0) { + Page1GSupport =3D TRUE; + } } } - } =20 - // - // Get physical address bits supported. - // - Hob =3D GetFirstHob (EFI_HOB_TYPE_CPU); - if (Hob !=3D NULL) { - PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace; - } else { - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D 0x80000008) { - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits =3D (UINT8)RegEax; + // + // Get physical address bits supported. + // + Hob =3D GetFirstHob (EFI_HOB_TYPE_CPU); + if (Hob !=3D NULL) { + PhysicalAddressBits =3D ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace; } else { - PhysicalAddressBits =3D 36; + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8)RegEax; + } else { + PhysicalAddressBits =3D 36; + } } - } =20 - Page5LevelSupport =3D FALSE; - if (PcdGetBool (PcdUse5LevelPageTable)) { - AsmCpuidEx ( - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, - NULL, - &EcxFlags.Uint32, - NULL - ); - if (EcxFlags.Bits.FiveLevelPage !=3D 0) { - Page5LevelSupport =3D TRUE; + if (PcdGetBool (PcdUse5LevelPageTable)) { + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, + NULL, + NULL, + &EcxFlags.Uint32, + NULL + ); + if (EcxFlags.Bits.FiveLevelPage !=3D 0) { + Page5LevelSupport =3D TRUE; + } } - } - - DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n", = PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); - - // - // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses - // when 5-Level Paging is disabled, - // due to either unsupported by HW, or disabled by PCD. - // - ASSERT (PhysicalAddressBits <=3D 52); - if (!Page5LevelSupport && (PhysicalAddressBits > 48)) { - PhysicalAddressBits =3D 48; - } =20 - // - // Calculate the table entries needed. - // - NumberOfPml5EntriesNeeded =3D 1; - if (PhysicalAddressBits > 48) { - NumberOfPml5EntriesNeeded =3D (UINT32)LShiftU64 (1, PhysicalAddressBit= s - 48); - PhysicalAddressBits =3D 48; - } + if (Page5LevelSupport) { + if (Page1GSupport) { + PagingMode =3D Paging5Level1GB; + } else { + PagingMode =3D Paging5Level; + } + } else { + if (Page1GSupport) { + PagingMode =3D Paging4Level1GB; + } else { + PagingMode =3D Paging4Level; + } + } =20 - NumberOfPml4EntriesNeeded =3D 1; - if (PhysicalAddressBits > 39) { - NumberOfPml4EntriesNeeded =3D (UINT32)LShiftU64 (1, PhysicalAddressBit= s - 39); - PhysicalAddressBits =3D 39; + DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n"= , PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); + // + // IA-32e paging translates 48-bit linear addresses to 52-bit physical= addresses + // when 5-Level Paging is disabled, due to either unsupported by HW, o= r disabled by PCD. + // + ASSERT (PhysicalAddressBits <=3D 52); + if (!Page5LevelSupport && (PhysicalAddressBits > 48)) { + PhysicalAddressBits =3D 48; + } } =20 - NumberOfPdpEntriesNeeded =3D 1; - ASSERT (PhysicalAddressBits > 30); - NumberOfPdpEntriesNeeded =3D (UINT32)LShiftU64 (1, PhysicalAddressBits -= 30); + PageTable =3D 0; + MapAttribute.Uint64 =3D AddressEncMask; + MapAttribute.Bits.Present =3D 1; + MapAttribute.Bits.ReadWrite =3D 1; + MapMask.Uint64 =3D MAX_UINT64; + CreateOrUpdatePageTable (&PageTable, PagingMode, 0, LShiftU64 (1, Physic= alAddressBits), &MapAttribute, &MapMask); =20 - // - // Pre-allocate big pages to avoid later allocations. - // - if (!Page1GSupport) { - TotalPagesNum =3D ((NumberOfPdpEntriesNeeded + 1) * NumberOfPml4Entrie= sNeeded + 1) * NumberOfPml5EntriesNeeded + 1; - } else { - TotalPagesNum =3D (NumberOfPml4EntriesNeeded + 1) * NumberOfPml5Entrie= sNeeded + 1; - } - - // - // Substract the one page occupied by PML5 entries if 5-Level Paging is = disabled. - // - if (!Page5LevelSupport) { - TotalPagesNum--; + if ((GhcbBase > 0) && (GhcbSize > 0) && (AddressEncMask !=3D 0)) { + // + // The GHCB range consists of two pages per CPU, the GHCB and a + // per-CPU variable page. The GHCB page needs to be mapped as an + // unencrypted page while the per-CPU variable page needs to be + // mapped encrypted. These pages alternate in assignment. + // + ASSERT (Is64BitPageTable =3D=3D TRUE); + GhcbBase4K =3D ALIGN_VALUE (GhcbBase, SIZE_4= KB); + GhcbBaseEnd =3D ALIGN_VALUE (GhcbBase + GhcbS= ize, SIZE_4KB); + MapMask.Uint64 =3D 0; + MapMask.Bits.PageTableBaseAddressLow =3D 1; + // + // Loop through the GHCB range, remapping the GHCB page unencrypted + // and skipping over the per-CPU variable page. + // + while (GhcbBase4K < GhcbBaseEnd) { + MapAttribute.Uint64 =3D GhcbBase4K; + CreateOrUpdatePageTable (&PageTable, PagingMode, GhcbBase4K, SIZE_4K= B, &MapAttribute, &MapMask); + GhcbBase4K +=3D (SIZE_4KB * 2); + } } =20 - DEBUG (( - DEBUG_INFO, - "Pml5=3D%u Pml4=3D%u Pdp=3D%u TotalPage=3D%Lu\n", - NumberOfPml5EntriesNeeded, - NumberOfPml4EntriesNeeded, - NumberOfPdpEntriesNeeded, - (UINT64)TotalPagesNum - )); - - BigPageAddress =3D (UINTN)AllocatePageTableMemory (TotalPagesNum); - ASSERT (BigPageAddress !=3D 0); - - // - // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. - // - PageMap =3D (VOID *)BigPageAddress; - if (Page5LevelSupport) { + if (PcdGetBool (PcdSetNxForStack)) { // - // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it. + // Set the stack as Nx in page table. // - PageMapLevel5Entry =3D PageMap; - BigPageAddress +=3D SIZE_4KB; + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.Nx =3D 1; + MapMask.Uint64 =3D 0; + MapMask.Bits.Nx =3D 1; + CreateOrUpdatePageTable (&PageTable, PagingMode, StackBase, StackSize,= &MapAttribute, &MapMask); } =20 - PageAddress =3D 0; - - for ( IndexOfPml5Entries =3D 0 - ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded - ; IndexOfPml5Entries++) - { + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.Present =3D 0; + MapMask.Uint64 =3D 0; + MapMask.Bits.Present =3D 1; + if (IsNullDetectionEnabled ()) { // - // Each PML5 entry points to a page of PML4 entires. - // So lets allocate space for them and fill them in in the IndexOfPml4= Entries loop. - // When 5-Level Paging is disabled, below allocation happens only once. + // Set [0, 4KB] as non-present in page table. // - PageMapLevel4Entry =3D (VOID *)BigPageAddress; - BigPageAddress +=3D SIZE_4KB; - - if (Page5LevelSupport) { - // - // Make a PML5 Entry - // - PageMapLevel5Entry->Uint64 =3D (UINT64)(UINTN)PageMapLevel4E= ntry | AddressEncMask; - PageMapLevel5Entry->Bits.ReadWrite =3D 1; - PageMapLevel5Entry->Bits.Present =3D 1; - PageMapLevel5Entry++; - } - - for ( IndexOfPml4Entries =3D 0 - ; IndexOfPml4Entries < (NumberOfPml5EntriesNeeded =3D=3D 1 ? Num= berOfPml4EntriesNeeded : 512) - ; IndexOfPml4Entries++, PageMapLevel4Entry++) - { - // - // Each PML4 entry points to a page of Page Directory Pointer entire= s. - // So lets allocate space for them and fill them in in the IndexOfPd= pEntries loop. - // - PageDirectoryPointerEntry =3D (VOID *)BigPageAddress; - BigPageAddress +=3D SIZE_4KB; - - // - // Make a PML4 Entry - // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryP= ointerEntry | AddressEncMask; - PageMapLevel4Entry->Bits.ReadWrite =3D 1; - PageMapLevel4Entry->Bits.Present =3D 1; - - if (Page1GSupport) { - PageDirectory1GEntry =3D (VOID *)PageDirectoryPointerEntry; - - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress= +=3D SIZE_1GB) { - if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSiz= e, GhcbBase, GhcbSize)) { - Split1GPageTo2M (PageAddress, (UINT64 *)PageDirectory1GEntry, = StackBase, StackSize, GhcbBase, GhcbSize); - } else { - // - // Fill in the Page Directory entries - // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress |= AddressEncMask; - PageDirectory1GEntry->Bits.ReadWrite =3D 1; - PageDirectory1GEntry->Bits.Present =3D 1; - PageDirectory1GEntry->Bits.MustBe1 =3D 1; - } - } - } else { - for ( IndexOfPdpEntries =3D 0 - ; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded =3D=3D 1 ? = NumberOfPdpEntriesNeeded : 512) - ; IndexOfPdpEntries++, PageDirectoryPointerEntry++) - { - // - // Each Directory Pointer entries points to a page of Page Direc= tory entires. - // So allocate space for them and fill them in in the IndexOfPag= eDirectoryEntries loop. - // - PageDirectoryEntry =3D (VOID *)BigPageAddress; - BigPageAddress +=3D SIZE_4KB; - - // - // Fill in a Page Directory Pointer Entries - // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)Pag= eDirectoryEntry | AddressEncMask; - PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; - PageDirectoryPointerEntry->Bits.Present =3D 1; - - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress= +=3D SIZE_2MB) { - if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackS= ize, GhcbBase, GhcbSize)) { - // - // Need to split this 2M page that covers NULL or stack rang= e. - // - Split2MPageTo4K (PageAddress, (UINT64 *)PageDirectoryEntry, = StackBase, StackSize, GhcbBase, GhcbSize); - } else { - // - // Fill in the Page Directory entries - // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress |= AddressEncMask; - PageDirectoryEntry->Bits.ReadWrite =3D 1; - PageDirectoryEntry->Bits.Present =3D 1; - PageDirectoryEntry->Bits.MustBe1 =3D 1; - } - } - } - - // - // Fill with null entry for unused PDPTE - // - ZeroMem (PageDirectoryPointerEntry, (512 - IndexOfPdpEntries) * si= zeof (PAGE_MAP_AND_DIRECTORY_POINTER)); - } - } + CreateOrUpdatePageTable (&PageTable, PagingMode, 0, SIZE_4KB, &MapAttr= ibute, &MapMask); + } =20 + if (PcdGetBool (PcdCpuStackGuard)) { // - // For the PML4 entries we are not using fill in a null entry. + // Set the the last 4KB of stack as non-present in page table. // - ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER)); + CreateOrUpdatePageTable (&PageTable, PagingMode, StackBase, SIZE_4KB, = &MapAttribute, &MapMask); } =20 if (Page5LevelSupport) { Cr4.UintN =3D AsmReadCr4 (); Cr4.Bits.LA57 =3D 1; AsmWriteCr4 (Cr4.UintN); - // - // For the PML5 entries we are not using fill in a null entry. - // - ZeroMem (PageMapLevel5Entry, (512 - IndexOfPml5Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER)); } =20 // // Protect the page table by marking the memory used for page table to be // read-only. // - EnablePageTableProtection ((UINTN)PageMap, TRUE); + EnablePageTableProtection ((UINTN)PageTable, TRUE); =20 // // Set IA32_EFER.NXE if necessary. @@ -956,5 +697,5 @@ CreateIdentityMappingPageTables ( EnableExecuteDisableBit (); } =20 - return (UINTN)PageMap; + return PageTable; } diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 616ebe42b0..a6cf31811d 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -7,7 +7,7 @@ 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -46,99 +46,6 @@ typedef struct { UINT32 Reserved; } X64_IDT_GATE_DESCRIPTOR; =20 -// -// Page-Map Level-4 Offset (PML4) and -// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB -// - -typedef union { - struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1= =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3D= Write-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acce= ssed (set by CPU) - UINT64 Reserved : 1; // Reserved - UINT64 MustBeZero : 2; // Must Be Zero - UINT64 Available : 3; // Available for use by system so= ftware - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 AvabilableHigh : 11; // Available for use by system so= ftware - UINT64 Nx : 1; // No Execute bit - } Bits; - UINT64 Uint64; -} PAGE_MAP_AND_DIRECTORY_POINTER; - -// -// Page Table Entry 4KB -// -typedef union { - struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1= =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3D= Write-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acce= ssed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not Dirty, 1 =3D written= by processor on access to page - UINT64 PAT : 1; // - UINT64 Global : 1; // 0 =3D Not global page, 1 =3D g= lobal page TLB not cleared on CR3 write - UINT64 Available : 3; // Available for use by system so= ftware - UINT64 PageTableBaseAddress : 40; // Page Table Base Address - UINT64 AvabilableHigh : 11; // Available for use by system so= ftware - UINT64 Nx : 1; // 0 =3D Execute Code, 1 =3D No C= ode Execution - } Bits; - UINT64 Uint64; -} PAGE_TABLE_4K_ENTRY; - -// -// Page Table Entry 2MB -// -typedef union { - struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1= =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3D= Write-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acce= ssed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not Dirty, 1 =3D written= by processor on access to page - UINT64 MustBe1 : 1; // Must be 1 - UINT64 Global : 1; // 0 =3D Not global page, 1 =3D g= lobal page TLB not cleared on CR3 write - UINT64 Available : 3; // Available for use by system so= ftware - UINT64 PAT : 1; // - UINT64 MustBeZero : 8; // Must be zero; - UINT64 PageTableBaseAddress : 31; // Page Table Base Address - UINT64 AvabilableHigh : 11; // Available for use by system so= ftware - UINT64 Nx : 1; // 0 =3D Execute Code, 1 =3D No C= ode Execution - } Bits; - UINT64 Uint64; -} PAGE_TABLE_ENTRY; - -// -// Page Table Entry 1GB -// -typedef union { - struct { - UINT64 Present : 1; // 0 =3D Not present in memory, 1= =3D Present in memory - UINT64 ReadWrite : 1; // 0 =3D Read-Only, 1=3D Read/Wri= te - UINT64 UserSupervisor : 1; // 0 =3D Supervisor, 1=3DUser - UINT64 WriteThrough : 1; // 0 =3D Write-Back caching, 1=3D= Write-Through caching - UINT64 CacheDisabled : 1; // 0 =3D Cached, 1=3DNon-Cached - UINT64 Accessed : 1; // 0 =3D Not accessed, 1 =3D Acce= ssed (set by CPU) - UINT64 Dirty : 1; // 0 =3D Not Dirty, 1 =3D written= by processor on access to page - UINT64 MustBe1 : 1; // Must be 1 - UINT64 Global : 1; // 0 =3D Not global page, 1 =3D g= lobal page TLB not cleared on CR3 write - UINT64 Available : 3; // Available for use by system so= ftware - UINT64 PAT : 1; // - UINT64 MustBeZero : 17; // Must be zero; - UINT64 PageTableBaseAddress : 22; // Page Table Base Address - UINT64 AvabilableHigh : 11; // Available for use by system so= ftware - UINT64 Nx : 1; // 0 =3D Execute Code, 1 =3D No C= ode Execution - } Bits; - UINT64 Uint64; -} PAGE_TABLE_1G_ENTRY; - #pragma pack() =20 #define CR0_WP BIT16 @@ -194,44 +101,25 @@ EnableExecuteDisableBit ( ); =20 /** - Split 2M page to 4K. - - @param[in] PhysicalAddress Start physical address the 2M page= covered. - @param[in, out] PageEntry2M Pointer to 2M page entry. - @param[in] StackBase Stack base address. - @param[in] StackSize Stack size. - @param[in] GhcbBase GHCB page area base address. - @param[in] GhcbSize GHCB page area size. - -**/ -VOID -Split2MPageTo4K ( - IN EFI_PHYSICAL_ADDRESS PhysicalAddress, - IN OUT UINT64 *PageEntry2M, - IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize, - IN EFI_PHYSICAL_ADDRESS GhcbBase, - IN UINTN GhcbSize - ); - -/** - Allocates and fills in the Page Directory and Page Table Entries to + Create IA32 PAE paging or 4-level/5-level paging for long mode to establish a 1:1 Virtual to Physical mapping. =20 - @param[in] StackBase Stack base address. - @param[in] StackSize Stack size. - @param[in] GhcbBase GHCB page area base address. - @param[in] GhcbSize GHCB page area size. + @param[in] Is64BitPageTable Whether to create 64-bit page table. + @param[in] StackBase Stack base address. + @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 - @return The address of 4 level page map. + @return The address of page table. =20 **/ UINTN CreateIdentityMappingPageTables ( + IN BOOLEAN Is64BitPageTable, IN EFI_PHYSICAL_ADDRESS StackBase, IN UINTN StackSize, IN EFI_PHYSICAL_ADDRESS GhcbBase, - IN UINTN GhcbkSize + IN UINTN GhcbSize ); =20 /** @@ -289,39 +177,4 @@ IsNullDetectionEnabled ( VOID ); =20 -/** - Prevent the memory pages used for page table from been overwritten. - - @param[in] PageTableBase Base address of page table (CR3). - @param[in] Level4Paging Level 4 paging flag. - -**/ -VOID -EnablePageTableProtection ( - IN UINTN PageTableBase, - IN BOOLEAN Level4Paging - ); - -/** - This API provides a way to allocate memory for page table. - - This API can be called more than once to allocate memory for page tables. - - Allocates the number of 4KB pages and returns a pointer to the allocated - buffer. The buffer returned is aligned on a 4KB boundary. - - If Pages is 0, then NULL is returned. - If there is not enough memory remaining to satisfy the request, then NUL= L is - returned. - - @param Pages The number of 4 KB pages to allocate. - - @return A pointer to the allocated buffer or NULL if allocation fails. - -**/ -VOID * -AllocatePageTableMemory ( - IN UINTN Pages - ); - #endif --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103470): https://edk2.groups.io/g/devel/message/103470 Mute This Topic: https://groups.io/mt/98466788/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103471+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103471+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330785; cv=none; d=zohomail.com; s=zohoarc; b=BxT14+mge2A6sMv895G6eqSefOK71gaylnqOGUZmjoHX4pdxWPyTloCs4AkcKX6IbPBPiC0Djscf6jMN7xEwMqsWizF0BVD1RcmkwRNAQrMucDERdsvV7JHrD+ZoD6QWq5h8r8RB5kEb26oh2EHIg8EhVCZ2EI/4XMQ7iRTaROc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330785; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NK07AduPH/QAeRFPEK7zLTBlv3cR2USS8WlK8dbFG0I=; b=CiPdMPfvpacM8Dsy6YSl9xKHJGR31fi17AxdfyDlcRvXsnYtKSlz88AHwr+DGA4T/I/joIDE2f1LuVs64Qvt6ay96KgNB7W3mDPGi5e3ztLTEpEwPFiey4MqeJC5iU3LVs7oMv7blt7fwHsucRNeUSG+JtT2Sb5rQbdKN17N98Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103471+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330785377756.068831363331; Mon, 24 Apr 2023 03:06:25 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id hKpdYY1788612xzLO5xuYxSY; Mon, 24 Apr 2023 03:06:25 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:24 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897905" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897905" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686766996" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686766996" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:22 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Ray Ni , Jian J Wang Subject: [edk2-devel] [Patch V3 7/8] MdeModulePkg/DxeIpl: Remove duplicated code to enable NX Date: Mon, 24 Apr 2023 18:05:51 +0800 Message-Id: <20230424100552.2718-8-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: psMU5Wp5ypRxNLKMzVzUWLrLx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330785; bh=nJtzSHymfPXBTSbRXduIe+8STXKGChmgRbs2ppjHkBw=; h=Cc:Date:From:Reply-To:Subject:To; b=SP65v8Jl+16cqxzhU9RDSkRpWi+pjtYxsYDYXal99LiM+yjOc26XwJoGQ6PeK7Iv70k vH6+i6mqZfDDull1e2sKEgVuUV/mBvs+aOHzLWp5OrGOuZle9HTfCo8VvsOJihAag45H+ sLxTkc4cU/GVEEDJlZ23cxV0ZuWNLcDjEDU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330787162100001 Content-Type: text/plain; charset="utf-8" In IA32 code, remove the duplicated code to enable NX. In the previous patch, IA32 code also uses the new CreateIdentityMappingPageTables() to create PAE page table. This function calls EnableExecuteDisableBit if needed. Signed-off-by: Dun Tan Cc: Dandan Bi Cc: Liming Gao Reviewed-by: Ray Ni Cc: Jian J Wang --- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 69d073fb58..dd7cbb6ce6 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -322,9 +322,6 @@ HandOffToDxeCore ( BuildPageTablesIa32Pae =3D ToBuildPageTable (); if (BuildPageTablesIa32Pae) { PageTables =3D CreateIdentityMappingPageTables (FALSE, BaseOfStack, = STACK_SIZE, 0, 0); - if (IsEnableNonExecNeeded ()) { - EnableExecuteDisableBit (); - } } =20 // --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103471): https://edk2.groups.io/g/devel/message/103471 Mute This Topic: https://groups.io/mt/98466790/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 20:12:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+103472+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103472+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1682330787; cv=none; d=zohomail.com; s=zohoarc; b=Unk+Bcq42EaQETcrkeFLxA0ZWljdid+JX0NDJJ06rGMmr//rZvENMw5qxmh4YrJwoFVOAz0cm6F5uS43jW6UbliJq6o0kmSCvn7E8ZVnp/iWR/i0+ap8lktuMem31FoYAMZLxVlJ9DDUt6WYEtLhXr/Ghjo/JQc95qCEDcfOzfo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682330787; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GkJj3NHYul0VoknEjrgTkflHkmEikeFNMSzLXpMMSZA=; b=FmglUogcDIONeBvlXSL5X6vc1oTQXaWowwQwrDCNG3H4rbiDh5RWaac2qmWUNTXu2hG/y1lQPYHJNlUzUzDWZZMdwGG3Nh3IeerVBzBJ9icsuDeekvwcr/kHdxXxlI7FE32/ZarX5Cyq4PIcrzxgXPKjxFt/yN3ctehR6TGkdS8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+103472+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1682330787900636.3501436840023; Mon, 24 Apr 2023 03:06:27 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id xEa8YY1788612xy5CX1Ihs1r; Mon, 24 Apr 2023 03:06:27 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.47111.1682330765582511830 for ; Mon, 24 Apr 2023 03:06:27 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="343897933" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="343897933" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="686767016" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="686767016" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.92]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 03:06:24 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Ray Ni , Jian J Wang Subject: [edk2-devel] [Patch V3 8/8] MdeModulePkg/DxeIpl: Refinement to the code to set PageTable as RO Date: Mon, 24 Apr 2023 18:05:52 +0800 Message-Id: <20230424100552.2718-9-dun.tan@intel.com> In-Reply-To: <20230424100552.2718-1-dun.tan@intel.com> References: <20230424100552.2718-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com X-Gm-Message-State: ciZJ4hHxkW41apNeSFsk2Aawx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1682330787; bh=vAoU9MOj0PU2PFQ5DoXUgUodx5Rn629OcaQ2Ast96NY=; h=Cc:Date:From:Reply-To:Subject:To; b=CfdwxBBOzp1xcYzdmWIlajWqZB3nFRUeuMJW0AarxWBXZ7PJWqsHhzeyiJiXQlt/v66 /p5HuFawO2qTxsnUWd9FOMpM6f7xVPWA1vfPV6oS9qJdHlJf22NK+aiQBnO2FRmuRUIzE NHgsp+rg9MOH/abCR77SVeMcBfcZVpiHIgo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1682330789242100007 Content-Type: text/plain; charset="utf-8" Code refinement to the code to set page table as RO in DxeIpl module. Set all page table pools as ReadOnly by calling PageTableMap() in CpuPageTableLib multiple times instead of searching each page table pool address in page table layer by layer. Also, this commit solve the issue that original SetPageTablePoolReadOnly() code in DxeIpl doesn't handle the Level5Paging case. Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4176 Signed-off-by: Dun Tan Cc: Dandan Bi Cc: Liming Gao Reviewed-by: Ray Ni Cc: Jian J Wang --- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 155 +++++++++++++++----= ---------------------------------------------------------------------------= ------------------------------------------------------------- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 15 --------------- 2 files changed, 15 insertions(+), 155 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 80482c7853..e6b6d602c1 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -330,154 +330,37 @@ CreateOrUpdatePageTable ( ASSERT (PageTableBufferSize =3D=3D 0); } =20 -/** - Set one page of page table pool memory to be read-only. - - @param[in] PageTableBase Base address of page table (CR3). - @param[in] Address Start address of a page to be set as read-on= ly. - @param[in] Level4Paging Level 4 paging flag. - -**/ -VOID -SetPageTablePoolReadOnly ( - IN UINTN PageTableBase, - IN EFI_PHYSICAL_ADDRESS Address, - IN BOOLEAN Level4Paging - ) -{ - UINTN Index; - UINTN EntryIndex; - UINT64 AddressEncMask; - EFI_PHYSICAL_ADDRESS PhysicalAddress; - UINT64 *PageTable; - UINT64 *NewPageTable; - UINT64 PageAttr; - UINT64 LevelSize[5]; - UINT64 LevelMask[5]; - UINTN LevelShift[5]; - UINTN Level; - UINT64 PoolUnitSize; - - ASSERT (PageTableBase !=3D 0); - - // - // Since the page table is always from page table pool, which is always - // located at the boundary of PcdPageTablePoolAlignment, we just need to - // set the whole pool unit to be read-only. - // - Address =3D Address & PAGE_TABLE_POOL_ALIGN_MASK; - - LevelShift[1] =3D PAGING_L1_ADDRESS_SHIFT; - LevelShift[2] =3D PAGING_L2_ADDRESS_SHIFT; - LevelShift[3] =3D PAGING_L3_ADDRESS_SHIFT; - LevelShift[4] =3D PAGING_L4_ADDRESS_SHIFT; - - LevelMask[1] =3D PAGING_4K_ADDRESS_MASK_64; - LevelMask[2] =3D PAGING_2M_ADDRESS_MASK_64; - LevelMask[3] =3D PAGING_1G_ADDRESS_MASK_64; - LevelMask[4] =3D PAGING_1G_ADDRESS_MASK_64; - - LevelSize[1] =3D SIZE_4KB; - LevelSize[2] =3D SIZE_2MB; - LevelSize[3] =3D SIZE_1GB; - LevelSize[4] =3D SIZE_512GB; - - AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & - PAGING_1G_ADDRESS_MASK_64; - PageTable =3D (UINT64 *)(UINTN)PageTableBase; - PoolUnitSize =3D PAGE_TABLE_POOL_UNIT_SIZE; - - for (Level =3D (Level4Paging) ? 4 : 3; Level > 0; --Level) { - Index =3D ((UINTN)RShiftU64 (Address, LevelShift[Level])); - Index &=3D PAGING_PAE_INDEX_MASK; - - PageAttr =3D PageTable[Index]; - if ((PageAttr & IA32_PG_PS) =3D=3D 0) { - // - // Go to next level of table. - // - PageTable =3D (UINT64 *)(UINTN)(PageAttr & ~AddressEncMask & - PAGING_4K_ADDRESS_MASK_64); - continue; - } - - if (PoolUnitSize >=3D LevelSize[Level]) { - // - // Clear R/W bit if current page granularity is not larger than pool= unit - // size. - // - if ((PageAttr & IA32_PG_RW) !=3D 0) { - while (PoolUnitSize > 0) { - // - // PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are f= it in - // one page (2MB). Then we don't need to update attributes for p= ages - // crossing page directory. ASSERT below is for that purpose. - // - ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64)); - - PageTable[Index] &=3D ~(UINT64)IA32_PG_RW; - PoolUnitSize -=3D LevelSize[Level]; - - ++Index; - } - } - - break; - } else { - // - // The smaller granularity of page must be needed. - // - ASSERT (Level > 1); - - NewPageTable =3D AllocatePageTableMemory (1); - ASSERT (NewPageTable !=3D NULL); - - PhysicalAddress =3D PageAttr & LevelMask[Level]; - for (EntryIndex =3D 0; - EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64); - ++EntryIndex) - { - NewPageTable[EntryIndex] =3D PhysicalAddress | AddressEncMask | - IA32_PG_P | IA32_PG_RW; - if (Level > 2) { - NewPageTable[EntryIndex] |=3D IA32_PG_PS; - } - - PhysicalAddress +=3D LevelSize[Level - 1]; - } - - PageTable[Index] =3D (UINT64)(UINTN)NewPageTable | AddressEncMask | - IA32_PG_P | IA32_PG_RW; - PageTable =3D NewPageTable; - } - } -} - /** Prevent the memory pages used for page table from been overwritten. =20 - @param[in] PageTableBase Base address of page table (CR3). - @param[in] Level4Paging Level 4 paging flag. + @param[in] PageTableBase Base address of page table (CR3). + @param[in] PagingMode The paging mode. =20 **/ VOID EnablePageTableProtection ( - IN UINTN PageTableBase, - IN BOOLEAN Level4Paging + IN UINTN PageTableBase, + IN PAGING_MODE PagingMode ) { PAGE_TABLE_POOL *HeadPool; PAGE_TABLE_POOL *Pool; UINT64 PoolSize; EFI_PHYSICAL_ADDRESS Address; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; =20 if (mPageTablePool =3D=3D NULL) { return; } =20 + MapAttribute.Uint64 =3D 0; + MapAttribute.Bits.ReadWrite =3D 0; + MapMask.Uint64 =3D 0; + MapMask.Bits.ReadWrite =3D 1; + // - // No need to clear CR0.WP since PageTableBase has't been written to CR3= yet. - // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to + // CreateOrUpdatePageTable might update mPageTablePool. It's safer to // remember original one in advance. // HeadPool =3D mPageTablePool; @@ -485,18 +368,10 @@ EnablePageTableProtection ( do { Address =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Pool; PoolSize =3D Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages); - // - // The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE,= which - // is one of page size of the processor (2MB by default). Let's apply = the - // protection to them one by one. + // Set entire pool including header, used-memory and left free-memory = as ReadOnly. // - while (PoolSize > 0) { - SetPageTablePoolReadOnly (PageTableBase, Address, Level4Paging); - Address +=3D PAGE_TABLE_POOL_UNIT_SIZE; - PoolSize -=3D PAGE_TABLE_POOL_UNIT_SIZE; - } - + CreateOrUpdatePageTable (&PageTableBase, PagingMode, Address, PoolSize= , &MapAttribute, &MapMask); Pool =3D Pool->NextPool; } while (Pool !=3D HeadPool); =20 @@ -688,7 +563,7 @@ CreateIdentityMappingPageTables ( // Protect the page table by marking the memory used for page table to be // read-only. // - EnablePageTableProtection ((UINTN)PageTable, TRUE); + EnablePageTableProtection (PageTable, PagingMode); =20 // // Set IA32_EFER.NXE if necessary. diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index a6cf31811d..034c4249d4 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -50,23 +50,8 @@ typedef struct { =20 #define CR0_WP BIT16 =20 -#define IA32_PG_P BIT0 -#define IA32_PG_RW BIT1 -#define IA32_PG_PS BIT7 - -#define PAGING_PAE_INDEX_MASK 0x1FF - -#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull -#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull =20 -#define PAGING_L1_ADDRESS_SHIFT 12 -#define PAGING_L2_ADDRESS_SHIFT 21 -#define PAGING_L3_ADDRESS_SHIFT 30 -#define PAGING_L4_ADDRESS_SHIFT 39 - -#define PAGING_PML4E_NUMBER 4 - #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB #define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB #define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNI= T_SIZE) --=20 2.31.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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